[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4_en.h

/*
 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _MLX4_EN_H_
#define _MLX4_EN_H_

#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>
#ifdef CONFIG_MLX4_EN_DCB
#include <linux/dcbnl.h>
#endif

#include <linux/mlx4/device.h>
#include <linux/mlx4/qp.h>
#include <linux/mlx4/cq.h>
#include <linux/mlx4/srq.h>
#include <linux/mlx4/doorbell.h>
#include <linux/mlx4/cmd.h>

#include "en_port.h"

#define DRV_NAME	"mlx4_en"
#define DRV_VERSION	"2.0"
#define DRV_RELDATE	"Dec 2011"

#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)

/*
 * Device constants
 */


#define MLX4_EN_PAGE_SHIFT	12
#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
#define MAX_RX_RINGS		16
#define MIN_RX_RINGS		4
#define TXBB_SIZE		64
#define HEADROOM		(2048 / TXBB_SIZE + 1)
#define STAMP_STRIDE		64
#define STAMP_DWORDS		(STAMP_STRIDE / 4)
#define STAMP_SHIFT		31
#define STAMP_VAL		0x7fffffff
#define STATS_DELAY		(HZ / 4)

/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
#define MAX_DESC_SIZE		512
#define MAX_DESC_TXBBS		(MAX_DESC_SIZE / TXBB_SIZE)

/*
 * OS related constants and tunables
 */

#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)

/* Use the maximum between 16384 and a single page */
#define MLX4_EN_ALLOC_SIZE	PAGE_ALIGN(16384)
#define MLX4_EN_ALLOC_ORDER	get_order(MLX4_EN_ALLOC_SIZE)

#define MLX4_EN_MAX_LRO_DESCRIPTORS	32

/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 * and 4K allocations) */
enum {
	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	FRAG_SZ1 = 1024,
	FRAG_SZ2 = 4096,
	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
};
#define MLX4_EN_MAX_RX_FRAGS	4

/* Maximum ring sizes */
#define MLX4_EN_MAX_TX_SIZE	8192
#define MLX4_EN_MAX_RX_SIZE	8192

/* Minimum ring size for our page-allocation sceme to work */
#define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)

#define MLX4_EN_SMALL_PKT_SIZE		64
#define MLX4_EN_MAX_TX_RING_P_UP	32
#define MLX4_EN_NUM_UP			8
#define MLX4_EN_DEF_TX_RING_SIZE	512
#define MLX4_EN_DEF_RX_RING_SIZE  	1024

/* Target number of packets to coalesce with interrupt moderation */
#define MLX4_EN_RX_COAL_TARGET	44
#define MLX4_EN_RX_COAL_TIME	0x10

#define MLX4_EN_TX_COAL_PKTS	16
#define MLX4_EN_TX_COAL_TIME	0x80

#define MLX4_EN_RX_RATE_LOW		400000
#define MLX4_EN_RX_COAL_TIME_LOW	0
#define MLX4_EN_RX_RATE_HIGH		450000
#define MLX4_EN_RX_COAL_TIME_HIGH	128
#define MLX4_EN_RX_SIZE_THRESH		1024
#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
#define MLX4_EN_SAMPLE_INTERVAL		0
#define MLX4_EN_AVG_PKT_SMALL		256

#define MLX4_EN_AUTO_CONF	0xffff

#define MLX4_EN_DEF_RX_PAUSE	1
#define MLX4_EN_DEF_TX_PAUSE	1

/* Interval between successive polls in the Tx routine when polling is used
   instead of interrupts (in per-core Tx rings) - should be power of 2 */
#define MLX4_EN_TX_POLL_MODER	16
#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)

#define ETH_LLC_SNAP_SIZE	8

#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
#define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)

#define MLX4_EN_MIN_MTU		46
#define ETH_BCAST		0xffffffffffffULL

#define MLX4_EN_LOOPBACK_RETRIES	5
#define MLX4_EN_LOOPBACK_TIMEOUT	100

#ifdef MLX4_EN_PERF_STAT
/* Number of samples to 'average' */
#define AVG_SIZE			128
#define AVG_FACTOR			1024
#define NUM_PERF_STATS			NUM_PERF_COUNTERS

#define INC_PERF_COUNTER(cnt)		(++(cnt))
#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
#define AVG_PERF_COUNTER(cnt, sample) \
	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
#define GET_PERF_COUNTER(cnt)		(cnt)
#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)

#else

#define NUM_PERF_STATS			0
#define INC_PERF_COUNTER(cnt)		do {} while (0)
#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
#define GET_PERF_COUNTER(cnt)		(0)
#define GET_AVG_PERF_COUNTER(cnt)	(0)
#endif /* MLX4_EN_PERF_STAT */

/*
 * Configurables
 */

enum cq_type {
	RX = 0,
	TX = 1,
};


/*
 * Useful macros
 */
#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
#define XNOR(x, y)		(!(x) == !(y))
#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)


struct mlx4_en_tx_info {
	struct sk_buff *skb;
	u32 nr_txbb;
	u32 nr_bytes;
	u8 linear;
	u8 data_offset;
	u8 inl;
};


#define MLX4_EN_BIT_DESC_OWN	0x80000000
#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
#define MLX4_EN_MEMTYPE_PAD	0x100
#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)


struct mlx4_en_tx_desc {
	struct mlx4_wqe_ctrl_seg ctrl;
	union {
		struct mlx4_wqe_data_seg data; /* at least one data segment */
		struct mlx4_wqe_lso_seg lso;
		struct mlx4_wqe_inline_seg inl;
	};
};

#define MLX4_EN_USE_SRQ		0x01000000

#define MLX4_EN_CX3_LOW_ID	0x1000
#define MLX4_EN_CX3_HIGH_ID	0x1005

struct mlx4_en_rx_alloc {
	struct page *page;
	u16 offset;
};

struct mlx4_en_tx_ring {
	struct mlx4_hwq_resources wqres;
	u32 size ; /* number of TXBBs */
	u32 size_mask;
	u16 stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	u32 doorbell_qpn;
	void *buf;
	u16 poll_cnt;
	int blocked;
	struct mlx4_en_tx_info *tx_info;
	u8 *bounce_buf;
	u32 last_nr_txbb;
	struct mlx4_qp qp;
	struct mlx4_qp_context context;
	int qpn;
	enum mlx4_qp_state qp_state;
	struct mlx4_srq dummy;
	unsigned long bytes;
	unsigned long packets;
	unsigned long tx_csum;
	struct mlx4_bf bf;
	bool bf_enabled;
	struct netdev_queue *tx_queue;
};

struct mlx4_en_rx_desc {
	/* actual number of entries depends on rx ring stride */
	struct mlx4_wqe_data_seg data[0];
};

struct mlx4_en_rx_ring {
	struct mlx4_hwq_resources wqres;
	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	u32 size ;	/* number of Rx descs*/
	u32 actual_size;
	u32 size_mask;
	u16 stride;
	u16 log_stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	u8  fcs_del;
	void *buf;
	void *rx_info;
	unsigned long bytes;
	unsigned long packets;
	unsigned long csum_ok;
	unsigned long csum_none;
};


static inline int mlx4_en_can_lro(__be16 status)
{
	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4	|
				     MLX4_CQE_STATUS_IPV4F	|
				     MLX4_CQE_STATUS_IPV6	|
				     MLX4_CQE_STATUS_IPV4OPT	|
				     MLX4_CQE_STATUS_TCP	|
				     MLX4_CQE_STATUS_UDP	|
				     MLX4_CQE_STATUS_IPOK)) ==
		cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
			    MLX4_CQE_STATUS_IPOK |
			    MLX4_CQE_STATUS_TCP);
}

struct mlx4_en_cq {
	struct mlx4_cq          mcq;
	struct mlx4_hwq_resources wqres;
	int                     ring;
	spinlock_t              lock;
	struct net_device      *dev;
	struct napi_struct	napi;
	int size;
	int buf_size;
	unsigned vector;
	enum cq_type is_tx;
	u16 moder_time;
	u16 moder_cnt;
	struct mlx4_cqe *buf;
#define MLX4_EN_OPCODE_ERROR	0x1e
};

struct mlx4_en_port_profile {
	u32 flags;
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 tx_ring_size;
	u32 rx_ring_size;
	u8 rx_pause;
	u8 rx_ppp;
	u8 tx_pause;
	u8 tx_ppp;
	int rss_rings;
};

struct mlx4_en_profile {
	int rss_xor;
	int udp_rss;
	u8 rss_mask;
	u32 active_ports;
	u32 small_pkt_int;
	u8 no_reset;
	u8 num_tx_rings_p_up;
	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
};

struct mlx4_en_dev {
	struct mlx4_dev         *dev;
	struct pci_dev		*pdev;
	struct mutex		state_lock;
	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
	u32                     port_cnt;
	bool			device_up;
	struct mlx4_en_profile  profile;
	u32			LSO_support;
	struct workqueue_struct *workqueue;
	struct device           *dma_device;
	void __iomem            *uar_map;
	struct mlx4_uar         priv_uar;
	struct mlx4_mr		mr;
	u32                     priv_pdn;
	spinlock_t              uar_lock;
	u8			mac_removed[MLX4_MAX_PORTS + 1];
};


struct mlx4_en_rss_map {
	int base_qpn;
	struct mlx4_qp qps[MAX_RX_RINGS];
	enum mlx4_qp_state state[MAX_RX_RINGS];
	struct mlx4_qp indir_qp;
	enum mlx4_qp_state indir_state;
};

struct mlx4_en_port_state {
	int link_state;
	int link_speed;
	int transciver;
};

struct mlx4_en_pkt_stats {
	unsigned long broadcast;
	unsigned long rx_prio[8];
	unsigned long tx_prio[8];
#define NUM_PKT_STATS		17
};

struct mlx4_en_port_stats {
	unsigned long tso_packets;
	unsigned long queue_stopped;
	unsigned long wake_queue;
	unsigned long tx_timeout;
	unsigned long rx_alloc_failed;
	unsigned long rx_chksum_good;
	unsigned long rx_chksum_none;
	unsigned long tx_chksum_offload;
#define NUM_PORT_STATS		8
};

struct mlx4_en_perf_stats {
	u32 tx_poll;
	u64 tx_pktsz_avg;
	u32 inflight_avg;
	u16 tx_coal_avg;
	u16 rx_coal_avg;
	u32 napi_quota;
#define NUM_PERF_COUNTERS		6
};

struct mlx4_en_frag_info {
	u16 frag_size;
	u16 frag_prefix_size;
	u16 frag_stride;
	u16 frag_align;
	u16 last_offset;

};

#ifdef CONFIG_MLX4_EN_DCB
/* Minimal TC BW - setting to 0 will block traffic */
#define MLX4_EN_BW_MIN 1
#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */

#define MLX4_EN_TC_ETS 7

#endif

struct mlx4_en_priv {
	struct mlx4_en_dev *mdev;
	struct mlx4_en_port_profile *prof;
	struct net_device *dev;
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	struct net_device_stats stats;
	struct net_device_stats ret_stats;
	struct mlx4_en_port_state port_state;
	spinlock_t stats_lock;

	unsigned long last_moder_packets[MAX_RX_RINGS];
	unsigned long last_moder_tx_packets;
	unsigned long last_moder_bytes[MAX_RX_RINGS];
	unsigned long last_moder_jiffies;
	int last_moder_time[MAX_RX_RINGS];
	u16 rx_usecs;
	u16 rx_frames;
	u16 tx_usecs;
	u16 tx_frames;
	u32 pkt_rate_low;
	u16 rx_usecs_low;
	u32 pkt_rate_high;
	u16 rx_usecs_high;
	u16 sample_interval;
	u16 adaptive_rx_coal;
	u32 msg_enable;
	u32 loopback_ok;
	u32 validate_loopback;

	struct mlx4_hwq_resources res;
	int link_state;
	int last_link_state;
	bool port_up;
	int port;
	int registered;
	int allocated;
	int stride;
	u64 mac;
	int mac_index;
	unsigned max_mtu;
	int base_qpn;

	struct mlx4_en_rss_map rss_map;
	__be32 ctrl_flags;
	u32 flags;
#define MLX4_EN_FLAG_PROMISC	0x1
#define MLX4_EN_FLAG_MC_PROMISC	0x2
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 rx_skb_size;
	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	u16 num_frags;
	u16 log_rx_info;

	struct mlx4_en_tx_ring *tx_ring;
	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	struct mlx4_en_cq *tx_cq;
	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	struct work_struct mcast_task;
	struct work_struct mac_task;
	struct work_struct watchdog_task;
	struct work_struct linkstate_task;
	struct delayed_work stats_task;
	struct mlx4_en_perf_stats pstats;
	struct mlx4_en_pkt_stats pkstats;
	struct mlx4_en_port_stats port_stats;
	u64 stats_bitmap;
	char *mc_addrs;
	int mc_addrs_cnt;
	struct mlx4_en_stat_out_mbox hw_stats;
	int vids[128];
	bool wol;
	struct device *ddev;
	int base_tx_qpn;

#ifdef CONFIG_MLX4_EN_DCB
	struct ieee_ets ets;
	u16 maxrate[IEEE_8021QAZ_MAX_TCS];
#endif
};

enum mlx4_en_wol {
	MLX4_EN_WOL_MAGIC = (1ULL << 61),
	MLX4_EN_WOL_ENABLED = (1ULL << 62),
};

#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)

void mlx4_en_destroy_netdev(struct net_device *dev);
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
			struct mlx4_en_port_profile *prof);

int mlx4_en_start_port(struct net_device *dev);
void mlx4_en_stop_port(struct net_device *dev);

void mlx4_en_free_resources(struct mlx4_en_priv *priv);
int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);

int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
		      int entries, int ring, enum cq_type mode);
void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
			int cq_idx);
void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);

void mlx4_en_tx_irq(struct mlx4_cq *mcq);
u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);

int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
			   int qpn, u32 size, u16 stride);
void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_tx_ring *ring,
			     int cq, int user_prio);
void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_tx_ring *ring);

int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
			   struct mlx4_en_rx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_rx_ring *ring,
			     u32 size, u16 stride);
int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_rx_ring *ring);
int mlx4_en_process_rx_cq(struct net_device *dev,
			  struct mlx4_en_cq *cq,
			  int budget);
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
		int is_tx, int rss, int qpn, int cqn, int user_prio,
		struct mlx4_qp_context *context);
void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
int mlx4_en_map_buffer(struct mlx4_buf *buf);
void mlx4_en_unmap_buffer(struct mlx4_buf *buf);

void mlx4_en_calc_rx_buf(struct net_device *dev);
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
void mlx4_en_rx_irq(struct mlx4_cq *mcq);

int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);

#ifdef CONFIG_MLX4_EN_DCB
extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
#endif

#define MLX4_EN_NUM_SELF_TEST	5
void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
u64 mlx4_en_mac_to_u64(u8 *addr);

/*
 * Globals
 */
extern const struct ethtool_ops mlx4_en_ethtool_ops;


/*
 * printk / logging functions
 */

__printf(3, 4)
int en_print(const char *level, const struct mlx4_en_priv *priv,
	     const char *format, ...);

#define en_dbg(mlevel, priv, format, arg...)			\
do {								\
	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
		en_print(KERN_DEBUG, priv, format, ##arg);	\
} while (0)
#define en_warn(priv, format, arg...)			\
	en_print(KERN_WARNING, priv, format, ##arg)
#define en_err(priv, format, arg...)			\
	en_print(KERN_ERR, priv, format, ##arg)
#define en_info(priv, format, arg...)			\
	en_print(KERN_INFO, priv, format, ## arg)

#define mlx4_err(mdev, format, arg...)			\
	pr_err("%s %s: " format, DRV_NAME,		\
	       dev_name(&mdev->pdev->dev), ##arg)
#define mlx4_info(mdev, format, arg...)			\
	pr_info("%s %s: " format, DRV_NAME,		\
		dev_name(&mdev->pdev->dev), ##arg)
#define mlx4_warn(mdev, format, arg...)			\
	pr_warning("%s %s: " format, DRV_NAME,		\
		   dev_name(&mdev->pdev->dev), ##arg)

#endif
Commit	Line	Data
c27a02cd YP	1	/*
	2	* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34	#ifndef _MLX4_EN_H_
	35	#define _MLX4_EN_H_
	36
f1b553fb	37	#include <linux/bitops.h>
c27a02cd YP	38	#include <linux/compiler.h>
	39	#include <linux/list.h>
	40	#include <linux/mutex.h>
	41	#include <linux/netdevice.h>
f1b553fb	42	#include <linux/if_vlan.h>
564c274c AV	43	#ifdef CONFIG_MLX4_EN_DCB
	44	#include <linux/dcbnl.h>
	45	#endif
c27a02cd YP	46
	47	#include <linux/mlx4/device.h>
	48	#include <linux/mlx4/qp.h>
	49	#include <linux/mlx4/cq.h>
	50	#include <linux/mlx4/srq.h>
	51	#include <linux/mlx4/doorbell.h>
e7c1c2c4	52	#include <linux/mlx4/cmd.h>
c27a02cd YP	53
	54	#include "en_port.h"
	55
	56	#define DRV_NAME "mlx4_en"
6edf91da YP	57	#define DRV_VERSION "2.0"
6edf91da YP	58	#define DRV_RELDATE "Dec 2011"
c27a02cd	59
c27a02cd YP	60	#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK \| NETIF_MSG_IFDOWN)
c27a02cd YP	61
c27a02cd YP	62	/*
	63	* Device constants
	64	*/
	65
	66
	67	#define MLX4_EN_PAGE_SHIFT 12
	68	#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
c27a02cd	69	#define MAX_RX_RINGS 16
1fb9876e	70	#define MIN_RX_RINGS 4
c27a02cd YP	71	#define TXBB_SIZE 64
c27a02cd YP	72	#define HEADROOM (2048 / TXBB_SIZE + 1)
c27a02cd YP	73	#define STAMP_STRIDE 64
	74	#define STAMP_DWORDS (STAMP_STRIDE / 4)
	75	#define STAMP_SHIFT 31
	76	#define STAMP_VAL 0x7fffffff
	77	#define STATS_DELAY (HZ / 4)
	78
	79	/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
	80	#define MAX_DESC_SIZE 512
	81	#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
	82
	83	/*
	84	* OS related constants and tunables
	85	*/
	86
	87	#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
	88
117980c4 TLSC	89	/* Use the maximum between 16384 and a single page */
	90	#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
	91	#define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
c27a02cd YP	92
	93	#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
	94
	95	/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
	96	* and 4K allocations) */
	97	enum {
	98	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	99	FRAG_SZ1 = 1024,
	100	FRAG_SZ2 = 4096,
	101	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
	102	};
	103	#define MLX4_EN_MAX_RX_FRAGS 4
	104
bd531e36 YP	105	/* Maximum ring sizes */
	106	#define MLX4_EN_MAX_TX_SIZE 8192
	107	#define MLX4_EN_MAX_RX_SIZE 8192
	108
c27a02cd YP	109	/* Minimum ring size for our page-allocation sceme to work */
	110	#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
	111	#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
	112
f813cad8	113	#define MLX4_EN_SMALL_PKT_SIZE 64
bc6a4744	114	#define MLX4_EN_MAX_TX_RING_P_UP 32
564c274c	115	#define MLX4_EN_NUM_UP 8
f813cad8	116	#define MLX4_EN_DEF_TX_RING_SIZE 512
c27a02cd YP	117	#define MLX4_EN_DEF_RX_RING_SIZE 1024
c27a02cd YP	118
3db36fb2 YP	119	/* Target number of packets to coalesce with interrupt moderation */
3db36fb2 YP	120	#define MLX4_EN_RX_COAL_TARGET 44
c27a02cd YP	121	#define MLX4_EN_RX_COAL_TIME 0x10
c27a02cd YP	122
e22979d9	123	#define MLX4_EN_TX_COAL_PKTS 16
c27a02cd YP	124	#define MLX4_EN_TX_COAL_TIME 0x80
	125
	126	#define MLX4_EN_RX_RATE_LOW 400000
	127	#define MLX4_EN_RX_COAL_TIME_LOW 0
	128	#define MLX4_EN_RX_RATE_HIGH 450000
	129	#define MLX4_EN_RX_COAL_TIME_HIGH 128
	130	#define MLX4_EN_RX_SIZE_THRESH 1024
	131	#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
	132	#define MLX4_EN_SAMPLE_INTERVAL 0
46afd0fb	133	#define MLX4_EN_AVG_PKT_SMALL 256
c27a02cd YP	134
	135	#define MLX4_EN_AUTO_CONF 0xffff
	136
	137	#define MLX4_EN_DEF_RX_PAUSE 1
	138	#define MLX4_EN_DEF_TX_PAUSE 1
	139
af901ca1	140	/* Interval between successive polls in the Tx routine when polling is used
c27a02cd YP	141	instead of interrupts (in per-core Tx rings) - should be power of 2 */
	142	#define MLX4_EN_TX_POLL_MODER 16
	143	#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
	144
	145	#define ETH_LLC_SNAP_SIZE 8
	146
	147	#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
	148	#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
e7c1c2c4	149	#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
c27a02cd YP	150
	151	#define MLX4_EN_MIN_MTU 46
	152	#define ETH_BCAST 0xffffffffffffULL
	153
e7c1c2c4 YP	154	#define MLX4_EN_LOOPBACK_RETRIES 5
	155	#define MLX4_EN_LOOPBACK_TIMEOUT 100
	156
c27a02cd YP	157	#ifdef MLX4_EN_PERF_STAT
	158	/* Number of samples to 'average' */
	159	#define AVG_SIZE 128
	160	#define AVG_FACTOR 1024
	161	#define NUM_PERF_STATS NUM_PERF_COUNTERS
	162
	163	#define INC_PERF_COUNTER(cnt) (++(cnt))
	164	#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
	165	#define AVG_PERF_COUNTER(cnt, sample) \
	166	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
	167	#define GET_PERF_COUNTER(cnt) (cnt)
	168	#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
	169
	170	#else
	171
	172	#define NUM_PERF_STATS 0
	173	#define INC_PERF_COUNTER(cnt) do {} while (0)
	174	#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
	175	#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
	176	#define GET_PERF_COUNTER(cnt) (0)
	177	#define GET_AVG_PERF_COUNTER(cnt) (0)
	178	#endif /* MLX4_EN_PERF_STAT */
	179
	180	/*
	181	* Configurables
	182	*/
	183
	184	enum cq_type {
	185	RX = 0,
	186	TX = 1,
	187	};
	188
	189
	190	/*
	191	* Useful macros
	192	*/
	193	#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
	194	#define XNOR(x, y) (!(x) == !(y))
	195	#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL \|\| addr == 0x0)
	196
	197
	198	struct mlx4_en_tx_info {
	199	struct sk_buff *skb;
	200	u32 nr_txbb;
5b263f53	201	u32 nr_bytes;
c27a02cd YP	202	u8 linear;
c27a02cd YP	203	u8 data_offset;
41efea5a	204	u8 inl;
c27a02cd YP	205	};
	206
	207
	208	#define MLX4_EN_BIT_DESC_OWN 0x80000000
	209	#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
	210	#define MLX4_EN_MEMTYPE_PAD 0x100
	211	#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
	212
	213
	214	struct mlx4_en_tx_desc {
	215	struct mlx4_wqe_ctrl_seg ctrl;
	216	union {
	217	struct mlx4_wqe_data_seg data; /* at least one data segment */
	218	struct mlx4_wqe_lso_seg lso;
	219	struct mlx4_wqe_inline_seg inl;
	220	};
	221	};
	222
	223	#define MLX4_EN_USE_SRQ 0x01000000
	224
725c8999 YP	225	#define MLX4_EN_CX3_LOW_ID 0x1000
	226	#define MLX4_EN_CX3_HIGH_ID 0x1005
	227
c27a02cd YP	228	struct mlx4_en_rx_alloc {
	229	struct page *page;
	230	u16 offset;
	231	};
	232
	233	struct mlx4_en_tx_ring {
	234	struct mlx4_hwq_resources wqres;
	235	u32 size ; /* number of TXBBs */
	236	u32 size_mask;
	237	u16 stride;
	238	u16 cqn; /* index of port CQ associated with this ring */
	239	u32 prod;
	240	u32 cons;
	241	u32 buf_size;
	242	u32 doorbell_qpn;
	243	void *buf;
	244	u16 poll_cnt;
	245	int blocked;
	246	struct mlx4_en_tx_info *tx_info;
	247	u8 *bounce_buf;
	248	u32 last_nr_txbb;
	249	struct mlx4_qp qp;
	250	struct mlx4_qp_context context;
	251	int qpn;
	252	enum mlx4_qp_state qp_state;
	253	struct mlx4_srq dummy;
	254	unsigned long bytes;
	255	unsigned long packets;
ad04378c	256	unsigned long tx_csum;
87a5c389 YP	257	struct mlx4_bf bf;
87a5c389 YP	258	bool bf_enabled;
5b263f53	259	struct netdev_queue *tx_queue;
c27a02cd YP	260	};
	261
	262	struct mlx4_en_rx_desc {
c27a02cd YP	263	/* actual number of entries depends on rx ring stride */
	264	struct mlx4_wqe_data_seg data[0];
	265	};
	266
	267	struct mlx4_en_rx_ring {
c27a02cd YP	268	struct mlx4_hwq_resources wqres;
c27a02cd YP	269	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
c27a02cd YP	270	u32 size ; /* number of Rx descs*/
	271	u32 actual_size;
	272	u32 size_mask;
	273	u16 stride;
	274	u16 log_stride;
	275	u16 cqn; /* index of port CQ associated with this ring */
	276	u32 prod;
	277	u32 cons;
	278	u32 buf_size;
4a5f4dd8	279	u8 fcs_del;
c27a02cd YP	280	void *buf;
	281	void *rx_info;
	282	unsigned long bytes;
	283	unsigned long packets;
ad04378c YP	284	unsigned long csum_ok;
ad04378c YP	285	unsigned long csum_none;
c27a02cd YP	286	};
	287
	288
	289	static inline int mlx4_en_can_lro(__be16 status)
	290	{
	291	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	292	MLX4_CQE_STATUS_IPV4F \|
	293	MLX4_CQE_STATUS_IPV6 \|
	294	MLX4_CQE_STATUS_IPV4OPT \|
	295	MLX4_CQE_STATUS_TCP \|
	296	MLX4_CQE_STATUS_UDP \|
	297	MLX4_CQE_STATUS_IPOK)) ==
	298	cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	299	MLX4_CQE_STATUS_IPOK \|
	300	MLX4_CQE_STATUS_TCP);
	301	}
	302
	303	struct mlx4_en_cq {
	304	struct mlx4_cq mcq;
	305	struct mlx4_hwq_resources wqres;
	306	int ring;
	307	spinlock_t lock;
	308	struct net_device *dev;
	309	struct napi_struct napi;
c27a02cd YP	310	int size;
	311	int buf_size;
	312	unsigned vector;
	313	enum cq_type is_tx;
	314	u16 moder_time;
	315	u16 moder_cnt;
c27a02cd YP	316	struct mlx4_cqe *buf;
	317	#define MLX4_EN_OPCODE_ERROR 0x1e
	318	};
	319
	320	struct mlx4_en_port_profile {
	321	u32 flags;
	322	u32 tx_ring_num;
	323	u32 rx_ring_num;
	324	u32 tx_ring_size;
	325	u32 rx_ring_size;
d53b93f2 YP	326	u8 rx_pause;
	327	u8 rx_ppp;
	328	u8 tx_pause;
	329	u8 tx_ppp;
93d3e367	330	int rss_rings;
c27a02cd YP	331	};
	332
	333	struct mlx4_en_profile {
	334	int rss_xor;
0533943c	335	int udp_rss;
c27a02cd YP	336	u8 rss_mask;
	337	u32 active_ports;
	338	u32 small_pkt_int;
c27a02cd	339	u8 no_reset;
bc6a4744	340	u8 num_tx_rings_p_up;
c27a02cd YP	341	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
	342	};
	343
	344	struct mlx4_en_dev {
	345	struct mlx4_dev *dev;
	346	struct pci_dev *pdev;
	347	struct mutex state_lock;
	348	struct net_device *pndev[MLX4_MAX_PORTS + 1];
	349	u32 port_cnt;
	350	bool device_up;
	351	struct mlx4_en_profile profile;
	352	u32 LSO_support;
	353	struct workqueue_struct *workqueue;
	354	struct device *dma_device;
	355	void __iomem *uar_map;
	356	struct mlx4_uar priv_uar;
	357	struct mlx4_mr mr;
	358	u32 priv_pdn;
	359	spinlock_t uar_lock;
d7e1a487	360	u8 mac_removed[MLX4_MAX_PORTS + 1];
c27a02cd YP	361	};
	362
	363
	364	struct mlx4_en_rss_map {
c27a02cd	365	int base_qpn;
b6b912e0 YP	366	struct mlx4_qp qps[MAX_RX_RINGS];
b6b912e0 YP	367	enum mlx4_qp_state state[MAX_RX_RINGS];
c27a02cd YP	368	struct mlx4_qp indir_qp;
	369	enum mlx4_qp_state indir_state;
	370	};
	371
e7c1c2c4 YP	372	struct mlx4_en_port_state {
	373	int link_state;
	374	int link_speed;
	375	int transciver;
	376	};
	377
c27a02cd YP	378	struct mlx4_en_pkt_stats {
	379	unsigned long broadcast;
	380	unsigned long rx_prio[8];
	381	unsigned long tx_prio[8];
	382	#define NUM_PKT_STATS 17
	383	};
	384
	385	struct mlx4_en_port_stats {
c27a02cd YP	386	unsigned long tso_packets;
	387	unsigned long queue_stopped;
	388	unsigned long wake_queue;
	389	unsigned long tx_timeout;
	390	unsigned long rx_alloc_failed;
	391	unsigned long rx_chksum_good;
	392	unsigned long rx_chksum_none;
	393	unsigned long tx_chksum_offload;
d61702f1	394	#define NUM_PORT_STATS 8
c27a02cd YP	395	};
	396
	397	struct mlx4_en_perf_stats {
	398	u32 tx_poll;
	399	u64 tx_pktsz_avg;
	400	u32 inflight_avg;
	401	u16 tx_coal_avg;
	402	u16 rx_coal_avg;
	403	u32 napi_quota;
	404	#define NUM_PERF_COUNTERS 6
	405	};
	406
	407	struct mlx4_en_frag_info {
	408	u16 frag_size;
	409	u16 frag_prefix_size;
	410	u16 frag_stride;
	411	u16 frag_align;
	412	u16 last_offset;
	413
	414	};
	415
564c274c AV	416	#ifdef CONFIG_MLX4_EN_DCB
	417	/* Minimal TC BW - setting to 0 will block traffic */
	418	#define MLX4_EN_BW_MIN 1
	419	#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
	420
	421	#define MLX4_EN_TC_ETS 7
	422
	423	#endif
	424
c27a02cd YP	425	struct mlx4_en_priv {
	426	struct mlx4_en_dev *mdev;
	427	struct mlx4_en_port_profile *prof;
	428	struct net_device *dev;
f1b553fb	429	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
c27a02cd YP	430	struct net_device_stats stats;
c27a02cd YP	431	struct net_device_stats ret_stats;
e7c1c2c4	432	struct mlx4_en_port_state port_state;
c27a02cd YP	433	spinlock_t stats_lock;
c27a02cd YP	434
6b4d8d9f	435	unsigned long last_moder_packets[MAX_RX_RINGS];
c27a02cd	436	unsigned long last_moder_tx_packets;
6b4d8d9f	437	unsigned long last_moder_bytes[MAX_RX_RINGS];
c27a02cd	438	unsigned long last_moder_jiffies;
6b4d8d9f	439	int last_moder_time[MAX_RX_RINGS];
c27a02cd YP	440	u16 rx_usecs;
	441	u16 rx_frames;
	442	u16 tx_usecs;
	443	u16 tx_frames;
	444	u32 pkt_rate_low;
	445	u16 rx_usecs_low;
	446	u32 pkt_rate_high;
	447	u16 rx_usecs_high;
	448	u16 sample_interval;
	449	u16 adaptive_rx_coal;
	450	u32 msg_enable;
e7c1c2c4 YP	451	u32 loopback_ok;
e7c1c2c4 YP	452	u32 validate_loopback;
c27a02cd YP	453
	454	struct mlx4_hwq_resources res;
	455	int link_state;
	456	int last_link_state;
	457	bool port_up;
	458	int port;
	459	int registered;
	460	int allocated;
	461	int stride;
c27a02cd YP	462	u64 mac;
	463	int mac_index;
	464	unsigned max_mtu;
	465	int base_qpn;
	466
	467	struct mlx4_en_rss_map rss_map;
4ef2a435	468	__be32 ctrl_flags;
c27a02cd YP	469	u32 flags;
c27a02cd YP	470	#define MLX4_EN_FLAG_PROMISC 0x1
1679200f	471	#define MLX4_EN_FLAG_MC_PROMISC 0x2
c27a02cd YP	472	u32 tx_ring_num;
	473	u32 rx_ring_num;
	474	u32 rx_skb_size;
	475	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	476	u16 num_frags;
	477	u16 log_rx_info;
	478
bc6a4744	479	struct mlx4_en_tx_ring *tx_ring;
c27a02cd	480	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
bc6a4744	481	struct mlx4_en_cq *tx_cq;
c27a02cd YP	482	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	483	struct work_struct mcast_task;
	484	struct work_struct mac_task;
c27a02cd YP	485	struct work_struct watchdog_task;
	486	struct work_struct linkstate_task;
	487	struct delayed_work stats_task;
	488	struct mlx4_en_perf_stats pstats;
	489	struct mlx4_en_pkt_stats pkstats;
	490	struct mlx4_en_port_stats port_stats;
93ece0c1	491	u64 stats_bitmap;
ff6e2163 JP	492	char *mc_addrs;
ff6e2163 JP	493	int mc_addrs_cnt;
c27a02cd	494	struct mlx4_en_stat_out_mbox hw_stats;
4c3eb3ca	495	int vids[128];
14c07b13	496	bool wol;
ebf8c9aa	497	struct device *ddev;
044ca2a5	498	int base_tx_qpn;
564c274c AV	499
	500	#ifdef CONFIG_MLX4_EN_DCB
	501	struct ieee_ets ets;
109d2446	502	u16 maxrate[IEEE_8021QAZ_MAX_TCS];
564c274c	503	#endif
14c07b13 YP	504	};
	505
	506	enum mlx4_en_wol {
	507	MLX4_EN_WOL_MAGIC = (1ULL << 61),
	508	MLX4_EN_WOL_ENABLED = (1ULL << 62),
c27a02cd YP	509	};
c27a02cd YP	510
0d9fdaa9	511	#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
c27a02cd YP	512
	513	void mlx4_en_destroy_netdev(struct net_device *dev);
	514	int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
	515	struct mlx4_en_port_profile *prof);
	516
18cc42a3 YP	517	int mlx4_en_start_port(struct net_device *dev);
	518	void mlx4_en_stop_port(struct net_device *dev);
	519
fe0af03c	520	void mlx4_en_free_resources(struct mlx4_en_priv *priv);
18cc42a3 YP	521	int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
18cc42a3 YP	522
c27a02cd YP	523	int mlx4_en_create_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
c27a02cd YP	524	int entries, int ring, enum cq_type mode);
fe0af03c	525	void mlx4_en_destroy_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
76532d0c AG	526	int mlx4_en_activate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
76532d0c AG	527	int cq_idx);
c27a02cd YP	528	void mlx4_en_deactivate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	529	int mlx4_en_set_cq_moder(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	530	int mlx4_en_arm_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	531
c27a02cd	532	void mlx4_en_tx_irq(struct mlx4_cq *mcq);
f813cad8	533	u16 mlx4_en_select_queue(struct net_device dev, struct sk_buff skb);
61357325	534	netdev_tx_t mlx4_en_xmit(struct sk_buff skb, struct net_device dev);
c27a02cd YP	535
c27a02cd YP	536	int mlx4_en_create_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring,
87a5c389	537	int qpn, u32 size, u16 stride);
c27a02cd YP	538	void mlx4_en_destroy_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring);
	539	int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
	540	struct mlx4_en_tx_ring *ring,
0e98b523	541	int cq, int user_prio);
c27a02cd YP	542	void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
	543	struct mlx4_en_tx_ring *ring);
	544
	545	int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
	546	struct mlx4_en_rx_ring *ring,
	547	u32 size, u16 stride);
	548	void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
68355f71 TLSC	549	struct mlx4_en_rx_ring *ring,
68355f71 TLSC	550	u32 size, u16 stride);
c27a02cd YP	551	int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
	552	void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
	553	struct mlx4_en_rx_ring *ring);
	554	int mlx4_en_process_rx_cq(struct net_device *dev,
	555	struct mlx4_en_cq *cq,
	556	int budget);
	557	int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
	558	void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
0e98b523 AV	559	int is_tx, int rss, int qpn, int cqn, int user_prio,
0e98b523 AV	560	struct mlx4_qp_context *context);
966508f7	561	void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
c27a02cd YP	562	int mlx4_en_map_buffer(struct mlx4_buf *buf);
	563	void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
	564
	565	void mlx4_en_calc_rx_buf(struct net_device *dev);
c27a02cd YP	566	int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
	567	void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
	568	int mlx4_en_free_tx_buf(struct net_device dev, struct mlx4_en_tx_ring ring);
c27a02cd YP	569	void mlx4_en_rx_irq(struct mlx4_cq *mcq);
	570
	571	int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
f1b553fb	572	int mlx4_SET_VLAN_FLTR(struct mlx4_dev dev, struct mlx4_en_priv priv);
c27a02cd YP	573
c27a02cd YP	574	int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
e7c1c2c4 YP	575	int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
e7c1c2c4 YP	576
564c274c AV	577	#ifdef CONFIG_MLX4_EN_DCB
	578	extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
	579	#endif
	580
e7c1c2c4 YP	581	#define MLX4_EN_NUM_SELF_TEST 5
	582	void mlx4_en_ex_selftest(struct net_device dev, u32 flags, u64 *buf);
	583	u64 mlx4_en_mac_to_u64(u8 *addr);
c27a02cd YP	584
	585	/*
	586	* Globals
	587	*/
	588	extern const struct ethtool_ops mlx4_en_ethtool_ops;
0a645e80 JP	589
	590
	591
	592	/*
	593	* printk / logging functions
	594	*/
	595
b9075fa9	596	__printf(3, 4)
0a645e80	597	int en_print(const char level, const struct mlx4_en_priv priv,
b9075fa9	598	const char *format, ...);
0a645e80 JP	599
	600	#define en_dbg(mlevel, priv, format, arg...) \
	601	do { \
	602	if (NETIF_MSG_##mlevel & priv->msg_enable) \
	603	en_print(KERN_DEBUG, priv, format, ##arg); \
	604	} while (0)
	605	#define en_warn(priv, format, arg...) \
	606	en_print(KERN_WARNING, priv, format, ##arg)
	607	#define en_err(priv, format, arg...) \
	608	en_print(KERN_ERR, priv, format, ##arg)
e5cc44b2 YP	609	#define en_info(priv, format, arg...) \
e5cc44b2 YP	610	en_print(KERN_INFO, priv, format, ## arg)
0a645e80 JP	611
	612	#define mlx4_err(mdev, format, arg...) \
	613	pr_err("%s %s: " format, DRV_NAME, \
	614	dev_name(&mdev->pdev->dev), ##arg)
	615	#define mlx4_info(mdev, format, arg...) \
	616	pr_info("%s %s: " format, DRV_NAME, \
	617	dev_name(&mdev->pdev->dev), ##arg)
	618	#define mlx4_warn(mdev, format, arg...) \
	619	pr_warning("%s %s: " format, DRV_NAME, \
	620	dev_name(&mdev->pdev->dev), ##arg)
	621
c27a02cd	622	#endif