Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #ifndef _MLX4_EN_H_ | |
35 | #define _MLX4_EN_H_ | |
36 | ||
f1b553fb | 37 | #include <linux/bitops.h> |
c27a02cd YP |
38 | #include <linux/compiler.h> |
39 | #include <linux/list.h> | |
40 | #include <linux/mutex.h> | |
41 | #include <linux/netdevice.h> | |
f1b553fb | 42 | #include <linux/if_vlan.h> |
ec693d47 | 43 | #include <linux/net_tstamp.h> |
564c274c AV |
44 | #ifdef CONFIG_MLX4_EN_DCB |
45 | #include <linux/dcbnl.h> | |
46 | #endif | |
1eb8c695 | 47 | #include <linux/cpu_rmap.h> |
ad7d4eae | 48 | #include <linux/ptp_clock_kernel.h> |
c27a02cd YP |
49 | |
50 | #include <linux/mlx4/device.h> | |
51 | #include <linux/mlx4/qp.h> | |
52 | #include <linux/mlx4/cq.h> | |
53 | #include <linux/mlx4/srq.h> | |
54 | #include <linux/mlx4/doorbell.h> | |
e7c1c2c4 | 55 | #include <linux/mlx4/cmd.h> |
c27a02cd YP |
56 | |
57 | #include "en_port.h" | |
58 | ||
59 | #define DRV_NAME "mlx4_en" | |
6edf91da YP |
60 | #define DRV_VERSION "2.0" |
61 | #define DRV_RELDATE "Dec 2011" | |
c27a02cd | 62 | |
c27a02cd YP |
63 | #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) |
64 | ||
c27a02cd YP |
65 | /* |
66 | * Device constants | |
67 | */ | |
68 | ||
69 | ||
70 | #define MLX4_EN_PAGE_SHIFT 12 | |
71 | #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) | |
d317966b AV |
72 | #define DEF_RX_RINGS 16 |
73 | #define MAX_RX_RINGS 128 | |
1fb9876e | 74 | #define MIN_RX_RINGS 4 |
c27a02cd YP |
75 | #define TXBB_SIZE 64 |
76 | #define HEADROOM (2048 / TXBB_SIZE + 1) | |
c27a02cd YP |
77 | #define STAMP_STRIDE 64 |
78 | #define STAMP_DWORDS (STAMP_STRIDE / 4) | |
79 | #define STAMP_SHIFT 31 | |
80 | #define STAMP_VAL 0x7fffffff | |
81 | #define STATS_DELAY (HZ / 4) | |
b6c39bfc | 82 | #define SERVICE_TASK_DELAY (HZ / 4) |
82067281 | 83 | #define MAX_NUM_OF_FS_RULES 256 |
c27a02cd | 84 | |
1eb8c695 AV |
85 | #define MLX4_EN_FILTER_HASH_SHIFT 4 |
86 | #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 | |
87 | ||
c27a02cd YP |
88 | /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ |
89 | #define MAX_DESC_SIZE 512 | |
90 | #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) | |
91 | ||
92 | /* | |
93 | * OS related constants and tunables | |
94 | */ | |
95 | ||
96 | #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) | |
97 | ||
117980c4 TLSC |
98 | /* Use the maximum between 16384 and a single page */ |
99 | #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) | |
51151a16 ED |
100 | |
101 | #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER | |
c27a02cd | 102 | |
e6309cff | 103 | /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU |
c27a02cd YP |
104 | * and 4K allocations) */ |
105 | enum { | |
e6309cff ED |
106 | FRAG_SZ0 = 1536 - NET_IP_ALIGN, |
107 | FRAG_SZ1 = 4096, | |
c27a02cd YP |
108 | FRAG_SZ2 = 4096, |
109 | FRAG_SZ3 = MLX4_EN_ALLOC_SIZE | |
110 | }; | |
111 | #define MLX4_EN_MAX_RX_FRAGS 4 | |
112 | ||
bd531e36 YP |
113 | /* Maximum ring sizes */ |
114 | #define MLX4_EN_MAX_TX_SIZE 8192 | |
115 | #define MLX4_EN_MAX_RX_SIZE 8192 | |
116 | ||
4cce66cd | 117 | /* Minimum ring size for our page-allocation scheme to work */ |
c27a02cd YP |
118 | #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) |
119 | #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) | |
120 | ||
f813cad8 | 121 | #define MLX4_EN_SMALL_PKT_SIZE 64 |
bc6a4744 | 122 | #define MLX4_EN_MAX_TX_RING_P_UP 32 |
564c274c | 123 | #define MLX4_EN_NUM_UP 8 |
f813cad8 | 124 | #define MLX4_EN_DEF_TX_RING_SIZE 512 |
c27a02cd | 125 | #define MLX4_EN_DEF_RX_RING_SIZE 1024 |
d317966b AV |
126 | #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ |
127 | MLX4_EN_NUM_UP) | |
c27a02cd | 128 | |
3db36fb2 YP |
129 | /* Target number of packets to coalesce with interrupt moderation */ |
130 | #define MLX4_EN_RX_COAL_TARGET 44 | |
c27a02cd YP |
131 | #define MLX4_EN_RX_COAL_TIME 0x10 |
132 | ||
e22979d9 | 133 | #define MLX4_EN_TX_COAL_PKTS 16 |
ecfd2ce1 | 134 | #define MLX4_EN_TX_COAL_TIME 0x10 |
c27a02cd YP |
135 | |
136 | #define MLX4_EN_RX_RATE_LOW 400000 | |
137 | #define MLX4_EN_RX_COAL_TIME_LOW 0 | |
138 | #define MLX4_EN_RX_RATE_HIGH 450000 | |
139 | #define MLX4_EN_RX_COAL_TIME_HIGH 128 | |
140 | #define MLX4_EN_RX_SIZE_THRESH 1024 | |
141 | #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) | |
142 | #define MLX4_EN_SAMPLE_INTERVAL 0 | |
46afd0fb | 143 | #define MLX4_EN_AVG_PKT_SMALL 256 |
c27a02cd YP |
144 | |
145 | #define MLX4_EN_AUTO_CONF 0xffff | |
146 | ||
147 | #define MLX4_EN_DEF_RX_PAUSE 1 | |
148 | #define MLX4_EN_DEF_TX_PAUSE 1 | |
149 | ||
af901ca1 | 150 | /* Interval between successive polls in the Tx routine when polling is used |
c27a02cd YP |
151 | instead of interrupts (in per-core Tx rings) - should be power of 2 */ |
152 | #define MLX4_EN_TX_POLL_MODER 16 | |
153 | #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) | |
154 | ||
155 | #define ETH_LLC_SNAP_SIZE 8 | |
156 | ||
157 | #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) | |
158 | #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) | |
e7c1c2c4 | 159 | #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) |
c27a02cd YP |
160 | |
161 | #define MLX4_EN_MIN_MTU 46 | |
162 | #define ETH_BCAST 0xffffffffffffULL | |
163 | ||
e7c1c2c4 YP |
164 | #define MLX4_EN_LOOPBACK_RETRIES 5 |
165 | #define MLX4_EN_LOOPBACK_TIMEOUT 100 | |
166 | ||
c27a02cd YP |
167 | #ifdef MLX4_EN_PERF_STAT |
168 | /* Number of samples to 'average' */ | |
169 | #define AVG_SIZE 128 | |
170 | #define AVG_FACTOR 1024 | |
171 | #define NUM_PERF_STATS NUM_PERF_COUNTERS | |
172 | ||
173 | #define INC_PERF_COUNTER(cnt) (++(cnt)) | |
174 | #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) | |
175 | #define AVG_PERF_COUNTER(cnt, sample) \ | |
176 | ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) | |
177 | #define GET_PERF_COUNTER(cnt) (cnt) | |
178 | #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) | |
179 | ||
180 | #else | |
181 | ||
182 | #define NUM_PERF_STATS 0 | |
183 | #define INC_PERF_COUNTER(cnt) do {} while (0) | |
184 | #define ADD_PERF_COUNTER(cnt, add) do {} while (0) | |
185 | #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) | |
186 | #define GET_PERF_COUNTER(cnt) (0) | |
187 | #define GET_AVG_PERF_COUNTER(cnt) (0) | |
188 | #endif /* MLX4_EN_PERF_STAT */ | |
189 | ||
190 | /* | |
191 | * Configurables | |
192 | */ | |
193 | ||
194 | enum cq_type { | |
195 | RX = 0, | |
196 | TX = 1, | |
197 | }; | |
198 | ||
199 | ||
200 | /* | |
201 | * Useful macros | |
202 | */ | |
203 | #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) | |
204 | #define XNOR(x, y) (!(x) == !(y)) | |
c27a02cd YP |
205 | |
206 | ||
207 | struct mlx4_en_tx_info { | |
208 | struct sk_buff *skb; | |
209 | u32 nr_txbb; | |
5b263f53 | 210 | u32 nr_bytes; |
c27a02cd YP |
211 | u8 linear; |
212 | u8 data_offset; | |
41efea5a | 213 | u8 inl; |
ec693d47 | 214 | u8 ts_requested; |
c27a02cd YP |
215 | }; |
216 | ||
217 | ||
218 | #define MLX4_EN_BIT_DESC_OWN 0x80000000 | |
219 | #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) | |
220 | #define MLX4_EN_MEMTYPE_PAD 0x100 | |
221 | #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) | |
222 | ||
223 | ||
224 | struct mlx4_en_tx_desc { | |
225 | struct mlx4_wqe_ctrl_seg ctrl; | |
226 | union { | |
227 | struct mlx4_wqe_data_seg data; /* at least one data segment */ | |
228 | struct mlx4_wqe_lso_seg lso; | |
229 | struct mlx4_wqe_inline_seg inl; | |
230 | }; | |
231 | }; | |
232 | ||
233 | #define MLX4_EN_USE_SRQ 0x01000000 | |
234 | ||
725c8999 YP |
235 | #define MLX4_EN_CX3_LOW_ID 0x1000 |
236 | #define MLX4_EN_CX3_HIGH_ID 0x1005 | |
237 | ||
c27a02cd | 238 | struct mlx4_en_rx_alloc { |
51151a16 ED |
239 | struct page *page; |
240 | dma_addr_t dma; | |
70fbe079 AV |
241 | u32 page_offset; |
242 | u32 page_size; | |
c27a02cd YP |
243 | }; |
244 | ||
245 | struct mlx4_en_tx_ring { | |
246 | struct mlx4_hwq_resources wqres; | |
247 | u32 size ; /* number of TXBBs */ | |
248 | u32 size_mask; | |
249 | u16 stride; | |
250 | u16 cqn; /* index of port CQ associated with this ring */ | |
251 | u32 prod; | |
252 | u32 cons; | |
253 | u32 buf_size; | |
254 | u32 doorbell_qpn; | |
255 | void *buf; | |
256 | u16 poll_cnt; | |
c27a02cd YP |
257 | struct mlx4_en_tx_info *tx_info; |
258 | u8 *bounce_buf; | |
d03a68f8 IS |
259 | u8 queue_index; |
260 | cpumask_t affinity_mask; | |
c27a02cd YP |
261 | u32 last_nr_txbb; |
262 | struct mlx4_qp qp; | |
263 | struct mlx4_qp_context context; | |
264 | int qpn; | |
265 | enum mlx4_qp_state qp_state; | |
266 | struct mlx4_srq dummy; | |
267 | unsigned long bytes; | |
268 | unsigned long packets; | |
ad04378c | 269 | unsigned long tx_csum; |
87a5c389 YP |
270 | struct mlx4_bf bf; |
271 | bool bf_enabled; | |
5b263f53 | 272 | struct netdev_queue *tx_queue; |
ec693d47 | 273 | int hwtstamp_tx_type; |
c27a02cd YP |
274 | }; |
275 | ||
276 | struct mlx4_en_rx_desc { | |
c27a02cd YP |
277 | /* actual number of entries depends on rx ring stride */ |
278 | struct mlx4_wqe_data_seg data[0]; | |
279 | }; | |
280 | ||
281 | struct mlx4_en_rx_ring { | |
c27a02cd YP |
282 | struct mlx4_hwq_resources wqres; |
283 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; | |
c27a02cd YP |
284 | u32 size ; /* number of Rx descs*/ |
285 | u32 actual_size; | |
286 | u32 size_mask; | |
287 | u16 stride; | |
288 | u16 log_stride; | |
289 | u16 cqn; /* index of port CQ associated with this ring */ | |
290 | u32 prod; | |
291 | u32 cons; | |
292 | u32 buf_size; | |
4a5f4dd8 | 293 | u8 fcs_del; |
c27a02cd YP |
294 | void *buf; |
295 | void *rx_info; | |
296 | unsigned long bytes; | |
297 | unsigned long packets; | |
e0d1095a | 298 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8501841a AV |
299 | unsigned long yields; |
300 | unsigned long misses; | |
301 | unsigned long cleaned; | |
302 | #endif | |
ad04378c YP |
303 | unsigned long csum_ok; |
304 | unsigned long csum_none; | |
ec693d47 | 305 | int hwtstamp_rx_filter; |
c27a02cd YP |
306 | }; |
307 | ||
c27a02cd YP |
308 | struct mlx4_en_cq { |
309 | struct mlx4_cq mcq; | |
310 | struct mlx4_hwq_resources wqres; | |
311 | int ring; | |
312 | spinlock_t lock; | |
313 | struct net_device *dev; | |
314 | struct napi_struct napi; | |
c27a02cd YP |
315 | int size; |
316 | int buf_size; | |
317 | unsigned vector; | |
318 | enum cq_type is_tx; | |
319 | u16 moder_time; | |
320 | u16 moder_cnt; | |
c27a02cd YP |
321 | struct mlx4_cqe *buf; |
322 | #define MLX4_EN_OPCODE_ERROR 0x1e | |
9e77a2b8 | 323 | |
e0d1095a | 324 | #ifdef CONFIG_NET_RX_BUSY_POLL |
9e77a2b8 AV |
325 | unsigned int state; |
326 | #define MLX4_EN_CQ_STATE_IDLE 0 | |
327 | #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ | |
328 | #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ | |
329 | #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) | |
330 | #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ | |
331 | #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ | |
332 | #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) | |
333 | #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) | |
334 | spinlock_t poll_lock; /* protects from LLS/napi conflicts */ | |
e0d1095a | 335 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
c27a02cd YP |
336 | }; |
337 | ||
338 | struct mlx4_en_port_profile { | |
339 | u32 flags; | |
340 | u32 tx_ring_num; | |
341 | u32 rx_ring_num; | |
342 | u32 tx_ring_size; | |
343 | u32 rx_ring_size; | |
d53b93f2 YP |
344 | u8 rx_pause; |
345 | u8 rx_ppp; | |
346 | u8 tx_pause; | |
347 | u8 tx_ppp; | |
93d3e367 | 348 | int rss_rings; |
c27a02cd YP |
349 | }; |
350 | ||
351 | struct mlx4_en_profile { | |
352 | int rss_xor; | |
0533943c | 353 | int udp_rss; |
c27a02cd YP |
354 | u8 rss_mask; |
355 | u32 active_ports; | |
356 | u32 small_pkt_int; | |
c27a02cd | 357 | u8 no_reset; |
bc6a4744 | 358 | u8 num_tx_rings_p_up; |
c27a02cd YP |
359 | struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; |
360 | }; | |
361 | ||
362 | struct mlx4_en_dev { | |
363 | struct mlx4_dev *dev; | |
364 | struct pci_dev *pdev; | |
365 | struct mutex state_lock; | |
366 | struct net_device *pndev[MLX4_MAX_PORTS + 1]; | |
367 | u32 port_cnt; | |
368 | bool device_up; | |
369 | struct mlx4_en_profile profile; | |
370 | u32 LSO_support; | |
371 | struct workqueue_struct *workqueue; | |
372 | struct device *dma_device; | |
373 | void __iomem *uar_map; | |
374 | struct mlx4_uar priv_uar; | |
375 | struct mlx4_mr mr; | |
376 | u32 priv_pdn; | |
377 | spinlock_t uar_lock; | |
d7e1a487 | 378 | u8 mac_removed[MLX4_MAX_PORTS + 1]; |
ad7d4eae SB |
379 | rwlock_t clock_lock; |
380 | u32 nominal_c_mult; | |
ec693d47 AV |
381 | struct cyclecounter cycles; |
382 | struct timecounter clock; | |
383 | unsigned long last_overflow_check; | |
b6c39bfc | 384 | unsigned long overflow_period; |
ad7d4eae SB |
385 | struct ptp_clock *ptp_clock; |
386 | struct ptp_clock_info ptp_clock_info; | |
c27a02cd YP |
387 | }; |
388 | ||
389 | ||
390 | struct mlx4_en_rss_map { | |
c27a02cd | 391 | int base_qpn; |
b6b912e0 YP |
392 | struct mlx4_qp qps[MAX_RX_RINGS]; |
393 | enum mlx4_qp_state state[MAX_RX_RINGS]; | |
c27a02cd YP |
394 | struct mlx4_qp indir_qp; |
395 | enum mlx4_qp_state indir_state; | |
396 | }; | |
397 | ||
e7c1c2c4 YP |
398 | struct mlx4_en_port_state { |
399 | int link_state; | |
400 | int link_speed; | |
401 | int transciver; | |
402 | }; | |
403 | ||
c27a02cd YP |
404 | struct mlx4_en_pkt_stats { |
405 | unsigned long broadcast; | |
406 | unsigned long rx_prio[8]; | |
407 | unsigned long tx_prio[8]; | |
408 | #define NUM_PKT_STATS 17 | |
409 | }; | |
410 | ||
411 | struct mlx4_en_port_stats { | |
c27a02cd YP |
412 | unsigned long tso_packets; |
413 | unsigned long queue_stopped; | |
414 | unsigned long wake_queue; | |
415 | unsigned long tx_timeout; | |
416 | unsigned long rx_alloc_failed; | |
417 | unsigned long rx_chksum_good; | |
418 | unsigned long rx_chksum_none; | |
419 | unsigned long tx_chksum_offload; | |
d61702f1 | 420 | #define NUM_PORT_STATS 8 |
c27a02cd YP |
421 | }; |
422 | ||
423 | struct mlx4_en_perf_stats { | |
424 | u32 tx_poll; | |
425 | u64 tx_pktsz_avg; | |
426 | u32 inflight_avg; | |
427 | u16 tx_coal_avg; | |
428 | u16 rx_coal_avg; | |
429 | u32 napi_quota; | |
430 | #define NUM_PERF_COUNTERS 6 | |
431 | }; | |
432 | ||
6d199937 YP |
433 | enum mlx4_en_mclist_act { |
434 | MCLIST_NONE, | |
435 | MCLIST_REM, | |
436 | MCLIST_ADD, | |
437 | }; | |
438 | ||
439 | struct mlx4_en_mc_list { | |
440 | struct list_head list; | |
441 | enum mlx4_en_mclist_act action; | |
442 | u8 addr[ETH_ALEN]; | |
0ff1fb65 | 443 | u64 reg_id; |
837052d0 | 444 | u64 tunnel_reg_id; |
6d199937 YP |
445 | }; |
446 | ||
c27a02cd YP |
447 | struct mlx4_en_frag_info { |
448 | u16 frag_size; | |
449 | u16 frag_prefix_size; | |
450 | u16 frag_stride; | |
451 | u16 frag_align; | |
c27a02cd YP |
452 | }; |
453 | ||
564c274c AV |
454 | #ifdef CONFIG_MLX4_EN_DCB |
455 | /* Minimal TC BW - setting to 0 will block traffic */ | |
456 | #define MLX4_EN_BW_MIN 1 | |
457 | #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ | |
458 | ||
459 | #define MLX4_EN_TC_ETS 7 | |
460 | ||
461 | #endif | |
462 | ||
82067281 | 463 | struct ethtool_flow_id { |
0d256c0e | 464 | struct list_head list; |
82067281 HHZ |
465 | struct ethtool_rx_flow_spec flow_spec; |
466 | u64 id; | |
467 | }; | |
468 | ||
79aeaccd YB |
469 | enum { |
470 | MLX4_EN_FLAG_PROMISC = (1 << 0), | |
471 | MLX4_EN_FLAG_MC_PROMISC = (1 << 1), | |
472 | /* whether we need to enable hardware loopback by putting dmac | |
473 | * in Tx WQE | |
474 | */ | |
475 | MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), | |
476 | /* whether we need to drop packets that hardware loopback-ed */ | |
cc5387f7 YB |
477 | MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), |
478 | MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4) | |
79aeaccd YB |
479 | }; |
480 | ||
c07cb4b0 YB |
481 | #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) |
482 | #define MLX4_EN_MAC_HASH_IDX 5 | |
483 | ||
c27a02cd YP |
484 | struct mlx4_en_priv { |
485 | struct mlx4_en_dev *mdev; | |
486 | struct mlx4_en_port_profile *prof; | |
487 | struct net_device *dev; | |
f1b553fb | 488 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
c27a02cd YP |
489 | struct net_device_stats stats; |
490 | struct net_device_stats ret_stats; | |
e7c1c2c4 | 491 | struct mlx4_en_port_state port_state; |
c27a02cd | 492 | spinlock_t stats_lock; |
82067281 | 493 | struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; |
0d256c0e HHZ |
494 | /* To allow rules removal while port is going down */ |
495 | struct list_head ethtool_list; | |
c27a02cd | 496 | |
6b4d8d9f | 497 | unsigned long last_moder_packets[MAX_RX_RINGS]; |
c27a02cd | 498 | unsigned long last_moder_tx_packets; |
6b4d8d9f | 499 | unsigned long last_moder_bytes[MAX_RX_RINGS]; |
c27a02cd | 500 | unsigned long last_moder_jiffies; |
6b4d8d9f | 501 | int last_moder_time[MAX_RX_RINGS]; |
c27a02cd YP |
502 | u16 rx_usecs; |
503 | u16 rx_frames; | |
504 | u16 tx_usecs; | |
505 | u16 tx_frames; | |
506 | u32 pkt_rate_low; | |
507 | u16 rx_usecs_low; | |
508 | u32 pkt_rate_high; | |
509 | u16 rx_usecs_high; | |
510 | u16 sample_interval; | |
511 | u16 adaptive_rx_coal; | |
512 | u32 msg_enable; | |
e7c1c2c4 YP |
513 | u32 loopback_ok; |
514 | u32 validate_loopback; | |
c27a02cd YP |
515 | |
516 | struct mlx4_hwq_resources res; | |
517 | int link_state; | |
518 | int last_link_state; | |
519 | bool port_up; | |
520 | int port; | |
521 | int registered; | |
522 | int allocated; | |
523 | int stride; | |
6bbb6d99 | 524 | unsigned char prev_mac[ETH_ALEN + 2]; |
c27a02cd YP |
525 | int mac_index; |
526 | unsigned max_mtu; | |
527 | int base_qpn; | |
08ff3235 | 528 | int cqe_factor; |
c27a02cd YP |
529 | |
530 | struct mlx4_en_rss_map rss_map; | |
4ef2a435 | 531 | __be32 ctrl_flags; |
c27a02cd | 532 | u32 flags; |
d317966b | 533 | u8 num_tx_rings_p_up; |
c27a02cd YP |
534 | u32 tx_ring_num; |
535 | u32 rx_ring_num; | |
536 | u32 rx_skb_size; | |
537 | struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; | |
538 | u16 num_frags; | |
539 | u16 log_rx_info; | |
540 | ||
41d942d5 EE |
541 | struct mlx4_en_tx_ring **tx_ring; |
542 | struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; | |
543 | struct mlx4_en_cq **tx_cq; | |
544 | struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; | |
cabdc8ee | 545 | struct mlx4_qp drop_qp; |
0eb74fdd | 546 | struct work_struct rx_mode_task; |
c27a02cd YP |
547 | struct work_struct watchdog_task; |
548 | struct work_struct linkstate_task; | |
549 | struct delayed_work stats_task; | |
b6c39bfc | 550 | struct delayed_work service_task; |
c27a02cd YP |
551 | struct mlx4_en_perf_stats pstats; |
552 | struct mlx4_en_pkt_stats pkstats; | |
553 | struct mlx4_en_port_stats port_stats; | |
93ece0c1 | 554 | u64 stats_bitmap; |
6d199937 YP |
555 | struct list_head mc_list; |
556 | struct list_head curr_list; | |
0ff1fb65 | 557 | u64 broadcast_id; |
c27a02cd | 558 | struct mlx4_en_stat_out_mbox hw_stats; |
4c3eb3ca | 559 | int vids[128]; |
14c07b13 | 560 | bool wol; |
ebf8c9aa | 561 | struct device *ddev; |
044ca2a5 | 562 | int base_tx_qpn; |
c07cb4b0 | 563 | struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; |
ec693d47 | 564 | struct hwtstamp_config hwtstamp_config; |
564c274c AV |
565 | |
566 | #ifdef CONFIG_MLX4_EN_DCB | |
567 | struct ieee_ets ets; | |
109d2446 | 568 | u16 maxrate[IEEE_8021QAZ_MAX_TCS]; |
564c274c | 569 | #endif |
1eb8c695 AV |
570 | #ifdef CONFIG_RFS_ACCEL |
571 | spinlock_t filters_lock; | |
572 | int last_filter_id; | |
573 | struct list_head filters; | |
574 | struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; | |
575 | #endif | |
837052d0 | 576 | u64 tunnel_reg_id; |
14c07b13 YP |
577 | }; |
578 | ||
579 | enum mlx4_en_wol { | |
580 | MLX4_EN_WOL_MAGIC = (1ULL << 61), | |
581 | MLX4_EN_WOL_ENABLED = (1ULL << 62), | |
c27a02cd YP |
582 | }; |
583 | ||
16a10ffd | 584 | struct mlx4_mac_entry { |
c07cb4b0 | 585 | struct hlist_node hlist; |
16a10ffd YB |
586 | unsigned char mac[ETH_ALEN + 2]; |
587 | u64 reg_id; | |
c07cb4b0 | 588 | struct rcu_head rcu; |
16a10ffd YB |
589 | }; |
590 | ||
e0d1095a | 591 | #ifdef CONFIG_NET_RX_BUSY_POLL |
9e77a2b8 AV |
592 | static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) |
593 | { | |
594 | spin_lock_init(&cq->poll_lock); | |
595 | cq->state = MLX4_EN_CQ_STATE_IDLE; | |
596 | } | |
597 | ||
598 | /* called from the device poll rutine to get ownership of a cq */ | |
599 | static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) | |
600 | { | |
601 | int rc = true; | |
602 | spin_lock(&cq->poll_lock); | |
603 | if (cq->state & MLX4_CQ_LOCKED) { | |
604 | WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); | |
605 | cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; | |
606 | rc = false; | |
607 | } else | |
608 | /* we don't care if someone yielded */ | |
609 | cq->state = MLX4_EN_CQ_STATE_NAPI; | |
610 | spin_unlock(&cq->poll_lock); | |
611 | return rc; | |
612 | } | |
613 | ||
614 | /* returns true is someone tried to get the cq while napi had it */ | |
615 | static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) | |
616 | { | |
617 | int rc = false; | |
618 | spin_lock(&cq->poll_lock); | |
619 | WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | | |
620 | MLX4_EN_CQ_STATE_NAPI_YIELD)); | |
621 | ||
622 | if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) | |
623 | rc = true; | |
624 | cq->state = MLX4_EN_CQ_STATE_IDLE; | |
625 | spin_unlock(&cq->poll_lock); | |
626 | return rc; | |
627 | } | |
628 | ||
629 | /* called from mlx4_en_low_latency_poll() */ | |
630 | static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) | |
631 | { | |
632 | int rc = true; | |
633 | spin_lock_bh(&cq->poll_lock); | |
634 | if ((cq->state & MLX4_CQ_LOCKED)) { | |
635 | struct net_device *dev = cq->dev; | |
636 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
41d942d5 | 637 | struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; |
9e77a2b8 AV |
638 | |
639 | cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; | |
640 | rc = false; | |
8501841a | 641 | rx_ring->yields++; |
9e77a2b8 AV |
642 | } else |
643 | /* preserve yield marks */ | |
644 | cq->state |= MLX4_EN_CQ_STATE_POLL; | |
645 | spin_unlock_bh(&cq->poll_lock); | |
646 | return rc; | |
647 | } | |
648 | ||
649 | /* returns true if someone tried to get the cq while it was locked */ | |
650 | static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) | |
651 | { | |
652 | int rc = false; | |
653 | spin_lock_bh(&cq->poll_lock); | |
654 | WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); | |
655 | ||
656 | if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) | |
657 | rc = true; | |
658 | cq->state = MLX4_EN_CQ_STATE_IDLE; | |
659 | spin_unlock_bh(&cq->poll_lock); | |
660 | return rc; | |
661 | } | |
662 | ||
663 | /* true if a socket is polling, even if it did not get the lock */ | |
e6a76758 | 664 | static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) |
9e77a2b8 AV |
665 | { |
666 | WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); | |
667 | return cq->state & CQ_USER_PEND; | |
668 | } | |
669 | #else | |
670 | static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) | |
671 | { | |
672 | } | |
673 | ||
674 | static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) | |
675 | { | |
676 | return true; | |
677 | } | |
678 | ||
679 | static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) | |
680 | { | |
681 | return false; | |
682 | } | |
683 | ||
684 | static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) | |
685 | { | |
686 | return false; | |
687 | } | |
688 | ||
689 | static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) | |
690 | { | |
691 | return false; | |
692 | } | |
693 | ||
e6a76758 | 694 | static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) |
9e77a2b8 AV |
695 | { |
696 | return false; | |
697 | } | |
e0d1095a | 698 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
9e77a2b8 | 699 | |
0d9fdaa9 | 700 | #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) |
c27a02cd | 701 | |
79aeaccd YB |
702 | void mlx4_en_update_loopback_state(struct net_device *dev, |
703 | netdev_features_t features); | |
704 | ||
c27a02cd YP |
705 | void mlx4_en_destroy_netdev(struct net_device *dev); |
706 | int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, | |
707 | struct mlx4_en_port_profile *prof); | |
708 | ||
18cc42a3 | 709 | int mlx4_en_start_port(struct net_device *dev); |
3484aac1 | 710 | void mlx4_en_stop_port(struct net_device *dev, int detach); |
18cc42a3 | 711 | |
fe0af03c | 712 | void mlx4_en_free_resources(struct mlx4_en_priv *priv); |
18cc42a3 YP |
713 | int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); |
714 | ||
41d942d5 | 715 | int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, |
163561a4 | 716 | int entries, int ring, enum cq_type mode, int node); |
41d942d5 | 717 | void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); |
76532d0c AG |
718 | int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, |
719 | int cq_idx); | |
c27a02cd YP |
720 | void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); |
721 | int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); | |
722 | int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); | |
723 | ||
c27a02cd | 724 | void mlx4_en_tx_irq(struct mlx4_cq *mcq); |
f663dd9a | 725 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 726 | void *accel_priv, select_queue_fallback_t fallback); |
61357325 | 727 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); |
c27a02cd | 728 | |
41d942d5 EE |
729 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
730 | struct mlx4_en_tx_ring **pring, | |
d03a68f8 IS |
731 | int qpn, u32 size, u16 stride, |
732 | int node, int queue_index); | |
41d942d5 EE |
733 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, |
734 | struct mlx4_en_tx_ring **pring); | |
c27a02cd YP |
735 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, |
736 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 737 | int cq, int user_prio); |
c27a02cd YP |
738 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, |
739 | struct mlx4_en_tx_ring *ring); | |
740 | ||
741 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 742 | struct mlx4_en_rx_ring **pring, |
163561a4 | 743 | u32 size, u16 stride, int node); |
c27a02cd | 744 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 745 | struct mlx4_en_rx_ring **pring, |
68355f71 | 746 | u32 size, u16 stride); |
c27a02cd YP |
747 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); |
748 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
749 | struct mlx4_en_rx_ring *ring); | |
750 | int mlx4_en_process_rx_cq(struct net_device *dev, | |
751 | struct mlx4_en_cq *cq, | |
752 | int budget); | |
753 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); | |
0276a330 | 754 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); |
c27a02cd | 755 | void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, |
0e98b523 AV |
756 | int is_tx, int rss, int qpn, int cqn, int user_prio, |
757 | struct mlx4_qp_context *context); | |
966508f7 | 758 | void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); |
c27a02cd YP |
759 | int mlx4_en_map_buffer(struct mlx4_buf *buf); |
760 | void mlx4_en_unmap_buffer(struct mlx4_buf *buf); | |
761 | ||
762 | void mlx4_en_calc_rx_buf(struct net_device *dev); | |
c27a02cd YP |
763 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); |
764 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); | |
cabdc8ee HHZ |
765 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); |
766 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); | |
c27a02cd | 767 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); |
c27a02cd YP |
768 | void mlx4_en_rx_irq(struct mlx4_cq *mcq); |
769 | ||
770 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
f1b553fb | 771 | int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); |
c27a02cd YP |
772 | |
773 | int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); | |
e7c1c2c4 YP |
774 | int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); |
775 | ||
564c274c AV |
776 | #ifdef CONFIG_MLX4_EN_DCB |
777 | extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; | |
540b3a39 | 778 | extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; |
564c274c AV |
779 | #endif |
780 | ||
d317966b AV |
781 | int mlx4_en_setup_tc(struct net_device *dev, u8 up); |
782 | ||
1eb8c695 | 783 | #ifdef CONFIG_RFS_ACCEL |
41d942d5 | 784 | void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); |
1eb8c695 AV |
785 | #endif |
786 | ||
e7c1c2c4 YP |
787 | #define MLX4_EN_NUM_SELF_TEST 5 |
788 | void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); | |
789 | u64 mlx4_en_mac_to_u64(u8 *addr); | |
b6c39bfc | 790 | void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); |
c27a02cd YP |
791 | |
792 | /* | |
ec693d47 AV |
793 | * Functions for time stamping |
794 | */ | |
795 | u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); | |
796 | void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, | |
797 | struct skb_shared_hwtstamps *hwts, | |
798 | u64 timestamp); | |
799 | void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); | |
ad7d4eae | 800 | void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); |
ec693d47 AV |
801 | int mlx4_en_timestamp_config(struct net_device *dev, |
802 | int tx_type, | |
803 | int rx_filter); | |
804 | ||
805 | /* Globals | |
c27a02cd YP |
806 | */ |
807 | extern const struct ethtool_ops mlx4_en_ethtool_ops; | |
0a645e80 JP |
808 | |
809 | ||
810 | ||
811 | /* | |
812 | * printk / logging functions | |
813 | */ | |
814 | ||
b9075fa9 | 815 | __printf(3, 4) |
0a645e80 | 816 | int en_print(const char *level, const struct mlx4_en_priv *priv, |
b9075fa9 | 817 | const char *format, ...); |
0a645e80 JP |
818 | |
819 | #define en_dbg(mlevel, priv, format, arg...) \ | |
820 | do { \ | |
821 | if (NETIF_MSG_##mlevel & priv->msg_enable) \ | |
822 | en_print(KERN_DEBUG, priv, format, ##arg); \ | |
823 | } while (0) | |
824 | #define en_warn(priv, format, arg...) \ | |
825 | en_print(KERN_WARNING, priv, format, ##arg) | |
826 | #define en_err(priv, format, arg...) \ | |
827 | en_print(KERN_ERR, priv, format, ##arg) | |
e5cc44b2 YP |
828 | #define en_info(priv, format, arg...) \ |
829 | en_print(KERN_INFO, priv, format, ## arg) | |
0a645e80 JP |
830 | |
831 | #define mlx4_err(mdev, format, arg...) \ | |
832 | pr_err("%s %s: " format, DRV_NAME, \ | |
833 | dev_name(&mdev->pdev->dev), ##arg) | |
834 | #define mlx4_info(mdev, format, arg...) \ | |
835 | pr_info("%s %s: " format, DRV_NAME, \ | |
836 | dev_name(&mdev->pdev->dev), ##arg) | |
837 | #define mlx4_warn(mdev, format, arg...) \ | |
838 | pr_warning("%s %s: " format, DRV_NAME, \ | |
839 | dev_name(&mdev->pdev->dev), ##arg) | |
840 | ||
c27a02cd | 841 | #endif |