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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
225c7b1f | 35 | #include <linux/errno.h> |
ee40fa06 | 36 | #include <linux/export.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
ea51b377 | 38 | #include <linux/kernel.h> |
89dd86db | 39 | #include <linux/vmalloc.h> |
225c7b1f RD |
40 | |
41 | #include <linux/mlx4/cmd.h> | |
42 | ||
43 | #include "mlx4.h" | |
44 | #include "icm.h" | |
45 | ||
225c7b1f RD |
46 | static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order) |
47 | { | |
48 | int o; | |
49 | int m; | |
50 | u32 seg; | |
51 | ||
52 | spin_lock(&buddy->lock); | |
53 | ||
e4044cfc RD |
54 | for (o = order; o <= buddy->max_order; ++o) |
55 | if (buddy->num_free[o]) { | |
56 | m = 1 << (buddy->max_order - o); | |
57 | seg = find_first_bit(buddy->bits[o], m); | |
58 | if (seg < m) | |
59 | goto found; | |
60 | } | |
225c7b1f RD |
61 | |
62 | spin_unlock(&buddy->lock); | |
63 | return -1; | |
64 | ||
65 | found: | |
66 | clear_bit(seg, buddy->bits[o]); | |
e4044cfc | 67 | --buddy->num_free[o]; |
225c7b1f RD |
68 | |
69 | while (o > order) { | |
70 | --o; | |
71 | seg <<= 1; | |
72 | set_bit(seg ^ 1, buddy->bits[o]); | |
e4044cfc | 73 | ++buddy->num_free[o]; |
225c7b1f RD |
74 | } |
75 | ||
76 | spin_unlock(&buddy->lock); | |
77 | ||
78 | seg <<= order; | |
79 | ||
80 | return seg; | |
81 | } | |
82 | ||
83 | static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order) | |
84 | { | |
85 | seg >>= order; | |
86 | ||
87 | spin_lock(&buddy->lock); | |
88 | ||
89 | while (test_bit(seg ^ 1, buddy->bits[order])) { | |
90 | clear_bit(seg ^ 1, buddy->bits[order]); | |
e4044cfc | 91 | --buddy->num_free[order]; |
225c7b1f RD |
92 | seg >>= 1; |
93 | ++order; | |
94 | } | |
95 | ||
96 | set_bit(seg, buddy->bits[order]); | |
e4044cfc | 97 | ++buddy->num_free[order]; |
225c7b1f RD |
98 | |
99 | spin_unlock(&buddy->lock); | |
100 | } | |
101 | ||
e8f9b2ed | 102 | static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order) |
225c7b1f RD |
103 | { |
104 | int i, s; | |
105 | ||
106 | buddy->max_order = max_order; | |
107 | spin_lock_init(&buddy->lock); | |
108 | ||
96f17d59 | 109 | buddy->bits = kcalloc(buddy->max_order + 1, sizeof (long *), |
225c7b1f | 110 | GFP_KERNEL); |
a8312755 | 111 | buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free, |
e4044cfc RD |
112 | GFP_KERNEL); |
113 | if (!buddy->bits || !buddy->num_free) | |
225c7b1f RD |
114 | goto err_out; |
115 | ||
116 | for (i = 0; i <= buddy->max_order; ++i) { | |
117 | s = BITS_TO_LONGS(1 << (buddy->max_order - i)); | |
96f17d59 | 118 | buddy->bits[i] = kcalloc(s, sizeof (long), GFP_KERNEL | __GFP_NOWARN); |
89dd86db | 119 | if (!buddy->bits[i]) { |
96f17d59 | 120 | buddy->bits[i] = vzalloc(s * sizeof(long)); |
89dd86db YH |
121 | if (!buddy->bits[i]) |
122 | goto err_out_free; | |
123 | } | |
225c7b1f RD |
124 | } |
125 | ||
126 | set_bit(0, buddy->bits[buddy->max_order]); | |
e4044cfc | 127 | buddy->num_free[buddy->max_order] = 1; |
225c7b1f RD |
128 | |
129 | return 0; | |
130 | ||
131 | err_out_free: | |
132 | for (i = 0; i <= buddy->max_order; ++i) | |
914efb02 | 133 | kvfree(buddy->bits[i]); |
225c7b1f | 134 | |
e4044cfc | 135 | err_out: |
225c7b1f | 136 | kfree(buddy->bits); |
e4044cfc | 137 | kfree(buddy->num_free); |
225c7b1f | 138 | |
225c7b1f RD |
139 | return -ENOMEM; |
140 | } | |
141 | ||
142 | static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy) | |
143 | { | |
144 | int i; | |
145 | ||
146 | for (i = 0; i <= buddy->max_order; ++i) | |
914efb02 | 147 | kvfree(buddy->bits[i]); |
225c7b1f RD |
148 | |
149 | kfree(buddy->bits); | |
e4044cfc | 150 | kfree(buddy->num_free); |
225c7b1f RD |
151 | } |
152 | ||
c82e9aa0 | 153 | u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order) |
225c7b1f RD |
154 | { |
155 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
156 | u32 seg; | |
2b8fb286 MA |
157 | int seg_order; |
158 | u32 offset; | |
225c7b1f | 159 | |
2b8fb286 MA |
160 | seg_order = max_t(int, order - log_mtts_per_seg, 0); |
161 | ||
162 | seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, seg_order); | |
225c7b1f RD |
163 | if (seg == -1) |
164 | return -1; | |
165 | ||
2b8fb286 MA |
166 | offset = seg * (1 << log_mtts_per_seg); |
167 | ||
168 | if (mlx4_table_get_range(dev, &mr_table->mtt_table, offset, | |
169 | offset + (1 << order) - 1)) { | |
170 | mlx4_buddy_free(&mr_table->mtt_buddy, seg, seg_order); | |
225c7b1f RD |
171 | return -1; |
172 | } | |
173 | ||
2b8fb286 | 174 | return offset; |
225c7b1f RD |
175 | } |
176 | ||
ea51b377 JM |
177 | static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order) |
178 | { | |
e7dbeba8 | 179 | u64 in_param = 0; |
ea51b377 JM |
180 | u64 out_param; |
181 | int err; | |
182 | ||
183 | if (mlx4_is_mfunc(dev)) { | |
184 | set_param_l(&in_param, order); | |
185 | err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT, | |
186 | RES_OP_RESERVE_AND_MAP, | |
187 | MLX4_CMD_ALLOC_RES, | |
188 | MLX4_CMD_TIME_CLASS_A, | |
189 | MLX4_CMD_WRAPPED); | |
190 | if (err) | |
191 | return -1; | |
192 | return get_param_l(&out_param); | |
193 | } | |
194 | return __mlx4_alloc_mtt_range(dev, order); | |
195 | } | |
196 | ||
225c7b1f RD |
197 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, |
198 | struct mlx4_mtt *mtt) | |
199 | { | |
200 | int i; | |
201 | ||
202 | if (!npages) { | |
203 | mtt->order = -1; | |
204 | mtt->page_shift = MLX4_ICM_PAGE_SHIFT; | |
205 | return 0; | |
206 | } else | |
207 | mtt->page_shift = page_shift; | |
208 | ||
2b8fb286 | 209 | for (mtt->order = 0, i = 1; i < npages; i <<= 1) |
225c7b1f RD |
210 | ++mtt->order; |
211 | ||
2b8fb286 MA |
212 | mtt->offset = mlx4_alloc_mtt_range(dev, mtt->order); |
213 | if (mtt->offset == -1) | |
225c7b1f RD |
214 | return -ENOMEM; |
215 | ||
216 | return 0; | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(mlx4_mtt_init); | |
219 | ||
2b8fb286 | 220 | void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order) |
225c7b1f | 221 | { |
2b8fb286 MA |
222 | u32 first_seg; |
223 | int seg_order; | |
225c7b1f RD |
224 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; |
225 | ||
2b8fb286 MA |
226 | seg_order = max_t(int, order - log_mtts_per_seg, 0); |
227 | first_seg = offset / (1 << log_mtts_per_seg); | |
228 | ||
229 | mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, seg_order); | |
1e27ca69 MA |
230 | mlx4_table_put_range(dev, &mr_table->mtt_table, offset, |
231 | offset + (1 << order) - 1); | |
ea51b377 JM |
232 | } |
233 | ||
2b8fb286 | 234 | static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order) |
ea51b377 | 235 | { |
e7dbeba8 | 236 | u64 in_param = 0; |
ea51b377 JM |
237 | int err; |
238 | ||
239 | if (mlx4_is_mfunc(dev)) { | |
2b8fb286 | 240 | set_param_l(&in_param, offset); |
ea51b377 JM |
241 | set_param_h(&in_param, order); |
242 | err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP, | |
243 | MLX4_CMD_FREE_RES, | |
244 | MLX4_CMD_TIME_CLASS_A, | |
245 | MLX4_CMD_WRAPPED); | |
246 | if (err) | |
1a91de28 JP |
247 | mlx4_warn(dev, "Failed to free mtt range at:%d order:%d\n", |
248 | offset, order); | |
ea51b377 JM |
249 | return; |
250 | } | |
2b8fb286 | 251 | __mlx4_free_mtt_range(dev, offset, order); |
ea51b377 JM |
252 | } |
253 | ||
254 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt) | |
255 | { | |
225c7b1f RD |
256 | if (mtt->order < 0) |
257 | return; | |
258 | ||
2b8fb286 | 259 | mlx4_free_mtt_range(dev, mtt->offset, mtt->order); |
225c7b1f RD |
260 | } |
261 | EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup); | |
262 | ||
263 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt) | |
264 | { | |
2b8fb286 | 265 | return (u64) mtt->offset * dev->caps.mtt_entry_sz; |
225c7b1f RD |
266 | } |
267 | EXPORT_SYMBOL_GPL(mlx4_mtt_addr); | |
268 | ||
269 | static u32 hw_index_to_key(u32 ind) | |
270 | { | |
271 | return (ind >> 24) | (ind << 8); | |
272 | } | |
273 | ||
274 | static u32 key_to_hw_index(u32 key) | |
275 | { | |
276 | return (key << 24) | (key >> 8); | |
277 | } | |
278 | ||
279 | static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, | |
280 | int mpt_index) | |
281 | { | |
eb41049f | 282 | return mlx4_cmd(dev, mailbox->dma, mpt_index, |
ea51b377 JM |
283 | 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B, |
284 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
285 | } |
286 | ||
287 | static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, | |
288 | int mpt_index) | |
289 | { | |
290 | return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, | |
f9baff50 JM |
291 | !mailbox, MLX4_CMD_HW2SW_MPT, |
292 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
225c7b1f RD |
293 | } |
294 | ||
4ff0acca | 295 | /* Must protect against concurrent access */ |
e630664c MB |
296 | int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
297 | struct mlx4_mpt_entry ***mpt_entry) | |
298 | { | |
299 | int err; | |
300 | int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); | |
301 | struct mlx4_cmd_mailbox *mailbox = NULL; | |
302 | ||
e630664c MB |
303 | if (mmr->enabled != MLX4_MPT_EN_HW) |
304 | return -EINVAL; | |
305 | ||
306 | err = mlx4_HW2SW_MPT(dev, NULL, key); | |
e630664c MB |
307 | if (err) { |
308 | mlx4_warn(dev, "HW2SW_MPT failed (%d).", err); | |
309 | mlx4_warn(dev, "Most likely the MR has MWs bound to it.\n"); | |
310 | return err; | |
311 | } | |
312 | ||
313 | mmr->enabled = MLX4_MPT_EN_SW; | |
314 | ||
315 | if (!mlx4_is_mfunc(dev)) { | |
316 | **mpt_entry = mlx4_table_find( | |
317 | &mlx4_priv(dev)->mr_table.dmpt_table, | |
318 | key, NULL); | |
319 | } else { | |
320 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
321 | if (IS_ERR_OR_NULL(mailbox)) | |
322 | return PTR_ERR(mailbox); | |
323 | ||
324 | err = mlx4_cmd_box(dev, 0, mailbox->dma, key, | |
325 | 0, MLX4_CMD_QUERY_MPT, | |
326 | MLX4_CMD_TIME_CLASS_B, | |
327 | MLX4_CMD_WRAPPED); | |
e630664c MB |
328 | if (err) |
329 | goto free_mailbox; | |
330 | ||
331 | *mpt_entry = (struct mlx4_mpt_entry **)&mailbox->buf; | |
332 | } | |
333 | ||
334 | if (!(*mpt_entry) || !(**mpt_entry)) { | |
335 | err = -ENOMEM; | |
336 | goto free_mailbox; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | ||
341 | free_mailbox: | |
342 | mlx4_free_cmd_mailbox(dev, mailbox); | |
343 | return err; | |
344 | } | |
345 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_get_mpt); | |
346 | ||
347 | int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, | |
348 | struct mlx4_mpt_entry **mpt_entry) | |
349 | { | |
350 | int err; | |
351 | ||
352 | if (!mlx4_is_mfunc(dev)) { | |
353 | /* Make sure any changes to this entry are flushed */ | |
354 | wmb(); | |
355 | ||
356 | *(u8 *)(*mpt_entry) = MLX4_MPT_STATUS_HW; | |
357 | ||
358 | /* Make sure the new status is written */ | |
359 | wmb(); | |
360 | ||
361 | err = mlx4_SYNC_TPT(dev); | |
362 | } else { | |
363 | int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); | |
364 | ||
365 | struct mlx4_cmd_mailbox *mailbox = | |
366 | container_of((void *)mpt_entry, struct mlx4_cmd_mailbox, | |
367 | buf); | |
368 | ||
369 | err = mlx4_SW2HW_MPT(dev, mailbox, key); | |
370 | } | |
371 | ||
4ff0acca MB |
372 | if (!err) { |
373 | mmr->pd = be32_to_cpu((*mpt_entry)->pd_flags) & MLX4_MPT_PD_MASK; | |
e630664c | 374 | mmr->enabled = MLX4_MPT_EN_HW; |
4ff0acca | 375 | } |
e630664c MB |
376 | return err; |
377 | } | |
378 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_write_mpt); | |
379 | ||
380 | void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, | |
381 | struct mlx4_mpt_entry **mpt_entry) | |
382 | { | |
383 | if (mlx4_is_mfunc(dev)) { | |
384 | struct mlx4_cmd_mailbox *mailbox = | |
385 | container_of((void *)mpt_entry, struct mlx4_cmd_mailbox, | |
386 | buf); | |
387 | mlx4_free_cmd_mailbox(dev, mailbox); | |
388 | } | |
389 | } | |
390 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_put_mpt); | |
391 | ||
392 | int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, | |
393 | u32 pdn) | |
394 | { | |
4ff0acca | 395 | u32 pd_flags = be32_to_cpu(mpt_entry->pd_flags) & ~MLX4_MPT_PD_MASK; |
e630664c MB |
396 | /* The wrapper function will put the slave's id here */ |
397 | if (mlx4_is_mfunc(dev)) | |
398 | pd_flags &= ~MLX4_MPT_PD_VF_MASK; | |
4ff0acca MB |
399 | |
400 | mpt_entry->pd_flags = cpu_to_be32(pd_flags | | |
e630664c MB |
401 | (pdn & MLX4_MPT_PD_MASK) |
402 | | MLX4_MPT_PD_FLAG_EN_INV); | |
403 | return 0; | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_pd); | |
406 | ||
407 | int mlx4_mr_hw_change_access(struct mlx4_dev *dev, | |
408 | struct mlx4_mpt_entry *mpt_entry, | |
409 | u32 access) | |
410 | { | |
411 | u32 flags = (be32_to_cpu(mpt_entry->flags) & ~MLX4_PERM_MASK) | | |
412 | (access & MLX4_PERM_MASK); | |
413 | ||
414 | mpt_entry->flags = cpu_to_be32(flags); | |
415 | return 0; | |
416 | } | |
417 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_access); | |
418 | ||
66431a7d | 419 | static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, |
ea51b377 JM |
420 | u64 iova, u64 size, u32 access, int npages, |
421 | int page_shift, struct mlx4_mr *mr) | |
422 | { | |
225c7b1f RD |
423 | mr->iova = iova; |
424 | mr->size = size; | |
425 | mr->pd = pd; | |
426 | mr->access = access; | |
b20e519a | 427 | mr->enabled = MLX4_MPT_DISABLED; |
ea51b377 JM |
428 | mr->key = hw_index_to_key(mridx); |
429 | ||
430 | return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); | |
431 | } | |
ea51b377 JM |
432 | |
433 | static int mlx4_WRITE_MTT(struct mlx4_dev *dev, | |
434 | struct mlx4_cmd_mailbox *mailbox, | |
435 | int num_entries) | |
436 | { | |
437 | return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT, | |
438 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
439 | } | |
440 | ||
b20e519a | 441 | int __mlx4_mpt_reserve(struct mlx4_dev *dev) |
ea51b377 JM |
442 | { |
443 | struct mlx4_priv *priv = mlx4_priv(dev); | |
444 | ||
445 | return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap); | |
446 | } | |
225c7b1f | 447 | |
b20e519a | 448 | static int mlx4_mpt_reserve(struct mlx4_dev *dev) |
ea51b377 JM |
449 | { |
450 | u64 out_param; | |
451 | ||
452 | if (mlx4_is_mfunc(dev)) { | |
453 | if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE, | |
454 | MLX4_CMD_ALLOC_RES, | |
455 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED)) | |
456 | return -1; | |
457 | return get_param_l(&out_param); | |
458 | } | |
b20e519a | 459 | return __mlx4_mpt_reserve(dev); |
ea51b377 JM |
460 | } |
461 | ||
b20e519a | 462 | void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index) |
ea51b377 JM |
463 | { |
464 | struct mlx4_priv *priv = mlx4_priv(dev); | |
465 | ||
7c6d74d2 | 466 | mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index, MLX4_NO_RR); |
ea51b377 JM |
467 | } |
468 | ||
b20e519a | 469 | static void mlx4_mpt_release(struct mlx4_dev *dev, u32 index) |
ea51b377 | 470 | { |
e7dbeba8 | 471 | u64 in_param = 0; |
ea51b377 JM |
472 | |
473 | if (mlx4_is_mfunc(dev)) { | |
474 | set_param_l(&in_param, index); | |
475 | if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE, | |
476 | MLX4_CMD_FREE_RES, | |
477 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED)) | |
478 | mlx4_warn(dev, "Failed to release mr index:%d\n", | |
479 | index); | |
480 | return; | |
481 | } | |
b20e519a | 482 | __mlx4_mpt_release(dev, index); |
ea51b377 JM |
483 | } |
484 | ||
40f2287b | 485 | int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp) |
ea51b377 JM |
486 | { |
487 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
488 | ||
40f2287b | 489 | return mlx4_table_get(dev, &mr_table->dmpt_table, index, gfp); |
ea51b377 JM |
490 | } |
491 | ||
40f2287b | 492 | static int mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp) |
ea51b377 | 493 | { |
e7dbeba8 | 494 | u64 param = 0; |
ea51b377 JM |
495 | |
496 | if (mlx4_is_mfunc(dev)) { | |
497 | set_param_l(¶m, index); | |
498 | return mlx4_cmd_imm(dev, param, ¶m, RES_MPT, RES_OP_MAP_ICM, | |
499 | MLX4_CMD_ALLOC_RES, | |
500 | MLX4_CMD_TIME_CLASS_A, | |
501 | MLX4_CMD_WRAPPED); | |
502 | } | |
40f2287b | 503 | return __mlx4_mpt_alloc_icm(dev, index, gfp); |
ea51b377 JM |
504 | } |
505 | ||
b20e519a | 506 | void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 JM |
507 | { |
508 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
509 | ||
510 | mlx4_table_put(dev, &mr_table->dmpt_table, index); | |
511 | } | |
512 | ||
b20e519a | 513 | static void mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 | 514 | { |
e7dbeba8 | 515 | u64 in_param = 0; |
ea51b377 JM |
516 | |
517 | if (mlx4_is_mfunc(dev)) { | |
518 | set_param_l(&in_param, index); | |
519 | if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM, | |
520 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
521 | MLX4_CMD_WRAPPED)) | |
522 | mlx4_warn(dev, "Failed to free icm of mr index:%d\n", | |
523 | index); | |
524 | return; | |
525 | } | |
b20e519a | 526 | return __mlx4_mpt_free_icm(dev, index); |
ea51b377 JM |
527 | } |
528 | ||
529 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
530 | int npages, int page_shift, struct mlx4_mr *mr) | |
531 | { | |
532 | u32 index; | |
533 | int err; | |
534 | ||
b20e519a | 535 | index = mlx4_mpt_reserve(dev); |
ea51b377 JM |
536 | if (index == -1) |
537 | return -ENOMEM; | |
538 | ||
539 | err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size, | |
540 | access, npages, page_shift, mr); | |
225c7b1f | 541 | if (err) |
b20e519a | 542 | mlx4_mpt_release(dev, index); |
225c7b1f | 543 | |
225c7b1f RD |
544 | return err; |
545 | } | |
546 | EXPORT_SYMBOL_GPL(mlx4_mr_alloc); | |
547 | ||
61083720 | 548 | static int mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr) |
225c7b1f | 549 | { |
225c7b1f RD |
550 | int err; |
551 | ||
b20e519a | 552 | if (mr->enabled == MLX4_MPT_EN_HW) { |
225c7b1f RD |
553 | err = mlx4_HW2SW_MPT(dev, NULL, |
554 | key_to_hw_index(mr->key) & | |
555 | (dev->caps.num_mpts - 1)); | |
61083720 | 556 | if (err) { |
1a91de28 JP |
557 | mlx4_warn(dev, "HW2SW_MPT failed (%d), MR has MWs bound to it\n", |
558 | err); | |
61083720 SM |
559 | return err; |
560 | } | |
225c7b1f | 561 | |
b20e519a | 562 | mr->enabled = MLX4_MPT_EN_SW; |
ea51b377 | 563 | } |
225c7b1f | 564 | mlx4_mtt_cleanup(dev, &mr->mtt); |
61083720 SM |
565 | |
566 | return 0; | |
ea51b377 | 567 | } |
ea51b377 | 568 | |
61083720 | 569 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr) |
ea51b377 | 570 | { |
61083720 SM |
571 | int ret; |
572 | ||
573 | ret = mlx4_mr_free_reserved(dev, mr); | |
574 | if (ret) | |
575 | return ret; | |
ea51b377 | 576 | if (mr->enabled) |
b20e519a SM |
577 | mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key)); |
578 | mlx4_mpt_release(dev, key_to_hw_index(mr->key)); | |
61083720 SM |
579 | |
580 | return 0; | |
225c7b1f RD |
581 | } |
582 | EXPORT_SYMBOL_GPL(mlx4_mr_free); | |
583 | ||
e630664c MB |
584 | void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr) |
585 | { | |
586 | mlx4_mtt_cleanup(dev, &mr->mtt); | |
587 | } | |
588 | EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_cleanup); | |
589 | ||
590 | int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, | |
591 | u64 iova, u64 size, int npages, | |
592 | int page_shift, struct mlx4_mpt_entry *mpt_entry) | |
593 | { | |
594 | int err; | |
595 | ||
4ff0acca MB |
596 | mpt_entry->start = cpu_to_be64(iova); |
597 | mpt_entry->length = cpu_to_be64(size); | |
598 | mpt_entry->entity_size = cpu_to_be32(page_shift); | |
e630664c MB |
599 | |
600 | err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); | |
601 | if (err) | |
602 | return err; | |
603 | ||
4ff0acca MB |
604 | mpt_entry->pd_flags &= cpu_to_be32(MLX4_MPT_PD_MASK | |
605 | MLX4_MPT_PD_FLAG_EN_INV); | |
606 | mpt_entry->flags &= cpu_to_be32(MLX4_MPT_FLAG_FREE | | |
607 | MLX4_MPT_FLAG_SW_OWNS); | |
e630664c MB |
608 | if (mr->mtt.order < 0) { |
609 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL); | |
610 | mpt_entry->mtt_addr = 0; | |
611 | } else { | |
612 | mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev, | |
613 | &mr->mtt)); | |
614 | if (mr->mtt.page_shift == 0) | |
615 | mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order); | |
616 | } | |
4ff0acca MB |
617 | if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) { |
618 | /* fast register MR in free state */ | |
619 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
620 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | | |
621 | MLX4_MPT_PD_FLAG_RAE); | |
622 | } else { | |
623 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); | |
624 | } | |
e630664c MB |
625 | mr->enabled = MLX4_MPT_EN_SW; |
626 | ||
627 | return 0; | |
628 | } | |
629 | EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_write); | |
630 | ||
225c7b1f RD |
631 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr) |
632 | { | |
225c7b1f RD |
633 | struct mlx4_cmd_mailbox *mailbox; |
634 | struct mlx4_mpt_entry *mpt_entry; | |
635 | int err; | |
636 | ||
40f2287b | 637 | err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mr->key), GFP_KERNEL); |
225c7b1f RD |
638 | if (err) |
639 | return err; | |
640 | ||
641 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
642 | if (IS_ERR(mailbox)) { | |
643 | err = PTR_ERR(mailbox); | |
644 | goto err_table; | |
645 | } | |
646 | mpt_entry = mailbox->buf; | |
95d04f07 | 647 | mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO | |
225c7b1f RD |
648 | MLX4_MPT_FLAG_REGION | |
649 | mr->access); | |
225c7b1f RD |
650 | |
651 | mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key)); | |
95d04f07 | 652 | mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV); |
225c7b1f RD |
653 | mpt_entry->start = cpu_to_be64(mr->iova); |
654 | mpt_entry->length = cpu_to_be64(mr->size); | |
655 | mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift); | |
95d04f07 | 656 | |
b2d9308a JM |
657 | if (mr->mtt.order < 0) { |
658 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL); | |
2b8fb286 | 659 | mpt_entry->mtt_addr = 0; |
95d04f07 | 660 | } else { |
2b8fb286 MA |
661 | mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev, |
662 | &mr->mtt)); | |
95d04f07 RD |
663 | } |
664 | ||
665 | if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) { | |
666 | /* fast register MR in free state */ | |
667 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
c9257433 VS |
668 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | |
669 | MLX4_MPT_PD_FLAG_RAE); | |
2b8fb286 | 670 | mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order); |
95d04f07 RD |
671 | } else { |
672 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); | |
673 | } | |
225c7b1f RD |
674 | |
675 | err = mlx4_SW2HW_MPT(dev, mailbox, | |
676 | key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1)); | |
677 | if (err) { | |
678 | mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err); | |
679 | goto err_cmd; | |
680 | } | |
b20e519a | 681 | mr->enabled = MLX4_MPT_EN_HW; |
225c7b1f RD |
682 | |
683 | mlx4_free_cmd_mailbox(dev, mailbox); | |
684 | ||
685 | return 0; | |
686 | ||
687 | err_cmd: | |
688 | mlx4_free_cmd_mailbox(dev, mailbox); | |
689 | ||
690 | err_table: | |
b20e519a | 691 | mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key)); |
225c7b1f RD |
692 | return err; |
693 | } | |
694 | EXPORT_SYMBOL_GPL(mlx4_mr_enable); | |
695 | ||
d7bb58fb JM |
696 | static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
697 | int start_index, int npages, u64 *page_list) | |
225c7b1f | 698 | { |
d7bb58fb JM |
699 | struct mlx4_priv *priv = mlx4_priv(dev); |
700 | __be64 *mtts; | |
701 | dma_addr_t dma_handle; | |
702 | int i; | |
d7bb58fb | 703 | |
2b8fb286 MA |
704 | mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->offset + |
705 | start_index, &dma_handle); | |
d7bb58fb | 706 | |
d7bb58fb JM |
707 | if (!mtts) |
708 | return -ENOMEM; | |
709 | ||
e727f5cd RD |
710 | dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle, |
711 | npages * sizeof (u64), DMA_TO_DEVICE); | |
712 | ||
d7bb58fb JM |
713 | for (i = 0; i < npages; ++i) |
714 | mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT); | |
715 | ||
e727f5cd RD |
716 | dma_sync_single_for_device(&dev->pdev->dev, dma_handle, |
717 | npages * sizeof (u64), DMA_TO_DEVICE); | |
d7bb58fb JM |
718 | |
719 | return 0; | |
225c7b1f RD |
720 | } |
721 | ||
c82e9aa0 | 722 | int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
ea51b377 | 723 | int start_index, int npages, u64 *page_list) |
225c7b1f | 724 | { |
ea51b377 | 725 | int err = 0; |
d7bb58fb | 726 | int chunk; |
2b8fb286 MA |
727 | int mtts_per_page; |
728 | int max_mtts_first_page; | |
729 | ||
730 | /* compute how may mtts fit in the first page */ | |
731 | mtts_per_page = PAGE_SIZE / sizeof(u64); | |
732 | max_mtts_first_page = mtts_per_page - (mtt->offset + start_index) | |
733 | % mtts_per_page; | |
734 | ||
735 | chunk = min_t(int, max_mtts_first_page, npages); | |
225c7b1f | 736 | |
225c7b1f | 737 | while (npages > 0) { |
d7bb58fb | 738 | err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list); |
225c7b1f | 739 | if (err) |
d7bb58fb | 740 | return err; |
d7bb58fb JM |
741 | npages -= chunk; |
742 | start_index += chunk; | |
743 | page_list += chunk; | |
2b8fb286 MA |
744 | |
745 | chunk = min_t(int, mtts_per_page, npages); | |
225c7b1f | 746 | } |
ea51b377 JM |
747 | return err; |
748 | } | |
225c7b1f | 749 | |
ea51b377 JM |
750 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
751 | int start_index, int npages, u64 *page_list) | |
752 | { | |
753 | struct mlx4_cmd_mailbox *mailbox = NULL; | |
754 | __be64 *inbox = NULL; | |
755 | int chunk; | |
756 | int err = 0; | |
757 | int i; | |
758 | ||
759 | if (mtt->order < 0) | |
760 | return -EINVAL; | |
761 | ||
762 | if (mlx4_is_mfunc(dev)) { | |
763 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
764 | if (IS_ERR(mailbox)) | |
765 | return PTR_ERR(mailbox); | |
766 | inbox = mailbox->buf; | |
767 | ||
768 | while (npages > 0) { | |
2b8fb286 MA |
769 | chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) - 2, |
770 | npages); | |
771 | inbox[0] = cpu_to_be64(mtt->offset + start_index); | |
ea51b377 JM |
772 | inbox[1] = 0; |
773 | for (i = 0; i < chunk; ++i) | |
774 | inbox[i + 2] = cpu_to_be64(page_list[i] | | |
775 | MLX4_MTT_FLAG_PRESENT); | |
776 | err = mlx4_WRITE_MTT(dev, mailbox, chunk); | |
777 | if (err) { | |
778 | mlx4_free_cmd_mailbox(dev, mailbox); | |
779 | return err; | |
780 | } | |
781 | ||
782 | npages -= chunk; | |
783 | start_index += chunk; | |
784 | page_list += chunk; | |
785 | } | |
786 | mlx4_free_cmd_mailbox(dev, mailbox); | |
787 | return err; | |
788 | } | |
789 | ||
790 | return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list); | |
225c7b1f RD |
791 | } |
792 | EXPORT_SYMBOL_GPL(mlx4_write_mtt); | |
793 | ||
794 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
40f2287b | 795 | struct mlx4_buf *buf, gfp_t gfp) |
225c7b1f RD |
796 | { |
797 | u64 *page_list; | |
798 | int err; | |
799 | int i; | |
800 | ||
40f2287b JK |
801 | page_list = kmalloc(buf->npages * sizeof *page_list, |
802 | gfp); | |
225c7b1f RD |
803 | if (!page_list) |
804 | return -ENOMEM; | |
805 | ||
806 | for (i = 0; i < buf->npages; ++i) | |
807 | if (buf->nbufs == 1) | |
b57aacfa | 808 | page_list[i] = buf->direct.map + (i << buf->page_shift); |
225c7b1f | 809 | else |
b57aacfa | 810 | page_list[i] = buf->page_list[i].map; |
225c7b1f RD |
811 | |
812 | err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list); | |
813 | ||
814 | kfree(page_list); | |
815 | return err; | |
816 | } | |
817 | EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt); | |
818 | ||
804d6a89 SM |
819 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
820 | struct mlx4_mw *mw) | |
821 | { | |
822 | u32 index; | |
823 | ||
824 | if ((type == MLX4_MW_TYPE_1 && | |
825 | !(dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)) || | |
826 | (type == MLX4_MW_TYPE_2 && | |
827 | !(dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN))) | |
828 | return -ENOTSUPP; | |
829 | ||
830 | index = mlx4_mpt_reserve(dev); | |
831 | if (index == -1) | |
832 | return -ENOMEM; | |
833 | ||
834 | mw->key = hw_index_to_key(index); | |
835 | mw->pd = pd; | |
836 | mw->type = type; | |
837 | mw->enabled = MLX4_MPT_DISABLED; | |
838 | ||
839 | return 0; | |
840 | } | |
841 | EXPORT_SYMBOL_GPL(mlx4_mw_alloc); | |
842 | ||
843 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw) | |
844 | { | |
845 | struct mlx4_cmd_mailbox *mailbox; | |
846 | struct mlx4_mpt_entry *mpt_entry; | |
847 | int err; | |
848 | ||
40f2287b | 849 | err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key), GFP_KERNEL); |
804d6a89 SM |
850 | if (err) |
851 | return err; | |
852 | ||
853 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
854 | if (IS_ERR(mailbox)) { | |
855 | err = PTR_ERR(mailbox); | |
856 | goto err_table; | |
857 | } | |
858 | mpt_entry = mailbox->buf; | |
859 | ||
804d6a89 SM |
860 | /* Note that the MLX4_MPT_FLAG_REGION bit in mpt_entry->flags is turned |
861 | * off, thus creating a memory window and not a memory region. | |
862 | */ | |
863 | mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key)); | |
864 | mpt_entry->pd_flags = cpu_to_be32(mw->pd); | |
865 | if (mw->type == MLX4_MW_TYPE_2) { | |
866 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
867 | mpt_entry->qpn = cpu_to_be32(MLX4_MPT_QP_FLAG_BOUND_QP); | |
868 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_EN_INV); | |
869 | } | |
870 | ||
871 | err = mlx4_SW2HW_MPT(dev, mailbox, | |
872 | key_to_hw_index(mw->key) & | |
873 | (dev->caps.num_mpts - 1)); | |
874 | if (err) { | |
875 | mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err); | |
876 | goto err_cmd; | |
877 | } | |
878 | mw->enabled = MLX4_MPT_EN_HW; | |
879 | ||
880 | mlx4_free_cmd_mailbox(dev, mailbox); | |
881 | ||
882 | return 0; | |
883 | ||
884 | err_cmd: | |
885 | mlx4_free_cmd_mailbox(dev, mailbox); | |
886 | ||
887 | err_table: | |
888 | mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key)); | |
889 | return err; | |
890 | } | |
891 | EXPORT_SYMBOL_GPL(mlx4_mw_enable); | |
892 | ||
893 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw) | |
894 | { | |
895 | int err; | |
896 | ||
897 | if (mw->enabled == MLX4_MPT_EN_HW) { | |
898 | err = mlx4_HW2SW_MPT(dev, NULL, | |
899 | key_to_hw_index(mw->key) & | |
900 | (dev->caps.num_mpts - 1)); | |
901 | if (err) | |
902 | mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err); | |
903 | ||
904 | mw->enabled = MLX4_MPT_EN_SW; | |
905 | } | |
906 | if (mw->enabled) | |
907 | mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key)); | |
908 | mlx4_mpt_release(dev, key_to_hw_index(mw->key)); | |
909 | } | |
910 | EXPORT_SYMBOL_GPL(mlx4_mw_free); | |
911 | ||
3d73c288 | 912 | int mlx4_init_mr_table(struct mlx4_dev *dev) |
225c7b1f | 913 | { |
ea51b377 JM |
914 | struct mlx4_priv *priv = mlx4_priv(dev); |
915 | struct mlx4_mr_table *mr_table = &priv->mr_table; | |
225c7b1f RD |
916 | int err; |
917 | ||
ea51b377 JM |
918 | /* Nothing to do for slaves - all MR handling is forwarded |
919 | * to the master */ | |
920 | if (mlx4_is_slave(dev)) | |
921 | return 0; | |
922 | ||
a30f1bc5 JM |
923 | if (!is_power_of_2(dev->caps.num_mpts)) |
924 | return -EINVAL; | |
925 | ||
225c7b1f | 926 | err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts, |
93fc9e1b | 927 | ~0, dev->caps.reserved_mrws, 0); |
225c7b1f RD |
928 | if (err) |
929 | return err; | |
930 | ||
931 | err = mlx4_buddy_init(&mr_table->mtt_buddy, | |
3de819e6 | 932 | ilog2((u32)dev->caps.num_mtts / |
2b8fb286 | 933 | (1 << log_mtts_per_seg))); |
225c7b1f RD |
934 | if (err) |
935 | goto err_buddy; | |
936 | ||
937 | if (dev->caps.reserved_mtts) { | |
ea51b377 JM |
938 | priv->reserved_mtts = |
939 | mlx4_alloc_mtt_range(dev, | |
940 | fls(dev->caps.reserved_mtts - 1)); | |
941 | if (priv->reserved_mtts < 0) { | |
1a91de28 | 942 | mlx4_warn(dev, "MTT table of order %u is too small\n", |
225c7b1f RD |
943 | mr_table->mtt_buddy.max_order); |
944 | err = -ENOMEM; | |
945 | goto err_reserve_mtts; | |
946 | } | |
947 | } | |
948 | ||
949 | return 0; | |
950 | ||
951 | err_reserve_mtts: | |
952 | mlx4_buddy_cleanup(&mr_table->mtt_buddy); | |
953 | ||
954 | err_buddy: | |
955 | mlx4_bitmap_cleanup(&mr_table->mpt_bitmap); | |
956 | ||
957 | return err; | |
958 | } | |
959 | ||
960 | void mlx4_cleanup_mr_table(struct mlx4_dev *dev) | |
961 | { | |
ea51b377 JM |
962 | struct mlx4_priv *priv = mlx4_priv(dev); |
963 | struct mlx4_mr_table *mr_table = &priv->mr_table; | |
225c7b1f | 964 | |
ea51b377 JM |
965 | if (mlx4_is_slave(dev)) |
966 | return; | |
967 | if (priv->reserved_mtts >= 0) | |
968 | mlx4_free_mtt_range(dev, priv->reserved_mtts, | |
969 | fls(dev->caps.reserved_mtts - 1)); | |
225c7b1f RD |
970 | mlx4_buddy_cleanup(&mr_table->mtt_buddy); |
971 | mlx4_bitmap_cleanup(&mr_table->mpt_bitmap); | |
972 | } | |
8ad11fb6 JM |
973 | |
974 | static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list, | |
975 | int npages, u64 iova) | |
976 | { | |
977 | int i, page_mask; | |
978 | ||
979 | if (npages > fmr->max_pages) | |
980 | return -EINVAL; | |
981 | ||
982 | page_mask = (1 << fmr->page_shift) - 1; | |
983 | ||
984 | /* We are getting page lists, so va must be page aligned. */ | |
985 | if (iova & page_mask) | |
986 | return -EINVAL; | |
987 | ||
988 | /* Trust the user not to pass misaligned data in page_list */ | |
989 | if (0) | |
990 | for (i = 0; i < npages; ++i) { | |
991 | if (page_list[i] & ~page_mask) | |
992 | return -EINVAL; | |
993 | } | |
994 | ||
995 | if (fmr->maps >= fmr->max_maps) | |
996 | return -EINVAL; | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
1001 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, | |
1002 | int npages, u64 iova, u32 *lkey, u32 *rkey) | |
1003 | { | |
1004 | u32 key; | |
1005 | int i, err; | |
1006 | ||
1007 | err = mlx4_check_fmr(fmr, page_list, npages, iova); | |
1008 | if (err) | |
1009 | return err; | |
1010 | ||
1011 | ++fmr->maps; | |
1012 | ||
1013 | key = key_to_hw_index(fmr->mr.key); | |
1014 | key += dev->caps.num_mpts; | |
1015 | *lkey = *rkey = fmr->mr.key = hw_index_to_key(key); | |
1016 | ||
1017 | *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW; | |
1018 | ||
1019 | /* Make sure MPT status is visible before writing MTT entries */ | |
1020 | wmb(); | |
1021 | ||
e727f5cd RD |
1022 | dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle, |
1023 | npages * sizeof(u64), DMA_TO_DEVICE); | |
1024 | ||
8ad11fb6 JM |
1025 | for (i = 0; i < npages; ++i) |
1026 | fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT); | |
1027 | ||
e727f5cd RD |
1028 | dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle, |
1029 | npages * sizeof(u64), DMA_TO_DEVICE); | |
8ad11fb6 JM |
1030 | |
1031 | fmr->mpt->key = cpu_to_be32(key); | |
1032 | fmr->mpt->lkey = cpu_to_be32(key); | |
1033 | fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift)); | |
1034 | fmr->mpt->start = cpu_to_be64(iova); | |
1035 | ||
1036 | /* Make MTT entries are visible before setting MPT status */ | |
1037 | wmb(); | |
1038 | ||
1039 | *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW; | |
1040 | ||
1041 | /* Make sure MPT status is visible before consumer can use FMR */ | |
1042 | wmb(); | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr); | |
1047 | ||
1048 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1049 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr) | |
1050 | { | |
1051 | struct mlx4_priv *priv = mlx4_priv(dev); | |
8ad11fb6 JM |
1052 | int err = -ENOMEM; |
1053 | ||
a5bbe892 EC |
1054 | if (max_maps > dev->caps.max_fmr_maps) |
1055 | return -EINVAL; | |
1056 | ||
c5057ddc | 1057 | if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32) |
8ad11fb6 JM |
1058 | return -EINVAL; |
1059 | ||
1060 | /* All MTTs must fit in the same page */ | |
1061 | if (max_pages * sizeof *fmr->mtts > PAGE_SIZE) | |
1062 | return -EINVAL; | |
1063 | ||
1064 | fmr->page_shift = page_shift; | |
1065 | fmr->max_pages = max_pages; | |
1066 | fmr->max_maps = max_maps; | |
1067 | fmr->maps = 0; | |
1068 | ||
1069 | err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages, | |
1070 | page_shift, &fmr->mr); | |
1071 | if (err) | |
1072 | return err; | |
1073 | ||
8ad11fb6 | 1074 | fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table, |
2b8fb286 | 1075 | fmr->mr.mtt.offset, |
8ad11fb6 | 1076 | &fmr->dma_handle); |
2b8fb286 | 1077 | |
8ad11fb6 JM |
1078 | if (!fmr->mtts) { |
1079 | err = -ENOMEM; | |
1080 | goto err_free; | |
1081 | } | |
1082 | ||
8ad11fb6 JM |
1083 | return 0; |
1084 | ||
1085 | err_free: | |
61083720 | 1086 | (void) mlx4_mr_free(dev, &fmr->mr); |
8ad11fb6 JM |
1087 | return err; |
1088 | } | |
1089 | EXPORT_SYMBOL_GPL(mlx4_fmr_alloc); | |
1090 | ||
1091 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr) | |
1092 | { | |
11e75a74 JM |
1093 | struct mlx4_priv *priv = mlx4_priv(dev); |
1094 | int err; | |
1095 | ||
1096 | err = mlx4_mr_enable(dev, &fmr->mr); | |
1097 | if (err) | |
1098 | return err; | |
1099 | ||
1100 | fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table, | |
1101 | key_to_hw_index(fmr->mr.key), NULL); | |
1102 | if (!fmr->mpt) | |
1103 | return -ENOMEM; | |
1104 | ||
1105 | return 0; | |
8ad11fb6 JM |
1106 | } |
1107 | EXPORT_SYMBOL_GPL(mlx4_fmr_enable); | |
1108 | ||
1109 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1110 | u32 *lkey, u32 *rkey) | |
1111 | { | |
ea51b377 JM |
1112 | struct mlx4_cmd_mailbox *mailbox; |
1113 | int err; | |
1114 | ||
8ad11fb6 JM |
1115 | if (!fmr->maps) |
1116 | return; | |
1117 | ||
8ad11fb6 JM |
1118 | fmr->maps = 0; |
1119 | ||
ea51b377 JM |
1120 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1121 | if (IS_ERR(mailbox)) { | |
1122 | err = PTR_ERR(mailbox); | |
c20862c8 | 1123 | pr_warn("mlx4_ib: mlx4_alloc_cmd_mailbox failed (%d)\n", err); |
ea51b377 JM |
1124 | return; |
1125 | } | |
1126 | ||
1127 | err = mlx4_HW2SW_MPT(dev, NULL, | |
1128 | key_to_hw_index(fmr->mr.key) & | |
1129 | (dev->caps.num_mpts - 1)); | |
1130 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1131 | if (err) { | |
c20862c8 | 1132 | pr_warn("mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n", err); |
ea51b377 JM |
1133 | return; |
1134 | } | |
b20e519a | 1135 | fmr->mr.enabled = MLX4_MPT_EN_SW; |
8ad11fb6 JM |
1136 | } |
1137 | EXPORT_SYMBOL_GPL(mlx4_fmr_unmap); | |
1138 | ||
1139 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr) | |
1140 | { | |
61083720 SM |
1141 | int ret; |
1142 | ||
8ad11fb6 JM |
1143 | if (fmr->maps) |
1144 | return -EBUSY; | |
1145 | ||
61083720 SM |
1146 | ret = mlx4_mr_free(dev, &fmr->mr); |
1147 | if (ret) | |
1148 | return ret; | |
b20e519a | 1149 | fmr->mr.enabled = MLX4_MPT_DISABLED; |
8ad11fb6 JM |
1150 | |
1151 | return 0; | |
1152 | } | |
1153 | EXPORT_SYMBOL_GPL(mlx4_fmr_free); | |
1154 | ||
1155 | int mlx4_SYNC_TPT(struct mlx4_dev *dev) | |
1156 | { | |
f9baff50 | 1157 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000, |
5e92d803 | 1158 | MLX4_CMD_NATIVE); |
8ad11fb6 JM |
1159 | } |
1160 | EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT); |