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mlx4_en: Allow communication between functions on same host
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mr.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
ea51b377 35#include <linux/init.h>
225c7b1f 36#include <linux/errno.h>
ee40fa06 37#include <linux/export.h>
5a0e3ad6 38#include <linux/slab.h>
ea51b377 39#include <linux/kernel.h>
225c7b1f
RD		 40
41#include <linux/mlx4/cmd.h>
42
43#include "mlx4.h"
44#include "icm.h"
45
225c7b1f 46#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
95d04f07 47#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
225c7b1f
RD		 48#define MLX4_MPT_FLAG_MIO (1 << 17)
49#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
50#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
51#define MLX4_MPT_FLAG_REGION (1 << 8)
52
c9257433
VS		 53#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
54#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
95d04f07
RD		 55#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
56
8ad11fb6
JM		 57#define MLX4_MPT_STATUS_SW 0xF0
58#define MLX4_MPT_STATUS_HW 0x00
59
225c7b1f
RD		 60static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
61{
62 int o;
63 int m;
64 u32 seg;
65
66 spin_lock(&buddy->lock);
67
e4044cfc
RD		 68 for (o = order; o <= buddy->max_order; ++o)
69 if (buddy->num_free[o]) {
70 m = 1 << (buddy->max_order - o);
71 seg = find_first_bit(buddy->bits[o], m);
72 if (seg < m)
73 goto found;
74 }
225c7b1f
RD		 75
76 spin_unlock(&buddy->lock);
77 return -1;
78
79 found:
80 clear_bit(seg, buddy->bits[o]);
e4044cfc 81 --buddy->num_free[o];
225c7b1f
RD		 82
83 while (o > order) {
84 --o;
85 seg <<= 1;
86 set_bit(seg ^ 1, buddy->bits[o]);
e4044cfc 87 ++buddy->num_free[o];
225c7b1f
RD		 88 }
89
90 spin_unlock(&buddy->lock);
91
92 seg <<= order;
93
94 return seg;
95}
96
97static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
98{
99 seg >>= order;
100
101 spin_lock(&buddy->lock);
102
103 while (test_bit(seg ^ 1, buddy->bits[order])) {
104 clear_bit(seg ^ 1, buddy->bits[order]);
e4044cfc 105 --buddy->num_free[order];
225c7b1f
RD		 106 seg >>= 1;
107 ++order;
108 }
109
110 set_bit(seg, buddy->bits[order]);
e4044cfc 111 ++buddy->num_free[order];
225c7b1f
RD		 112
113 spin_unlock(&buddy->lock);
114}
115
e8f9b2ed 116static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
225c7b1f
RD		 117{
118 int i, s;
119
120 buddy->max_order = max_order;
121 spin_lock_init(&buddy->lock);
122
123 buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
124 GFP_KERNEL);
a8312755 125 buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
e4044cfc
RD		 126 GFP_KERNEL);
127 if (!buddy->bits || !buddy->num_free)
225c7b1f
RD		 128 goto err_out;
129
130 for (i = 0; i <= buddy->max_order; ++i) {
131 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
132 buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
133 if (!buddy->bits[i])
134 goto err_out_free;
135 bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
136 }
137
138 set_bit(0, buddy->bits[buddy->max_order]);
e4044cfc 139 buddy->num_free[buddy->max_order] = 1;
225c7b1f
RD		 140
141 return 0;
142
143err_out_free:
144 for (i = 0; i <= buddy->max_order; ++i)
145 kfree(buddy->bits[i]);
146
e4044cfc 147err_out:
225c7b1f 148 kfree(buddy->bits);
e4044cfc 149 kfree(buddy->num_free);
225c7b1f 150
225c7b1f
RD		 151 return -ENOMEM;
152}
153
154static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
155{
156 int i;
157
158 for (i = 0; i <= buddy->max_order; ++i)
159 kfree(buddy->bits[i]);
160
161 kfree(buddy->bits);
e4044cfc 162 kfree(buddy->num_free);
225c7b1f
RD		 163}
164
c82e9aa0 165u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
225c7b1f
RD		 166{
167 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
168 u32 seg;
169
170 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
171 if (seg == -1)
172 return -1;
173
174 if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
175 seg + (1 << order) - 1)) {
176 mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
177 return -1;
178 }
179
180 return seg;
181}
182
ea51b377
JM		 183static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
184{
185 u64 in_param;
186 u64 out_param;
187 int err;
188
189 if (mlx4_is_mfunc(dev)) {
190 set_param_l(&in_param, order);
191 err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT,
192 RES_OP_RESERVE_AND_MAP,
193 MLX4_CMD_ALLOC_RES,
194 MLX4_CMD_TIME_CLASS_A,
195 MLX4_CMD_WRAPPED);
196 if (err)
197 return -1;
198 return get_param_l(&out_param);
199 }
200 return __mlx4_alloc_mtt_range(dev, order);
201}
202
225c7b1f
RD		 203int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
204 struct mlx4_mtt *mtt)
205{
206 int i;
207
208 if (!npages) {
209 mtt->order = -1;
210 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
211 return 0;
212 } else
213 mtt->page_shift = page_shift;
214
ab6bf42e 215 for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1)
225c7b1f
RD		 216 ++mtt->order;
217
218 mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
219 if (mtt->first_seg == -1)
220 return -ENOMEM;
221
222 return 0;
223}
224EXPORT_SYMBOL_GPL(mlx4_mtt_init);
225
c82e9aa0 226void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg,
ea51b377 227 int order)
225c7b1f
RD		 228{
229 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
230
ea51b377
JM		 231 mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, order);
232 mlx4_table_put_range(dev, &mr_table->mtt_table, first_seg,
233 first_seg + (1 << order) - 1);
234}
235
236static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order)
237{
238 u64 in_param;
239 int err;
240
241 if (mlx4_is_mfunc(dev)) {
242 set_param_l(&in_param, first_seg);
243 set_param_h(&in_param, order);
244 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
245 MLX4_CMD_FREE_RES,
246 MLX4_CMD_TIME_CLASS_A,
247 MLX4_CMD_WRAPPED);
248 if (err)
249 mlx4_warn(dev, "Failed to free mtt range at:%d"
250 " order:%d\n", first_seg, order);
251 return;
252 }
253 __mlx4_free_mtt_range(dev, first_seg, order);
254}
255
256void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
257{
225c7b1f
RD		 258 if (mtt->order < 0)
259 return;
260
ea51b377 261 mlx4_free_mtt_range(dev, mtt->first_seg, mtt->order);
225c7b1f
RD		 262}
263EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
264
265u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
266{
267 return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
268}
269EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
270
271static u32 hw_index_to_key(u32 ind)
272{
273 return (ind >> 24) | (ind << 8);
274}
275
276static u32 key_to_hw_index(u32 key)
277{
278 return (key << 24) | (key >> 8);
279}
280
281static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
282 int mpt_index)
283{
ea51b377
JM		 284 return mlx4_cmd(dev, mailbox->dma | dev->caps.function , mpt_index,
285 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B,
286 MLX4_CMD_WRAPPED);
225c7b1f
RD		 287}
288
289static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
290 int mpt_index)
291{
292 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
f9baff50
JM		 293 !mailbox, MLX4_CMD_HW2SW_MPT,
294 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
225c7b1f
RD		 295}
296
ea51b377
JM		 297static int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align,
298 u32 *base_mridx)
225c7b1f
RD		 299{
300 struct mlx4_priv *priv = mlx4_priv(dev);
ea51b377 301 u32 mridx;
225c7b1f 302
ea51b377
JM		 303 mridx = mlx4_bitmap_alloc_range(&priv->mr_table.mpt_bitmap, cnt, align);
304 if (mridx == -1)
0172e2e1 305 return -ENOMEM;
225c7b1f 306
ea51b377
JM		 307 *base_mridx = mridx;
308 return 0;
309
310}
311EXPORT_SYMBOL_GPL(mlx4_mr_reserve_range);
312
313static void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt)
314{
315 struct mlx4_priv *priv = mlx4_priv(dev);
316 mlx4_bitmap_free_range(&priv->mr_table.mpt_bitmap, base_mridx, cnt);
317}
318EXPORT_SYMBOL_GPL(mlx4_mr_release_range);
319
320static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
321 u64 iova, u64 size, u32 access, int npages,
322 int page_shift, struct mlx4_mr *mr)
323{
225c7b1f
RD		 324 mr->iova = iova;
325 mr->size = size;
326 mr->pd = pd;
327 mr->access = access;
ea51b377
JM		 328 mr->enabled = MLX4_MR_DISABLED;
329 mr->key = hw_index_to_key(mridx);
330
331 return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
332}
333EXPORT_SYMBOL_GPL(mlx4_mr_alloc_reserved);
334
335static int mlx4_WRITE_MTT(struct mlx4_dev *dev,
336 struct mlx4_cmd_mailbox *mailbox,
337 int num_entries)
338{
339 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
340 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
341}
342
c82e9aa0 343int __mlx4_mr_reserve(struct mlx4_dev *dev)
ea51b377
JM		 344{
345 struct mlx4_priv *priv = mlx4_priv(dev);
346
347 return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
348}
225c7b1f 349
ea51b377
JM		 350static int mlx4_mr_reserve(struct mlx4_dev *dev)
351{
352 u64 out_param;
353
354 if (mlx4_is_mfunc(dev)) {
355 if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE,
356 MLX4_CMD_ALLOC_RES,
357 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
358 return -1;
359 return get_param_l(&out_param);
360 }
361 return __mlx4_mr_reserve(dev);
362}
363
c82e9aa0 364void __mlx4_mr_release(struct mlx4_dev *dev, u32 index)
ea51b377
JM		 365{
366 struct mlx4_priv *priv = mlx4_priv(dev);
367
368 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
369}
370
371static void mlx4_mr_release(struct mlx4_dev *dev, u32 index)
372{
373 u64 in_param;
374
375 if (mlx4_is_mfunc(dev)) {
376 set_param_l(&in_param, index);
377 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
378 MLX4_CMD_FREE_RES,
379 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
380 mlx4_warn(dev, "Failed to release mr index:%d\n",
381 index);
382 return;
383 }
384 __mlx4_mr_release(dev, index);
385}
386
c82e9aa0 387int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index)
ea51b377
JM		 388{
389 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
390
391 return mlx4_table_get(dev, &mr_table->dmpt_table, index);
392}
393
394static int mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index)
395{
396 u64 param;
397
398 if (mlx4_is_mfunc(dev)) {
399 set_param_l(&param, index);
400 return mlx4_cmd_imm(dev, param, &param, RES_MPT, RES_OP_MAP_ICM,
401 MLX4_CMD_ALLOC_RES,
402 MLX4_CMD_TIME_CLASS_A,
403 MLX4_CMD_WRAPPED);
404 }
405 return __mlx4_mr_alloc_icm(dev, index);
406}
407
c82e9aa0 408void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index)
ea51b377
JM		 409{
410 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
411
412 mlx4_table_put(dev, &mr_table->dmpt_table, index);
413}
414
415static void mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index)
416{
417 u64 in_param;
418
419 if (mlx4_is_mfunc(dev)) {
420 set_param_l(&in_param, index);
421 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
422 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
423 MLX4_CMD_WRAPPED))
424 mlx4_warn(dev, "Failed to free icm of mr index:%d\n",
425 index);
426 return;
427 }
428 return __mlx4_mr_free_icm(dev, index);
429}
430
431int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
432 int npages, int page_shift, struct mlx4_mr *mr)
433{
434 u32 index;
435 int err;
436
437 index = mlx4_mr_reserve(dev);
438 if (index == -1)
439 return -ENOMEM;
440
441 err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size,
442 access, npages, page_shift, mr);
225c7b1f 443 if (err)
ea51b377 444 mlx4_mr_release(dev, index);
225c7b1f 445
225c7b1f
RD		 446 return err;
447}
448EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
449
ea51b377 450static void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
225c7b1f 451{
225c7b1f
RD		 452 int err;
453
ea51b377 454 if (mr->enabled == MLX4_MR_EN_HW) {
225c7b1f
RD		 455 err = mlx4_HW2SW_MPT(dev, NULL,
456 key_to_hw_index(mr->key) &
457 (dev->caps.num_mpts - 1));
458 if (err)
ea51b377 459 mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err);
225c7b1f 460
ea51b377
JM		 461 mr->enabled = MLX4_MR_EN_SW;
462 }
225c7b1f 463 mlx4_mtt_cleanup(dev, &mr->mtt);
ea51b377
JM		 464}
465EXPORT_SYMBOL_GPL(mlx4_mr_free_reserved);
466
467void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
468{
469 mlx4_mr_free_reserved(dev, mr);
470 if (mr->enabled)
471 mlx4_mr_free_icm(dev, key_to_hw_index(mr->key));
472 mlx4_mr_release(dev, key_to_hw_index(mr->key));
225c7b1f
RD		 473}
474EXPORT_SYMBOL_GPL(mlx4_mr_free);
475
476int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
477{
225c7b1f
RD		 478 struct mlx4_cmd_mailbox *mailbox;
479 struct mlx4_mpt_entry *mpt_entry;
480 int err;
481
ea51b377 482 err = mlx4_mr_alloc_icm(dev, key_to_hw_index(mr->key));
225c7b1f
RD		 483 if (err)
484 return err;
485
486 mailbox = mlx4_alloc_cmd_mailbox(dev);
487 if (IS_ERR(mailbox)) {
488 err = PTR_ERR(mailbox);
489 goto err_table;
490 }
491 mpt_entry = mailbox->buf;
492
493 memset(mpt_entry, 0, sizeof *mpt_entry);
494
95d04f07 495 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
225c7b1f
RD		 496 MLX4_MPT_FLAG_REGION |
497 mr->access);
225c7b1f
RD		 498
499 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
95d04f07 500 mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
225c7b1f
RD		 501 mpt_entry->start = cpu_to_be64(mr->iova);
502 mpt_entry->length = cpu_to_be64(mr->size);
503 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
95d04f07 504
b2d9308a
JM		 505 if (mr->mtt.order < 0) {
506 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
507 mpt_entry->mtt_seg = 0;
95d04f07 508 } else {
b2d9308a 509 mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
95d04f07
RD		 510 }
511
512 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
513 /* fast register MR in free state */
514 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
c9257433
VS		 515 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
516 MLX4_MPT_PD_FLAG_RAE);
517 mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) *
ab6bf42e 518 dev->caps.mtts_per_seg);
95d04f07
RD		 519 } else {
520 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
521 }
225c7b1f
RD		 522
523 err = mlx4_SW2HW_MPT(dev, mailbox,
524 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
525 if (err) {
526 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
527 goto err_cmd;
528 }
ea51b377 529 mr->enabled = MLX4_MR_EN_HW;
225c7b1f
RD		 530
531 mlx4_free_cmd_mailbox(dev, mailbox);
532
533 return 0;
534
535err_cmd:
536 mlx4_free_cmd_mailbox(dev, mailbox);
537
538err_table:
ea51b377 539 mlx4_mr_free_icm(dev, key_to_hw_index(mr->key));
225c7b1f
RD		 540 return err;
541}
542EXPORT_SYMBOL_GPL(mlx4_mr_enable);
543
d7bb58fb
JM		 544static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
545 int start_index, int npages, u64 *page_list)
225c7b1f 546{
d7bb58fb
JM		 547 struct mlx4_priv *priv = mlx4_priv(dev);
548 __be64 *mtts;
549 dma_addr_t dma_handle;
550 int i;
551 int s = start_index * sizeof (u64);
552
553 /* All MTTs must fit in the same page */
554 if (start_index / (PAGE_SIZE / sizeof (u64)) !=
555 (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64)))
556 return -EINVAL;
557
ab6bf42e 558 if (start_index & (dev->caps.mtts_per_seg - 1))
d7bb58fb
JM		 559 return -EINVAL;
560
561 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg +
562 s / dev->caps.mtt_entry_sz, &dma_handle);
563 if (!mtts)
564 return -ENOMEM;
565
e727f5cd
RD		 566 dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
567 npages * sizeof (u64), DMA_TO_DEVICE);
568
d7bb58fb
JM		 569 for (i = 0; i < npages; ++i)
570 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
571
e727f5cd
RD		 572 dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
573 npages * sizeof (u64), DMA_TO_DEVICE);
d7bb58fb
JM		 574
575 return 0;
225c7b1f
RD		 576}
577
c82e9aa0 578int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
ea51b377 579 int start_index, int npages, u64 *page_list)
225c7b1f 580{
ea51b377 581 int err = 0;
d7bb58fb 582 int chunk;
225c7b1f 583
225c7b1f 584 while (npages > 0) {
d7bb58fb
JM		 585 chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
586 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
225c7b1f 587 if (err)
d7bb58fb 588 return err;
d7bb58fb
JM		 589 npages -= chunk;
590 start_index += chunk;
591 page_list += chunk;
225c7b1f 592 }
ea51b377
JM		 593 return err;
594}
225c7b1f 595
ea51b377
JM		 596int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
597 int start_index, int npages, u64 *page_list)
598{
599 struct mlx4_cmd_mailbox *mailbox = NULL;
600 __be64 *inbox = NULL;
601 int chunk;
602 int err = 0;
603 int i;
604
605 if (mtt->order < 0)
606 return -EINVAL;
607
608 if (mlx4_is_mfunc(dev)) {
609 mailbox = mlx4_alloc_cmd_mailbox(dev);
610 if (IS_ERR(mailbox))
611 return PTR_ERR(mailbox);
612 inbox = mailbox->buf;
613
614 while (npages > 0) {
615 int s = mtt->first_seg * dev->caps.mtts_per_seg +
616 start_index;
617 chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) -
618 dev->caps.mtts_per_seg, npages);
619 if (s / (PAGE_SIZE / sizeof(u64)) !=
620 (s + chunk - 1) / (PAGE_SIZE / sizeof(u64)))
621 chunk = PAGE_SIZE / sizeof(u64) -
622 (s % (PAGE_SIZE / sizeof(u64)));
623
624 inbox[0] = cpu_to_be64(mtt->first_seg *
625 dev->caps.mtts_per_seg +
626 start_index);
627 inbox[1] = 0;
628 for (i = 0; i < chunk; ++i)
629 inbox[i + 2] = cpu_to_be64(page_list[i] |
630 MLX4_MTT_FLAG_PRESENT);
631 err = mlx4_WRITE_MTT(dev, mailbox, chunk);
632 if (err) {
633 mlx4_free_cmd_mailbox(dev, mailbox);
634 return err;
635 }
636
637 npages -= chunk;
638 start_index += chunk;
639 page_list += chunk;
640 }
641 mlx4_free_cmd_mailbox(dev, mailbox);
642 return err;
643 }
644
645 return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list);
225c7b1f
RD		 646}
647EXPORT_SYMBOL_GPL(mlx4_write_mtt);
648
649int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
650 struct mlx4_buf *buf)
651{
652 u64 *page_list;
653 int err;
654 int i;
655
656 page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
657 if (!page_list)
658 return -ENOMEM;
659
660 for (i = 0; i < buf->npages; ++i)
661 if (buf->nbufs == 1)
b57aacfa 662 page_list[i] = buf->direct.map + (i << buf->page_shift);
225c7b1f 663 else
b57aacfa 664 page_list[i] = buf->page_list[i].map;
225c7b1f
RD		 665
666 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
667
668 kfree(page_list);
669 return err;
670}
671EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
672
3d73c288 673int mlx4_init_mr_table(struct mlx4_dev *dev)
225c7b1f 674{
ea51b377
JM		 675 struct mlx4_priv *priv = mlx4_priv(dev);
676 struct mlx4_mr_table *mr_table = &priv->mr_table;
225c7b1f
RD		 677 int err;
678
ea51b377
JM		 679 if (!is_power_of_2(dev->caps.num_mpts))
680 return -EINVAL;
681
682 /* Nothing to do for slaves - all MR handling is forwarded
683 * to the master */
684 if (mlx4_is_slave(dev))
685 return 0;
686
225c7b1f 687 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
93fc9e1b 688 ~0, dev->caps.reserved_mrws, 0);
225c7b1f
RD		 689 if (err)
690 return err;
691
692 err = mlx4_buddy_init(&mr_table->mtt_buddy,
693 ilog2(dev->caps.num_mtt_segs));
694 if (err)
695 goto err_buddy;
696
697 if (dev->caps.reserved_mtts) {
ea51b377
JM		 698 priv->reserved_mtts =
699 mlx4_alloc_mtt_range(dev,
700 fls(dev->caps.reserved_mtts - 1));
701 if (priv->reserved_mtts < 0) {
225c7b1f
RD		 702 mlx4_warn(dev, "MTT table of order %d is too small.\n",
703 mr_table->mtt_buddy.max_order);
704 err = -ENOMEM;
705 goto err_reserve_mtts;
706 }
707 }
708
709 return 0;
710
711err_reserve_mtts:
712 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
713
714err_buddy:
715 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
716
717 return err;
718}
719
720void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
721{
ea51b377
JM		 722 struct mlx4_priv *priv = mlx4_priv(dev);
723 struct mlx4_mr_table *mr_table = &priv->mr_table;
225c7b1f 724
ea51b377
JM		 725 if (mlx4_is_slave(dev))
726 return;
727 if (priv->reserved_mtts >= 0)
728 mlx4_free_mtt_range(dev, priv->reserved_mtts,
729 fls(dev->caps.reserved_mtts - 1));
225c7b1f
RD		 730 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
731 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
732}
8ad11fb6
JM		 733
734static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
735 int npages, u64 iova)
736{
737 int i, page_mask;
738
739 if (npages > fmr->max_pages)
740 return -EINVAL;
741
742 page_mask = (1 << fmr->page_shift) - 1;
743
744 /* We are getting page lists, so va must be page aligned. */
745 if (iova & page_mask)
746 return -EINVAL;
747
748 /* Trust the user not to pass misaligned data in page_list */
749 if (0)
750 for (i = 0; i < npages; ++i) {
751 if (page_list[i] & ~page_mask)
752 return -EINVAL;
753 }
754
755 if (fmr->maps >= fmr->max_maps)
756 return -EINVAL;
757
758 return 0;
759}
760
761int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
762 int npages, u64 iova, u32 *lkey, u32 *rkey)
763{
764 u32 key;
765 int i, err;
766
767 err = mlx4_check_fmr(fmr, page_list, npages, iova);
768 if (err)
769 return err;
770
771 ++fmr->maps;
772
773 key = key_to_hw_index(fmr->mr.key);
774 key += dev->caps.num_mpts;
775 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
776
777 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
778
779 /* Make sure MPT status is visible before writing MTT entries */
780 wmb();
781
e727f5cd
RD		 782 dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle,
783 npages * sizeof(u64), DMA_TO_DEVICE);
784
8ad11fb6
JM		 785 for (i = 0; i < npages; ++i)
786 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
787
e727f5cd
RD		 788 dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle,
789 npages * sizeof(u64), DMA_TO_DEVICE);
8ad11fb6
JM		 790
791 fmr->mpt->key = cpu_to_be32(key);
792 fmr->mpt->lkey = cpu_to_be32(key);
793 fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
794 fmr->mpt->start = cpu_to_be64(iova);
795
796 /* Make MTT entries are visible before setting MPT status */
797 wmb();
798
799 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
800
801 /* Make sure MPT status is visible before consumer can use FMR */
802 wmb();
803
804 return 0;
805}
806EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
807
808int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
809 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
810{
811 struct mlx4_priv *priv = mlx4_priv(dev);
812 u64 mtt_seg;
813 int err = -ENOMEM;
814
c5057ddc 815 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
8ad11fb6
JM		 816 return -EINVAL;
817
818 /* All MTTs must fit in the same page */
819 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
820 return -EINVAL;
821
822 fmr->page_shift = page_shift;
823 fmr->max_pages = max_pages;
824 fmr->max_maps = max_maps;
825 fmr->maps = 0;
826
827 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
828 page_shift, &fmr->mr);
829 if (err)
830 return err;
831
832 mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
833
834 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
835 fmr->mr.mtt.first_seg,
836 &fmr->dma_handle);
837 if (!fmr->mtts) {
838 err = -ENOMEM;
839 goto err_free;
840 }
841
8ad11fb6
JM		 842 return 0;
843
844err_free:
845 mlx4_mr_free(dev, &fmr->mr);
846 return err;
847}
848EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
849
ea51b377
JM		 850static int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx,
851 u32 pd, u32 access, int max_pages,
852 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
853{
854 struct mlx4_priv *priv = mlx4_priv(dev);
855 int err = -ENOMEM;
856
857 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
858 return -EINVAL;
859
860 /* All MTTs must fit in the same page */
861 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
862 return -EINVAL;
863
864 fmr->page_shift = page_shift;
865 fmr->max_pages = max_pages;
866 fmr->max_maps = max_maps;
867 fmr->maps = 0;
868
869 err = mlx4_mr_alloc_reserved(dev, mridx, pd, 0, 0, access, max_pages,
870 page_shift, &fmr->mr);
871 if (err)
872 return err;
873
874 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
875 fmr->mr.mtt.first_seg,
876 &fmr->dma_handle);
877 if (!fmr->mtts) {
878 err = -ENOMEM;
879 goto err_free;
880 }
881
882 return 0;
883
884err_free:
885 mlx4_mr_free_reserved(dev, &fmr->mr);
886 return err;
887}
888EXPORT_SYMBOL_GPL(mlx4_fmr_alloc_reserved);
889
8ad11fb6
JM		 890int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
891{
11e75a74
JM		 892 struct mlx4_priv *priv = mlx4_priv(dev);
893 int err;
894
895 err = mlx4_mr_enable(dev, &fmr->mr);
896 if (err)
897 return err;
898
899 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
900 key_to_hw_index(fmr->mr.key), NULL);
901 if (!fmr->mpt)
902 return -ENOMEM;
903
904 return 0;
8ad11fb6
JM		 905}
906EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
907
908void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
909 u32 *lkey, u32 *rkey)
910{
ea51b377
JM		 911 struct mlx4_cmd_mailbox *mailbox;
912 int err;
913
8ad11fb6
JM		 914 if (!fmr->maps)
915 return;
916
8ad11fb6
JM		 917 fmr->maps = 0;
918
ea51b377
JM		 919 mailbox = mlx4_alloc_cmd_mailbox(dev);
920 if (IS_ERR(mailbox)) {
921 err = PTR_ERR(mailbox);
922 printk(KERN_WARNING "mlx4_ib: mlx4_alloc_cmd_mailbox"
923 " failed (%d)\n", err);
924 return;
925 }
926
927 err = mlx4_HW2SW_MPT(dev, NULL,
928 key_to_hw_index(fmr->mr.key) &
929 (dev->caps.num_mpts - 1));
930 mlx4_free_cmd_mailbox(dev, mailbox);
931 if (err) {
932 printk(KERN_WARNING "mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n",
933 err);
934 return;
935 }
936 fmr->mr.enabled = MLX4_MR_EN_SW;
8ad11fb6
JM		 937}
938EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
939
940int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
941{
942 if (fmr->maps)
943 return -EBUSY;
944
8ad11fb6 945 mlx4_mr_free(dev, &fmr->mr);
ea51b377 946 fmr->mr.enabled = MLX4_MR_DISABLED;
8ad11fb6
JM		 947
948 return 0;
949}
950EXPORT_SYMBOL_GPL(mlx4_fmr_free);
951
ea51b377
JM		 952static int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
953{
954 if (fmr->maps)
955 return -EBUSY;
956
957 mlx4_mr_free_reserved(dev, &fmr->mr);
958 fmr->mr.enabled = MLX4_MR_DISABLED;
959
960 return 0;
961}
962EXPORT_SYMBOL_GPL(mlx4_fmr_free_reserved);
963
8ad11fb6
JM		 964int mlx4_SYNC_TPT(struct mlx4_dev *dev)
965{
f9baff50
JM		 966 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000,
967 MLX4_CMD_WRAPPED);
8ad11fb6
JM		 968}
969EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);
Linux kernel - Deliverables
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