[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mr.c

/*
 * Copyright (c) 2004 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/errno.h>
#include <linux/export.h>
#include <linux/slab.h>

#include <linux/mlx4/cmd.h>

#include "mlx4.h"
#include "icm.h"

/*
 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 */
struct mlx4_mpt_entry {
	__be32 flags;
	__be32 qpn;
	__be32 key;
	__be32 pd_flags;
	__be64 start;
	__be64 length;
	__be32 lkey;
	__be32 win_cnt;
	u8	reserved1[3];
	u8	mtt_rep;
	__be64 mtt_seg;
	__be32 mtt_sz;
	__be32 entity_size;
	__be32 first_byte_offset;
} __packed;

#define MLX4_MPT_FLAG_SW_OWNS	    (0xfUL << 28)
#define MLX4_MPT_FLAG_FREE	    (0x3UL << 28)
#define MLX4_MPT_FLAG_MIO	    (1 << 17)
#define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
#define MLX4_MPT_FLAG_PHYSICAL	    (1 <<  9)
#define MLX4_MPT_FLAG_REGION	    (1 <<  8)

#define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
#define MLX4_MPT_PD_FLAG_RAE	    (1 << 28)
#define MLX4_MPT_PD_FLAG_EN_INV	    (3 << 24)

#define MLX4_MPT_STATUS_SW		0xF0
#define MLX4_MPT_STATUS_HW		0x00

static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
{
	int o;
	int m;
	u32 seg;

	spin_lock(&buddy->lock);

	for (o = order; o <= buddy->max_order; ++o)
		if (buddy->num_free[o]) {
			m = 1 << (buddy->max_order - o);
			seg = find_first_bit(buddy->bits[o], m);
			if (seg < m)
				goto found;
		}

	spin_unlock(&buddy->lock);
	return -1;

 found:
	clear_bit(seg, buddy->bits[o]);
	--buddy->num_free[o];

	while (o > order) {
		--o;
		seg <<= 1;
		set_bit(seg ^ 1, buddy->bits[o]);
		++buddy->num_free[o];
	}

	spin_unlock(&buddy->lock);

	seg <<= order;

	return seg;
}

static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
{
	seg >>= order;

	spin_lock(&buddy->lock);

	while (test_bit(seg ^ 1, buddy->bits[order])) {
		clear_bit(seg ^ 1, buddy->bits[order]);
		--buddy->num_free[order];
		seg >>= 1;
		++order;
	}

	set_bit(seg, buddy->bits[order]);
	++buddy->num_free[order];

	spin_unlock(&buddy->lock);
}

static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
{
	int i, s;

	buddy->max_order = max_order;
	spin_lock_init(&buddy->lock);

	buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
			      GFP_KERNEL);
	buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
				  GFP_KERNEL);
	if (!buddy->bits || !buddy->num_free)
		goto err_out;

	for (i = 0; i <= buddy->max_order; ++i) {
		s = BITS_TO_LONGS(1 << (buddy->max_order - i));
		buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
		if (!buddy->bits[i])
			goto err_out_free;
		bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
	}

	set_bit(0, buddy->bits[buddy->max_order]);
	buddy->num_free[buddy->max_order] = 1;

	return 0;

err_out_free:
	for (i = 0; i <= buddy->max_order; ++i)
		kfree(buddy->bits[i]);

err_out:
	kfree(buddy->bits);
	kfree(buddy->num_free);

	return -ENOMEM;
}

static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
{
	int i;

	for (i = 0; i <= buddy->max_order; ++i)
		kfree(buddy->bits[i]);

	kfree(buddy->bits);
	kfree(buddy->num_free);
}

static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	u32 seg;

	seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
	if (seg == -1)
		return -1;

	if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
				 seg + (1 << order) - 1)) {
		mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
		return -1;
	}

	return seg;
}

int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
		  struct mlx4_mtt *mtt)
{
	int i;

	if (!npages) {
		mtt->order      = -1;
		mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
		return 0;
	} else
		mtt->page_shift = page_shift;

	for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1)
		++mtt->order;

	mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
	if (mtt->first_seg == -1)
		return -ENOMEM;

	return 0;
}
EXPORT_SYMBOL_GPL(mlx4_mtt_init);

void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;

	if (mtt->order < 0)
		return;

	mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
	mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
			     mtt->first_seg + (1 << mtt->order) - 1);
}
EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);

u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
{
	return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
}
EXPORT_SYMBOL_GPL(mlx4_mtt_addr);

static u32 hw_index_to_key(u32 ind)
{
	return (ind >> 24) | (ind << 8);
}

static u32 key_to_hw_index(u32 key)
{
	return (key << 24) | (key >> 8);
}

static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			  int mpt_index)
{
	return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
			MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
}

static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			  int mpt_index)
{
	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
			    !mailbox, MLX4_CMD_HW2SW_MPT,
			    MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
}

int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
		  int npages, int page_shift, struct mlx4_mr *mr)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	u32 index;
	int err;

	index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
	if (index == -1)
		return -ENOMEM;

	mr->iova       = iova;
	mr->size       = size;
	mr->pd	       = pd;
	mr->access     = access;
	mr->enabled    = 0;
	mr->key	       = hw_index_to_key(index);

	err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
	if (err)
		mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);

	return err;
}
EXPORT_SYMBOL_GPL(mlx4_mr_alloc);

void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int err;

	if (mr->enabled) {
		err = mlx4_HW2SW_MPT(dev, NULL,
				     key_to_hw_index(mr->key) &
				     (dev->caps.num_mpts - 1));
		if (err)
			mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
	}

	mlx4_mtt_cleanup(dev, &mr->mtt);
	mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
}
EXPORT_SYMBOL_GPL(mlx4_mr_free);

int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_mpt_entry *mpt_entry;
	int err;

	err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	if (err)
		return err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox)) {
		err = PTR_ERR(mailbox);
		goto err_table;
	}
	mpt_entry = mailbox->buf;

	memset(mpt_entry, 0, sizeof *mpt_entry);

	mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO	 |
				       MLX4_MPT_FLAG_REGION	 |
				       mr->access);

	mpt_entry->key	       = cpu_to_be32(key_to_hw_index(mr->key));
	mpt_entry->pd_flags    = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
	mpt_entry->start       = cpu_to_be64(mr->iova);
	mpt_entry->length      = cpu_to_be64(mr->size);
	mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);

	if (mr->mtt.order < 0) {
		mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
		mpt_entry->mtt_seg = 0;
	} else {
		mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
	}

	if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
		/* fast register MR in free state */
		mpt_entry->flags    |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
		mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
						   MLX4_MPT_PD_FLAG_RAE);
		mpt_entry->mtt_sz    = cpu_to_be32((1 << mr->mtt.order) *
						   dev->caps.mtts_per_seg);
	} else {
		mpt_entry->flags    |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
	}

	err = mlx4_SW2HW_MPT(dev, mailbox,
			     key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
	if (err) {
		mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
		goto err_cmd;
	}

	mr->enabled = 1;

	mlx4_free_cmd_mailbox(dev, mailbox);

	return 0;

err_cmd:
	mlx4_free_cmd_mailbox(dev, mailbox);

err_table:
	mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_mr_enable);

static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
				int start_index, int npages, u64 *page_list)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	__be64 *mtts;
	dma_addr_t dma_handle;
	int i;
	int s = start_index * sizeof (u64);

	/* All MTTs must fit in the same page */
	if (start_index / (PAGE_SIZE / sizeof (u64)) !=
	    (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64)))
		return -EINVAL;

	if (start_index & (dev->caps.mtts_per_seg - 1))
		return -EINVAL;

	mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg +
				s / dev->caps.mtt_entry_sz, &dma_handle);
	if (!mtts)
		return -ENOMEM;

	dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
				npages * sizeof (u64), DMA_TO_DEVICE);

	for (i = 0; i < npages; ++i)
		mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);

	dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
				   npages * sizeof (u64), DMA_TO_DEVICE);

	return 0;
}

int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   int start_index, int npages, u64 *page_list)
{
	int chunk;
	int err;

	if (mtt->order < 0)
		return -EINVAL;

	while (npages > 0) {
		chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
		err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
		if (err)
			return err;

		npages      -= chunk;
		start_index += chunk;
		page_list   += chunk;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mlx4_write_mtt);

int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		       struct mlx4_buf *buf)
{
	u64 *page_list;
	int err;
	int i;

	page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
	if (!page_list)
		return -ENOMEM;

	for (i = 0; i < buf->npages; ++i)
		if (buf->nbufs == 1)
			page_list[i] = buf->direct.map + (i << buf->page_shift);
		else
			page_list[i] = buf->page_list[i].map;

	err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);

	kfree(page_list);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);

int mlx4_init_mr_table(struct mlx4_dev *dev)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	int err;

	err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
			       ~0, dev->caps.reserved_mrws, 0);
	if (err)
		return err;

	err = mlx4_buddy_init(&mr_table->mtt_buddy,
			      ilog2(dev->caps.num_mtt_segs));
	if (err)
		goto err_buddy;

	if (dev->caps.reserved_mtts) {
		if (mlx4_alloc_mtt_range(dev, fls(dev->caps.reserved_mtts - 1)) == -1) {
			mlx4_warn(dev, "MTT table of order %d is too small.\n",
				  mr_table->mtt_buddy.max_order);
			err = -ENOMEM;
			goto err_reserve_mtts;
		}
	}

	return 0;

err_reserve_mtts:
	mlx4_buddy_cleanup(&mr_table->mtt_buddy);

err_buddy:
	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);

	return err;
}

void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
{
	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;

	mlx4_buddy_cleanup(&mr_table->mtt_buddy);
	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
}

static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
				  int npages, u64 iova)
{
	int i, page_mask;

	if (npages > fmr->max_pages)
		return -EINVAL;

	page_mask = (1 << fmr->page_shift) - 1;

	/* We are getting page lists, so va must be page aligned. */
	if (iova & page_mask)
		return -EINVAL;

	/* Trust the user not to pass misaligned data in page_list */
	if (0)
		for (i = 0; i < npages; ++i) {
			if (page_list[i] & ~page_mask)
				return -EINVAL;
		}

	if (fmr->maps >= fmr->max_maps)
		return -EINVAL;

	return 0;
}

int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
		      int npages, u64 iova, u32 *lkey, u32 *rkey)
{
	u32 key;
	int i, err;

	err = mlx4_check_fmr(fmr, page_list, npages, iova);
	if (err)
		return err;

	++fmr->maps;

	key = key_to_hw_index(fmr->mr.key);
	key += dev->caps.num_mpts;
	*lkey = *rkey = fmr->mr.key = hw_index_to_key(key);

	*(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;

	/* Make sure MPT status is visible before writing MTT entries */
	wmb();

	dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle,
				npages * sizeof(u64), DMA_TO_DEVICE);

	for (i = 0; i < npages; ++i)
		fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);

	dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle,
				   npages * sizeof(u64), DMA_TO_DEVICE);

	fmr->mpt->key    = cpu_to_be32(key);
	fmr->mpt->lkey   = cpu_to_be32(key);
	fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
	fmr->mpt->start  = cpu_to_be64(iova);

	/* Make MTT entries are visible before setting MPT status */
	wmb();

	*(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;

	/* Make sure MPT status is visible before consumer can use FMR */
	wmb();

	return 0;
}
EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);

int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
		   int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	u64 mtt_seg;
	int err = -ENOMEM;

	if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
		return -EINVAL;

	/* All MTTs must fit in the same page */
	if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
		return -EINVAL;

	fmr->page_shift = page_shift;
	fmr->max_pages  = max_pages;
	fmr->max_maps   = max_maps;
	fmr->maps = 0;

	err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
			    page_shift, &fmr->mr);
	if (err)
		return err;

	mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;

	fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
				    fmr->mr.mtt.first_seg,
				    &fmr->dma_handle);
	if (!fmr->mtts) {
		err = -ENOMEM;
		goto err_free;
	}

	return 0;

err_free:
	mlx4_mr_free(dev, &fmr->mr);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);

int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int err;

	err = mlx4_mr_enable(dev, &fmr->mr);
	if (err)
		return err;

	fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
				    key_to_hw_index(fmr->mr.key), NULL);
	if (!fmr->mpt)
		return -ENOMEM;

	return 0;
}
EXPORT_SYMBOL_GPL(mlx4_fmr_enable);

void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
		    u32 *lkey, u32 *rkey)
{
	if (!fmr->maps)
		return;

	fmr->maps = 0;

	*(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
}
EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);

int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
{
	if (fmr->maps)
		return -EBUSY;

	fmr->mr.enabled = 0;
	mlx4_mr_free(dev, &fmr->mr);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx4_fmr_free);

int mlx4_SYNC_TPT(struct mlx4_dev *dev)
{
	return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000,
			MLX4_CMD_WRAPPED);
}
EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);
Commit	Line	Data
225c7b1f RD	1	/*
225c7b1f RD	2	* Copyright (c) 2004 Topspin Communications. All rights reserved.
51a379d0	3	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	4	* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
	33	*/
	34
225c7b1f	35	#include <linux/errno.h>
ee40fa06	36	#include <linux/export.h>
5a0e3ad6	37	#include <linux/slab.h>
225c7b1f RD	38
	39	#include <linux/mlx4/cmd.h>
	40
	41	#include "mlx4.h"
	42	#include "icm.h"
	43
	44	/*
	45	* Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
	46	*/
	47	struct mlx4_mpt_entry {
	48	__be32 flags;
	49	__be32 qpn;
	50	__be32 key;
95d04f07	51	__be32 pd_flags;
225c7b1f RD	52	__be64 start;
	53	__be64 length;
	54	__be32 lkey;
	55	__be32 win_cnt;
	56	u8 reserved1[3];
	57	u8 mtt_rep;
	58	__be64 mtt_seg;
	59	__be32 mtt_sz;
	60	__be32 entity_size;
	61	__be32 first_byte_offset;
ba2d3587	62	} __packed;
225c7b1f RD	63
225c7b1f RD	64	#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
95d04f07	65	#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
225c7b1f RD	66	#define MLX4_MPT_FLAG_MIO (1 << 17)
	67	#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
	68	#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
	69	#define MLX4_MPT_FLAG_REGION (1 << 8)
	70
c9257433 VS	71	#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
c9257433 VS	72	#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
95d04f07 RD	73	#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
95d04f07 RD	74
8ad11fb6 JM	75	#define MLX4_MPT_STATUS_SW 0xF0
	76	#define MLX4_MPT_STATUS_HW 0x00
	77
225c7b1f RD	78	static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
	79	{
	80	int o;
	81	int m;
	82	u32 seg;
	83
	84	spin_lock(&buddy->lock);
	85
e4044cfc RD	86	for (o = order; o <= buddy->max_order; ++o)
	87	if (buddy->num_free[o]) {
	88	m = 1 << (buddy->max_order - o);
	89	seg = find_first_bit(buddy->bits[o], m);
	90	if (seg < m)
	91	goto found;
	92	}
225c7b1f RD	93
	94	spin_unlock(&buddy->lock);
	95	return -1;
	96
	97	found:
	98	clear_bit(seg, buddy->bits[o]);
e4044cfc	99	--buddy->num_free[o];
225c7b1f RD	100
	101	while (o > order) {
	102	--o;
	103	seg <<= 1;
	104	set_bit(seg ^ 1, buddy->bits[o]);
e4044cfc	105	++buddy->num_free[o];
225c7b1f RD	106	}
	107
	108	spin_unlock(&buddy->lock);
	109
	110	seg <<= order;
	111
	112	return seg;
	113	}
	114
	115	static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
	116	{
	117	seg >>= order;
	118
	119	spin_lock(&buddy->lock);
	120
	121	while (test_bit(seg ^ 1, buddy->bits[order])) {
	122	clear_bit(seg ^ 1, buddy->bits[order]);
e4044cfc	123	--buddy->num_free[order];
225c7b1f RD	124	seg >>= 1;
	125	++order;
	126	}
	127
	128	set_bit(seg, buddy->bits[order]);
e4044cfc	129	++buddy->num_free[order];
225c7b1f RD	130
	131	spin_unlock(&buddy->lock);
	132	}
	133
e8f9b2ed	134	static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
225c7b1f RD	135	{
	136	int i, s;
	137
	138	buddy->max_order = max_order;
	139	spin_lock_init(&buddy->lock);
	140
	141	buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
	142	GFP_KERNEL);
a8312755	143	buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
e4044cfc RD	144	GFP_KERNEL);
e4044cfc RD	145	if (!buddy->bits \|\| !buddy->num_free)
225c7b1f RD	146	goto err_out;
	147
	148	for (i = 0; i <= buddy->max_order; ++i) {
	149	s = BITS_TO_LONGS(1 << (buddy->max_order - i));
	150	buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
	151	if (!buddy->bits[i])
	152	goto err_out_free;
	153	bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
	154	}
	155
	156	set_bit(0, buddy->bits[buddy->max_order]);
e4044cfc	157	buddy->num_free[buddy->max_order] = 1;
225c7b1f RD	158
	159	return 0;
	160
	161	err_out_free:
	162	for (i = 0; i <= buddy->max_order; ++i)
	163	kfree(buddy->bits[i]);
	164
e4044cfc	165	err_out:
225c7b1f	166	kfree(buddy->bits);
e4044cfc	167	kfree(buddy->num_free);
225c7b1f	168
225c7b1f RD	169	return -ENOMEM;
	170	}
	171
	172	static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
	173	{
	174	int i;
	175
	176	for (i = 0; i <= buddy->max_order; ++i)
	177	kfree(buddy->bits[i]);
	178
	179	kfree(buddy->bits);
e4044cfc	180	kfree(buddy->num_free);
225c7b1f RD	181	}
	182
	183	static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
	184	{
	185	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	186	u32 seg;
	187
	188	seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
	189	if (seg == -1)
	190	return -1;
	191
	192	if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
	193	seg + (1 << order) - 1)) {
	194	mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
	195	return -1;
	196	}
	197
	198	return seg;
	199	}
	200
	201	int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
	202	struct mlx4_mtt *mtt)
	203	{
	204	int i;
	205
	206	if (!npages) {
	207	mtt->order = -1;
	208	mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
	209	return 0;
	210	} else
	211	mtt->page_shift = page_shift;
	212
ab6bf42e	213	for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1)
225c7b1f RD	214	++mtt->order;
	215
	216	mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
	217	if (mtt->first_seg == -1)
	218	return -ENOMEM;
	219
	220	return 0;
	221	}
	222	EXPORT_SYMBOL_GPL(mlx4_mtt_init);
	223
	224	void mlx4_mtt_cleanup(struct mlx4_dev dev, struct mlx4_mtt mtt)
	225	{
	226	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	227
	228	if (mtt->order < 0)
	229	return;
	230
	231	mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
	232	mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
	233	mtt->first_seg + (1 << mtt->order) - 1);
	234	}
	235	EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
	236
	237	u64 mlx4_mtt_addr(struct mlx4_dev dev, struct mlx4_mtt mtt)
	238	{
	239	return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
	240	}
	241	EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
	242
	243	static u32 hw_index_to_key(u32 ind)
	244	{
	245	return (ind >> 24) \| (ind << 8);
	246	}
	247
	248	static u32 key_to_hw_index(u32 key)
	249	{
	250	return (key << 24) \| (key >> 8);
	251	}
	252
	253	static int mlx4_SW2HW_MPT(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	254	int mpt_index)
	255	{
	256	return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
f9baff50	257	MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
225c7b1f RD	258	}
	259
	260	static int mlx4_HW2SW_MPT(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	261	int mpt_index)
	262	{
	263	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
f9baff50 JM	264	!mailbox, MLX4_CMD_HW2SW_MPT,
f9baff50 JM	265	MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
225c7b1f RD	266	}
	267
	268	int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
	269	int npages, int page_shift, struct mlx4_mr *mr)
	270	{
	271	struct mlx4_priv *priv = mlx4_priv(dev);
	272	u32 index;
	273	int err;
	274
	275	index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
0172e2e1 JM	276	if (index == -1)
0172e2e1 JM	277	return -ENOMEM;
225c7b1f RD	278
	279	mr->iova = iova;
	280	mr->size = size;
	281	mr->pd = pd;
	282	mr->access = access;
	283	mr->enabled = 0;
	284	mr->key = hw_index_to_key(index);
	285
	286	err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
	287	if (err)
0172e2e1	288	mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
225c7b1f	289
225c7b1f RD	290	return err;
	291	}
	292	EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
	293
	294	void mlx4_mr_free(struct mlx4_dev dev, struct mlx4_mr mr)
	295	{
	296	struct mlx4_priv *priv = mlx4_priv(dev);
	297	int err;
	298
	299	if (mr->enabled) {
	300	err = mlx4_HW2SW_MPT(dev, NULL,
	301	key_to_hw_index(mr->key) &
	302	(dev->caps.num_mpts - 1));
	303	if (err)
	304	mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
	305	}
	306
	307	mlx4_mtt_cleanup(dev, &mr->mtt);
	308	mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
	309	}
	310	EXPORT_SYMBOL_GPL(mlx4_mr_free);
	311
	312	int mlx4_mr_enable(struct mlx4_dev dev, struct mlx4_mr mr)
	313	{
	314	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	315	struct mlx4_cmd_mailbox *mailbox;
	316	struct mlx4_mpt_entry *mpt_entry;
	317	int err;
	318
	319	err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	320	if (err)
	321	return err;
	322
	323	mailbox = mlx4_alloc_cmd_mailbox(dev);
	324	if (IS_ERR(mailbox)) {
	325	err = PTR_ERR(mailbox);
	326	goto err_table;
	327	}
	328	mpt_entry = mailbox->buf;
	329
	330	memset(mpt_entry, 0, sizeof *mpt_entry);
	331
95d04f07	332	mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO \|
225c7b1f RD	333	MLX4_MPT_FLAG_REGION \|
225c7b1f RD	334	mr->access);
225c7b1f RD	335
225c7b1f RD	336	mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
95d04f07	337	mpt_entry->pd_flags = cpu_to_be32(mr->pd \| MLX4_MPT_PD_FLAG_EN_INV);
225c7b1f RD	338	mpt_entry->start = cpu_to_be64(mr->iova);
	339	mpt_entry->length = cpu_to_be64(mr->size);
	340	mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
95d04f07	341
b2d9308a JM	342	if (mr->mtt.order < 0) {
	343	mpt_entry->flags \|= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
	344	mpt_entry->mtt_seg = 0;
95d04f07	345	} else {
b2d9308a	346	mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
95d04f07 RD	347	}
	348
	349	if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
	350	/* fast register MR in free state */
	351	mpt_entry->flags \|= cpu_to_be32(MLX4_MPT_FLAG_FREE);
c9257433 VS	352	mpt_entry->pd_flags \|= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG \|
	353	MLX4_MPT_PD_FLAG_RAE);
	354	mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) *
ab6bf42e	355	dev->caps.mtts_per_seg);
95d04f07 RD	356	} else {
	357	mpt_entry->flags \|= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
	358	}
225c7b1f RD	359
	360	err = mlx4_SW2HW_MPT(dev, mailbox,
	361	key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
	362	if (err) {
	363	mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
	364	goto err_cmd;
	365	}
	366
	367	mr->enabled = 1;
	368
	369	mlx4_free_cmd_mailbox(dev, mailbox);
	370
	371	return 0;
	372
	373	err_cmd:
	374	mlx4_free_cmd_mailbox(dev, mailbox);
	375
	376	err_table:
	377	mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
	378	return err;
	379	}
	380	EXPORT_SYMBOL_GPL(mlx4_mr_enable);
	381
d7bb58fb JM	382	static int mlx4_write_mtt_chunk(struct mlx4_dev dev, struct mlx4_mtt mtt,
d7bb58fb JM	383	int start_index, int npages, u64 *page_list)
225c7b1f	384	{
d7bb58fb JM	385	struct mlx4_priv *priv = mlx4_priv(dev);
	386	__be64 *mtts;
	387	dma_addr_t dma_handle;
	388	int i;
	389	int s = start_index * sizeof (u64);
	390
	391	/* All MTTs must fit in the same page */
	392	if (start_index / (PAGE_SIZE / sizeof (u64)) !=
	393	(start_index + npages - 1) / (PAGE_SIZE / sizeof (u64)))
	394	return -EINVAL;
	395
ab6bf42e	396	if (start_index & (dev->caps.mtts_per_seg - 1))
d7bb58fb JM	397	return -EINVAL;
	398
	399	mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg +
	400	s / dev->caps.mtt_entry_sz, &dma_handle);
	401	if (!mtts)
	402	return -ENOMEM;
	403
e727f5cd RD	404	dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
	405	npages * sizeof (u64), DMA_TO_DEVICE);
	406
d7bb58fb JM	407	for (i = 0; i < npages; ++i)
	408	mtts[i] = cpu_to_be64(page_list[i] \| MLX4_MTT_FLAG_PRESENT);
	409
e727f5cd RD	410	dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
e727f5cd RD	411	npages * sizeof (u64), DMA_TO_DEVICE);
d7bb58fb JM	412
d7bb58fb JM	413	return 0;
225c7b1f RD	414	}
	415
	416	int mlx4_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	417	int start_index, int npages, u64 *page_list)
	418	{
d7bb58fb JM	419	int chunk;
d7bb58fb JM	420	int err;
225c7b1f RD	421
	422	if (mtt->order < 0)
	423	return -EINVAL;
	424
225c7b1f	425	while (npages > 0) {
d7bb58fb JM	426	chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
d7bb58fb JM	427	err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
225c7b1f	428	if (err)
d7bb58fb	429	return err;
225c7b1f	430
d7bb58fb JM	431	npages -= chunk;
	432	start_index += chunk;
	433	page_list += chunk;
225c7b1f RD	434	}
225c7b1f RD	435
d7bb58fb	436	return 0;
225c7b1f RD	437	}
	438	EXPORT_SYMBOL_GPL(mlx4_write_mtt);
	439
	440	int mlx4_buf_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	441	struct mlx4_buf *buf)
	442	{
	443	u64 *page_list;
	444	int err;
	445	int i;
	446
	447	page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
	448	if (!page_list)
	449	return -ENOMEM;
	450
	451	for (i = 0; i < buf->npages; ++i)
	452	if (buf->nbufs == 1)
b57aacfa	453	page_list[i] = buf->direct.map + (i << buf->page_shift);
225c7b1f	454	else
b57aacfa	455	page_list[i] = buf->page_list[i].map;
225c7b1f RD	456
	457	err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
	458
	459	kfree(page_list);
	460	return err;
	461	}
	462	EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
	463
3d73c288	464	int mlx4_init_mr_table(struct mlx4_dev *dev)
225c7b1f RD	465	{
	466	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	467	int err;
	468
	469	err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
93fc9e1b	470	~0, dev->caps.reserved_mrws, 0);
225c7b1f RD	471	if (err)
	472	return err;
	473
	474	err = mlx4_buddy_init(&mr_table->mtt_buddy,
	475	ilog2(dev->caps.num_mtt_segs));
	476	if (err)
	477	goto err_buddy;
	478
	479	if (dev->caps.reserved_mtts) {
cf78237d	480	if (mlx4_alloc_mtt_range(dev, fls(dev->caps.reserved_mtts - 1)) == -1) {
225c7b1f RD	481	mlx4_warn(dev, "MTT table of order %d is too small.\n",
	482	mr_table->mtt_buddy.max_order);
	483	err = -ENOMEM;
	484	goto err_reserve_mtts;
	485	}
	486	}
	487
	488	return 0;
	489
	490	err_reserve_mtts:
	491	mlx4_buddy_cleanup(&mr_table->mtt_buddy);
	492
	493	err_buddy:
	494	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
	495
	496	return err;
	497	}
	498
	499	void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
	500	{
	501	struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
	502
	503	mlx4_buddy_cleanup(&mr_table->mtt_buddy);
	504	mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
	505	}
8ad11fb6 JM	506
	507	static inline int mlx4_check_fmr(struct mlx4_fmr fmr, u64 page_list,
	508	int npages, u64 iova)
	509	{
	510	int i, page_mask;
	511
	512	if (npages > fmr->max_pages)
	513	return -EINVAL;
	514
	515	page_mask = (1 << fmr->page_shift) - 1;
	516
	517	/* We are getting page lists, so va must be page aligned. */
	518	if (iova & page_mask)
	519	return -EINVAL;
	520
	521	/* Trust the user not to pass misaligned data in page_list */
	522	if (0)
	523	for (i = 0; i < npages; ++i) {
	524	if (page_list[i] & ~page_mask)
	525	return -EINVAL;
	526	}
	527
	528	if (fmr->maps >= fmr->max_maps)
	529	return -EINVAL;
	530
	531	return 0;
	532	}
	533
	534	int mlx4_map_phys_fmr(struct mlx4_dev dev, struct mlx4_fmr fmr, u64 *page_list,
	535	int npages, u64 iova, u32 lkey, u32 rkey)
	536	{
	537	u32 key;
	538	int i, err;
	539
	540	err = mlx4_check_fmr(fmr, page_list, npages, iova);
	541	if (err)
	542	return err;
	543
	544	++fmr->maps;
	545
	546	key = key_to_hw_index(fmr->mr.key);
	547	key += dev->caps.num_mpts;
	548	lkey = rkey = fmr->mr.key = hw_index_to_key(key);
	549
	550	(u8 ) fmr->mpt = MLX4_MPT_STATUS_SW;
	551
	552	/* Make sure MPT status is visible before writing MTT entries */
	553	wmb();
	554
e727f5cd RD	555	dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle,
	556	npages * sizeof(u64), DMA_TO_DEVICE);
	557
8ad11fb6 JM	558	for (i = 0; i < npages; ++i)
	559	fmr->mtts[i] = cpu_to_be64(page_list[i] \| MLX4_MTT_FLAG_PRESENT);
	560
e727f5cd RD	561	dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle,
e727f5cd RD	562	npages * sizeof(u64), DMA_TO_DEVICE);
8ad11fb6 JM	563
	564	fmr->mpt->key = cpu_to_be32(key);
	565	fmr->mpt->lkey = cpu_to_be32(key);
	566	fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
	567	fmr->mpt->start = cpu_to_be64(iova);
	568
	569	/* Make MTT entries are visible before setting MPT status */
	570	wmb();
	571
	572	(u8 ) fmr->mpt = MLX4_MPT_STATUS_HW;
	573
	574	/* Make sure MPT status is visible before consumer can use FMR */
	575	wmb();
	576
	577	return 0;
	578	}
	579	EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
	580
	581	int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
	582	int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
	583	{
	584	struct mlx4_priv *priv = mlx4_priv(dev);
	585	u64 mtt_seg;
	586	int err = -ENOMEM;
	587
c5057ddc	588	if (page_shift < (ffs(dev->caps.page_size_cap) - 1) \|\| page_shift >= 32)
8ad11fb6 JM	589	return -EINVAL;
	590
	591	/* All MTTs must fit in the same page */
	592	if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
	593	return -EINVAL;
	594
	595	fmr->page_shift = page_shift;
	596	fmr->max_pages = max_pages;
	597	fmr->max_maps = max_maps;
	598	fmr->maps = 0;
	599
	600	err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
	601	page_shift, &fmr->mr);
	602	if (err)
	603	return err;
	604
	605	mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
	606
	607	fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
	608	fmr->mr.mtt.first_seg,
	609	&fmr->dma_handle);
	610	if (!fmr->mtts) {
	611	err = -ENOMEM;
	612	goto err_free;
	613	}
	614
8ad11fb6 JM	615	return 0;
	616
	617	err_free:
	618	mlx4_mr_free(dev, &fmr->mr);
	619	return err;
	620	}
	621	EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
	622
	623	int mlx4_fmr_enable(struct mlx4_dev dev, struct mlx4_fmr fmr)
	624	{
11e75a74 JM	625	struct mlx4_priv *priv = mlx4_priv(dev);
	626	int err;
	627
	628	err = mlx4_mr_enable(dev, &fmr->mr);
	629	if (err)
	630	return err;
	631
	632	fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
	633	key_to_hw_index(fmr->mr.key), NULL);
	634	if (!fmr->mpt)
	635	return -ENOMEM;
	636
	637	return 0;
8ad11fb6 JM	638	}
	639	EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
	640
	641	void mlx4_fmr_unmap(struct mlx4_dev dev, struct mlx4_fmr fmr,
	642	u32 lkey, u32 rkey)
	643	{
8ad11fb6 JM	644	if (!fmr->maps)
	645	return;
	646
8ad11fb6 JM	647	fmr->maps = 0;
	648
	649	(u8 ) fmr->mpt = MLX4_MPT_STATUS_SW;
	650	}
	651	EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
	652
	653	int mlx4_fmr_free(struct mlx4_dev dev, struct mlx4_fmr fmr)
	654	{
	655	if (fmr->maps)
	656	return -EBUSY;
	657
	658	fmr->mr.enabled = 0;
	659	mlx4_mr_free(dev, &fmr->mr);
	660
	661	return 0;
	662	}
	663	EXPORT_SYMBOL_GPL(mlx4_fmr_free);
	664
	665	int mlx4_SYNC_TPT(struct mlx4_dev *dev)
	666	{
f9baff50 JM	667	return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000,
f9baff50 JM	668	MLX4_CMD_WRAPPED);
8ad11fb6 JM	669	}
8ad11fb6 JM	670	EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);