Commit | Line | Data |
---|---|---|
2a2336f8 YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/errno.h> | |
34 | #include <linux/if_ether.h> | |
ee40fa06 | 35 | #include <linux/export.h> |
2a2336f8 YP |
36 | |
37 | #include <linux/mlx4/cmd.h> | |
38 | ||
39 | #include "mlx4.h" | |
40 | ||
41 | #define MLX4_MAC_VALID (1ull << 63) | |
42 | #define MLX4_MAC_MASK 0xffffffffffffULL | |
43 | ||
44 | #define MLX4_VLAN_VALID (1u << 31) | |
45 | #define MLX4_VLAN_MASK 0xfff | |
46 | ||
93ece0c1 EE |
47 | #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL |
48 | #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL | |
49 | #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL | |
50 | #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL | |
51 | ||
2a2336f8 YP |
52 | void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table) |
53 | { | |
54 | int i; | |
55 | ||
56 | mutex_init(&table->mutex); | |
57 | for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { | |
58 | table->entries[i] = 0; | |
59 | table->refs[i] = 0; | |
60 | } | |
61 | table->max = 1 << dev->caps.log_num_macs; | |
62 | table->total = 0; | |
63 | } | |
64 | ||
65 | void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table) | |
66 | { | |
67 | int i; | |
68 | ||
69 | mutex_init(&table->mutex); | |
70 | for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) { | |
71 | table->entries[i] = 0; | |
72 | table->refs[i] = 0; | |
73 | } | |
e72ebf5a | 74 | table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR; |
2a2336f8 YP |
75 | table->total = 0; |
76 | } | |
77 | ||
0ff1fb65 HHZ |
78 | static int mlx4_uc_steer_add(struct mlx4_dev *dev, u8 port, |
79 | u64 mac, int *qpn, u64 *reg_id) | |
2a2336f8 | 80 | { |
2ab573c5 | 81 | __be64 be_mac; |
1679200f YP |
82 | int err; |
83 | ||
0ff1fb65 | 84 | mac &= MLX4_MAC_MASK; |
2ab573c5 | 85 | be_mac = cpu_to_be64(mac << 16); |
1679200f | 86 | |
0ff1fb65 HHZ |
87 | switch (dev->caps.steering_mode) { |
88 | case MLX4_STEERING_MODE_B0: { | |
89 | struct mlx4_qp qp; | |
90 | u8 gid[16] = {0}; | |
91 | ||
92 | qp.qpn = *qpn; | |
93 | memcpy(&gid[10], &be_mac, ETH_ALEN); | |
94 | gid[5] = port; | |
95 | ||
96 | err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH); | |
97 | break; | |
98 | } | |
99 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
100 | struct mlx4_spec_list spec_eth = { {NULL} }; | |
101 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); | |
102 | ||
103 | struct mlx4_net_trans_rule rule = { | |
104 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
105 | .exclusive = 0, | |
106 | .allow_loopback = 1, | |
107 | .promisc_mode = MLX4_FS_PROMISC_NONE, | |
108 | .priority = MLX4_DOMAIN_NIC, | |
109 | }; | |
110 | ||
111 | rule.port = port; | |
112 | rule.qpn = *qpn; | |
113 | INIT_LIST_HEAD(&rule.list); | |
114 | ||
115 | spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH; | |
116 | memcpy(spec_eth.eth.dst_mac, &be_mac, ETH_ALEN); | |
117 | memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN); | |
118 | list_add_tail(&spec_eth.list, &rule.list); | |
119 | ||
120 | err = mlx4_flow_attach(dev, &rule, reg_id); | |
121 | break; | |
122 | } | |
123 | default: | |
124 | return -EINVAL; | |
125 | } | |
ffe455ad EE |
126 | if (err) |
127 | mlx4_warn(dev, "Failed Attaching Unicast\n"); | |
1679200f YP |
128 | |
129 | return err; | |
130 | } | |
131 | ||
132 | static void mlx4_uc_steer_release(struct mlx4_dev *dev, u8 port, | |
0ff1fb65 | 133 | u64 mac, int qpn, u64 reg_id) |
1679200f | 134 | { |
0ff1fb65 HHZ |
135 | switch (dev->caps.steering_mode) { |
136 | case MLX4_STEERING_MODE_B0: { | |
137 | struct mlx4_qp qp; | |
138 | u8 gid[16] = {0}; | |
139 | __be64 be_mac; | |
140 | ||
141 | qp.qpn = qpn; | |
142 | mac &= MLX4_MAC_MASK; | |
143 | be_mac = cpu_to_be64(mac << 16); | |
144 | memcpy(&gid[10], &be_mac, ETH_ALEN); | |
145 | gid[5] = port; | |
146 | ||
147 | mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH); | |
148 | break; | |
149 | } | |
150 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
151 | mlx4_flow_detach(dev, reg_id); | |
152 | break; | |
153 | } | |
154 | default: | |
155 | mlx4_err(dev, "Invalid steering mode.\n"); | |
156 | } | |
ffe455ad EE |
157 | } |
158 | ||
159 | static int validate_index(struct mlx4_dev *dev, | |
160 | struct mlx4_mac_table *table, int index) | |
161 | { | |
162 | int err = 0; | |
163 | ||
164 | if (index < 0 || index >= table->max || !table->entries[index]) { | |
165 | mlx4_warn(dev, "No valid Mac entry for the given index\n"); | |
166 | err = -EINVAL; | |
167 | } | |
168 | return err; | |
169 | } | |
170 | ||
171 | static int find_index(struct mlx4_dev *dev, | |
172 | struct mlx4_mac_table *table, u64 mac) | |
173 | { | |
174 | int i; | |
175 | ||
176 | for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { | |
177 | if ((mac & MLX4_MAC_MASK) == | |
178 | (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) | |
179 | return i; | |
180 | } | |
181 | /* Mac not found */ | |
182 | return -EINVAL; | |
1679200f YP |
183 | } |
184 | ||
ffe455ad | 185 | int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn) |
1679200f YP |
186 | { |
187 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
1679200f | 188 | struct mlx4_mac_entry *entry; |
ffe455ad EE |
189 | int index = 0; |
190 | int err = 0; | |
0ff1fb65 | 191 | u64 reg_id; |
2a2336f8 | 192 | |
ffe455ad EE |
193 | mlx4_dbg(dev, "Registering MAC: 0x%llx for adding\n", |
194 | (unsigned long long) mac); | |
195 | index = mlx4_register_mac(dev, port, mac); | |
196 | if (index < 0) { | |
197 | err = index; | |
198 | mlx4_err(dev, "Failed adding MAC: 0x%llx\n", | |
199 | (unsigned long long) mac); | |
200 | return err; | |
201 | } | |
0f6740c7 | 202 | |
c96d97f4 | 203 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) { |
ffe455ad EE |
204 | *qpn = info->base_qpn + index; |
205 | return 0; | |
206 | } | |
207 | ||
208 | err = mlx4_qp_reserve_range(dev, 1, 1, qpn); | |
209 | mlx4_dbg(dev, "Reserved qp %d\n", *qpn); | |
210 | if (err) { | |
211 | mlx4_err(dev, "Failed to reserve qp for mac registration\n"); | |
212 | goto qp_err; | |
213 | } | |
214 | ||
0ff1fb65 | 215 | err = mlx4_uc_steer_add(dev, port, mac, qpn, ®_id); |
ffe455ad EE |
216 | if (err) |
217 | goto steer_err; | |
218 | ||
219 | entry = kmalloc(sizeof *entry, GFP_KERNEL); | |
220 | if (!entry) { | |
221 | err = -ENOMEM; | |
222 | goto alloc_err; | |
223 | } | |
224 | entry->mac = mac; | |
0ff1fb65 | 225 | entry->reg_id = reg_id; |
ffe455ad EE |
226 | err = radix_tree_insert(&info->mac_tree, *qpn, entry); |
227 | if (err) | |
228 | goto insert_err; | |
229 | return 0; | |
230 | ||
231 | insert_err: | |
232 | kfree(entry); | |
233 | ||
234 | alloc_err: | |
0ff1fb65 | 235 | mlx4_uc_steer_release(dev, port, mac, *qpn, reg_id); |
ffe455ad EE |
236 | |
237 | steer_err: | |
238 | mlx4_qp_release_range(dev, *qpn, 1); | |
0f6740c7 | 239 | |
ffe455ad EE |
240 | qp_err: |
241 | mlx4_unregister_mac(dev, port, mac); | |
242 | return err; | |
243 | } | |
244 | EXPORT_SYMBOL_GPL(mlx4_get_eth_qp); | |
245 | ||
246 | void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn) | |
247 | { | |
248 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
249 | struct mlx4_mac_entry *entry; | |
250 | ||
251 | mlx4_dbg(dev, "Registering MAC: 0x%llx for deleting\n", | |
252 | (unsigned long long) mac); | |
253 | mlx4_unregister_mac(dev, port, mac); | |
254 | ||
c96d97f4 | 255 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) { |
ffe455ad EE |
256 | entry = radix_tree_lookup(&info->mac_tree, qpn); |
257 | if (entry) { | |
258 | mlx4_dbg(dev, "Releasing qp: port %d, mac 0x%llx," | |
259 | " qpn %d\n", port, | |
260 | (unsigned long long) mac, qpn); | |
0ff1fb65 HHZ |
261 | mlx4_uc_steer_release(dev, port, entry->mac, |
262 | qpn, entry->reg_id); | |
ffe455ad EE |
263 | mlx4_qp_release_range(dev, qpn, 1); |
264 | radix_tree_delete(&info->mac_tree, qpn); | |
0f6740c7 | 265 | kfree(entry); |
0f6740c7 | 266 | } |
1679200f | 267 | } |
ffe455ad EE |
268 | } |
269 | EXPORT_SYMBOL_GPL(mlx4_put_eth_qp); | |
270 | ||
271 | static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port, | |
272 | __be64 *entries) | |
273 | { | |
274 | struct mlx4_cmd_mailbox *mailbox; | |
275 | u32 in_mod; | |
276 | int err; | |
277 | ||
278 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
279 | if (IS_ERR(mailbox)) | |
280 | return PTR_ERR(mailbox); | |
281 | ||
282 | memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE); | |
283 | ||
284 | in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port; | |
0f6740c7 | 285 | |
ffe455ad EE |
286 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, |
287 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
288 | ||
289 | mlx4_free_cmd_mailbox(dev, mailbox); | |
290 | return err; | |
291 | } | |
292 | ||
293 | int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac) | |
294 | { | |
295 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
296 | struct mlx4_mac_table *table = &info->mac_table; | |
297 | int i, err = 0; | |
298 | int free = -1; | |
299 | ||
300 | mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n", | |
301 | (unsigned long long) mac, port); | |
0f6740c7 | 302 | |
2a2336f8 | 303 | mutex_lock(&table->mutex); |
ffe455ad EE |
304 | for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { |
305 | if (free < 0 && !table->entries[i]) { | |
2a2336f8 YP |
306 | free = i; |
307 | continue; | |
308 | } | |
309 | ||
310 | if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) { | |
ffe455ad EE |
311 | /* MAC already registered, Must not have duplicates */ |
312 | err = -EEXIST; | |
2a2336f8 YP |
313 | goto out; |
314 | } | |
315 | } | |
0926f910 | 316 | |
2a2336f8 YP |
317 | mlx4_dbg(dev, "Free MAC index is %d\n", free); |
318 | ||
319 | if (table->total == table->max) { | |
320 | /* No free mac entries */ | |
321 | err = -ENOSPC; | |
322 | goto out; | |
323 | } | |
324 | ||
325 | /* Register new MAC */ | |
2a2336f8 YP |
326 | table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID); |
327 | ||
328 | err = mlx4_set_port_mac_table(dev, port, table->entries); | |
329 | if (unlikely(err)) { | |
ffe455ad EE |
330 | mlx4_err(dev, "Failed adding MAC: 0x%llx\n", |
331 | (unsigned long long) mac); | |
2a2336f8 YP |
332 | table->entries[free] = 0; |
333 | goto out; | |
334 | } | |
335 | ||
ffe455ad | 336 | err = free; |
2a2336f8 YP |
337 | ++table->total; |
338 | out: | |
339 | mutex_unlock(&table->mutex); | |
340 | return err; | |
341 | } | |
ffe455ad | 342 | EXPORT_SYMBOL_GPL(__mlx4_register_mac); |
2a2336f8 | 343 | |
ffe455ad | 344 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac) |
2a2336f8 | 345 | { |
ffe455ad EE |
346 | u64 out_param; |
347 | int err; | |
2a2336f8 | 348 | |
ffe455ad EE |
349 | if (mlx4_is_mfunc(dev)) { |
350 | set_param_l(&out_param, port); | |
351 | err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC, | |
352 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES, | |
353 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
354 | if (err) | |
355 | return err; | |
1679200f | 356 | |
ffe455ad | 357 | return get_param_l(&out_param); |
1679200f | 358 | } |
ffe455ad | 359 | return __mlx4_register_mac(dev, port, mac); |
1679200f | 360 | } |
ffe455ad EE |
361 | EXPORT_SYMBOL_GPL(mlx4_register_mac); |
362 | ||
1679200f | 363 | |
ffe455ad | 364 | void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac) |
1679200f YP |
365 | { |
366 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
367 | struct mlx4_mac_table *table = &info->mac_table; | |
ffe455ad | 368 | int index; |
1679200f | 369 | |
ffe455ad | 370 | index = find_index(dev, table, mac); |
1679200f YP |
371 | |
372 | mutex_lock(&table->mutex); | |
373 | ||
374 | if (validate_index(dev, table, index)) | |
375 | goto out; | |
376 | ||
ffe455ad EE |
377 | table->entries[index] = 0; |
378 | mlx4_set_port_mac_table(dev, port, table->entries); | |
379 | --table->total; | |
2a2336f8 YP |
380 | out: |
381 | mutex_unlock(&table->mutex); | |
382 | } | |
ffe455ad EE |
383 | EXPORT_SYMBOL_GPL(__mlx4_unregister_mac); |
384 | ||
385 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac) | |
386 | { | |
387 | u64 out_param; | |
ffe455ad EE |
388 | |
389 | if (mlx4_is_mfunc(dev)) { | |
390 | set_param_l(&out_param, port); | |
162344ed OG |
391 | (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC, |
392 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES, | |
393 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
ffe455ad EE |
394 | return; |
395 | } | |
396 | __mlx4_unregister_mac(dev, port, mac); | |
397 | return; | |
398 | } | |
2a2336f8 YP |
399 | EXPORT_SYMBOL_GPL(mlx4_unregister_mac); |
400 | ||
ffe455ad | 401 | int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac) |
1679200f YP |
402 | { |
403 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
404 | struct mlx4_mac_table *table = &info->mac_table; | |
1679200f | 405 | struct mlx4_mac_entry *entry; |
ffe455ad EE |
406 | int index = qpn - info->base_qpn; |
407 | int err = 0; | |
1679200f | 408 | |
c96d97f4 | 409 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) { |
1679200f YP |
410 | entry = radix_tree_lookup(&info->mac_tree, qpn); |
411 | if (!entry) | |
412 | return -EINVAL; | |
0ff1fb65 HHZ |
413 | mlx4_uc_steer_release(dev, port, entry->mac, |
414 | qpn, entry->reg_id); | |
ffe455ad | 415 | mlx4_unregister_mac(dev, port, entry->mac); |
1679200f | 416 | entry->mac = new_mac; |
0ff1fb65 | 417 | entry->reg_id = 0; |
ffe455ad | 418 | mlx4_register_mac(dev, port, new_mac); |
0ff1fb65 HHZ |
419 | err = mlx4_uc_steer_add(dev, port, entry->mac, |
420 | &qpn, &entry->reg_id); | |
ffe455ad | 421 | return err; |
1679200f YP |
422 | } |
423 | ||
ffe455ad | 424 | /* CX1 doesn't support multi-functions */ |
1679200f YP |
425 | mutex_lock(&table->mutex); |
426 | ||
427 | err = validate_index(dev, table, index); | |
428 | if (err) | |
429 | goto out; | |
430 | ||
431 | table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID); | |
432 | ||
433 | err = mlx4_set_port_mac_table(dev, port, table->entries); | |
434 | if (unlikely(err)) { | |
ffe455ad EE |
435 | mlx4_err(dev, "Failed adding MAC: 0x%llx\n", |
436 | (unsigned long long) new_mac); | |
1679200f YP |
437 | table->entries[index] = 0; |
438 | } | |
439 | out: | |
440 | mutex_unlock(&table->mutex); | |
441 | return err; | |
442 | } | |
443 | EXPORT_SYMBOL_GPL(mlx4_replace_mac); | |
ffe455ad | 444 | |
2a2336f8 YP |
445 | static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port, |
446 | __be32 *entries) | |
447 | { | |
448 | struct mlx4_cmd_mailbox *mailbox; | |
449 | u32 in_mod; | |
450 | int err; | |
451 | ||
452 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
453 | if (IS_ERR(mailbox)) | |
454 | return PTR_ERR(mailbox); | |
455 | ||
456 | memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE); | |
457 | in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port; | |
458 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
f9baff50 | 459 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); |
2a2336f8 YP |
460 | |
461 | mlx4_free_cmd_mailbox(dev, mailbox); | |
462 | ||
463 | return err; | |
464 | } | |
465 | ||
4c3eb3ca EC |
466 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx) |
467 | { | |
468 | struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; | |
469 | int i; | |
470 | ||
471 | for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) { | |
472 | if (table->refs[i] && | |
473 | (vid == (MLX4_VLAN_MASK & | |
474 | be32_to_cpu(table->entries[i])))) { | |
475 | /* VLAN already registered, increase reference count */ | |
476 | *idx = i; | |
477 | return 0; | |
478 | } | |
479 | } | |
480 | ||
481 | return -ENOENT; | |
482 | } | |
483 | EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan); | |
484 | ||
ffe455ad EE |
485 | static int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, |
486 | int *index) | |
2a2336f8 YP |
487 | { |
488 | struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; | |
489 | int i, err = 0; | |
490 | int free = -1; | |
491 | ||
492 | mutex_lock(&table->mutex); | |
e72ebf5a YP |
493 | |
494 | if (table->total == table->max) { | |
495 | /* No free vlan entries */ | |
496 | err = -ENOSPC; | |
497 | goto out; | |
498 | } | |
499 | ||
2a2336f8 YP |
500 | for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) { |
501 | if (free < 0 && (table->refs[i] == 0)) { | |
502 | free = i; | |
503 | continue; | |
504 | } | |
505 | ||
506 | if (table->refs[i] && | |
507 | (vlan == (MLX4_VLAN_MASK & | |
508 | be32_to_cpu(table->entries[i])))) { | |
25985edc | 509 | /* Vlan already registered, increase references count */ |
2a2336f8 YP |
510 | *index = i; |
511 | ++table->refs[i]; | |
512 | goto out; | |
513 | } | |
514 | } | |
515 | ||
0926f910 EC |
516 | if (free < 0) { |
517 | err = -ENOMEM; | |
518 | goto out; | |
519 | } | |
520 | ||
ffe455ad | 521 | /* Register new VLAN */ |
2a2336f8 YP |
522 | table->refs[free] = 1; |
523 | table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID); | |
524 | ||
525 | err = mlx4_set_port_vlan_table(dev, port, table->entries); | |
526 | if (unlikely(err)) { | |
527 | mlx4_warn(dev, "Failed adding vlan: %u\n", vlan); | |
528 | table->refs[free] = 0; | |
529 | table->entries[free] = 0; | |
530 | goto out; | |
531 | } | |
532 | ||
533 | *index = free; | |
534 | ++table->total; | |
535 | out: | |
536 | mutex_unlock(&table->mutex); | |
537 | return err; | |
538 | } | |
ffe455ad EE |
539 | |
540 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index) | |
541 | { | |
542 | u64 out_param; | |
543 | int err; | |
544 | ||
545 | if (mlx4_is_mfunc(dev)) { | |
546 | set_param_l(&out_param, port); | |
547 | err = mlx4_cmd_imm(dev, vlan, &out_param, RES_VLAN, | |
548 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES, | |
549 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
550 | if (!err) | |
551 | *index = get_param_l(&out_param); | |
552 | ||
553 | return err; | |
554 | } | |
555 | return __mlx4_register_vlan(dev, port, vlan, index); | |
556 | } | |
2a2336f8 YP |
557 | EXPORT_SYMBOL_GPL(mlx4_register_vlan); |
558 | ||
ffe455ad | 559 | static void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index) |
2a2336f8 YP |
560 | { |
561 | struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; | |
562 | ||
563 | if (index < MLX4_VLAN_REGULAR) { | |
564 | mlx4_warn(dev, "Trying to free special vlan index %d\n", index); | |
565 | return; | |
566 | } | |
567 | ||
568 | mutex_lock(&table->mutex); | |
569 | if (!table->refs[index]) { | |
570 | mlx4_warn(dev, "No vlan entry for index %d\n", index); | |
571 | goto out; | |
572 | } | |
573 | if (--table->refs[index]) { | |
574 | mlx4_dbg(dev, "Have more references for index %d," | |
575 | "no need to modify vlan table\n", index); | |
576 | goto out; | |
577 | } | |
578 | table->entries[index] = 0; | |
579 | mlx4_set_port_vlan_table(dev, port, table->entries); | |
580 | --table->total; | |
581 | out: | |
582 | mutex_unlock(&table->mutex); | |
583 | } | |
ffe455ad EE |
584 | |
585 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index) | |
586 | { | |
587 | u64 in_param; | |
588 | int err; | |
589 | ||
590 | if (mlx4_is_mfunc(dev)) { | |
591 | set_param_l(&in_param, port); | |
592 | err = mlx4_cmd(dev, in_param, RES_VLAN, RES_OP_RESERVE_AND_MAP, | |
593 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
594 | MLX4_CMD_WRAPPED); | |
595 | if (!err) | |
596 | mlx4_warn(dev, "Failed freeing vlan at index:%d\n", | |
597 | index); | |
598 | ||
599 | return; | |
600 | } | |
601 | __mlx4_unregister_vlan(dev, port, index); | |
602 | } | |
2a2336f8 | 603 | EXPORT_SYMBOL_GPL(mlx4_unregister_vlan); |
7ff93f8b | 604 | |
9a5aa622 JM |
605 | int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps) |
606 | { | |
607 | struct mlx4_cmd_mailbox *inmailbox, *outmailbox; | |
608 | u8 *inbuf, *outbuf; | |
609 | int err; | |
610 | ||
611 | inmailbox = mlx4_alloc_cmd_mailbox(dev); | |
612 | if (IS_ERR(inmailbox)) | |
613 | return PTR_ERR(inmailbox); | |
614 | ||
615 | outmailbox = mlx4_alloc_cmd_mailbox(dev); | |
616 | if (IS_ERR(outmailbox)) { | |
617 | mlx4_free_cmd_mailbox(dev, inmailbox); | |
618 | return PTR_ERR(outmailbox); | |
619 | } | |
620 | ||
621 | inbuf = inmailbox->buf; | |
622 | outbuf = outmailbox->buf; | |
623 | memset(inbuf, 0, 256); | |
624 | memset(outbuf, 0, 256); | |
625 | inbuf[0] = 1; | |
626 | inbuf[1] = 1; | |
627 | inbuf[2] = 1; | |
628 | inbuf[3] = 1; | |
629 | *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015); | |
630 | *(__be32 *) (&inbuf[20]) = cpu_to_be32(port); | |
631 | ||
632 | err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3, | |
f9baff50 JM |
633 | MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, |
634 | MLX4_CMD_NATIVE); | |
9a5aa622 JM |
635 | if (!err) |
636 | *caps = *(__be32 *) (outbuf + 84); | |
637 | mlx4_free_cmd_mailbox(dev, inmailbox); | |
638 | mlx4_free_cmd_mailbox(dev, outmailbox); | |
639 | return err; | |
640 | } | |
641 | ||
ffe455ad EE |
642 | static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod, |
643 | u8 op_mod, struct mlx4_cmd_mailbox *inbox) | |
644 | { | |
645 | struct mlx4_priv *priv = mlx4_priv(dev); | |
646 | struct mlx4_port_info *port_info; | |
647 | struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master; | |
648 | struct mlx4_slave_state *slave_st = &master->slave_state[slave]; | |
649 | struct mlx4_set_port_rqp_calc_context *qpn_context; | |
650 | struct mlx4_set_port_general_context *gen_context; | |
651 | int reset_qkey_viols; | |
652 | int port; | |
653 | int is_eth; | |
654 | u32 in_modifier; | |
655 | u32 promisc; | |
656 | u16 mtu, prev_mtu; | |
657 | int err; | |
658 | int i; | |
659 | __be32 agg_cap_mask; | |
660 | __be32 slave_cap_mask; | |
661 | __be32 new_cap_mask; | |
662 | ||
663 | port = in_mod & 0xff; | |
664 | in_modifier = in_mod >> 8; | |
665 | is_eth = op_mod; | |
666 | port_info = &priv->port[port]; | |
667 | ||
668 | /* Slaves cannot perform SET_PORT operations except changing MTU */ | |
669 | if (is_eth) { | |
670 | if (slave != dev->caps.function && | |
671 | in_modifier != MLX4_SET_PORT_GENERAL) { | |
672 | mlx4_warn(dev, "denying SET_PORT for slave:%d\n", | |
673 | slave); | |
674 | return -EINVAL; | |
675 | } | |
676 | switch (in_modifier) { | |
677 | case MLX4_SET_PORT_RQP_CALC: | |
678 | qpn_context = inbox->buf; | |
679 | qpn_context->base_qpn = | |
680 | cpu_to_be32(port_info->base_qpn); | |
681 | qpn_context->n_mac = 0x7; | |
682 | promisc = be32_to_cpu(qpn_context->promisc) >> | |
683 | SET_PORT_PROMISC_SHIFT; | |
684 | qpn_context->promisc = cpu_to_be32( | |
685 | promisc << SET_PORT_PROMISC_SHIFT | | |
686 | port_info->base_qpn); | |
687 | promisc = be32_to_cpu(qpn_context->mcast) >> | |
688 | SET_PORT_MC_PROMISC_SHIFT; | |
689 | qpn_context->mcast = cpu_to_be32( | |
690 | promisc << SET_PORT_MC_PROMISC_SHIFT | | |
691 | port_info->base_qpn); | |
692 | break; | |
693 | case MLX4_SET_PORT_GENERAL: | |
694 | gen_context = inbox->buf; | |
695 | /* Mtu is configured as the max MTU among all the | |
696 | * the functions on the port. */ | |
697 | mtu = be16_to_cpu(gen_context->mtu); | |
698 | mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port]); | |
699 | prev_mtu = slave_st->mtu[port]; | |
700 | slave_st->mtu[port] = mtu; | |
701 | if (mtu > master->max_mtu[port]) | |
702 | master->max_mtu[port] = mtu; | |
703 | if (mtu < prev_mtu && prev_mtu == | |
704 | master->max_mtu[port]) { | |
705 | slave_st->mtu[port] = mtu; | |
706 | master->max_mtu[port] = mtu; | |
707 | for (i = 0; i < dev->num_slaves; i++) { | |
708 | master->max_mtu[port] = | |
709 | max(master->max_mtu[port], | |
710 | master->slave_state[i].mtu[port]); | |
711 | } | |
712 | } | |
713 | ||
714 | gen_context->mtu = cpu_to_be16(master->max_mtu[port]); | |
715 | break; | |
716 | } | |
717 | return mlx4_cmd(dev, inbox->dma, in_mod, op_mod, | |
718 | MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, | |
719 | MLX4_CMD_NATIVE); | |
720 | } | |
721 | ||
722 | /* For IB, we only consider: | |
723 | * - The capability mask, which is set to the aggregate of all | |
724 | * slave function capabilities | |
725 | * - The QKey violatin counter - reset according to each request. | |
726 | */ | |
727 | ||
728 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { | |
729 | reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40; | |
730 | new_cap_mask = ((__be32 *) inbox->buf)[2]; | |
731 | } else { | |
732 | reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1; | |
733 | new_cap_mask = ((__be32 *) inbox->buf)[1]; | |
734 | } | |
735 | ||
736 | agg_cap_mask = 0; | |
737 | slave_cap_mask = | |
738 | priv->mfunc.master.slave_state[slave].ib_cap_mask[port]; | |
739 | priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask; | |
740 | for (i = 0; i < dev->num_slaves; i++) | |
741 | agg_cap_mask |= | |
742 | priv->mfunc.master.slave_state[i].ib_cap_mask[port]; | |
743 | ||
744 | /* only clear mailbox for guests. Master may be setting | |
745 | * MTU or PKEY table size | |
746 | */ | |
747 | if (slave != dev->caps.function) | |
748 | memset(inbox->buf, 0, 256); | |
749 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { | |
edc4a67e | 750 | *(u8 *) inbox->buf |= !!reset_qkey_viols << 6; |
ffe455ad EE |
751 | ((__be32 *) inbox->buf)[2] = agg_cap_mask; |
752 | } else { | |
edc4a67e | 753 | ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols; |
ffe455ad EE |
754 | ((__be32 *) inbox->buf)[1] = agg_cap_mask; |
755 | } | |
756 | ||
757 | err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT, | |
758 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
759 | if (err) | |
760 | priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = | |
761 | slave_cap_mask; | |
762 | return err; | |
763 | } | |
764 | ||
765 | int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
766 | struct mlx4_vhcr *vhcr, | |
767 | struct mlx4_cmd_mailbox *inbox, | |
768 | struct mlx4_cmd_mailbox *outbox, | |
769 | struct mlx4_cmd_info *cmd) | |
770 | { | |
771 | return mlx4_common_set_port(dev, slave, vhcr->in_modifier, | |
772 | vhcr->op_modifier, inbox); | |
773 | } | |
774 | ||
096335b3 OG |
775 | /* bit locations for set port command with zero op modifier */ |
776 | enum { | |
777 | MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */ | |
778 | MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */ | |
779 | MLX4_CHANGE_PORT_VL_CAP = 21, | |
780 | MLX4_CHANGE_PORT_MTU_CAP = 22, | |
781 | }; | |
782 | ||
7ff93f8b YP |
783 | int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port) |
784 | { | |
785 | struct mlx4_cmd_mailbox *mailbox; | |
096335b3 | 786 | int err, vl_cap; |
7ff93f8b | 787 | |
352b09ed RD |
788 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) |
789 | return 0; | |
790 | ||
7ff93f8b YP |
791 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
792 | if (IS_ERR(mailbox)) | |
793 | return PTR_ERR(mailbox); | |
794 | ||
795 | memset(mailbox->buf, 0, 256); | |
793730bf YP |
796 | |
797 | ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port]; | |
096335b3 OG |
798 | |
799 | /* IB VL CAP enum isn't used by the firmware, just numerical values */ | |
800 | for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) { | |
801 | ((__be32 *) mailbox->buf)[0] = cpu_to_be32( | |
802 | (1 << MLX4_CHANGE_PORT_MTU_CAP) | | |
803 | (1 << MLX4_CHANGE_PORT_VL_CAP) | | |
804 | (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) | | |
805 | (vl_cap << MLX4_SET_PORT_VL_CAP)); | |
806 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT, | |
807 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
808 | if (err != -ENOMEM) | |
809 | break; | |
810 | } | |
7ff93f8b YP |
811 | |
812 | mlx4_free_cmd_mailbox(dev, mailbox); | |
813 | return err; | |
814 | } | |
ffe455ad | 815 | |
cb9ffb76 | 816 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
ffe455ad EE |
817 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) |
818 | { | |
819 | struct mlx4_cmd_mailbox *mailbox; | |
820 | struct mlx4_set_port_general_context *context; | |
821 | int err; | |
822 | u32 in_mod; | |
823 | ||
824 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
825 | if (IS_ERR(mailbox)) | |
826 | return PTR_ERR(mailbox); | |
827 | context = mailbox->buf; | |
828 | memset(context, 0, sizeof *context); | |
829 | ||
830 | context->flags = SET_PORT_GEN_ALL_VALID; | |
831 | context->mtu = cpu_to_be16(mtu); | |
832 | context->pptx = (pptx * (!pfctx)) << 7; | |
833 | context->pfctx = pfctx; | |
834 | context->pprx = (pprx * (!pfcrx)) << 7; | |
835 | context->pfcrx = pfcrx; | |
836 | ||
837 | in_mod = MLX4_SET_PORT_GENERAL << 8 | port; | |
838 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
839 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
840 | ||
841 | mlx4_free_cmd_mailbox(dev, mailbox); | |
842 | return err; | |
843 | } | |
844 | EXPORT_SYMBOL(mlx4_SET_PORT_general); | |
845 | ||
cb9ffb76 | 846 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, |
ffe455ad EE |
847 | u8 promisc) |
848 | { | |
849 | struct mlx4_cmd_mailbox *mailbox; | |
850 | struct mlx4_set_port_rqp_calc_context *context; | |
851 | int err; | |
852 | u32 in_mod; | |
853 | u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ? | |
854 | MCAST_DIRECT : MCAST_DEFAULT; | |
855 | ||
c96d97f4 | 856 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) |
ffe455ad EE |
857 | return 0; |
858 | ||
859 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
860 | if (IS_ERR(mailbox)) | |
861 | return PTR_ERR(mailbox); | |
862 | context = mailbox->buf; | |
863 | memset(context, 0, sizeof *context); | |
864 | ||
865 | context->base_qpn = cpu_to_be32(base_qpn); | |
866 | context->n_mac = dev->caps.log_num_macs; | |
867 | context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT | | |
868 | base_qpn); | |
869 | context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT | | |
870 | base_qpn); | |
871 | context->intra_no_vlan = 0; | |
872 | context->no_vlan = MLX4_NO_VLAN_IDX; | |
873 | context->intra_vlan_miss = 0; | |
874 | context->vlan_miss = MLX4_VLAN_MISS_IDX; | |
875 | ||
876 | in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port; | |
877 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
878 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
879 | ||
880 | mlx4_free_cmd_mailbox(dev, mailbox); | |
881 | return err; | |
882 | } | |
883 | EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc); | |
884 | ||
e5395e92 AV |
885 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc) |
886 | { | |
887 | struct mlx4_cmd_mailbox *mailbox; | |
888 | struct mlx4_set_port_prio2tc_context *context; | |
889 | int err; | |
890 | u32 in_mod; | |
891 | int i; | |
892 | ||
893 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
894 | if (IS_ERR(mailbox)) | |
895 | return PTR_ERR(mailbox); | |
896 | context = mailbox->buf; | |
897 | memset(context, 0, sizeof *context); | |
898 | ||
899 | for (i = 0; i < MLX4_NUM_UP; i += 2) | |
900 | context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1]; | |
901 | ||
902 | in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port; | |
903 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
904 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
905 | ||
906 | mlx4_free_cmd_mailbox(dev, mailbox); | |
907 | return err; | |
908 | } | |
909 | EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC); | |
910 | ||
911 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
912 | u8 *pg, u16 *ratelimit) | |
913 | { | |
914 | struct mlx4_cmd_mailbox *mailbox; | |
915 | struct mlx4_set_port_scheduler_context *context; | |
916 | int err; | |
917 | u32 in_mod; | |
918 | int i; | |
919 | ||
920 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
921 | if (IS_ERR(mailbox)) | |
922 | return PTR_ERR(mailbox); | |
923 | context = mailbox->buf; | |
924 | memset(context, 0, sizeof *context); | |
925 | ||
926 | for (i = 0; i < MLX4_NUM_TC; i++) { | |
927 | struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i]; | |
928 | u16 r = ratelimit && ratelimit[i] ? ratelimit[i] : | |
929 | MLX4_RATELIMIT_DEFAULT; | |
930 | ||
931 | tc->pg = htons(pg[i]); | |
932 | tc->bw_precentage = htons(tc_tx_bw[i]); | |
933 | ||
934 | tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS); | |
935 | tc->max_bw_value = htons(r); | |
936 | } | |
937 | ||
938 | in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port; | |
939 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
940 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
941 | ||
942 | mlx4_free_cmd_mailbox(dev, mailbox); | |
943 | return err; | |
944 | } | |
945 | EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER); | |
946 | ||
ffe455ad EE |
947 | int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, |
948 | struct mlx4_vhcr *vhcr, | |
949 | struct mlx4_cmd_mailbox *inbox, | |
950 | struct mlx4_cmd_mailbox *outbox, | |
951 | struct mlx4_cmd_info *cmd) | |
952 | { | |
953 | int err = 0; | |
954 | ||
955 | return err; | |
956 | } | |
957 | ||
958 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, | |
959 | u64 mac, u64 clear, u8 mode) | |
960 | { | |
961 | return mlx4_cmd(dev, (mac | (clear << 63)), port, mode, | |
962 | MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B, | |
963 | MLX4_CMD_WRAPPED); | |
964 | } | |
965 | EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR); | |
966 | ||
967 | int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, | |
968 | struct mlx4_vhcr *vhcr, | |
969 | struct mlx4_cmd_mailbox *inbox, | |
970 | struct mlx4_cmd_mailbox *outbox, | |
971 | struct mlx4_cmd_info *cmd) | |
972 | { | |
973 | int err = 0; | |
974 | ||
975 | return err; | |
976 | } | |
977 | ||
978 | int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, | |
979 | u32 in_mod, struct mlx4_cmd_mailbox *outbox) | |
980 | { | |
981 | return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0, | |
982 | MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B, | |
983 | MLX4_CMD_NATIVE); | |
984 | } | |
985 | ||
986 | int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, | |
987 | struct mlx4_vhcr *vhcr, | |
988 | struct mlx4_cmd_mailbox *inbox, | |
989 | struct mlx4_cmd_mailbox *outbox, | |
990 | struct mlx4_cmd_info *cmd) | |
991 | { | |
35fb9afb EE |
992 | if (slave != dev->caps.function) |
993 | return 0; | |
ffe455ad EE |
994 | return mlx4_common_dump_eth_stats(dev, slave, |
995 | vhcr->in_modifier, outbox); | |
996 | } | |
93ece0c1 EE |
997 | |
998 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap) | |
999 | { | |
1000 | if (!mlx4_is_mfunc(dev)) { | |
1001 | *stats_bitmap = 0; | |
1002 | return; | |
1003 | } | |
1004 | ||
1005 | *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK | | |
1006 | MLX4_STATS_TRAFFIC_DROPS_MASK | | |
1007 | MLX4_STATS_PORT_COUNTERS_MASK); | |
1008 | ||
1009 | if (mlx4_is_master(dev)) | |
1010 | *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK; | |
1011 | } | |
1012 | EXPORT_SYMBOL(mlx4_set_stats_bitmap); |