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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
5a0e3ad6 TH |
35 | #include <linux/slab.h> |
36 | ||
225c7b1f RD |
37 | #include "mlx4.h" |
38 | #include "fw.h" | |
39 | ||
40 | enum { | |
41 | MLX4_RES_QP, | |
42 | MLX4_RES_RDMARC, | |
43 | MLX4_RES_ALTC, | |
44 | MLX4_RES_AUXC, | |
45 | MLX4_RES_SRQ, | |
46 | MLX4_RES_CQ, | |
47 | MLX4_RES_EQ, | |
48 | MLX4_RES_DMPT, | |
49 | MLX4_RES_CMPT, | |
50 | MLX4_RES_MTT, | |
51 | MLX4_RES_MCG, | |
52 | MLX4_RES_NUM | |
53 | }; | |
54 | ||
55 | static const char *res_name[] = { | |
56 | [MLX4_RES_QP] = "QP", | |
57 | [MLX4_RES_RDMARC] = "RDMARC", | |
58 | [MLX4_RES_ALTC] = "ALTC", | |
59 | [MLX4_RES_AUXC] = "AUXC", | |
60 | [MLX4_RES_SRQ] = "SRQ", | |
61 | [MLX4_RES_CQ] = "CQ", | |
62 | [MLX4_RES_EQ] = "EQ", | |
63 | [MLX4_RES_DMPT] = "DMPT", | |
64 | [MLX4_RES_CMPT] = "CMPT", | |
65 | [MLX4_RES_MTT] = "MTT", | |
66 | [MLX4_RES_MCG] = "MCG", | |
67 | }; | |
68 | ||
69 | u64 mlx4_make_profile(struct mlx4_dev *dev, | |
70 | struct mlx4_profile *request, | |
71 | struct mlx4_dev_cap *dev_cap, | |
72 | struct mlx4_init_hca_param *init_hca) | |
73 | { | |
74 | struct mlx4_priv *priv = mlx4_priv(dev); | |
75 | struct mlx4_resource { | |
76 | u64 size; | |
77 | u64 start; | |
78 | int type; | |
3de819e6 | 79 | u32 num; |
225c7b1f RD |
80 | int log_num; |
81 | }; | |
82 | ||
83 | u64 total_size = 0; | |
84 | struct mlx4_resource *profile; | |
db5a7a65 | 85 | struct sysinfo si; |
225c7b1f RD |
86 | int i, j; |
87 | ||
baeb2ffa | 88 | profile = kcalloc(MLX4_RES_NUM, sizeof(*profile), GFP_KERNEL); |
225c7b1f RD |
89 | if (!profile) |
90 | return -ENOMEM; | |
91 | ||
db5a7a65 RD |
92 | /* |
93 | * We want to scale the number of MTTs with the size of the | |
94 | * system memory, since it makes sense to register a lot of | |
95 | * memory on a system with a lot of memory. As a heuristic, | |
96 | * make sure we have enough MTTs to cover twice the system | |
97 | * memory (with PAGE_SIZE entries). | |
98 | * | |
99 | * This number has to be a power of two and fit into 32 bits | |
100 | * due to device limitations, so cap this at 2^31 as well. | |
101 | * That limits us to 8TB of memory registration per HCA with | |
102 | * 4KB pages, which is probably OK for the next few months. | |
103 | */ | |
104 | si_meminfo(&si); | |
105 | request->num_mtt = | |
106 | roundup_pow_of_two(max_t(unsigned, request->num_mtt, | |
3de819e6 | 107 | min(1UL << (31 - log_mtts_per_seg), |
db5a7a65 RD |
108 | si.totalram >> (log_mtts_per_seg - 1)))); |
109 | ||
225c7b1f RD |
110 | profile[MLX4_RES_QP].size = dev_cap->qpc_entry_sz; |
111 | profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz; | |
112 | profile[MLX4_RES_ALTC].size = dev_cap->altc_entry_sz; | |
113 | profile[MLX4_RES_AUXC].size = dev_cap->aux_entry_sz; | |
114 | profile[MLX4_RES_SRQ].size = dev_cap->srq_entry_sz; | |
115 | profile[MLX4_RES_CQ].size = dev_cap->cqc_entry_sz; | |
116 | profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz; | |
117 | profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz; | |
118 | profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz; | |
2b8fb286 | 119 | profile[MLX4_RES_MTT].size = dev_cap->mtt_entry_sz; |
0ec2c0f8 | 120 | profile[MLX4_RES_MCG].size = mlx4_get_mgm_entry_size(dev); |
225c7b1f RD |
121 | |
122 | profile[MLX4_RES_QP].num = request->num_qp; | |
123 | profile[MLX4_RES_RDMARC].num = request->num_qp * request->rdmarc_per_qp; | |
124 | profile[MLX4_RES_ALTC].num = request->num_qp; | |
125 | profile[MLX4_RES_AUXC].num = request->num_qp; | |
126 | profile[MLX4_RES_SRQ].num = request->num_srq; | |
127 | profile[MLX4_RES_CQ].num = request->num_cq; | |
7ae0e400 | 128 | profile[MLX4_RES_EQ].num = mlx4_is_mfunc(dev) ? dev->phys_caps.num_phys_eqs : |
3fc929e2 | 129 | min_t(unsigned, dev_cap->max_eqs, MAX_MSIX); |
225c7b1f RD |
130 | profile[MLX4_RES_DMPT].num = request->num_mpt; |
131 | profile[MLX4_RES_CMPT].num = MLX4_NUM_CMPTS; | |
9fd7a1e1 | 132 | profile[MLX4_RES_MTT].num = request->num_mtt * (1 << log_mtts_per_seg); |
225c7b1f RD |
133 | profile[MLX4_RES_MCG].num = request->num_mcg; |
134 | ||
135 | for (i = 0; i < MLX4_RES_NUM; ++i) { | |
136 | profile[i].type = i; | |
137 | profile[i].num = roundup_pow_of_two(profile[i].num); | |
138 | profile[i].log_num = ilog2(profile[i].num); | |
139 | profile[i].size *= profile[i].num; | |
140 | profile[i].size = max(profile[i].size, (u64) PAGE_SIZE); | |
141 | } | |
142 | ||
143 | /* | |
144 | * Sort the resources in decreasing order of size. Since they | |
145 | * all have sizes that are powers of 2, we'll be able to keep | |
146 | * resources aligned to their size and pack them without gaps | |
147 | * using the sorted order. | |
148 | */ | |
149 | for (i = MLX4_RES_NUM; i > 0; --i) | |
150 | for (j = 1; j < i; ++j) { | |
e55898a7 FF |
151 | if (profile[j].size > profile[j - 1].size) |
152 | swap(profile[j], profile[j - 1]); | |
225c7b1f RD |
153 | } |
154 | ||
155 | for (i = 0; i < MLX4_RES_NUM; ++i) { | |
156 | if (profile[i].size) { | |
157 | profile[i].start = total_size; | |
158 | total_size += profile[i].size; | |
159 | } | |
160 | ||
161 | if (total_size > dev_cap->max_icm_sz) { | |
1a91de28 JP |
162 | mlx4_err(dev, "Profile requires 0x%llx bytes; won't fit in 0x%llx bytes of context memory\n", |
163 | (unsigned long long) total_size, | |
164 | (unsigned long long) dev_cap->max_icm_sz); | |
225c7b1f RD |
165 | kfree(profile); |
166 | return -ENOMEM; | |
167 | } | |
168 | ||
169 | if (profile[i].size) | |
1a91de28 JP |
170 | mlx4_dbg(dev, " profile[%2d] (%6s): 2^%02d entries @ 0x%10llx, size 0x%10llx\n", |
171 | i, res_name[profile[i].type], | |
172 | profile[i].log_num, | |
225c7b1f RD |
173 | (unsigned long long) profile[i].start, |
174 | (unsigned long long) profile[i].size); | |
175 | } | |
176 | ||
177 | mlx4_dbg(dev, "HCA context memory: reserving %d KB\n", | |
178 | (int) (total_size >> 10)); | |
179 | ||
180 | for (i = 0; i < MLX4_RES_NUM; ++i) { | |
181 | switch (profile[i].type) { | |
182 | case MLX4_RES_QP: | |
183 | dev->caps.num_qps = profile[i].num; | |
184 | init_hca->qpc_base = profile[i].start; | |
185 | init_hca->log_num_qps = profile[i].log_num; | |
186 | break; | |
187 | case MLX4_RES_RDMARC: | |
188 | for (priv->qp_table.rdmarc_shift = 0; | |
189 | request->num_qp << priv->qp_table.rdmarc_shift < profile[i].num; | |
190 | ++priv->qp_table.rdmarc_shift) | |
191 | ; /* nothing */ | |
192 | dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift; | |
193 | priv->qp_table.rdmarc_base = (u32) profile[i].start; | |
194 | init_hca->rdmarc_base = profile[i].start; | |
195 | init_hca->log_rd_per_qp = priv->qp_table.rdmarc_shift; | |
196 | break; | |
197 | case MLX4_RES_ALTC: | |
198 | init_hca->altc_base = profile[i].start; | |
199 | break; | |
200 | case MLX4_RES_AUXC: | |
201 | init_hca->auxc_base = profile[i].start; | |
202 | break; | |
203 | case MLX4_RES_SRQ: | |
204 | dev->caps.num_srqs = profile[i].num; | |
205 | init_hca->srqc_base = profile[i].start; | |
206 | init_hca->log_num_srqs = profile[i].log_num; | |
207 | break; | |
208 | case MLX4_RES_CQ: | |
209 | dev->caps.num_cqs = profile[i].num; | |
210 | init_hca->cqc_base = profile[i].start; | |
211 | init_hca->log_num_cqs = profile[i].log_num; | |
212 | break; | |
213 | case MLX4_RES_EQ: | |
7ae0e400 MB |
214 | if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { |
215 | init_hca->log_num_eqs = 0x1f; | |
216 | init_hca->eqc_base = profile[i].start; | |
217 | init_hca->num_sys_eqs = dev_cap->num_sys_eqs; | |
218 | } else { | |
219 | dev->caps.num_eqs = roundup_pow_of_two( | |
220 | min_t(unsigned, | |
221 | dev_cap->max_eqs, | |
222 | MAX_MSIX)); | |
223 | init_hca->eqc_base = profile[i].start; | |
224 | init_hca->log_num_eqs = ilog2(dev->caps.num_eqs); | |
225 | } | |
225c7b1f RD |
226 | break; |
227 | case MLX4_RES_DMPT: | |
228 | dev->caps.num_mpts = profile[i].num; | |
229 | priv->mr_table.mpt_base = profile[i].start; | |
230 | init_hca->dmpt_base = profile[i].start; | |
231 | init_hca->log_mpt_sz = profile[i].log_num; | |
232 | break; | |
233 | case MLX4_RES_CMPT: | |
234 | init_hca->cmpt_base = profile[i].start; | |
235 | break; | |
236 | case MLX4_RES_MTT: | |
2b8fb286 | 237 | dev->caps.num_mtts = profile[i].num; |
225c7b1f RD |
238 | priv->mr_table.mtt_base = profile[i].start; |
239 | init_hca->mtt_base = profile[i].start; | |
240 | break; | |
241 | case MLX4_RES_MCG: | |
225c7b1f | 242 | init_hca->mc_base = profile[i].start; |
0ec2c0f8 EE |
243 | init_hca->log_mc_entry_sz = |
244 | ilog2(mlx4_get_mgm_entry_size(dev)); | |
225c7b1f | 245 | init_hca->log_mc_table_sz = profile[i].log_num; |
0ff1fb65 HHZ |
246 | if (dev->caps.steering_mode == |
247 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
248 | dev->caps.num_mgms = profile[i].num; | |
249 | } else { | |
250 | init_hca->log_mc_hash_sz = | |
251 | profile[i].log_num - 1; | |
252 | dev->caps.num_mgms = profile[i].num >> 1; | |
253 | dev->caps.num_amgms = profile[i].num >> 1; | |
254 | } | |
225c7b1f RD |
255 | break; |
256 | default: | |
257 | break; | |
258 | } | |
259 | } | |
260 | ||
261 | /* | |
262 | * PDs don't take any HCA memory, but we assign them as part | |
263 | * of the HCA profile anyway. | |
264 | */ | |
265 | dev->caps.num_pds = MLX4_NUM_PDS; | |
266 | ||
267 | kfree(profile); | |
268 | return total_size; | |
269 | } |