[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / qp.c

/*
 * Copyright (c) 2004 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/gfp.h>
#include <linux/export.h>
#include <linux/init.h>

#include <linux/mlx4/cmd.h>
#include <linux/mlx4/qp.h>

#include "mlx4.h"
#include "icm.h"

void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
{
	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
	struct mlx4_qp *qp;

	spin_lock(&qp_table->lock);

	qp = __mlx4_qp_lookup(dev, qpn);
	if (qp)
		atomic_inc(&qp->refcount);

	spin_unlock(&qp_table->lock);

	if (!qp) {
		mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
		return;
	}

	qp->event(qp, event_type);

	if (atomic_dec_and_test(&qp->refcount))
		complete(&qp->free);
}

static int is_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp)
{
	return qp->qpn >= dev->caps.sqp_start &&
		qp->qpn <= dev->caps.sqp_start + 1;
}

static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		     enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
		     struct mlx4_qp_context *context,
		     enum mlx4_qp_optpar optpar,
		     int sqd_event, struct mlx4_qp *qp, int native)
{
	static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
		[MLX4_QP_STATE_RST] = {
			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
			[MLX4_QP_STATE_INIT]	= MLX4_CMD_RST2INIT_QP,
		},
		[MLX4_QP_STATE_INIT]  = {
			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
			[MLX4_QP_STATE_INIT]	= MLX4_CMD_INIT2INIT_QP,
			[MLX4_QP_STATE_RTR]	= MLX4_CMD_INIT2RTR_QP,
		},
		[MLX4_QP_STATE_RTR]   = {
			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
			[MLX4_QP_STATE_RTS]	= MLX4_CMD_RTR2RTS_QP,
		},
		[MLX4_QP_STATE_RTS]   = {
			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
			[MLX4_QP_STATE_RTS]	= MLX4_CMD_RTS2RTS_QP,
			[MLX4_QP_STATE_SQD]	= MLX4_CMD_RTS2SQD_QP,
		},
		[MLX4_QP_STATE_SQD] = {
			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
			[MLX4_QP_STATE_RTS]	= MLX4_CMD_SQD2RTS_QP,
			[MLX4_QP_STATE_SQD]	= MLX4_CMD_SQD2SQD_QP,
		},
		[MLX4_QP_STATE_SQER] = {
			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
			[MLX4_QP_STATE_RTS]	= MLX4_CMD_SQERR2RTS_QP,
		},
		[MLX4_QP_STATE_ERR] = {
			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
		}
	};

	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cmd_mailbox *mailbox;
	int ret = 0;
	u8 port;

	if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
	    !op[cur_state][new_state])
		return -EINVAL;

	if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
		ret = mlx4_cmd(dev, 0, qp->qpn, 2,
			MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
		if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
		    cur_state != MLX4_QP_STATE_RST &&
		    is_qp0(dev, qp)) {
			port = (qp->qpn & 1) + 1;
			priv->mfunc.master.qp0_state[port].qp0_active = 0;
		}
		return ret;
	}

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
		u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
		context->mtt_base_addr_h = mtt_addr >> 32;
		context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
		context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
	}

	*(__be32 *) mailbox->buf = cpu_to_be32(optpar);
	memcpy(mailbox->buf + 8, context, sizeof *context);

	((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
		cpu_to_be32(qp->qpn);

	ret = mlx4_cmd(dev, mailbox->dma,
		       qp->qpn | (!!sqd_event << 31),
		       new_state == MLX4_QP_STATE_RST ? 2 : 0,
		       op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return ret;
}

int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
		   struct mlx4_qp_context *context,
		   enum mlx4_qp_optpar optpar,
		   int sqd_event, struct mlx4_qp *qp)
{
	return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
				optpar, sqd_event, qp, 0);
}
EXPORT_SYMBOL_GPL(mlx4_qp_modify);

int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
				   int *base)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_qp_table *qp_table = &priv->qp_table;

	*base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align);
	if (*base == -1)
		return -ENOMEM;

	return 0;
}

int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base)
{
	u64 in_param;
	u64 out_param;
	int err;

	if (mlx4_is_mfunc(dev)) {
		set_param_l(&in_param, cnt);
		set_param_h(&in_param, align);
		err = mlx4_cmd_imm(dev, in_param, &out_param,
				   RES_QP, RES_OP_RESERVE,
				   MLX4_CMD_ALLOC_RES,
				   MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
		if (err)
			return err;

		*base = get_param_l(&out_param);
		return 0;
	}
	return __mlx4_qp_reserve_range(dev, cnt, align, base);
}
EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);

void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_qp_table *qp_table = &priv->qp_table;

	if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
		return;
	mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt);
}

void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
{
	u64 in_param;
	int err;

	if (mlx4_is_mfunc(dev)) {
		set_param_l(&in_param, base_qpn);
		set_param_h(&in_param, cnt);
		err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
			       MLX4_CMD_FREE_RES,
			       MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
		if (err) {
			mlx4_warn(dev, "Failed to release qp range"
				  " base:%d cnt:%d\n", base_qpn, cnt);
		}
	} else
		 __mlx4_qp_release_range(dev, base_qpn, cnt);
}
EXPORT_SYMBOL_GPL(mlx4_qp_release_range);

int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_qp_table *qp_table = &priv->qp_table;
	int err;

	err = mlx4_table_get(dev, &qp_table->qp_table, qpn);
	if (err)
		goto err_out;

	err = mlx4_table_get(dev, &qp_table->auxc_table, qpn);
	if (err)
		goto err_put_qp;

	err = mlx4_table_get(dev, &qp_table->altc_table, qpn);
	if (err)
		goto err_put_auxc;

	err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn);
	if (err)
		goto err_put_altc;

	err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn);
	if (err)
		goto err_put_rdmarc;

	return 0;

err_put_rdmarc:
	mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);

err_put_altc:
	mlx4_table_put(dev, &qp_table->altc_table, qpn);

err_put_auxc:
	mlx4_table_put(dev, &qp_table->auxc_table, qpn);

err_put_qp:
	mlx4_table_put(dev, &qp_table->qp_table, qpn);

err_out:
	return err;
}

static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
{
	u64 param;

	if (mlx4_is_mfunc(dev)) {
		set_param_l(&param, qpn);
		return mlx4_cmd_imm(dev, param, &param, RES_QP, RES_OP_MAP_ICM,
				    MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
				    MLX4_CMD_WRAPPED);
	}
	return __mlx4_qp_alloc_icm(dev, qpn);
}

void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_qp_table *qp_table = &priv->qp_table;

	mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
	mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
	mlx4_table_put(dev, &qp_table->altc_table, qpn);
	mlx4_table_put(dev, &qp_table->auxc_table, qpn);
	mlx4_table_put(dev, &qp_table->qp_table, qpn);
}

static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
{
	u64 in_param;

	if (mlx4_is_mfunc(dev)) {
		set_param_l(&in_param, qpn);
		if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
			     MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
			     MLX4_CMD_WRAPPED))
			mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
	} else
		__mlx4_qp_free_icm(dev, qpn);
}

int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_qp_table *qp_table = &priv->qp_table;
	int err;

	if (!qpn)
		return -EINVAL;

	qp->qpn = qpn;

	err = mlx4_qp_alloc_icm(dev, qpn);
	if (err)
		return err;

	spin_lock_irq(&qp_table->lock);
	err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
				(dev->caps.num_qps - 1), qp);
	spin_unlock_irq(&qp_table->lock);
	if (err)
		goto err_icm;

	atomic_set(&qp->refcount, 1);
	init_completion(&qp->free);

	return 0;

err_icm:
	mlx4_qp_free_icm(dev, qpn);
	return err;
}

EXPORT_SYMBOL_GPL(mlx4_qp_alloc);

void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
{
	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
	unsigned long flags;

	spin_lock_irqsave(&qp_table->lock, flags);
	radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
	spin_unlock_irqrestore(&qp_table->lock, flags);
}
EXPORT_SYMBOL_GPL(mlx4_qp_remove);

void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
{
	if (atomic_dec_and_test(&qp->refcount))
		complete(&qp->free);
	wait_for_completion(&qp->free);

	mlx4_qp_free_icm(dev, qp->qpn);
}
EXPORT_SYMBOL_GPL(mlx4_qp_free);

static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
{
	return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
			MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
}

int mlx4_init_qp_table(struct mlx4_dev *dev)
{
	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
	int err;
	int reserved_from_top = 0;

	spin_lock_init(&qp_table->lock);
	INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
	if (mlx4_is_slave(dev))
		return 0;

	/*
	 * We reserve 2 extra QPs per port for the special QPs.  The
	 * block of special QPs must be aligned to a multiple of 8, so
	 * round up.
	 *
	 * We also reserve the MSB of the 24-bit QP number to indicate
	 * that a QP is an XRC QP.
	 */
	dev->caps.sqp_start =
		ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8);

	{
		int sort[MLX4_NUM_QP_REGION];
		int i, j, tmp;
		int last_base = dev->caps.num_qps;

		for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
			sort[i] = i;

		for (i = MLX4_NUM_QP_REGION; i > 0; --i) {
			for (j = 2; j < i; ++j) {
				if (dev->caps.reserved_qps_cnt[sort[j]] >
				    dev->caps.reserved_qps_cnt[sort[j - 1]]) {
					tmp             = sort[j];
					sort[j]         = sort[j - 1];
					sort[j - 1]     = tmp;
				}
			}
		}

		for (i = 1; i < MLX4_NUM_QP_REGION; ++i) {
			last_base -= dev->caps.reserved_qps_cnt[sort[i]];
			dev->caps.reserved_qps_base[sort[i]] = last_base;
			reserved_from_top +=
				dev->caps.reserved_qps_cnt[sort[i]];
		}

	}

	err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps,
			       (1 << 23) - 1, dev->caps.sqp_start + 8,
			       reserved_from_top);
	if (err)
		return err;

	return mlx4_CONF_SPECIAL_QP(dev, dev->caps.sqp_start);
}

void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
{
	if (mlx4_is_slave(dev))
		return;

	mlx4_CONF_SPECIAL_QP(dev, 0);
	mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap);
}

int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
		  struct mlx4_qp_context *context)
{
	struct mlx4_cmd_mailbox *mailbox;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
			   MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
			   MLX4_CMD_WRAPPED);
	if (!err)
		memcpy(context, mailbox->buf + 8, sizeof *context);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_qp_query);

int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		     struct mlx4_qp_context *context,
		     struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
{
	int err;
	int i;
	enum mlx4_qp_state states[] = {
		MLX4_QP_STATE_RST,
		MLX4_QP_STATE_INIT,
		MLX4_QP_STATE_RTR,
		MLX4_QP_STATE_RTS
	};

	for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
		context->flags &= cpu_to_be32(~(0xf << 28));
		context->flags |= cpu_to_be32(states[i + 1] << 28);
		err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
				     context, 0, 0, qp);
		if (err) {
			mlx4_err(dev, "Failed to bring QP to state: "
				 "%d with error: %d\n",
				 states[i + 1], err);
			return err;
		}

		*qp_state = states[i + 1];
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0	4	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	5	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
	6	*
	7	* This software is available to you under a choice of one of two
	8	* licenses. You may choose to be licensed under the terms of the GNU
	9	* General Public License (GPL) Version 2, available from the file
	10	* COPYING in the main directory of this source tree, or the
	11	* OpenIB.org BSD license below:
	12	*
	13	* Redistribution and use in source and binary forms, with or
	14	* without modification, are permitted provided that the following
	15	* conditions are met:
	16	*
	17	* - Redistributions of source code must retain the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer.
	20	*
	21	* - Redistributions in binary form must reproduce the above
	22	* copyright notice, this list of conditions and the following
	23	* disclaimer in the documentation and/or other materials
	24	* provided with the distribution.
	25	*
	26	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	27	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	28	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	29	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	30	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	31	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	32	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	33	* SOFTWARE.
	34	*/
	35
5a0e3ad6	36	#include <linux/gfp.h>
ee40fa06	37	#include <linux/export.h>
fe9a2603 JM	38	#include <linux/init.h>
fe9a2603 JM	39
225c7b1f RD	40	#include <linux/mlx4/cmd.h>
	41	#include <linux/mlx4/qp.h>
	42
	43	#include "mlx4.h"
	44	#include "icm.h"
	45
	46	void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
	47	{
	48	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
	49	struct mlx4_qp *qp;
	50
	51	spin_lock(&qp_table->lock);
	52
	53	qp = __mlx4_qp_lookup(dev, qpn);
	54	if (qp)
	55	atomic_inc(&qp->refcount);
	56
	57	spin_unlock(&qp_table->lock);
	58
	59	if (!qp) {
fe9a2603	60	mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
225c7b1f RD	61	return;
	62	}
	63
	64	qp->event(qp, event_type);
	65
	66	if (atomic_dec_and_test(&qp->refcount))
	67	complete(&qp->free);
	68	}
	69
fe9a2603 JM	70	static int is_qp0(struct mlx4_dev dev, struct mlx4_qp qp)
	71	{
	72	return qp->qpn >= dev->caps.sqp_start &&
	73	qp->qpn <= dev->caps.sqp_start + 1;
	74	}
	75
	76	static int __mlx4_qp_modify(struct mlx4_dev dev, struct mlx4_mtt mtt,
	77	enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
	78	struct mlx4_qp_context *context,
	79	enum mlx4_qp_optpar optpar,
	80	int sqd_event, struct mlx4_qp *qp, int native)
225c7b1f RD	81	{
	82	static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
	83	[MLX4_QP_STATE_RST] = {
	84	[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
	85	[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
	86	[MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP,
	87	},
	88	[MLX4_QP_STATE_INIT] = {
	89	[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
	90	[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
	91	[MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP,
	92	[MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP,
	93	},
	94	[MLX4_QP_STATE_RTR] = {
	95	[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
	96	[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
	97	[MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP,
	98	},
	99	[MLX4_QP_STATE_RTS] = {
	100	[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
	101	[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
	102	[MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP,
	103	[MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP,
	104	},
	105	[MLX4_QP_STATE_SQD] = {
	106	[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
	107	[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
	108	[MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP,
	109	[MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP,
	110	},
	111	[MLX4_QP_STATE_SQER] = {
	112	[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
	113	[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
	114	[MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP,
	115	},
	116	[MLX4_QP_STATE_ERR] = {
	117	[MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
	118	[MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
	119	}
	120	};
	121
fe9a2603	122	struct mlx4_priv *priv = mlx4_priv(dev);
225c7b1f RD	123	struct mlx4_cmd_mailbox *mailbox;
225c7b1f RD	124	int ret = 0;
fe9a2603	125	u8 port;
225c7b1f	126
9ed87fd3	127	if (cur_state >= MLX4_QP_NUM_STATE \|\| new_state >= MLX4_QP_NUM_STATE \|\|
225c7b1f RD	128	!op[cur_state][new_state])
	129	return -EINVAL;
	130
fe9a2603 JM	131	if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
	132	ret = mlx4_cmd(dev, 0, qp->qpn, 2,
	133	MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
	134	if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
	135	cur_state != MLX4_QP_STATE_RST &&
	136	is_qp0(dev, qp)) {
	137	port = (qp->qpn & 1) + 1;
	138	priv->mfunc.master.qp0_state[port].qp0_active = 0;
	139	}
	140	return ret;
	141	}
225c7b1f RD	142
	143	mailbox = mlx4_alloc_cmd_mailbox(dev);
	144	if (IS_ERR(mailbox))
	145	return PTR_ERR(mailbox);
	146
	147	if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
	148	u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
	149	context->mtt_base_addr_h = mtt_addr >> 32;
	150	context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	151	context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
	152	}
	153
	154	(__be32 ) mailbox->buf = cpu_to_be32(optpar);
	155	memcpy(mailbox->buf + 8, context, sizeof *context);
	156
	157	((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
	158	cpu_to_be32(qp->qpn);
	159
eb41049f	160	ret = mlx4_cmd(dev, mailbox->dma,
fe9a2603	161	qp->qpn \| (!!sqd_event << 31),
225c7b1f	162	new_state == MLX4_QP_STATE_RST ? 2 : 0,
fe9a2603	163	op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
225c7b1f RD	164
	165	mlx4_free_cmd_mailbox(dev, mailbox);
	166	return ret;
	167	}
fe9a2603 JM	168
	169	int mlx4_qp_modify(struct mlx4_dev dev, struct mlx4_mtt mtt,
	170	enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
	171	struct mlx4_qp_context *context,
	172	enum mlx4_qp_optpar optpar,
	173	int sqd_event, struct mlx4_qp *qp)
	174	{
	175	return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
	176	optpar, sqd_event, qp, 0);
	177	}
225c7b1f RD	178	EXPORT_SYMBOL_GPL(mlx4_qp_modify);
225c7b1f RD	179
c82e9aa0	180	int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
fe9a2603	181	int *base)
a3cdcbfa YP	182	{
	183	struct mlx4_priv *priv = mlx4_priv(dev);
	184	struct mlx4_qp_table *qp_table = &priv->qp_table;
a3cdcbfa	185
fe9a2603 JM	186	*base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align);
fe9a2603 JM	187	if (*base == -1)
a3cdcbfa YP	188	return -ENOMEM;
a3cdcbfa YP	189
a3cdcbfa YP	190	return 0;
a3cdcbfa YP	191	}
fe9a2603 JM	192
	193	int mlx4_qp_reserve_range(struct mlx4_dev dev, int cnt, int align, int base)
	194	{
	195	u64 in_param;
	196	u64 out_param;
	197	int err;
	198
	199	if (mlx4_is_mfunc(dev)) {
	200	set_param_l(&in_param, cnt);
	201	set_param_h(&in_param, align);
	202	err = mlx4_cmd_imm(dev, in_param, &out_param,
	203	RES_QP, RES_OP_RESERVE,
	204	MLX4_CMD_ALLOC_RES,
	205	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
	206	if (err)
	207	return err;
	208
	209	*base = get_param_l(&out_param);
	210	return 0;
	211	}
	212	return __mlx4_qp_reserve_range(dev, cnt, align, base);
	213	}
a3cdcbfa YP	214	EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
a3cdcbfa YP	215
c82e9aa0	216	void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
a3cdcbfa YP	217	{
	218	struct mlx4_priv *priv = mlx4_priv(dev);
	219	struct mlx4_qp_table *qp_table = &priv->qp_table;
a3cdcbfa	220
fe9a2603 JM	221	if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
fe9a2603 JM	222	return;
a3cdcbfa YP	223	mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt);
a3cdcbfa YP	224	}
fe9a2603 JM	225
	226	void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
	227	{
	228	u64 in_param;
	229	int err;
	230
	231	if (mlx4_is_mfunc(dev)) {
	232	set_param_l(&in_param, base_qpn);
	233	set_param_h(&in_param, cnt);
	234	err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
	235	MLX4_CMD_FREE_RES,
	236	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
	237	if (err) {
	238	mlx4_warn(dev, "Failed to release qp range"
	239	" base:%d cnt:%d\n", base_qpn, cnt);
	240	}
	241	} else
	242	__mlx4_qp_release_range(dev, base_qpn, cnt);
	243	}
a3cdcbfa YP	244	EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
a3cdcbfa YP	245
c82e9aa0	246	int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
225c7b1f RD	247	{
	248	struct mlx4_priv *priv = mlx4_priv(dev);
	249	struct mlx4_qp_table *qp_table = &priv->qp_table;
	250	int err;
	251
fe9a2603	252	err = mlx4_table_get(dev, &qp_table->qp_table, qpn);
225c7b1f RD	253	if (err)
	254	goto err_out;
	255
fe9a2603	256	err = mlx4_table_get(dev, &qp_table->auxc_table, qpn);
225c7b1f RD	257	if (err)
	258	goto err_put_qp;
	259
fe9a2603	260	err = mlx4_table_get(dev, &qp_table->altc_table, qpn);
225c7b1f RD	261	if (err)
	262	goto err_put_auxc;
	263
fe9a2603	264	err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn);
225c7b1f RD	265	if (err)
	266	goto err_put_altc;
	267
fe9a2603	268	err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn);
225c7b1f RD	269	if (err)
	270	goto err_put_rdmarc;
	271
225c7b1f RD	272	return 0;
225c7b1f RD	273
225c7b1f	274	err_put_rdmarc:
fe9a2603	275	mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
225c7b1f RD	276
225c7b1f RD	277	err_put_altc:
fe9a2603	278	mlx4_table_put(dev, &qp_table->altc_table, qpn);
225c7b1f RD	279
225c7b1f RD	280	err_put_auxc:
fe9a2603	281	mlx4_table_put(dev, &qp_table->auxc_table, qpn);
225c7b1f RD	282
225c7b1f RD	283	err_put_qp:
fe9a2603	284	mlx4_table_put(dev, &qp_table->qp_table, qpn);
225c7b1f RD	285
225c7b1f RD	286	err_out:
225c7b1f RD	287	return err;
225c7b1f RD	288	}
fe9a2603 JM	289
	290	static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
	291	{
	292	u64 param;
	293
	294	if (mlx4_is_mfunc(dev)) {
	295	set_param_l(&param, qpn);
	296	return mlx4_cmd_imm(dev, param, &param, RES_QP, RES_OP_MAP_ICM,
	297	MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
	298	MLX4_CMD_WRAPPED);
	299	}
	300	return __mlx4_qp_alloc_icm(dev, qpn);
	301	}
	302
c82e9aa0	303	void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
fe9a2603 JM	304	{
	305	struct mlx4_priv *priv = mlx4_priv(dev);
	306	struct mlx4_qp_table *qp_table = &priv->qp_table;
	307
	308	mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
	309	mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
	310	mlx4_table_put(dev, &qp_table->altc_table, qpn);
	311	mlx4_table_put(dev, &qp_table->auxc_table, qpn);
	312	mlx4_table_put(dev, &qp_table->qp_table, qpn);
	313	}
	314
	315	static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
	316	{
	317	u64 in_param;
	318
	319	if (mlx4_is_mfunc(dev)) {
	320	set_param_l(&in_param, qpn);
	321	if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
	322	MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
	323	MLX4_CMD_WRAPPED))
	324	mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
	325	} else
	326	__mlx4_qp_free_icm(dev, qpn);
	327	}
	328
	329	int mlx4_qp_alloc(struct mlx4_dev dev, int qpn, struct mlx4_qp qp)
	330	{
	331	struct mlx4_priv *priv = mlx4_priv(dev);
	332	struct mlx4_qp_table *qp_table = &priv->qp_table;
	333	int err;
	334
	335	if (!qpn)
	336	return -EINVAL;
	337
	338	qp->qpn = qpn;
	339
	340	err = mlx4_qp_alloc_icm(dev, qpn);
	341	if (err)
	342	return err;
	343
	344	spin_lock_irq(&qp_table->lock);
	345	err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
	346	(dev->caps.num_qps - 1), qp);
	347	spin_unlock_irq(&qp_table->lock);
	348	if (err)
	349	goto err_icm;
	350
	351	atomic_set(&qp->refcount, 1);
	352	init_completion(&qp->free);
	353
	354	return 0;
	355
	356	err_icm:
	357	mlx4_qp_free_icm(dev, qpn);
	358	return err;
	359	}
	360
225c7b1f RD	361	EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
	362
	363	void mlx4_qp_remove(struct mlx4_dev dev, struct mlx4_qp qp)
	364	{
	365	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
	366	unsigned long flags;
	367
	368	spin_lock_irqsave(&qp_table->lock, flags);
	369	radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
	370	spin_unlock_irqrestore(&qp_table->lock, flags);
	371	}
	372	EXPORT_SYMBOL_GPL(mlx4_qp_remove);
	373
	374	void mlx4_qp_free(struct mlx4_dev dev, struct mlx4_qp qp)
	375	{
225c7b1f RD	376	if (atomic_dec_and_test(&qp->refcount))
	377	complete(&qp->free);
	378	wait_for_completion(&qp->free);
	379
fe9a2603	380	mlx4_qp_free_icm(dev, qp->qpn);
225c7b1f RD	381	}
	382	EXPORT_SYMBOL_GPL(mlx4_qp_free);
	383
	384	static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
	385	{
	386	return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
f9baff50	387	MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f RD	388	}
225c7b1f RD	389
3d73c288	390	int mlx4_init_qp_table(struct mlx4_dev *dev)
225c7b1f RD	391	{
	392	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
	393	int err;
93fc9e1b	394	int reserved_from_top = 0;
225c7b1f RD	395
	396	spin_lock_init(&qp_table->lock);
	397	INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
fe9a2603 JM	398	if (mlx4_is_slave(dev))
fe9a2603 JM	399	return 0;
225c7b1f RD	400
	401	/*
	402	* We reserve 2 extra QPs per port for the special QPs. The
	403	* block of special QPs must be aligned to a multiple of 8, so
	404	* round up.
0a1405da SH	405	*
	406	* We also reserve the MSB of the 24-bit QP number to indicate
	407	* that a QP is an XRC QP.
225c7b1f	408	*/
93fc9e1b YP	409	dev->caps.sqp_start =
	410	ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8);
	411
	412	{
	413	int sort[MLX4_NUM_QP_REGION];
	414	int i, j, tmp;
	415	int last_base = dev->caps.num_qps;
	416
	417	for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
	418	sort[i] = i;
	419
	420	for (i = MLX4_NUM_QP_REGION; i > 0; --i) {
	421	for (j = 2; j < i; ++j) {
	422	if (dev->caps.reserved_qps_cnt[sort[j]] >
	423	dev->caps.reserved_qps_cnt[sort[j - 1]]) {
	424	tmp = sort[j];
	425	sort[j] = sort[j - 1];
	426	sort[j - 1] = tmp;
	427	}
	428	}
	429	}
	430
	431	for (i = 1; i < MLX4_NUM_QP_REGION; ++i) {
	432	last_base -= dev->caps.reserved_qps_cnt[sort[i]];
	433	dev->caps.reserved_qps_base[sort[i]] = last_base;
	434	reserved_from_top +=
	435	dev->caps.reserved_qps_cnt[sort[i]];
	436	}
	437
	438	}
	439
225c7b1f	440	err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps,
93fc9e1b YP	441	(1 << 23) - 1, dev->caps.sqp_start + 8,
93fc9e1b YP	442	reserved_from_top);
225c7b1f RD	443	if (err)
	444	return err;
	445
	446	return mlx4_CONF_SPECIAL_QP(dev, dev->caps.sqp_start);
	447	}
	448
	449	void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
	450	{
fe9a2603 JM	451	if (mlx4_is_slave(dev))
	452	return;
	453
225c7b1f RD	454	mlx4_CONF_SPECIAL_QP(dev, 0);
	455	mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap);
	456	}
6a775e2b JM	457
	458	int mlx4_qp_query(struct mlx4_dev dev, struct mlx4_qp qp,
	459	struct mlx4_qp_context *context)
	460	{
	461	struct mlx4_cmd_mailbox *mailbox;
	462	int err;
	463
	464	mailbox = mlx4_alloc_cmd_mailbox(dev);
	465	if (IS_ERR(mailbox))
	466	return PTR_ERR(mailbox);
	467
	468	err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
f9baff50 JM	469	MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
f9baff50 JM	470	MLX4_CMD_WRAPPED);
6a775e2b JM	471	if (!err)
	472	memcpy(context, mailbox->buf + 8, sizeof *context);
	473
	474	mlx4_free_cmd_mailbox(dev, mailbox);
	475	return err;
	476	}
	477	EXPORT_SYMBOL_GPL(mlx4_qp_query);
	478
ed4d3c10 YP	479	int mlx4_qp_to_ready(struct mlx4_dev dev, struct mlx4_mtt mtt,
	480	struct mlx4_qp_context *context,
	481	struct mlx4_qp qp, enum mlx4_qp_state qp_state)
	482	{
	483	int err;
	484	int i;
	485	enum mlx4_qp_state states[] = {
	486	MLX4_QP_STATE_RST,
	487	MLX4_QP_STATE_INIT,
	488	MLX4_QP_STATE_RTR,
	489	MLX4_QP_STATE_RTS
	490	};
	491
	492	for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
	493	context->flags &= cpu_to_be32(~(0xf << 28));
	494	context->flags \|= cpu_to_be32(states[i + 1] << 28);
	495	err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
	496	context, 0, 0, qp);
	497	if (err) {
	498	mlx4_err(dev, "Failed to bring QP to state: "
	499	"%d with error: %d\n",
	500	states[i + 1], err);
	501	return err;
	502	}
	503
	504	*qp_state = states[i + 1];
	505	}
	506
	507	return 0;
	508	}
	509	EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);