Commit | Line | Data |
---|---|---|
f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/if_vlan.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/mlx5/driver.h> | |
36 | #include <linux/mlx5/qp.h> | |
37 | #include <linux/mlx5/cq.h> | |
d18a9470 | 38 | #include <linux/mlx5/vport.h> |
f62b8bb8 AV |
39 | #include "wq.h" |
40 | #include "transobj.h" | |
41 | #include "mlx5_core.h" | |
42 | ||
43 | #define MLX5E_MAX_NUM_TC 8 | |
44 | ||
e842b100 | 45 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
46 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
47 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
48 | ||
e842b100 | 49 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
50 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
51 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
52 | ||
d9a40271 | 53 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 AV |
54 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
55 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
56 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
57 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
58 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
f62b8bb8 | 59 | |
936896e9 AS |
60 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
61 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
62 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
63 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
64 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 65 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 AV |
66 | |
67 | static const char vport_strings[][ETH_GSTRING_LEN] = { | |
68 | /* vport statistics */ | |
69 | "rx_packets", | |
70 | "rx_bytes", | |
71 | "tx_packets", | |
72 | "tx_bytes", | |
73 | "rx_error_packets", | |
74 | "rx_error_bytes", | |
75 | "tx_error_packets", | |
76 | "tx_error_bytes", | |
77 | "rx_unicast_packets", | |
78 | "rx_unicast_bytes", | |
79 | "tx_unicast_packets", | |
80 | "tx_unicast_bytes", | |
81 | "rx_multicast_packets", | |
82 | "rx_multicast_bytes", | |
83 | "tx_multicast_packets", | |
84 | "tx_multicast_bytes", | |
85 | "rx_broadcast_packets", | |
86 | "rx_broadcast_bytes", | |
87 | "tx_broadcast_packets", | |
88 | "tx_broadcast_bytes", | |
89 | ||
90 | /* SW counters */ | |
91 | "tso_packets", | |
92 | "tso_bytes", | |
93 | "lro_packets", | |
94 | "lro_bytes", | |
95 | "rx_csum_good", | |
96 | "rx_csum_none", | |
bbceefce | 97 | "rx_csum_sw", |
f62b8bb8 AV |
98 | "tx_csum_offload", |
99 | "tx_queue_stopped", | |
100 | "tx_queue_wake", | |
101 | "tx_queue_dropped", | |
102 | "rx_wqe_err", | |
103 | }; | |
104 | ||
105 | struct mlx5e_vport_stats { | |
106 | /* HW counters */ | |
107 | u64 rx_packets; | |
108 | u64 rx_bytes; | |
109 | u64 tx_packets; | |
110 | u64 tx_bytes; | |
111 | u64 rx_error_packets; | |
112 | u64 rx_error_bytes; | |
113 | u64 tx_error_packets; | |
114 | u64 tx_error_bytes; | |
115 | u64 rx_unicast_packets; | |
116 | u64 rx_unicast_bytes; | |
117 | u64 tx_unicast_packets; | |
118 | u64 tx_unicast_bytes; | |
119 | u64 rx_multicast_packets; | |
120 | u64 rx_multicast_bytes; | |
121 | u64 tx_multicast_packets; | |
122 | u64 tx_multicast_bytes; | |
123 | u64 rx_broadcast_packets; | |
124 | u64 rx_broadcast_bytes; | |
125 | u64 tx_broadcast_packets; | |
126 | u64 tx_broadcast_bytes; | |
127 | ||
128 | /* SW counters */ | |
129 | u64 tso_packets; | |
130 | u64 tso_bytes; | |
131 | u64 lro_packets; | |
132 | u64 lro_bytes; | |
133 | u64 rx_csum_good; | |
134 | u64 rx_csum_none; | |
bbceefce | 135 | u64 rx_csum_sw; |
f62b8bb8 AV |
136 | u64 tx_csum_offload; |
137 | u64 tx_queue_stopped; | |
138 | u64 tx_queue_wake; | |
139 | u64 tx_queue_dropped; | |
140 | u64 rx_wqe_err; | |
141 | ||
bbceefce | 142 | #define NUM_VPORT_COUNTERS 32 |
f62b8bb8 AV |
143 | }; |
144 | ||
efea389d GP |
145 | static const char pport_strings[][ETH_GSTRING_LEN] = { |
146 | /* IEEE802.3 counters */ | |
147 | "frames_tx", | |
148 | "frames_rx", | |
149 | "check_seq_err", | |
150 | "alignment_err", | |
151 | "octets_tx", | |
152 | "octets_received", | |
153 | "multicast_xmitted", | |
154 | "broadcast_xmitted", | |
155 | "multicast_rx", | |
156 | "broadcast_rx", | |
157 | "in_range_len_errors", | |
158 | "out_of_range_len", | |
159 | "too_long_errors", | |
160 | "symbol_err", | |
161 | "mac_control_tx", | |
162 | "mac_control_rx", | |
163 | "unsupported_op_rx", | |
164 | "pause_ctrl_rx", | |
165 | "pause_ctrl_tx", | |
166 | ||
167 | /* RFC2863 counters */ | |
168 | "in_octets", | |
169 | "in_ucast_pkts", | |
170 | "in_discards", | |
171 | "in_errors", | |
172 | "in_unknown_protos", | |
173 | "out_octets", | |
174 | "out_ucast_pkts", | |
175 | "out_discards", | |
176 | "out_errors", | |
177 | "in_multicast_pkts", | |
178 | "in_broadcast_pkts", | |
179 | "out_multicast_pkts", | |
180 | "out_broadcast_pkts", | |
181 | ||
182 | /* RFC2819 counters */ | |
183 | "drop_events", | |
184 | "octets", | |
185 | "pkts", | |
186 | "broadcast_pkts", | |
187 | "multicast_pkts", | |
188 | "crc_align_errors", | |
189 | "undersize_pkts", | |
190 | "oversize_pkts", | |
191 | "fragments", | |
192 | "jabbers", | |
193 | "collisions", | |
194 | "p64octets", | |
195 | "p65to127octets", | |
196 | "p128to255octets", | |
197 | "p256to511octets", | |
198 | "p512to1023octets", | |
199 | "p1024to1518octets", | |
200 | "p1519to2047octets", | |
201 | "p2048to4095octets", | |
202 | "p4096to8191octets", | |
203 | "p8192to10239octets", | |
204 | }; | |
205 | ||
206 | #define NUM_IEEE_802_3_COUNTERS 19 | |
207 | #define NUM_RFC_2863_COUNTERS 13 | |
208 | #define NUM_RFC_2819_COUNTERS 21 | |
209 | #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \ | |
210 | NUM_RFC_2863_COUNTERS + \ | |
211 | NUM_RFC_2819_COUNTERS) | |
212 | ||
213 | struct mlx5e_pport_stats { | |
214 | __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS]; | |
215 | __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS]; | |
216 | __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS]; | |
217 | }; | |
218 | ||
f62b8bb8 AV |
219 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { |
220 | "packets", | |
221 | "csum_none", | |
bbceefce | 222 | "csum_sw", |
f62b8bb8 AV |
223 | "lro_packets", |
224 | "lro_bytes", | |
225 | "wqe_err" | |
226 | }; | |
227 | ||
228 | struct mlx5e_rq_stats { | |
229 | u64 packets; | |
230 | u64 csum_none; | |
bbceefce | 231 | u64 csum_sw; |
f62b8bb8 AV |
232 | u64 lro_packets; |
233 | u64 lro_bytes; | |
234 | u64 wqe_err; | |
bbceefce | 235 | #define NUM_RQ_STATS 6 |
f62b8bb8 AV |
236 | }; |
237 | ||
238 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { | |
239 | "packets", | |
240 | "tso_packets", | |
241 | "tso_bytes", | |
242 | "csum_offload_none", | |
243 | "stopped", | |
244 | "wake", | |
245 | "dropped", | |
246 | "nop" | |
247 | }; | |
248 | ||
249 | struct mlx5e_sq_stats { | |
250 | u64 packets; | |
251 | u64 tso_packets; | |
252 | u64 tso_bytes; | |
253 | u64 csum_offload_none; | |
254 | u64 stopped; | |
255 | u64 wake; | |
256 | u64 dropped; | |
257 | u64 nop; | |
258 | #define NUM_SQ_STATS 8 | |
259 | }; | |
260 | ||
261 | struct mlx5e_stats { | |
262 | struct mlx5e_vport_stats vport; | |
efea389d | 263 | struct mlx5e_pport_stats pport; |
f62b8bb8 AV |
264 | }; |
265 | ||
266 | struct mlx5e_params { | |
267 | u8 log_sq_size; | |
268 | u8 log_rq_size; | |
269 | u16 num_channels; | |
270 | u8 default_vlan_prio; | |
271 | u8 num_tc; | |
272 | u16 rx_cq_moderation_usec; | |
273 | u16 rx_cq_moderation_pkts; | |
274 | u16 tx_cq_moderation_usec; | |
275 | u16 tx_cq_moderation_pkts; | |
276 | u16 min_rx_wqes; | |
f62b8bb8 AV |
277 | bool lro_en; |
278 | u32 lro_wqe_sz; | |
58d52291 | 279 | u16 tx_max_inline; |
2d75b2bc AS |
280 | u8 rss_hfunc; |
281 | u8 toeplitz_hash_key[40]; | |
282 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
f62b8bb8 AV |
283 | }; |
284 | ||
285 | enum { | |
286 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
287 | }; | |
288 | ||
289 | enum cq_flags { | |
290 | MLX5E_CQ_HAS_CQES = 1, | |
291 | }; | |
292 | ||
293 | struct mlx5e_cq { | |
294 | /* data path - accessed per cqe */ | |
295 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
296 | unsigned long flags; |
297 | ||
298 | /* data path - accessed per napi poll */ | |
299 | struct napi_struct *napi; | |
300 | struct mlx5_core_cq mcq; | |
301 | struct mlx5e_channel *channel; | |
50cfa25a | 302 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
303 | |
304 | /* control */ | |
305 | struct mlx5_wq_ctrl wq_ctrl; | |
306 | } ____cacheline_aligned_in_smp; | |
307 | ||
308 | struct mlx5e_rq { | |
309 | /* data path */ | |
310 | struct mlx5_wq_ll wq; | |
311 | u32 wqe_sz; | |
312 | struct sk_buff **skb; | |
313 | ||
314 | struct device *pdev; | |
315 | struct net_device *netdev; | |
316 | struct mlx5e_rq_stats stats; | |
317 | struct mlx5e_cq cq; | |
318 | ||
319 | unsigned long state; | |
320 | int ix; | |
321 | ||
322 | /* control */ | |
323 | struct mlx5_wq_ctrl wq_ctrl; | |
324 | u32 rqn; | |
325 | struct mlx5e_channel *channel; | |
50cfa25a | 326 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
327 | } ____cacheline_aligned_in_smp; |
328 | ||
329 | struct mlx5e_tx_skb_cb { | |
330 | u32 num_bytes; | |
331 | u8 num_wqebbs; | |
332 | u8 num_dma; | |
333 | }; | |
334 | ||
335 | #define MLX5E_TX_SKB_CB(__skb) ((struct mlx5e_tx_skb_cb *)__skb->cb) | |
336 | ||
d4e28cbd AS |
337 | enum mlx5e_dma_map_type { |
338 | MLX5E_DMA_MAP_SINGLE, | |
339 | MLX5E_DMA_MAP_PAGE | |
340 | }; | |
341 | ||
f62b8bb8 | 342 | struct mlx5e_sq_dma { |
d4e28cbd AS |
343 | dma_addr_t addr; |
344 | u32 size; | |
345 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
346 | }; |
347 | ||
348 | enum { | |
349 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
350 | }; | |
351 | ||
352 | struct mlx5e_sq { | |
353 | /* data path */ | |
354 | ||
355 | /* dirtied @completion */ | |
356 | u16 cc; | |
357 | u32 dma_fifo_cc; | |
358 | ||
359 | /* dirtied @xmit */ | |
360 | u16 pc ____cacheline_aligned_in_smp; | |
361 | u32 dma_fifo_pc; | |
88a85f99 AS |
362 | u16 bf_offset; |
363 | u16 prev_cc; | |
364 | u8 bf_budget; | |
f62b8bb8 AV |
365 | struct mlx5e_sq_stats stats; |
366 | ||
367 | struct mlx5e_cq cq; | |
368 | ||
369 | /* pointers to per packet info: write@xmit, read@completion */ | |
370 | struct sk_buff **skb; | |
371 | struct mlx5e_sq_dma *dma_fifo; | |
372 | ||
373 | /* read only */ | |
374 | struct mlx5_wq_cyc wq; | |
375 | u32 dma_fifo_mask; | |
376 | void __iomem *uar_map; | |
88a85f99 | 377 | void __iomem *uar_bf_map; |
f62b8bb8 AV |
378 | struct netdev_queue *txq; |
379 | u32 sqn; | |
88a85f99 | 380 | u16 bf_buf_size; |
12be4b21 SM |
381 | u16 max_inline; |
382 | u16 edge; | |
f62b8bb8 AV |
383 | struct device *pdev; |
384 | __be32 mkey_be; | |
385 | unsigned long state; | |
386 | ||
387 | /* control path */ | |
388 | struct mlx5_wq_ctrl wq_ctrl; | |
389 | struct mlx5_uar uar; | |
390 | struct mlx5e_channel *channel; | |
391 | int tc; | |
392 | } ____cacheline_aligned_in_smp; | |
393 | ||
394 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
395 | { | |
396 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
397 | (sq->cc == sq->pc)); | |
398 | } | |
399 | ||
400 | enum channel_flags { | |
401 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
402 | }; | |
403 | ||
404 | struct mlx5e_channel { | |
405 | /* data path */ | |
406 | struct mlx5e_rq rq; | |
407 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
408 | struct napi_struct napi; | |
409 | struct device *pdev; | |
410 | struct net_device *netdev; | |
411 | __be32 mkey_be; | |
412 | u8 num_tc; | |
413 | unsigned long flags; | |
414 | ||
415 | /* control */ | |
416 | struct mlx5e_priv *priv; | |
417 | int ix; | |
418 | int cpu; | |
419 | }; | |
420 | ||
421 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
422 | MLX5E_TT_IPV4_TCP, |
423 | MLX5E_TT_IPV6_TCP, | |
424 | MLX5E_TT_IPV4_UDP, | |
425 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
426 | MLX5E_TT_IPV4_IPSEC_AH, |
427 | MLX5E_TT_IPV6_IPSEC_AH, | |
428 | MLX5E_TT_IPV4_IPSEC_ESP, | |
429 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
430 | MLX5E_TT_IPV4, |
431 | MLX5E_TT_IPV6, | |
432 | MLX5E_TT_ANY, | |
433 | MLX5E_NUM_TT, | |
f62b8bb8 AV |
434 | }; |
435 | ||
4cbeaff5 AS |
436 | enum mlx5e_rqt_ix { |
437 | MLX5E_INDIRECTION_RQT, | |
438 | MLX5E_SINGLE_RQ_RQT, | |
439 | MLX5E_NUM_RQT, | |
f62b8bb8 AV |
440 | }; |
441 | ||
442 | struct mlx5e_eth_addr_info { | |
443 | u8 addr[ETH_ALEN + 2]; | |
444 | u32 tt_vec; | |
445 | u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */ | |
446 | }; | |
447 | ||
448 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
449 | ||
450 | struct mlx5e_eth_addr_db { | |
451 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
452 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
453 | struct mlx5e_eth_addr_info broadcast; | |
454 | struct mlx5e_eth_addr_info allmulti; | |
455 | struct mlx5e_eth_addr_info promisc; | |
456 | bool broadcast_enabled; | |
457 | bool allmulti_enabled; | |
458 | bool promisc_enabled; | |
459 | }; | |
460 | ||
461 | enum { | |
462 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
463 | MLX5E_STATE_OPENED, | |
9b37b07f | 464 | MLX5E_STATE_DESTROYING, |
f62b8bb8 AV |
465 | }; |
466 | ||
467 | struct mlx5e_vlan_db { | |
f62b8bb8 AV |
468 | u32 active_vlans_ft_ix[VLAN_N_VID]; |
469 | u32 untagged_rule_ft_ix; | |
470 | u32 any_vlan_rule_ft_ix; | |
471 | bool filter_disabled; | |
472 | }; | |
473 | ||
474 | struct mlx5e_flow_table { | |
475 | void *vlan; | |
476 | void *main; | |
477 | }; | |
478 | ||
479 | struct mlx5e_priv { | |
480 | /* priv data path fields - start */ | |
f62b8bb8 | 481 | int default_vlan_prio; |
03289b88 | 482 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 483 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
484 | /* priv data path fields - end */ |
485 | ||
486 | unsigned long state; | |
487 | struct mutex state_lock; /* Protects Interface state */ | |
488 | struct mlx5_uar cq_uar; | |
489 | u32 pdn; | |
3191e05f | 490 | u32 tdn; |
f62b8bb8 | 491 | struct mlx5_core_mr mr; |
50cfa25a | 492 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
493 | |
494 | struct mlx5e_channel **channel; | |
495 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
4cbeaff5 | 496 | u32 rqtn[MLX5E_NUM_RQT]; |
f62b8bb8 AV |
497 | u32 tirn[MLX5E_NUM_TT]; |
498 | ||
499 | struct mlx5e_flow_table ft; | |
500 | struct mlx5e_eth_addr_db eth_addr; | |
501 | struct mlx5e_vlan_db vlan; | |
502 | ||
503 | struct mlx5e_params params; | |
504 | spinlock_t async_events_spinlock; /* sync hw events */ | |
505 | struct work_struct update_carrier_work; | |
506 | struct work_struct set_rx_mode_work; | |
507 | struct delayed_work update_stats_work; | |
508 | ||
509 | struct mlx5_core_dev *mdev; | |
510 | struct net_device *netdev; | |
511 | struct mlx5e_stats stats; | |
512 | }; | |
513 | ||
514 | #define MLX5E_NET_IP_ALIGN 2 | |
515 | ||
516 | struct mlx5e_tx_wqe { | |
517 | struct mlx5_wqe_ctrl_seg ctrl; | |
518 | struct mlx5_wqe_eth_seg eth; | |
519 | }; | |
520 | ||
521 | struct mlx5e_rx_wqe { | |
522 | struct mlx5_wqe_srq_next_seg next; | |
523 | struct mlx5_wqe_data_seg data; | |
524 | }; | |
525 | ||
526 | enum mlx5e_link_mode { | |
527 | MLX5E_1000BASE_CX_SGMII = 0, | |
528 | MLX5E_1000BASE_KX = 1, | |
529 | MLX5E_10GBASE_CX4 = 2, | |
530 | MLX5E_10GBASE_KX4 = 3, | |
531 | MLX5E_10GBASE_KR = 4, | |
532 | MLX5E_20GBASE_KR2 = 5, | |
533 | MLX5E_40GBASE_CR4 = 6, | |
534 | MLX5E_40GBASE_KR4 = 7, | |
535 | MLX5E_56GBASE_R4 = 8, | |
536 | MLX5E_10GBASE_CR = 12, | |
537 | MLX5E_10GBASE_SR = 13, | |
538 | MLX5E_10GBASE_ER = 14, | |
539 | MLX5E_40GBASE_SR4 = 15, | |
540 | MLX5E_40GBASE_LR4 = 16, | |
541 | MLX5E_100GBASE_CR4 = 20, | |
542 | MLX5E_100GBASE_SR4 = 21, | |
543 | MLX5E_100GBASE_KR4 = 22, | |
544 | MLX5E_100GBASE_LR4 = 23, | |
545 | MLX5E_100BASE_TX = 24, | |
546 | MLX5E_100BASE_T = 25, | |
547 | MLX5E_10GBASE_T = 26, | |
548 | MLX5E_25GBASE_CR = 27, | |
549 | MLX5E_25GBASE_KR = 28, | |
550 | MLX5E_25GBASE_SR = 29, | |
551 | MLX5E_50GBASE_CR2 = 30, | |
552 | MLX5E_50GBASE_KR2 = 31, | |
553 | MLX5E_LINK_MODES_NUMBER, | |
554 | }; | |
555 | ||
556 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
557 | ||
12be4b21 | 558 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
559 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
560 | void *accel_priv, select_queue_fallback_t fallback); | |
561 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
562 | |
563 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
564 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
565 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
566 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); | |
44fb6fbb | 567 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
f62b8bb8 AV |
568 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
569 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); | |
570 | ||
571 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
572 | ||
40ab6a6e AS |
573 | int mlx5e_create_flow_tables(struct mlx5e_priv *priv); |
574 | void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv); | |
f62b8bb8 | 575 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); |
f62b8bb8 AV |
576 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
577 | ||
578 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, | |
579 | u16 vid); | |
580 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
581 | u16 vid); | |
582 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
583 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 584 | |
2d75b2bc AS |
585 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix); |
586 | ||
f62b8bb8 AV |
587 | int mlx5e_open_locked(struct net_device *netdev); |
588 | int mlx5e_close_locked(struct net_device *netdev); | |
f62b8bb8 AV |
589 | |
590 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
88a85f99 | 591 | struct mlx5e_tx_wqe *wqe, int bf_sz) |
f62b8bb8 | 592 | { |
88a85f99 AS |
593 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
594 | ||
f62b8bb8 AV |
595 | /* ensure wqe is visible to device before updating doorbell record */ |
596 | dma_wmb(); | |
597 | ||
598 | *sq->wq.db = cpu_to_be32(sq->pc); | |
599 | ||
600 | /* ensure doorbell record is visible to device before ringing the | |
601 | * doorbell | |
602 | */ | |
603 | wmb(); | |
604 | ||
88a85f99 AS |
605 | if (bf_sz) { |
606 | __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz); | |
607 | ||
608 | /* flush the write-combining mapped buffer */ | |
609 | wmb(); | |
610 | ||
611 | } else { | |
612 | mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); | |
613 | } | |
f62b8bb8 AV |
614 | |
615 | sq->bf_offset ^= sq->bf_buf_size; | |
616 | } | |
617 | ||
618 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
619 | { | |
620 | struct mlx5_core_cq *mcq; | |
621 | ||
622 | mcq = &cq->mcq; | |
623 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
624 | } | |
625 | ||
3435ab59 AS |
626 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
627 | { | |
628 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
629 | MLX5E_MAX_NUM_CHANNELS); | |
630 | } | |
631 | ||
f62b8bb8 | 632 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
58d52291 | 633 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |