Commit | Line | Data |
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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
f62b8bb8 AV |
54 | #define MLX5E_MAX_NUM_TC 8 |
55 | ||
e842b100 | 56 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
57 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
58 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
59 | ||
e842b100 | 60 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
61 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
62 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
63 | ||
461017cb TT |
64 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
65 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4 | |
66 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 | |
67 | ||
461017cb | 68 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 TT |
69 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
70 | #define MLX5_MPWRQ_LOG_WQE_SZ 17 | |
461017cb TT |
71 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
72 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
73 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
74 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
75 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
76 | |
77 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
78 | #define MLX5E_REQUIRED_MTTS(rqs, wqes)\ | |
79 | (rqs * wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
80 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) <= U16_MAX) | |
81 | ||
bc77b240 | 82 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
83 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
84 | ||
d9a40271 | 85 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 | 86 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 87 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
88 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
89 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
90 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
91 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 92 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 93 | |
936896e9 AS |
94 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
95 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
96 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
507f0c81 | 97 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
98 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
99 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 100 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 101 | |
86d722ad | 102 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 103 | |
461017cb TT |
104 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
105 | { | |
106 | switch (wq_type) { | |
107 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
108 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
109 | wq_size / 2); | |
110 | default: | |
111 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
112 | wq_size / 2); | |
113 | } | |
114 | } | |
115 | ||
116 | static inline int mlx5_min_log_rq_size(int wq_type) | |
117 | { | |
118 | switch (wq_type) { | |
119 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
120 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
121 | default: | |
122 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
123 | } | |
124 | } | |
125 | ||
126 | static inline int mlx5_max_log_rq_size(int wq_type) | |
127 | { | |
128 | switch (wq_type) { | |
129 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
130 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
131 | default: | |
132 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
133 | } | |
134 | } | |
135 | ||
cff92d7c HHZ |
136 | enum { |
137 | MLX5E_INLINE_MODE_L2, | |
138 | MLX5E_INLINE_MODE_VPORT_CONTEXT, | |
139 | MLX5_INLINE_MODE_NOT_REQUIRED, | |
140 | }; | |
141 | ||
2f48af12 TT |
142 | struct mlx5e_tx_wqe { |
143 | struct mlx5_wqe_ctrl_seg ctrl; | |
144 | struct mlx5_wqe_eth_seg eth; | |
145 | }; | |
146 | ||
147 | struct mlx5e_rx_wqe { | |
148 | struct mlx5_wqe_srq_next_seg next; | |
149 | struct mlx5_wqe_data_seg data; | |
150 | }; | |
86d722ad | 151 | |
bc77b240 TT |
152 | struct mlx5e_umr_wqe { |
153 | struct mlx5_wqe_ctrl_seg ctrl; | |
154 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
155 | struct mlx5_mkey_seg mkc; | |
156 | struct mlx5_wqe_data_seg data; | |
157 | }; | |
158 | ||
4e59e288 | 159 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 160 | "rx_cqe_moder", |
4e59e288 GP |
161 | }; |
162 | ||
163 | enum mlx5e_priv_flag { | |
9908aa29 | 164 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
4e59e288 GP |
165 | }; |
166 | ||
167 | #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \ | |
168 | do { \ | |
169 | if (enable) \ | |
170 | priv->pflags |= pflag; \ | |
171 | else \ | |
172 | priv->pflags &= ~pflag; \ | |
173 | } while (0) | |
174 | ||
08fb1dac SM |
175 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
176 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
177 | #endif |
178 | ||
9908aa29 TT |
179 | struct mlx5e_cq_moder { |
180 | u16 usec; | |
181 | u16 pkts; | |
182 | }; | |
183 | ||
f62b8bb8 AV |
184 | struct mlx5e_params { |
185 | u8 log_sq_size; | |
461017cb | 186 | u8 rq_wq_type; |
d9d9f156 TT |
187 | u8 mpwqe_log_stride_sz; |
188 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
189 | u8 log_rq_size; |
190 | u16 num_channels; | |
f62b8bb8 | 191 | u8 num_tc; |
9908aa29 | 192 | u8 rx_cq_period_mode; |
7219ab34 TT |
193 | bool rx_cqe_compress_admin; |
194 | bool rx_cqe_compress; | |
9908aa29 TT |
195 | struct mlx5e_cq_moder rx_cq_moderation; |
196 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 197 | u16 min_rx_wqes; |
f62b8bb8 AV |
198 | bool lro_en; |
199 | u32 lro_wqe_sz; | |
58d52291 | 200 | u16 tx_max_inline; |
cff92d7c | 201 | u8 tx_min_inline_mode; |
2d75b2bc AS |
202 | u8 rss_hfunc; |
203 | u8 toeplitz_hash_key[40]; | |
204 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 205 | bool vlan_strip_disable; |
08fb1dac SM |
206 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
207 | struct ieee_ets ets; | |
208 | #endif | |
cb3c7fd4 | 209 | bool rx_am_enabled; |
f62b8bb8 AV |
210 | }; |
211 | ||
ef9814de EBE |
212 | struct mlx5e_tstamp { |
213 | rwlock_t lock; | |
214 | struct cyclecounter cycles; | |
215 | struct timecounter clock; | |
216 | struct hwtstamp_config hwtstamp_config; | |
217 | u32 nominal_c_mult; | |
218 | unsigned long overflow_period; | |
219 | struct delayed_work overflow_work; | |
220 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
221 | struct ptp_clock *ptp; |
222 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
223 | }; |
224 | ||
f62b8bb8 | 225 | enum { |
f2fde18c | 226 | MLX5E_RQ_STATE_FLUSH, |
bc77b240 | 227 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 228 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
229 | }; |
230 | ||
f62b8bb8 AV |
231 | struct mlx5e_cq { |
232 | /* data path - accessed per cqe */ | |
233 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
234 | |
235 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 236 | u16 event_ctr; |
f62b8bb8 AV |
237 | struct napi_struct *napi; |
238 | struct mlx5_core_cq mcq; | |
239 | struct mlx5e_channel *channel; | |
50cfa25a | 240 | struct mlx5e_priv *priv; |
f62b8bb8 | 241 | |
7219ab34 TT |
242 | /* cqe decompression */ |
243 | struct mlx5_cqe64 title; | |
244 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
245 | u8 mini_arr_idx; | |
246 | u16 decmprs_left; | |
247 | u16 decmprs_wqe_counter; | |
248 | ||
f62b8bb8 AV |
249 | /* control */ |
250 | struct mlx5_wq_ctrl wq_ctrl; | |
251 | } ____cacheline_aligned_in_smp; | |
252 | ||
2f48af12 TT |
253 | struct mlx5e_rq; |
254 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
255 | struct mlx5_cqe64 *cqe); | |
256 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
257 | u16 ix); | |
258 | ||
6cd392a0 DJ |
259 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix); |
260 | ||
461017cb TT |
261 | struct mlx5e_dma_info { |
262 | struct page *page; | |
263 | dma_addr_t addr; | |
264 | }; | |
265 | ||
cb3c7fd4 GR |
266 | struct mlx5e_rx_am_stats { |
267 | int ppms; /* packets per msec */ | |
268 | int epms; /* events per msec */ | |
269 | }; | |
270 | ||
271 | struct mlx5e_rx_am_sample { | |
272 | ktime_t time; | |
273 | unsigned int pkt_ctr; | |
274 | u16 event_ctr; | |
275 | }; | |
276 | ||
277 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
278 | u8 state; | |
279 | struct mlx5e_rx_am_stats prev_stats; | |
280 | struct mlx5e_rx_am_sample start_sample; | |
281 | struct work_struct work; | |
282 | u8 profile_ix; | |
283 | u8 mode; | |
284 | u8 tune_state; | |
285 | u8 steps_right; | |
286 | u8 steps_left; | |
287 | u8 tired; | |
288 | }; | |
289 | ||
f62b8bb8 AV |
290 | struct mlx5e_rq { |
291 | /* data path */ | |
292 | struct mlx5_wq_ll wq; | |
293 | u32 wqe_sz; | |
294 | struct sk_buff **skb; | |
461017cb | 295 | struct mlx5e_mpw_info *wqe_info; |
bc77b240 TT |
296 | __be32 mkey_be; |
297 | __be32 umr_mkey_be; | |
f62b8bb8 AV |
298 | |
299 | struct device *pdev; | |
300 | struct net_device *netdev; | |
ef9814de | 301 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
302 | struct mlx5e_rq_stats stats; |
303 | struct mlx5e_cq cq; | |
2f48af12 TT |
304 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
305 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 306 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
307 | |
308 | unsigned long state; | |
309 | int ix; | |
fe4c988b | 310 | u32 mpwqe_mtt_offset; |
f62b8bb8 | 311 | |
cb3c7fd4 GR |
312 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
313 | ||
f62b8bb8 AV |
314 | /* control */ |
315 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 316 | u8 wq_type; |
d9d9f156 TT |
317 | u32 mpwqe_stride_sz; |
318 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
319 | u32 rqn; |
320 | struct mlx5e_channel *channel; | |
50cfa25a | 321 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
322 | } ____cacheline_aligned_in_smp; |
323 | ||
bc77b240 TT |
324 | struct mlx5e_umr_dma_info { |
325 | __be64 *mtt; | |
326 | __be64 *mtt_no_align; | |
327 | dma_addr_t mtt_addr; | |
328 | struct mlx5e_dma_info *dma_info; | |
329 | }; | |
330 | ||
331 | struct mlx5e_mpw_info { | |
332 | union { | |
333 | struct mlx5e_dma_info dma_info; | |
334 | struct mlx5e_umr_dma_info umr; | |
335 | }; | |
336 | u16 consumed_strides; | |
337 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
338 | ||
339 | void (*dma_pre_sync)(struct device *pdev, | |
340 | struct mlx5e_mpw_info *wi, | |
341 | u32 wqe_offset, u32 len); | |
d9d9f156 | 342 | void (*add_skb_frag)(struct mlx5e_rq *rq, |
bc77b240 TT |
343 | struct sk_buff *skb, |
344 | struct mlx5e_mpw_info *wi, | |
345 | u32 page_idx, u32 frag_offset, u32 len); | |
346 | void (*copy_skb_header)(struct device *pdev, | |
347 | struct sk_buff *skb, | |
348 | struct mlx5e_mpw_info *wi, | |
349 | u32 page_idx, u32 offset, | |
350 | u32 headlen); | |
351 | void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
352 | }; | |
353 | ||
34802a42 | 354 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
355 | u32 num_bytes; |
356 | u8 num_wqebbs; | |
357 | u8 num_dma; | |
358 | }; | |
359 | ||
d4e28cbd AS |
360 | enum mlx5e_dma_map_type { |
361 | MLX5E_DMA_MAP_SINGLE, | |
362 | MLX5E_DMA_MAP_PAGE | |
363 | }; | |
364 | ||
f62b8bb8 | 365 | struct mlx5e_sq_dma { |
d4e28cbd AS |
366 | dma_addr_t addr; |
367 | u32 size; | |
368 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
369 | }; |
370 | ||
371 | enum { | |
6e8dd6d6 | 372 | MLX5E_SQ_STATE_FLUSH, |
0ba42241 | 373 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
374 | }; |
375 | ||
d3c9bc27 TT |
376 | struct mlx5e_ico_wqe_info { |
377 | u8 opcode; | |
378 | u8 num_wqebbs; | |
379 | }; | |
380 | ||
f62b8bb8 AV |
381 | struct mlx5e_sq { |
382 | /* data path */ | |
383 | ||
384 | /* dirtied @completion */ | |
385 | u16 cc; | |
386 | u32 dma_fifo_cc; | |
387 | ||
388 | /* dirtied @xmit */ | |
389 | u16 pc ____cacheline_aligned_in_smp; | |
390 | u32 dma_fifo_pc; | |
88a85f99 AS |
391 | u16 bf_offset; |
392 | u16 prev_cc; | |
393 | u8 bf_budget; | |
f62b8bb8 AV |
394 | struct mlx5e_sq_stats stats; |
395 | ||
396 | struct mlx5e_cq cq; | |
397 | ||
398 | /* pointers to per packet info: write@xmit, read@completion */ | |
399 | struct sk_buff **skb; | |
400 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 401 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
402 | |
403 | /* read only */ | |
404 | struct mlx5_wq_cyc wq; | |
405 | u32 dma_fifo_mask; | |
406 | void __iomem *uar_map; | |
407 | struct netdev_queue *txq; | |
408 | u32 sqn; | |
88a85f99 | 409 | u16 bf_buf_size; |
12be4b21 | 410 | u16 max_inline; |
ae76715d | 411 | u8 min_inline_mode; |
12be4b21 | 412 | u16 edge; |
f62b8bb8 | 413 | struct device *pdev; |
ef9814de | 414 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
415 | __be32 mkey_be; |
416 | unsigned long state; | |
417 | ||
418 | /* control path */ | |
419 | struct mlx5_wq_ctrl wq_ctrl; | |
420 | struct mlx5_uar uar; | |
421 | struct mlx5e_channel *channel; | |
422 | int tc; | |
d3c9bc27 | 423 | struct mlx5e_ico_wqe_info *ico_wqe_info; |
507f0c81 | 424 | u32 rate_limit; |
f62b8bb8 AV |
425 | } ____cacheline_aligned_in_smp; |
426 | ||
427 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
428 | { | |
429 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
430 | (sq->cc == sq->pc)); | |
431 | } | |
432 | ||
433 | enum channel_flags { | |
434 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
435 | }; | |
436 | ||
437 | struct mlx5e_channel { | |
438 | /* data path */ | |
439 | struct mlx5e_rq rq; | |
440 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 441 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
442 | struct napi_struct napi; |
443 | struct device *pdev; | |
444 | struct net_device *netdev; | |
445 | __be32 mkey_be; | |
446 | u8 num_tc; | |
447 | unsigned long flags; | |
448 | ||
449 | /* control */ | |
450 | struct mlx5e_priv *priv; | |
451 | int ix; | |
452 | int cpu; | |
453 | }; | |
454 | ||
455 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
456 | MLX5E_TT_IPV4_TCP, |
457 | MLX5E_TT_IPV6_TCP, | |
458 | MLX5E_TT_IPV4_UDP, | |
459 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
460 | MLX5E_TT_IPV4_IPSEC_AH, |
461 | MLX5E_TT_IPV6_IPSEC_AH, | |
462 | MLX5E_TT_IPV4_IPSEC_ESP, | |
463 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
464 | MLX5E_TT_IPV4, |
465 | MLX5E_TT_IPV6, | |
466 | MLX5E_TT_ANY, | |
467 | MLX5E_NUM_TT, | |
1da36696 | 468 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
469 | }; |
470 | ||
acff797c | 471 | enum { |
e0f46eb9 | 472 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
473 | MLX5E_STATE_OPENED, |
474 | MLX5E_STATE_DESTROYING, | |
475 | }; | |
476 | ||
477 | struct mlx5e_vxlan_db { | |
478 | spinlock_t lock; /* protect vxlan table */ | |
479 | struct radix_tree_root tree; | |
480 | }; | |
481 | ||
33cfaaa8 | 482 | struct mlx5e_l2_rule { |
f62b8bb8 | 483 | u8 addr[ETH_ALEN + 2]; |
33cfaaa8 | 484 | struct mlx5_flow_rule *rule; |
f62b8bb8 AV |
485 | }; |
486 | ||
acff797c MG |
487 | struct mlx5e_flow_table { |
488 | int num_groups; | |
489 | struct mlx5_flow_table *t; | |
490 | struct mlx5_flow_group **g; | |
491 | }; | |
492 | ||
33cfaaa8 | 493 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 494 | |
acff797c MG |
495 | struct mlx5e_tc_table { |
496 | struct mlx5_flow_table *t; | |
497 | ||
498 | struct rhashtable_params ht_params; | |
499 | struct rhashtable ht; | |
f62b8bb8 AV |
500 | }; |
501 | ||
acff797c MG |
502 | struct mlx5e_vlan_table { |
503 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 504 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
505 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
506 | struct mlx5_flow_rule *untagged_rule; | |
507 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
508 | bool filter_disabled; |
509 | }; | |
510 | ||
33cfaaa8 MG |
511 | struct mlx5e_l2_table { |
512 | struct mlx5e_flow_table ft; | |
513 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
514 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
515 | struct mlx5e_l2_rule broadcast; | |
516 | struct mlx5e_l2_rule allmulti; | |
517 | struct mlx5e_l2_rule promisc; | |
518 | bool broadcast_enabled; | |
519 | bool allmulti_enabled; | |
520 | bool promisc_enabled; | |
521 | }; | |
522 | ||
523 | /* L3/L4 traffic type classifier */ | |
524 | struct mlx5e_ttc_table { | |
525 | struct mlx5e_flow_table ft; | |
526 | struct mlx5_flow_rule *rules[MLX5E_NUM_TT]; | |
527 | }; | |
528 | ||
18c908e4 MG |
529 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
530 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
531 | struct arfs_table { |
532 | struct mlx5e_flow_table ft; | |
533 | struct mlx5_flow_rule *default_rule; | |
18c908e4 | 534 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
535 | }; |
536 | ||
537 | enum arfs_type { | |
538 | ARFS_IPV4_TCP, | |
539 | ARFS_IPV6_TCP, | |
540 | ARFS_IPV4_UDP, | |
541 | ARFS_IPV6_UDP, | |
542 | ARFS_NUM_TYPES, | |
543 | }; | |
544 | ||
545 | struct mlx5e_arfs_tables { | |
546 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
547 | /* Protect aRFS rules list */ |
548 | spinlock_t arfs_lock; | |
549 | struct list_head rules; | |
550 | int last_filter_id; | |
551 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
552 | }; |
553 | ||
554 | /* NIC prio FTS */ | |
555 | enum { | |
556 | MLX5E_VLAN_FT_LEVEL = 0, | |
557 | MLX5E_L2_FT_LEVEL, | |
558 | MLX5E_TTC_FT_LEVEL, | |
559 | MLX5E_ARFS_FT_LEVEL | |
560 | }; | |
561 | ||
6dc6071c MG |
562 | struct mlx5e_ethtool_table { |
563 | struct mlx5_flow_table *ft; | |
564 | int num_rules; | |
565 | }; | |
566 | ||
1174fce8 | 567 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
568 | #define ETHTOOL_NUM_L2_FTS 4 |
569 | ||
570 | struct mlx5e_ethtool_steering { | |
1174fce8 | 571 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
572 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
573 | struct list_head rules; | |
574 | int tot_num_rules; | |
575 | }; | |
576 | ||
acff797c MG |
577 | struct mlx5e_flow_steering { |
578 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 579 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
580 | struct mlx5e_tc_table tc; |
581 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
582 | struct mlx5e_l2_table l2; |
583 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 584 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
585 | }; |
586 | ||
398f3351 | 587 | struct mlx5e_rqt { |
1da36696 | 588 | u32 rqtn; |
398f3351 HHZ |
589 | bool enabled; |
590 | }; | |
591 | ||
592 | struct mlx5e_tir { | |
593 | u32 tirn; | |
594 | struct mlx5e_rqt rqt; | |
595 | struct list_head list; | |
1da36696 TT |
596 | }; |
597 | ||
acff797c MG |
598 | enum { |
599 | MLX5E_TC_PRIO = 0, | |
600 | MLX5E_NIC_PRIO | |
601 | }; | |
602 | ||
6bfd390b HHZ |
603 | struct mlx5e_profile { |
604 | void (*init)(struct mlx5_core_dev *mdev, | |
605 | struct net_device *netdev, | |
127ea380 | 606 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
607 | void (*cleanup)(struct mlx5e_priv *priv); |
608 | int (*init_rx)(struct mlx5e_priv *priv); | |
609 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
610 | int (*init_tx)(struct mlx5e_priv *priv); | |
611 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
612 | void (*enable)(struct mlx5e_priv *priv); | |
613 | void (*disable)(struct mlx5e_priv *priv); | |
614 | void (*update_stats)(struct mlx5e_priv *priv); | |
615 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
616 | int max_tc; | |
617 | }; | |
618 | ||
f62b8bb8 AV |
619 | struct mlx5e_priv { |
620 | /* priv data path fields - start */ | |
03289b88 | 621 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 622 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
623 | /* priv data path fields - end */ |
624 | ||
625 | unsigned long state; | |
626 | struct mutex state_lock; /* Protects Interface state */ | |
bc77b240 | 627 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 628 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
629 | |
630 | struct mlx5e_channel **channel; | |
631 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 632 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
633 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
634 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 635 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 636 | |
acff797c | 637 | struct mlx5e_flow_steering fs; |
b3f63c3d | 638 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
639 | |
640 | struct mlx5e_params params; | |
7bb29755 | 641 | struct workqueue_struct *wq; |
f62b8bb8 AV |
642 | struct work_struct update_carrier_work; |
643 | struct work_struct set_rx_mode_work; | |
3947ca18 | 644 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
645 | struct delayed_work update_stats_work; |
646 | ||
4e59e288 | 647 | u32 pflags; |
f62b8bb8 AV |
648 | struct mlx5_core_dev *mdev; |
649 | struct net_device *netdev; | |
650 | struct mlx5e_stats stats; | |
ef9814de | 651 | struct mlx5e_tstamp tstamp; |
593cf338 | 652 | u16 q_counter; |
6bfd390b | 653 | const struct mlx5e_profile *profile; |
127ea380 | 654 | void *ppriv; |
f62b8bb8 AV |
655 | }; |
656 | ||
f62b8bb8 AV |
657 | enum mlx5e_link_mode { |
658 | MLX5E_1000BASE_CX_SGMII = 0, | |
659 | MLX5E_1000BASE_KX = 1, | |
660 | MLX5E_10GBASE_CX4 = 2, | |
661 | MLX5E_10GBASE_KX4 = 3, | |
662 | MLX5E_10GBASE_KR = 4, | |
663 | MLX5E_20GBASE_KR2 = 5, | |
664 | MLX5E_40GBASE_CR4 = 6, | |
665 | MLX5E_40GBASE_KR4 = 7, | |
666 | MLX5E_56GBASE_R4 = 8, | |
667 | MLX5E_10GBASE_CR = 12, | |
668 | MLX5E_10GBASE_SR = 13, | |
669 | MLX5E_10GBASE_ER = 14, | |
670 | MLX5E_40GBASE_SR4 = 15, | |
671 | MLX5E_40GBASE_LR4 = 16, | |
4a50e35b | 672 | MLX5E_50GBASE_SR2 = 18, |
f62b8bb8 AV |
673 | MLX5E_100GBASE_CR4 = 20, |
674 | MLX5E_100GBASE_SR4 = 21, | |
675 | MLX5E_100GBASE_KR4 = 22, | |
676 | MLX5E_100GBASE_LR4 = 23, | |
677 | MLX5E_100BASE_TX = 24, | |
6e4c2189 | 678 | MLX5E_1000BASE_T = 25, |
f62b8bb8 AV |
679 | MLX5E_10GBASE_T = 26, |
680 | MLX5E_25GBASE_CR = 27, | |
681 | MLX5E_25GBASE_KR = 28, | |
682 | MLX5E_25GBASE_SR = 29, | |
683 | MLX5E_50GBASE_CR2 = 30, | |
684 | MLX5E_50GBASE_KR2 = 31, | |
685 | MLX5E_LINK_MODES_NUMBER, | |
686 | }; | |
687 | ||
688 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
689 | ||
665bc539 GP |
690 | |
691 | void mlx5e_build_ptys2ethtool_map(void); | |
692 | ||
12be4b21 | 693 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
694 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
695 | void *accel_priv, select_queue_fallback_t fallback); | |
696 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
697 | |
698 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
699 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
700 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 701 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 702 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
29429f33 | 703 | void mlx5e_free_tx_descs(struct mlx5e_sq *sq); |
461017cb | 704 | |
2f48af12 | 705 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 706 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 707 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 708 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
461017cb | 709 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
710 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
711 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
bc77b240 TT |
712 | void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq); |
713 | void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
714 | struct mlx5_cqe64 *cqe, | |
715 | u16 byte_cnt, | |
716 | struct mlx5e_mpw_info *wi, | |
717 | struct sk_buff *skb); | |
718 | void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
719 | struct mlx5_cqe64 *cqe, | |
720 | u16 byte_cnt, | |
721 | struct mlx5e_mpw_info *wi, | |
722 | struct sk_buff *skb); | |
723 | void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
724 | struct mlx5e_mpw_info *wi); | |
725 | void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
726 | struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
727 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
728 | ||
cb3c7fd4 GR |
729 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
730 | void mlx5e_rx_am_work(struct work_struct *work); | |
731 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
732 | ||
f62b8bb8 AV |
733 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
734 | ||
acff797c MG |
735 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
736 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 737 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 738 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
f913a72a MG |
739 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
740 | int location); | |
741 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
742 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
743 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
744 | struct ethtool_rx_flow_spec *fs); | |
745 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
746 | int location); | |
747 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
748 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
749 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
750 | ||
ef9814de EBE |
751 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
752 | struct skb_shared_hwtstamps *hwts); | |
753 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
754 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
755 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
756 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 757 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 758 | |
f62b8bb8 AV |
759 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
760 | u16 vid); | |
761 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
762 | u16 vid); | |
763 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
764 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 765 | |
36350114 GP |
766 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
767 | ||
1da36696 | 768 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 769 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 770 | |
f62b8bb8 AV |
771 | int mlx5e_open_locked(struct net_device *netdev); |
772 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
773 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
774 | u32 *indirection_rqt, int len, | |
85082dba | 775 | int num_channels); |
b797a684 | 776 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 777 | |
9908aa29 TT |
778 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
779 | u8 cq_period_mode); | |
780 | ||
f62b8bb8 | 781 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 782 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 783 | { |
88a85f99 AS |
784 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
785 | ||
f62b8bb8 AV |
786 | /* ensure wqe is visible to device before updating doorbell record */ |
787 | dma_wmb(); | |
788 | ||
789 | *sq->wq.db = cpu_to_be32(sq->pc); | |
790 | ||
791 | /* ensure doorbell record is visible to device before ringing the | |
792 | * doorbell | |
793 | */ | |
794 | wmb(); | |
0ba42241 | 795 | if (bf_sz) |
bc77b240 | 796 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 797 | else |
bc77b240 | 798 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
799 | /* flush the write-combining mapped buffer */ |
800 | wmb(); | |
f62b8bb8 AV |
801 | |
802 | sq->bf_offset ^= sq->bf_buf_size; | |
803 | } | |
804 | ||
805 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
806 | { | |
807 | struct mlx5_core_cq *mcq; | |
808 | ||
809 | mcq = &cq->mcq; | |
810 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
811 | } | |
812 | ||
3435ab59 AS |
813 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
814 | { | |
815 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
816 | MLX5E_MAX_NUM_CHANNELS); | |
817 | } | |
818 | ||
f62b8bb8 | 819 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
820 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
821 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
822 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
823 | #endif | |
824 | ||
1cabe6b0 MG |
825 | #ifndef CONFIG_RFS_ACCEL |
826 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
827 | { | |
828 | return 0; | |
829 | } | |
830 | ||
831 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
832 | |
833 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
834 | { | |
835 | return -ENOTSUPP; | |
836 | } | |
837 | ||
838 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
839 | { | |
840 | return -ENOTSUPP; | |
841 | } | |
1cabe6b0 MG |
842 | #else |
843 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
844 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
845 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
846 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
847 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
848 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
849 | #endif |
850 | ||
58d52291 | 851 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
852 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
853 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
854 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
855 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
856 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
857 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
724b2aa1 | 858 | int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev); |
1afff42c | 859 | |
cb67b832 HHZ |
860 | struct mlx5_eswitch_rep; |
861 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
862 | struct mlx5_eswitch_rep *rep); | |
863 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
864 | struct mlx5_eswitch_rep *rep); | |
865 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
866 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
867 | struct mlx5_eswitch_rep *rep); | |
868 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
869 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
870 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
871 | ||
872 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
873 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
874 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
875 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
876 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
877 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
878 | int mlx5e_close(struct net_device *netdev); | |
879 | int mlx5e_open(struct net_device *netdev); | |
880 | void mlx5e_update_stats_work(struct work_struct *work); | |
881 | void *mlx5e_create_netdev(struct mlx5_core_dev *mdev, | |
882 | const struct mlx5e_profile *profile, void *ppriv); | |
883 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); | |
884 | struct rtnl_link_stats64 * | |
885 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); | |
886 | ||
1afff42c | 887 | #endif /* __MLX5_EN_H__ */ |