Commit | Line | Data |
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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
f62b8bb8 | 47 | #include "wq.h" |
f62b8bb8 AV |
48 | #include "mlx5_core.h" |
49 | ||
50 | #define MLX5E_MAX_NUM_TC 8 | |
51 | ||
e842b100 | 52 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
53 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
54 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
55 | ||
e842b100 | 56 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
57 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
58 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
59 | ||
d9a40271 | 60 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 AV |
61 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
62 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
63 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
64 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
65 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
f62b8bb8 | 66 | |
936896e9 AS |
67 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
68 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
69 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
70 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
71 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 72 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 73 | |
86d722ad MG |
74 | #define MLX5E_NUM_MAIN_GROUPS 9 |
75 | ||
08fb1dac SM |
76 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
77 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
78 | #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */ | |
79 | #endif | |
80 | ||
f62b8bb8 AV |
81 | static const char vport_strings[][ETH_GSTRING_LEN] = { |
82 | /* vport statistics */ | |
83 | "rx_packets", | |
84 | "rx_bytes", | |
85 | "tx_packets", | |
86 | "tx_bytes", | |
87 | "rx_error_packets", | |
88 | "rx_error_bytes", | |
89 | "tx_error_packets", | |
90 | "tx_error_bytes", | |
91 | "rx_unicast_packets", | |
92 | "rx_unicast_bytes", | |
93 | "tx_unicast_packets", | |
94 | "tx_unicast_bytes", | |
95 | "rx_multicast_packets", | |
96 | "rx_multicast_bytes", | |
97 | "tx_multicast_packets", | |
98 | "tx_multicast_bytes", | |
99 | "rx_broadcast_packets", | |
100 | "rx_broadcast_bytes", | |
101 | "tx_broadcast_packets", | |
102 | "tx_broadcast_bytes", | |
103 | ||
104 | /* SW counters */ | |
105 | "tso_packets", | |
106 | "tso_bytes", | |
89db09eb MF |
107 | "tso_inner_packets", |
108 | "tso_inner_bytes", | |
f62b8bb8 AV |
109 | "lro_packets", |
110 | "lro_bytes", | |
111 | "rx_csum_good", | |
112 | "rx_csum_none", | |
bbceefce | 113 | "rx_csum_sw", |
f62b8bb8 | 114 | "tx_csum_offload", |
89db09eb | 115 | "tx_csum_inner", |
f62b8bb8 AV |
116 | "tx_queue_stopped", |
117 | "tx_queue_wake", | |
118 | "tx_queue_dropped", | |
119 | "rx_wqe_err", | |
120 | }; | |
121 | ||
122 | struct mlx5e_vport_stats { | |
123 | /* HW counters */ | |
124 | u64 rx_packets; | |
125 | u64 rx_bytes; | |
126 | u64 tx_packets; | |
127 | u64 tx_bytes; | |
128 | u64 rx_error_packets; | |
129 | u64 rx_error_bytes; | |
130 | u64 tx_error_packets; | |
131 | u64 tx_error_bytes; | |
132 | u64 rx_unicast_packets; | |
133 | u64 rx_unicast_bytes; | |
134 | u64 tx_unicast_packets; | |
135 | u64 tx_unicast_bytes; | |
136 | u64 rx_multicast_packets; | |
137 | u64 rx_multicast_bytes; | |
138 | u64 tx_multicast_packets; | |
139 | u64 tx_multicast_bytes; | |
140 | u64 rx_broadcast_packets; | |
141 | u64 rx_broadcast_bytes; | |
142 | u64 tx_broadcast_packets; | |
143 | u64 tx_broadcast_bytes; | |
144 | ||
145 | /* SW counters */ | |
146 | u64 tso_packets; | |
147 | u64 tso_bytes; | |
89db09eb MF |
148 | u64 tso_inner_packets; |
149 | u64 tso_inner_bytes; | |
f62b8bb8 AV |
150 | u64 lro_packets; |
151 | u64 lro_bytes; | |
152 | u64 rx_csum_good; | |
153 | u64 rx_csum_none; | |
bbceefce | 154 | u64 rx_csum_sw; |
f62b8bb8 | 155 | u64 tx_csum_offload; |
89db09eb | 156 | u64 tx_csum_inner; |
f62b8bb8 AV |
157 | u64 tx_queue_stopped; |
158 | u64 tx_queue_wake; | |
159 | u64 tx_queue_dropped; | |
160 | u64 rx_wqe_err; | |
161 | ||
89db09eb | 162 | #define NUM_VPORT_COUNTERS 35 |
f62b8bb8 AV |
163 | }; |
164 | ||
efea389d GP |
165 | static const char pport_strings[][ETH_GSTRING_LEN] = { |
166 | /* IEEE802.3 counters */ | |
167 | "frames_tx", | |
168 | "frames_rx", | |
169 | "check_seq_err", | |
170 | "alignment_err", | |
171 | "octets_tx", | |
172 | "octets_received", | |
173 | "multicast_xmitted", | |
174 | "broadcast_xmitted", | |
175 | "multicast_rx", | |
176 | "broadcast_rx", | |
177 | "in_range_len_errors", | |
178 | "out_of_range_len", | |
179 | "too_long_errors", | |
180 | "symbol_err", | |
181 | "mac_control_tx", | |
182 | "mac_control_rx", | |
183 | "unsupported_op_rx", | |
184 | "pause_ctrl_rx", | |
185 | "pause_ctrl_tx", | |
186 | ||
187 | /* RFC2863 counters */ | |
188 | "in_octets", | |
189 | "in_ucast_pkts", | |
190 | "in_discards", | |
191 | "in_errors", | |
192 | "in_unknown_protos", | |
193 | "out_octets", | |
194 | "out_ucast_pkts", | |
195 | "out_discards", | |
196 | "out_errors", | |
197 | "in_multicast_pkts", | |
198 | "in_broadcast_pkts", | |
199 | "out_multicast_pkts", | |
200 | "out_broadcast_pkts", | |
201 | ||
202 | /* RFC2819 counters */ | |
203 | "drop_events", | |
204 | "octets", | |
205 | "pkts", | |
206 | "broadcast_pkts", | |
207 | "multicast_pkts", | |
208 | "crc_align_errors", | |
209 | "undersize_pkts", | |
210 | "oversize_pkts", | |
211 | "fragments", | |
212 | "jabbers", | |
213 | "collisions", | |
214 | "p64octets", | |
215 | "p65to127octets", | |
216 | "p128to255octets", | |
217 | "p256to511octets", | |
218 | "p512to1023octets", | |
219 | "p1024to1518octets", | |
220 | "p1519to2047octets", | |
221 | "p2048to4095octets", | |
222 | "p4096to8191octets", | |
223 | "p8192to10239octets", | |
224 | }; | |
225 | ||
226 | #define NUM_IEEE_802_3_COUNTERS 19 | |
227 | #define NUM_RFC_2863_COUNTERS 13 | |
228 | #define NUM_RFC_2819_COUNTERS 21 | |
229 | #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \ | |
230 | NUM_RFC_2863_COUNTERS + \ | |
231 | NUM_RFC_2819_COUNTERS) | |
232 | ||
233 | struct mlx5e_pport_stats { | |
234 | __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS]; | |
235 | __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS]; | |
236 | __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS]; | |
237 | }; | |
238 | ||
f62b8bb8 AV |
239 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { |
240 | "packets", | |
b081da5e | 241 | "bytes", |
f62b8bb8 | 242 | "csum_none", |
bbceefce | 243 | "csum_sw", |
f62b8bb8 AV |
244 | "lro_packets", |
245 | "lro_bytes", | |
246 | "wqe_err" | |
247 | }; | |
248 | ||
249 | struct mlx5e_rq_stats { | |
250 | u64 packets; | |
b081da5e | 251 | u64 bytes; |
f62b8bb8 | 252 | u64 csum_none; |
bbceefce | 253 | u64 csum_sw; |
f62b8bb8 AV |
254 | u64 lro_packets; |
255 | u64 lro_bytes; | |
256 | u64 wqe_err; | |
b081da5e | 257 | #define NUM_RQ_STATS 7 |
f62b8bb8 AV |
258 | }; |
259 | ||
260 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { | |
261 | "packets", | |
b081da5e | 262 | "bytes", |
f62b8bb8 AV |
263 | "tso_packets", |
264 | "tso_bytes", | |
89db09eb MF |
265 | "tso_inner_packets", |
266 | "tso_inner_bytes", | |
89db09eb | 267 | "csum_offload_inner", |
c89fb18b TT |
268 | "nop", |
269 | "csum_offload_none", | |
f62b8bb8 AV |
270 | "stopped", |
271 | "wake", | |
272 | "dropped", | |
f62b8bb8 AV |
273 | }; |
274 | ||
275 | struct mlx5e_sq_stats { | |
c89fb18b | 276 | /* commonly accessed in data path */ |
f62b8bb8 | 277 | u64 packets; |
b081da5e | 278 | u64 bytes; |
f62b8bb8 AV |
279 | u64 tso_packets; |
280 | u64 tso_bytes; | |
89db09eb MF |
281 | u64 tso_inner_packets; |
282 | u64 tso_inner_bytes; | |
89db09eb | 283 | u64 csum_offload_inner; |
c89fb18b TT |
284 | u64 nop; |
285 | /* less likely accessed in data path */ | |
286 | u64 csum_offload_none; | |
f62b8bb8 AV |
287 | u64 stopped; |
288 | u64 wake; | |
289 | u64 dropped; | |
810813c4 | 290 | #define NUM_SQ_STATS 12 |
f62b8bb8 AV |
291 | }; |
292 | ||
293 | struct mlx5e_stats { | |
294 | struct mlx5e_vport_stats vport; | |
efea389d | 295 | struct mlx5e_pport_stats pport; |
f62b8bb8 AV |
296 | }; |
297 | ||
298 | struct mlx5e_params { | |
299 | u8 log_sq_size; | |
300 | u8 log_rq_size; | |
301 | u16 num_channels; | |
f62b8bb8 AV |
302 | u8 num_tc; |
303 | u16 rx_cq_moderation_usec; | |
304 | u16 rx_cq_moderation_pkts; | |
305 | u16 tx_cq_moderation_usec; | |
306 | u16 tx_cq_moderation_pkts; | |
307 | u16 min_rx_wqes; | |
f62b8bb8 AV |
308 | bool lro_en; |
309 | u32 lro_wqe_sz; | |
58d52291 | 310 | u16 tx_max_inline; |
2d75b2bc AS |
311 | u8 rss_hfunc; |
312 | u8 toeplitz_hash_key[40]; | |
313 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
08fb1dac SM |
314 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
315 | struct ieee_ets ets; | |
316 | #endif | |
f62b8bb8 AV |
317 | }; |
318 | ||
ef9814de EBE |
319 | struct mlx5e_tstamp { |
320 | rwlock_t lock; | |
321 | struct cyclecounter cycles; | |
322 | struct timecounter clock; | |
323 | struct hwtstamp_config hwtstamp_config; | |
324 | u32 nominal_c_mult; | |
325 | unsigned long overflow_period; | |
326 | struct delayed_work overflow_work; | |
327 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
328 | struct ptp_clock *ptp; |
329 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
330 | }; |
331 | ||
f62b8bb8 AV |
332 | enum { |
333 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
334 | }; | |
335 | ||
f62b8bb8 AV |
336 | struct mlx5e_cq { |
337 | /* data path - accessed per cqe */ | |
338 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
339 | |
340 | /* data path - accessed per napi poll */ | |
341 | struct napi_struct *napi; | |
342 | struct mlx5_core_cq mcq; | |
343 | struct mlx5e_channel *channel; | |
50cfa25a | 344 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
345 | |
346 | /* control */ | |
347 | struct mlx5_wq_ctrl wq_ctrl; | |
348 | } ____cacheline_aligned_in_smp; | |
349 | ||
350 | struct mlx5e_rq { | |
351 | /* data path */ | |
352 | struct mlx5_wq_ll wq; | |
353 | u32 wqe_sz; | |
354 | struct sk_buff **skb; | |
355 | ||
356 | struct device *pdev; | |
357 | struct net_device *netdev; | |
ef9814de | 358 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
359 | struct mlx5e_rq_stats stats; |
360 | struct mlx5e_cq cq; | |
361 | ||
362 | unsigned long state; | |
363 | int ix; | |
364 | ||
365 | /* control */ | |
366 | struct mlx5_wq_ctrl wq_ctrl; | |
367 | u32 rqn; | |
368 | struct mlx5e_channel *channel; | |
50cfa25a | 369 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
370 | } ____cacheline_aligned_in_smp; |
371 | ||
34802a42 | 372 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
373 | u32 num_bytes; |
374 | u8 num_wqebbs; | |
375 | u8 num_dma; | |
376 | }; | |
377 | ||
d4e28cbd AS |
378 | enum mlx5e_dma_map_type { |
379 | MLX5E_DMA_MAP_SINGLE, | |
380 | MLX5E_DMA_MAP_PAGE | |
381 | }; | |
382 | ||
f62b8bb8 | 383 | struct mlx5e_sq_dma { |
d4e28cbd AS |
384 | dma_addr_t addr; |
385 | u32 size; | |
386 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
387 | }; |
388 | ||
389 | enum { | |
390 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
0ba42241 | 391 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
392 | }; |
393 | ||
394 | struct mlx5e_sq { | |
395 | /* data path */ | |
396 | ||
397 | /* dirtied @completion */ | |
398 | u16 cc; | |
399 | u32 dma_fifo_cc; | |
400 | ||
401 | /* dirtied @xmit */ | |
402 | u16 pc ____cacheline_aligned_in_smp; | |
403 | u32 dma_fifo_pc; | |
88a85f99 AS |
404 | u16 bf_offset; |
405 | u16 prev_cc; | |
406 | u8 bf_budget; | |
f62b8bb8 AV |
407 | struct mlx5e_sq_stats stats; |
408 | ||
409 | struct mlx5e_cq cq; | |
410 | ||
411 | /* pointers to per packet info: write@xmit, read@completion */ | |
412 | struct sk_buff **skb; | |
413 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 414 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
415 | |
416 | /* read only */ | |
417 | struct mlx5_wq_cyc wq; | |
418 | u32 dma_fifo_mask; | |
419 | void __iomem *uar_map; | |
420 | struct netdev_queue *txq; | |
421 | u32 sqn; | |
88a85f99 | 422 | u16 bf_buf_size; |
12be4b21 SM |
423 | u16 max_inline; |
424 | u16 edge; | |
f62b8bb8 | 425 | struct device *pdev; |
ef9814de | 426 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
427 | __be32 mkey_be; |
428 | unsigned long state; | |
429 | ||
430 | /* control path */ | |
431 | struct mlx5_wq_ctrl wq_ctrl; | |
432 | struct mlx5_uar uar; | |
433 | struct mlx5e_channel *channel; | |
434 | int tc; | |
435 | } ____cacheline_aligned_in_smp; | |
436 | ||
437 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
438 | { | |
439 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
440 | (sq->cc == sq->pc)); | |
441 | } | |
442 | ||
443 | enum channel_flags { | |
444 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
445 | }; | |
446 | ||
447 | struct mlx5e_channel { | |
448 | /* data path */ | |
449 | struct mlx5e_rq rq; | |
450 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
451 | struct napi_struct napi; | |
452 | struct device *pdev; | |
453 | struct net_device *netdev; | |
454 | __be32 mkey_be; | |
455 | u8 num_tc; | |
456 | unsigned long flags; | |
457 | ||
458 | /* control */ | |
459 | struct mlx5e_priv *priv; | |
460 | int ix; | |
461 | int cpu; | |
462 | }; | |
463 | ||
464 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
465 | MLX5E_TT_IPV4_TCP, |
466 | MLX5E_TT_IPV6_TCP, | |
467 | MLX5E_TT_IPV4_UDP, | |
468 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
469 | MLX5E_TT_IPV4_IPSEC_AH, |
470 | MLX5E_TT_IPV6_IPSEC_AH, | |
471 | MLX5E_TT_IPV4_IPSEC_ESP, | |
472 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
473 | MLX5E_TT_IPV4, |
474 | MLX5E_TT_IPV6, | |
475 | MLX5E_TT_ANY, | |
476 | MLX5E_NUM_TT, | |
f62b8bb8 AV |
477 | }; |
478 | ||
bdfc028d TT |
479 | #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY) |
480 | ||
4cbeaff5 AS |
481 | enum mlx5e_rqt_ix { |
482 | MLX5E_INDIRECTION_RQT, | |
483 | MLX5E_SINGLE_RQ_RQT, | |
484 | MLX5E_NUM_RQT, | |
f62b8bb8 AV |
485 | }; |
486 | ||
487 | struct mlx5e_eth_addr_info { | |
488 | u8 addr[ETH_ALEN + 2]; | |
489 | u32 tt_vec; | |
86d722ad | 490 | struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; |
f62b8bb8 AV |
491 | }; |
492 | ||
493 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
494 | ||
495 | struct mlx5e_eth_addr_db { | |
496 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
497 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
498 | struct mlx5e_eth_addr_info broadcast; | |
499 | struct mlx5e_eth_addr_info allmulti; | |
500 | struct mlx5e_eth_addr_info promisc; | |
501 | bool broadcast_enabled; | |
502 | bool allmulti_enabled; | |
503 | bool promisc_enabled; | |
504 | }; | |
505 | ||
506 | enum { | |
507 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
508 | MLX5E_STATE_OPENED, | |
9b37b07f | 509 | MLX5E_STATE_DESTROYING, |
f62b8bb8 AV |
510 | }; |
511 | ||
512 | struct mlx5e_vlan_db { | |
aad9e6e4 | 513 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
514 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
515 | struct mlx5_flow_rule *untagged_rule; | |
516 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
517 | bool filter_disabled; |
518 | }; | |
519 | ||
b3f63c3d MF |
520 | struct mlx5e_vxlan_db { |
521 | spinlock_t lock; /* protect vxlan table */ | |
522 | struct radix_tree_root tree; | |
523 | }; | |
524 | ||
f62b8bb8 | 525 | struct mlx5e_flow_table { |
86d722ad MG |
526 | int num_groups; |
527 | struct mlx5_flow_table *t; | |
528 | struct mlx5_flow_group **g; | |
529 | }; | |
530 | ||
e8f887ac AV |
531 | struct mlx5e_tc_flow_table { |
532 | struct mlx5_flow_table *t; | |
533 | ||
534 | struct rhashtable_params ht_params; | |
535 | struct rhashtable ht; | |
536 | }; | |
537 | ||
86d722ad MG |
538 | struct mlx5e_flow_tables { |
539 | struct mlx5_flow_namespace *ns; | |
e8f887ac | 540 | struct mlx5e_tc_flow_table tc; |
86d722ad MG |
541 | struct mlx5e_flow_table vlan; |
542 | struct mlx5e_flow_table main; | |
f62b8bb8 AV |
543 | }; |
544 | ||
545 | struct mlx5e_priv { | |
546 | /* priv data path fields - start */ | |
03289b88 | 547 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 548 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
549 | /* priv data path fields - end */ |
550 | ||
551 | unsigned long state; | |
552 | struct mutex state_lock; /* Protects Interface state */ | |
553 | struct mlx5_uar cq_uar; | |
554 | u32 pdn; | |
3191e05f | 555 | u32 tdn; |
f62b8bb8 | 556 | struct mlx5_core_mr mr; |
50cfa25a | 557 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
558 | |
559 | struct mlx5e_channel **channel; | |
560 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
4cbeaff5 | 561 | u32 rqtn[MLX5E_NUM_RQT]; |
f62b8bb8 AV |
562 | u32 tirn[MLX5E_NUM_TT]; |
563 | ||
86d722ad | 564 | struct mlx5e_flow_tables fts; |
f62b8bb8 AV |
565 | struct mlx5e_eth_addr_db eth_addr; |
566 | struct mlx5e_vlan_db vlan; | |
b3f63c3d | 567 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
568 | |
569 | struct mlx5e_params params; | |
f62b8bb8 AV |
570 | struct work_struct update_carrier_work; |
571 | struct work_struct set_rx_mode_work; | |
572 | struct delayed_work update_stats_work; | |
573 | ||
574 | struct mlx5_core_dev *mdev; | |
575 | struct net_device *netdev; | |
576 | struct mlx5e_stats stats; | |
ef9814de | 577 | struct mlx5e_tstamp tstamp; |
f62b8bb8 AV |
578 | }; |
579 | ||
580 | #define MLX5E_NET_IP_ALIGN 2 | |
581 | ||
582 | struct mlx5e_tx_wqe { | |
583 | struct mlx5_wqe_ctrl_seg ctrl; | |
584 | struct mlx5_wqe_eth_seg eth; | |
585 | }; | |
586 | ||
587 | struct mlx5e_rx_wqe { | |
588 | struct mlx5_wqe_srq_next_seg next; | |
589 | struct mlx5_wqe_data_seg data; | |
590 | }; | |
591 | ||
592 | enum mlx5e_link_mode { | |
593 | MLX5E_1000BASE_CX_SGMII = 0, | |
594 | MLX5E_1000BASE_KX = 1, | |
595 | MLX5E_10GBASE_CX4 = 2, | |
596 | MLX5E_10GBASE_KX4 = 3, | |
597 | MLX5E_10GBASE_KR = 4, | |
598 | MLX5E_20GBASE_KR2 = 5, | |
599 | MLX5E_40GBASE_CR4 = 6, | |
600 | MLX5E_40GBASE_KR4 = 7, | |
601 | MLX5E_56GBASE_R4 = 8, | |
602 | MLX5E_10GBASE_CR = 12, | |
603 | MLX5E_10GBASE_SR = 13, | |
604 | MLX5E_10GBASE_ER = 14, | |
605 | MLX5E_40GBASE_SR4 = 15, | |
606 | MLX5E_40GBASE_LR4 = 16, | |
607 | MLX5E_100GBASE_CR4 = 20, | |
608 | MLX5E_100GBASE_SR4 = 21, | |
609 | MLX5E_100GBASE_KR4 = 22, | |
610 | MLX5E_100GBASE_LR4 = 23, | |
611 | MLX5E_100BASE_TX = 24, | |
612 | MLX5E_100BASE_T = 25, | |
613 | MLX5E_10GBASE_T = 26, | |
614 | MLX5E_25GBASE_CR = 27, | |
615 | MLX5E_25GBASE_KR = 28, | |
616 | MLX5E_25GBASE_SR = 29, | |
617 | MLX5E_50GBASE_CR2 = 30, | |
618 | MLX5E_50GBASE_KR2 = 31, | |
619 | MLX5E_LINK_MODES_NUMBER, | |
620 | }; | |
621 | ||
622 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
623 | ||
12be4b21 | 624 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
625 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
626 | void *accel_priv, select_queue_fallback_t fallback); | |
627 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
628 | |
629 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
630 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
631 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
632 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); | |
44fb6fbb | 633 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
f62b8bb8 AV |
634 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
635 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); | |
636 | ||
637 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
638 | ||
40ab6a6e AS |
639 | int mlx5e_create_flow_tables(struct mlx5e_priv *priv); |
640 | void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv); | |
f62b8bb8 | 641 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); |
f62b8bb8 AV |
642 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
643 | ||
ef9814de EBE |
644 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
645 | struct skb_shared_hwtstamps *hwts); | |
646 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
647 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
648 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
649 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
650 | ||
f62b8bb8 AV |
651 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
652 | u16 vid); | |
653 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
654 | u16 vid); | |
655 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
656 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 657 | |
2d75b2bc | 658 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix); |
bdfc028d | 659 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 660 | |
f62b8bb8 AV |
661 | int mlx5e_open_locked(struct net_device *netdev); |
662 | int mlx5e_close_locked(struct net_device *netdev); | |
85082dba TT |
663 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
664 | int num_channels); | |
f62b8bb8 AV |
665 | |
666 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
88a85f99 | 667 | struct mlx5e_tx_wqe *wqe, int bf_sz) |
f62b8bb8 | 668 | { |
88a85f99 AS |
669 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
670 | ||
f62b8bb8 AV |
671 | /* ensure wqe is visible to device before updating doorbell record */ |
672 | dma_wmb(); | |
673 | ||
674 | *sq->wq.db = cpu_to_be32(sq->pc); | |
675 | ||
676 | /* ensure doorbell record is visible to device before ringing the | |
677 | * doorbell | |
678 | */ | |
679 | wmb(); | |
0ba42241 ML |
680 | if (bf_sz) |
681 | __iowrite64_copy(sq->uar_map + ofst, &wqe->ctrl, bf_sz); | |
682 | else | |
88a85f99 | 683 | mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
684 | /* flush the write-combining mapped buffer */ |
685 | wmb(); | |
f62b8bb8 AV |
686 | |
687 | sq->bf_offset ^= sq->bf_buf_size; | |
688 | } | |
689 | ||
690 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
691 | { | |
692 | struct mlx5_core_cq *mcq; | |
693 | ||
694 | mcq = &cq->mcq; | |
695 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
696 | } | |
697 | ||
3435ab59 AS |
698 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
699 | { | |
700 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
701 | MLX5E_MAX_NUM_CHANNELS); | |
702 | } | |
703 | ||
f62b8bb8 | 704 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
705 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
706 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
707 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
708 | #endif | |
709 | ||
58d52291 | 710 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
1afff42c MF |
711 | |
712 | #endif /* __MLX5_EN_H__ */ |