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net/mlx5e: Support DCBNL IEEE ETS
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
86d722ad 33#include <linux/mlx5/fs.h>
f62b8bb8 34#include "en.h"
66e49ded 35#include "eswitch.h"
f62b8bb8
AV		 36
37struct mlx5e_rq_param {
38 u32 rqc[MLX5_ST_SZ_DW(rqc)];
39 struct mlx5_wq_param wq;
40};
41
42struct mlx5e_sq_param {
43 u32 sqc[MLX5_ST_SZ_DW(sqc)];
44 struct mlx5_wq_param wq;
58d52291 45 u16 max_inline;
f62b8bb8
AV		 46};
47
48struct mlx5e_cq_param {
49 u32 cqc[MLX5_ST_SZ_DW(cqc)];
50 struct mlx5_wq_param wq;
51 u16 eq_ix;
52};
53
54struct mlx5e_channel_param {
55 struct mlx5e_rq_param rq;
56 struct mlx5e_sq_param sq;
57 struct mlx5e_cq_param rx_cq;
58 struct mlx5e_cq_param tx_cq;
59};
60
61static void mlx5e_update_carrier(struct mlx5e_priv *priv)
62{
63 struct mlx5_core_dev *mdev = priv->mdev;
64 u8 port_state;
65
66 port_state = mlx5_query_vport_state(mdev,
e7546514 67 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 68
69 if (port_state == VPORT_STATE_UP)
70 netif_carrier_on(priv->netdev);
71 else
72 netif_carrier_off(priv->netdev);
73}
74
75static void mlx5e_update_carrier_work(struct work_struct *work)
76{
77 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
78 update_carrier_work);
79
80 mutex_lock(&priv->state_lock);
81 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
82 mlx5e_update_carrier(priv);
83 mutex_unlock(&priv->state_lock);
84}
85
efea389d
GP		 86static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
87{
88 struct mlx5_core_dev *mdev = priv->mdev;
89 struct mlx5e_pport_stats *s = &priv->stats.pport;
90 u32 *in;
91 u32 *out;
92 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
93
94 in = mlx5_vzalloc(sz);
95 out = mlx5_vzalloc(sz);
96 if (!in || !out)
97 goto free_out;
98
99 MLX5_SET(ppcnt_reg, in, local_port, 1);
100
101 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
102 mlx5_core_access_reg(mdev, in, sz, out,
103 sz, MLX5_REG_PPCNT, 0, 0);
104 memcpy(s->IEEE_802_3_counters,
105 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
106 sizeof(s->IEEE_802_3_counters));
107
108 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
109 mlx5_core_access_reg(mdev, in, sz, out,
110 sz, MLX5_REG_PPCNT, 0, 0);
111 memcpy(s->RFC_2863_counters,
112 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
113 sizeof(s->RFC_2863_counters));
114
115 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
116 mlx5_core_access_reg(mdev, in, sz, out,
117 sz, MLX5_REG_PPCNT, 0, 0);
118 memcpy(s->RFC_2819_counters,
119 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
120 sizeof(s->RFC_2819_counters));
121
122free_out:
123 kvfree(in);
124 kvfree(out);
125}
126
f62b8bb8
AV		 127void mlx5e_update_stats(struct mlx5e_priv *priv)
128{
129 struct mlx5_core_dev *mdev = priv->mdev;
130 struct mlx5e_vport_stats *s = &priv->stats.vport;
131 struct mlx5e_rq_stats *rq_stats;
132 struct mlx5e_sq_stats *sq_stats;
133 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
134 u32 *out;
135 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
136 u64 tx_offload_none;
137 int i, j;
138
139 out = mlx5_vzalloc(outlen);
140 if (!out)
141 return;
142
143 /* Collect firts the SW counters and then HW for consistency */
144 s->tso_packets = 0;
145 s->tso_bytes = 0;
146 s->tx_queue_stopped = 0;
147 s->tx_queue_wake = 0;
148 s->tx_queue_dropped = 0;
149 tx_offload_none = 0;
150 s->lro_packets = 0;
151 s->lro_bytes = 0;
152 s->rx_csum_none = 0;
bbceefce 153 s->rx_csum_sw = 0;
f62b8bb8
AV		 154 s->rx_wqe_err = 0;
155 for (i = 0; i < priv->params.num_channels; i++) {
156 rq_stats = &priv->channel[i]->rq.stats;
157
158 s->lro_packets += rq_stats->lro_packets;
159 s->lro_bytes += rq_stats->lro_bytes;
160 s->rx_csum_none += rq_stats->csum_none;
bbceefce 161 s->rx_csum_sw += rq_stats->csum_sw;
f62b8bb8
AV		 162 s->rx_wqe_err += rq_stats->wqe_err;
163
a4418a6c 164 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 165 sq_stats = &priv->channel[i]->sq[j].stats;
166
167 s->tso_packets += sq_stats->tso_packets;
168 s->tso_bytes += sq_stats->tso_bytes;
169 s->tx_queue_stopped += sq_stats->stopped;
170 s->tx_queue_wake += sq_stats->wake;
171 s->tx_queue_dropped += sq_stats->dropped;
172 tx_offload_none += sq_stats->csum_offload_none;
173 }
174 }
175
176 /* HW counters */
177 memset(in, 0, sizeof(in));
178
179 MLX5_SET(query_vport_counter_in, in, opcode,
180 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
181 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
182 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
183
184 memset(out, 0, outlen);
185
186 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
187 goto free_out;
188
189#define MLX5_GET_CTR(p, x) \
190 MLX5_GET64(query_vport_counter_out, p, x)
191
192 s->rx_error_packets =
193 MLX5_GET_CTR(out, received_errors.packets);
194 s->rx_error_bytes =
195 MLX5_GET_CTR(out, received_errors.octets);
196 s->tx_error_packets =
197 MLX5_GET_CTR(out, transmit_errors.packets);
198 s->tx_error_bytes =
199 MLX5_GET_CTR(out, transmit_errors.octets);
200
201 s->rx_unicast_packets =
202 MLX5_GET_CTR(out, received_eth_unicast.packets);
203 s->rx_unicast_bytes =
204 MLX5_GET_CTR(out, received_eth_unicast.octets);
205 s->tx_unicast_packets =
206 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
207 s->tx_unicast_bytes =
208 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
209
210 s->rx_multicast_packets =
211 MLX5_GET_CTR(out, received_eth_multicast.packets);
212 s->rx_multicast_bytes =
213 MLX5_GET_CTR(out, received_eth_multicast.octets);
214 s->tx_multicast_packets =
215 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
216 s->tx_multicast_bytes =
217 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
218
219 s->rx_broadcast_packets =
220 MLX5_GET_CTR(out, received_eth_broadcast.packets);
221 s->rx_broadcast_bytes =
222 MLX5_GET_CTR(out, received_eth_broadcast.octets);
223 s->tx_broadcast_packets =
224 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
225 s->tx_broadcast_bytes =
226 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
227
228 s->rx_packets =
229 s->rx_unicast_packets +
230 s->rx_multicast_packets +
231 s->rx_broadcast_packets;
232 s->rx_bytes =
233 s->rx_unicast_bytes +
234 s->rx_multicast_bytes +
235 s->rx_broadcast_bytes;
236 s->tx_packets =
237 s->tx_unicast_packets +
238 s->tx_multicast_packets +
239 s->tx_broadcast_packets;
240 s->tx_bytes =
241 s->tx_unicast_bytes +
242 s->tx_multicast_bytes +
243 s->tx_broadcast_bytes;
244
245 /* Update calculated offload counters */
246 s->tx_csum_offload = s->tx_packets - tx_offload_none;
bbceefce
AS		 247 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
248 s->rx_csum_sw;
f62b8bb8 249
efea389d 250 mlx5e_update_pport_counters(priv);
f62b8bb8
AV		 251free_out:
252 kvfree(out);
253}
254
255static void mlx5e_update_stats_work(struct work_struct *work)
256{
257 struct delayed_work *dwork = to_delayed_work(work);
258 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
259 update_stats_work);
260 mutex_lock(&priv->state_lock);
261 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
262 mlx5e_update_stats(priv);
263 schedule_delayed_work(dwork,
264 msecs_to_jiffies(
265 MLX5E_UPDATE_STATS_INTERVAL));
266 }
267 mutex_unlock(&priv->state_lock);
268}
269
270static void __mlx5e_async_event(struct mlx5e_priv *priv,
271 enum mlx5_dev_event event)
272{
273 switch (event) {
274 case MLX5_DEV_EVENT_PORT_UP:
275 case MLX5_DEV_EVENT_PORT_DOWN:
276 schedule_work(&priv->update_carrier_work);
277 break;
278
279 default:
280 break;
281 }
282}
283
284static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
285 enum mlx5_dev_event event, unsigned long param)
286{
287 struct mlx5e_priv *priv = vpriv;
288
289 spin_lock(&priv->async_events_spinlock);
290 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
291 __mlx5e_async_event(priv, event);
292 spin_unlock(&priv->async_events_spinlock);
293}
294
295static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
296{
297 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
298}
299
300static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
301{
302 spin_lock_irq(&priv->async_events_spinlock);
303 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
304 spin_unlock_irq(&priv->async_events_spinlock);
305}
306
facc9699
SM		 307#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
308#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
309
f62b8bb8
AV		 310static int mlx5e_create_rq(struct mlx5e_channel *c,
311 struct mlx5e_rq_param *param,
312 struct mlx5e_rq *rq)
313{
314 struct mlx5e_priv *priv = c->priv;
315 struct mlx5_core_dev *mdev = priv->mdev;
316 void *rqc = param->rqc;
317 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
318 int wq_sz;
319 int err;
320 int i;
321
311c7c71
SM		 322 param->wq.db_numa_node = cpu_to_node(c->cpu);
323
f62b8bb8
AV		 324 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
325 &rq->wq_ctrl);
326 if (err)
327 return err;
328
329 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
330
331 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
332 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
333 cpu_to_node(c->cpu));
334 if (!rq->skb) {
335 err = -ENOMEM;
336 goto err_rq_wq_destroy;
337 }
338
339 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 340 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 341 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 342
343 for (i = 0; i < wq_sz; i++) {
344 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 345 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 346
347 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 348 wqe->data.byte_count =
349 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 350 }
351
352 rq->pdev = c->pdev;
353 rq->netdev = c->netdev;
ef9814de 354 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 355 rq->channel = c;
356 rq->ix = c->ix;
50cfa25a 357 rq->priv = c->priv;
f62b8bb8
AV		 358
359 return 0;
360
361err_rq_wq_destroy:
362 mlx5_wq_destroy(&rq->wq_ctrl);
363
364 return err;
365}
366
367static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
368{
369 kfree(rq->skb);
370 mlx5_wq_destroy(&rq->wq_ctrl);
371}
372
373static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
374{
50cfa25a 375 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 376 struct mlx5_core_dev *mdev = priv->mdev;
377
378 void *in;
379 void *rqc;
380 void *wq;
381 int inlen;
382 int err;
383
384 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
385 sizeof(u64) * rq->wq_ctrl.buf.npages;
386 in = mlx5_vzalloc(inlen);
387 if (!in)
388 return -ENOMEM;
389
390 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
391 wq = MLX5_ADDR_OF(rqc, rqc, wq);
392
393 memcpy(rqc, param->rqc, sizeof(param->rqc));
394
97de9f31 395 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 396 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
397 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8 398 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 399 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 400 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
401
402 mlx5_fill_page_array(&rq->wq_ctrl.buf,
403 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
404
7db22ffb 405 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 406
407 kvfree(in);
408
409 return err;
410}
411
412static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
413{
414 struct mlx5e_channel *c = rq->channel;
415 struct mlx5e_priv *priv = c->priv;
416 struct mlx5_core_dev *mdev = priv->mdev;
417
418 void *in;
419 void *rqc;
420 int inlen;
421 int err;
422
423 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
424 in = mlx5_vzalloc(inlen);
425 if (!in)
426 return -ENOMEM;
427
428 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
429
430 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
431 MLX5_SET(rqc, rqc, state, next_state);
432
7db22ffb 433 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 434
435 kvfree(in);
436
437 return err;
438}
439
440static void mlx5e_disable_rq(struct mlx5e_rq *rq)
441{
50cfa25a 442 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 443}
444
445static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
446{
01c196a2 447 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 448 struct mlx5e_channel *c = rq->channel;
449 struct mlx5e_priv *priv = c->priv;
450 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 451
01c196a2 452 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 453 if (wq->cur_sz >= priv->params.min_rx_wqes)
454 return 0;
455
456 msleep(20);
457 }
458
459 return -ETIMEDOUT;
460}
461
462static int mlx5e_open_rq(struct mlx5e_channel *c,
463 struct mlx5e_rq_param *param,
464 struct mlx5e_rq *rq)
465{
466 int err;
467
468 err = mlx5e_create_rq(c, param, rq);
469 if (err)
470 return err;
471
472 err = mlx5e_enable_rq(rq, param);
473 if (err)
474 goto err_destroy_rq;
475
476 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
477 if (err)
478 goto err_disable_rq;
479
480 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 481 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 482
483 return 0;
484
485err_disable_rq:
486 mlx5e_disable_rq(rq);
487err_destroy_rq:
488 mlx5e_destroy_rq(rq);
489
490 return err;
491}
492
493static void mlx5e_close_rq(struct mlx5e_rq *rq)
494{
495 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
496 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
497
498 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
499 while (!mlx5_wq_ll_is_empty(&rq->wq))
500 msleep(20);
501
502 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
503 napi_synchronize(&rq->channel->napi);
504
505 mlx5e_disable_rq(rq);
506 mlx5e_destroy_rq(rq);
507}
508
509static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
510{
34802a42 511 kfree(sq->wqe_info);
f62b8bb8
AV		 512 kfree(sq->dma_fifo);
513 kfree(sq->skb);
514}
515
516static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
517{
518 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
519 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
520
521 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
522 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
523 numa);
34802a42
AS		 524 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
525 numa);
f62b8bb8 526
34802a42 527 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 528 mlx5e_free_sq_db(sq);
529 return -ENOMEM;
530 }
531
532 sq->dma_fifo_mask = df_sz - 1;
533
534 return 0;
535}
536
537static int mlx5e_create_sq(struct mlx5e_channel *c,
538 int tc,
539 struct mlx5e_sq_param *param,
540 struct mlx5e_sq *sq)
541{
542 struct mlx5e_priv *priv = c->priv;
543 struct mlx5_core_dev *mdev = priv->mdev;
544
545 void *sqc = param->sqc;
546 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
03289b88 547 int txq_ix;
f62b8bb8
AV		 548 int err;
549
550 err = mlx5_alloc_map_uar(mdev, &sq->uar);
551 if (err)
552 return err;
553
311c7c71
SM		 554 param->wq.db_numa_node = cpu_to_node(c->cpu);
555
f62b8bb8
AV		 556 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
557 &sq->wq_ctrl);
558 if (err)
559 goto err_unmap_free_uar;
560
561 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
562 sq->uar_map = sq->uar.map;
88a85f99 563 sq->uar_bf_map = sq->uar.bf_map;
f62b8bb8 564 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 565 sq->max_inline = param->max_inline;
f62b8bb8 566
7ec0bb22
DC		 567 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
568 if (err)
f62b8bb8
AV		 569 goto err_sq_wq_destroy;
570
03289b88
SM		 571 txq_ix = c->ix + tc * priv->params.num_channels;
572 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
f62b8bb8 573
88a85f99 574 sq->pdev = c->pdev;
ef9814de 575 sq->tstamp = &priv->tstamp;
88a85f99
AS		 576 sq->mkey_be = c->mkey_be;
577 sq->channel = c;
578 sq->tc = tc;
579 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
580 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
03289b88 581 priv->txq_to_sq_map[txq_ix] = sq;
f62b8bb8
AV		 582
583 return 0;
584
585err_sq_wq_destroy:
586 mlx5_wq_destroy(&sq->wq_ctrl);
587
588err_unmap_free_uar:
589 mlx5_unmap_free_uar(mdev, &sq->uar);
590
591 return err;
592}
593
594static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
595{
596 struct mlx5e_channel *c = sq->channel;
597 struct mlx5e_priv *priv = c->priv;
598
599 mlx5e_free_sq_db(sq);
600 mlx5_wq_destroy(&sq->wq_ctrl);
601 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
602}
603
604static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
605{
606 struct mlx5e_channel *c = sq->channel;
607 struct mlx5e_priv *priv = c->priv;
608 struct mlx5_core_dev *mdev = priv->mdev;
609
610 void *in;
611 void *sqc;
612 void *wq;
613 int inlen;
614 int err;
615
616 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
617 sizeof(u64) * sq->wq_ctrl.buf.npages;
618 in = mlx5_vzalloc(inlen);
619 if (!in)
620 return -ENOMEM;
621
622 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
623 wq = MLX5_ADDR_OF(sqc, sqc, wq);
624
625 memcpy(sqc, param->sqc, sizeof(param->sqc));
626
f62b8bb8
AV		 627 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
628 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
629 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
630 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
631 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
632
633 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
634 MLX5_SET(wq, wq, uar_page, sq->uar.index);
635 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 636 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 637 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
638
639 mlx5_fill_page_array(&sq->wq_ctrl.buf,
640 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
641
7db22ffb 642 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 643
644 kvfree(in);
645
646 return err;
647}
648
649static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
650{
651 struct mlx5e_channel *c = sq->channel;
652 struct mlx5e_priv *priv = c->priv;
653 struct mlx5_core_dev *mdev = priv->mdev;
654
655 void *in;
656 void *sqc;
657 int inlen;
658 int err;
659
660 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
661 in = mlx5_vzalloc(inlen);
662 if (!in)
663 return -ENOMEM;
664
665 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
666
667 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
668 MLX5_SET(sqc, sqc, state, next_state);
669
7db22ffb 670 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 671
672 kvfree(in);
673
674 return err;
675}
676
677static void mlx5e_disable_sq(struct mlx5e_sq *sq)
678{
679 struct mlx5e_channel *c = sq->channel;
680 struct mlx5e_priv *priv = c->priv;
681 struct mlx5_core_dev *mdev = priv->mdev;
682
7db22ffb 683 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 684}
685
686static int mlx5e_open_sq(struct mlx5e_channel *c,
687 int tc,
688 struct mlx5e_sq_param *param,
689 struct mlx5e_sq *sq)
690{
691 int err;
692
693 err = mlx5e_create_sq(c, tc, param, sq);
694 if (err)
695 return err;
696
697 err = mlx5e_enable_sq(sq, param);
698 if (err)
699 goto err_destroy_sq;
700
701 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
702 if (err)
703 goto err_disable_sq;
704
705 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
706 netdev_tx_reset_queue(sq->txq);
707 netif_tx_start_queue(sq->txq);
708
709 return 0;
710
711err_disable_sq:
712 mlx5e_disable_sq(sq);
713err_destroy_sq:
714 mlx5e_destroy_sq(sq);
715
716 return err;
717}
718
719static inline void netif_tx_disable_queue(struct netdev_queue *txq)
720{
721 __netif_tx_lock_bh(txq);
722 netif_tx_stop_queue(txq);
723 __netif_tx_unlock_bh(txq);
724}
725
726static void mlx5e_close_sq(struct mlx5e_sq *sq)
727{
728 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
729 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
730 netif_tx_disable_queue(sq->txq);
731
732 /* ensure hw is notified of all pending wqes */
733 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 734 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 735
736 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
737 while (sq->cc != sq->pc) /* wait till sq is empty */
738 msleep(20);
739
740 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
741 napi_synchronize(&sq->channel->napi);
742
743 mlx5e_disable_sq(sq);
744 mlx5e_destroy_sq(sq);
745}
746
747static int mlx5e_create_cq(struct mlx5e_channel *c,
748 struct mlx5e_cq_param *param,
749 struct mlx5e_cq *cq)
750{
751 struct mlx5e_priv *priv = c->priv;
752 struct mlx5_core_dev *mdev = priv->mdev;
753 struct mlx5_core_cq *mcq = &cq->mcq;
754 int eqn_not_used;
0b6e26ce 755 unsigned int irqn;
f62b8bb8
AV		 756 int err;
757 u32 i;
758
311c7c71
SM		 759 param->wq.buf_numa_node = cpu_to_node(c->cpu);
760 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 761 param->eq_ix = c->ix;
762
763 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
764 &cq->wq_ctrl);
765 if (err)
766 return err;
767
768 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
769
770 cq->napi = &c->napi;
771
772 mcq->cqe_sz = 64;
773 mcq->set_ci_db = cq->wq_ctrl.db.db;
774 mcq->arm_db = cq->wq_ctrl.db.db + 1;
775 *mcq->set_ci_db = 0;
776 *mcq->arm_db = 0;
777 mcq->vector = param->eq_ix;
778 mcq->comp = mlx5e_completion_event;
779 mcq->event = mlx5e_cq_error_event;
780 mcq->irqn = irqn;
781 mcq->uar = &priv->cq_uar;
782
783 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
784 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
785
786 cqe->op_own = 0xf1;
787 }
788
789 cq->channel = c;
50cfa25a 790 cq->priv = priv;
f62b8bb8
AV		 791
792 return 0;
793}
794
795static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
796{
797 mlx5_wq_destroy(&cq->wq_ctrl);
798}
799
800static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
801{
50cfa25a 802 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 803 struct mlx5_core_dev *mdev = priv->mdev;
804 struct mlx5_core_cq *mcq = &cq->mcq;
805
806 void *in;
807 void *cqc;
808 int inlen;
0b6e26ce 809 unsigned int irqn_not_used;
f62b8bb8
AV		 810 int eqn;
811 int err;
812
813 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
814 sizeof(u64) * cq->wq_ctrl.buf.npages;
815 in = mlx5_vzalloc(inlen);
816 if (!in)
817 return -ENOMEM;
818
819 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
820
821 memcpy(cqc, param->cqc, sizeof(param->cqc));
822
823 mlx5_fill_page_array(&cq->wq_ctrl.buf,
824 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
825
826 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
827
828 MLX5_SET(cqc, cqc, c_eqn, eqn);
829 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
830 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 831 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 832 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
833
834 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
835
836 kvfree(in);
837
838 if (err)
839 return err;
840
841 mlx5e_cq_arm(cq);
842
843 return 0;
844}
845
846static void mlx5e_disable_cq(struct mlx5e_cq *cq)
847{
50cfa25a 848 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 849 struct mlx5_core_dev *mdev = priv->mdev;
850
851 mlx5_core_destroy_cq(mdev, &cq->mcq);
852}
853
854static int mlx5e_open_cq(struct mlx5e_channel *c,
855 struct mlx5e_cq_param *param,
856 struct mlx5e_cq *cq,
857 u16 moderation_usecs,
858 u16 moderation_frames)
859{
860 int err;
861 struct mlx5e_priv *priv = c->priv;
862 struct mlx5_core_dev *mdev = priv->mdev;
863
864 err = mlx5e_create_cq(c, param, cq);
865 if (err)
866 return err;
867
868 err = mlx5e_enable_cq(cq, param);
869 if (err)
870 goto err_destroy_cq;
871
872 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
873 moderation_usecs,
874 moderation_frames);
875 if (err)
876 goto err_destroy_cq;
877
878 return 0;
879
880err_destroy_cq:
881 mlx5e_destroy_cq(cq);
882
883 return err;
884}
885
886static void mlx5e_close_cq(struct mlx5e_cq *cq)
887{
888 mlx5e_disable_cq(cq);
889 mlx5e_destroy_cq(cq);
890}
891
892static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
893{
894 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
895}
896
897static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
898 struct mlx5e_channel_param *cparam)
899{
900 struct mlx5e_priv *priv = c->priv;
901 int err;
902 int tc;
903
904 for (tc = 0; tc < c->num_tc; tc++) {
905 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
906 priv->params.tx_cq_moderation_usec,
907 priv->params.tx_cq_moderation_pkts);
908 if (err)
909 goto err_close_tx_cqs;
f62b8bb8
AV		 910 }
911
912 return 0;
913
914err_close_tx_cqs:
915 for (tc--; tc >= 0; tc--)
916 mlx5e_close_cq(&c->sq[tc].cq);
917
918 return err;
919}
920
921static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
922{
923 int tc;
924
925 for (tc = 0; tc < c->num_tc; tc++)
926 mlx5e_close_cq(&c->sq[tc].cq);
927}
928
929static int mlx5e_open_sqs(struct mlx5e_channel *c,
930 struct mlx5e_channel_param *cparam)
931{
932 int err;
933 int tc;
934
935 for (tc = 0; tc < c->num_tc; tc++) {
936 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
937 if (err)
938 goto err_close_sqs;
939 }
940
941 return 0;
942
943err_close_sqs:
944 for (tc--; tc >= 0; tc--)
945 mlx5e_close_sq(&c->sq[tc]);
946
947 return err;
948}
949
950static void mlx5e_close_sqs(struct mlx5e_channel *c)
951{
952 int tc;
953
954 for (tc = 0; tc < c->num_tc; tc++)
955 mlx5e_close_sq(&c->sq[tc]);
956}
957
5283af89 958static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 959{
960 int i;
961
962 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 963 priv->channeltc_to_txq_map[ix][i] =
964 ix + i * priv->params.num_channels;
03289b88
SM		 965}
966
f62b8bb8
AV		 967static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
968 struct mlx5e_channel_param *cparam,
969 struct mlx5e_channel **cp)
970{
971 struct net_device *netdev = priv->netdev;
972 int cpu = mlx5e_get_cpu(priv, ix);
973 struct mlx5e_channel *c;
974 int err;
975
976 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
977 if (!c)
978 return -ENOMEM;
979
980 c->priv = priv;
981 c->ix = ix;
982 c->cpu = cpu;
983 c->pdev = &priv->mdev->pdev->dev;
984 c->netdev = priv->netdev;
985 c->mkey_be = cpu_to_be32(priv->mr.key);
a4418a6c 986 c->num_tc = priv->params.num_tc;
f62b8bb8 987
5283af89 988 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 989
f62b8bb8
AV		 990 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
991
992 err = mlx5e_open_tx_cqs(c, cparam);
993 if (err)
994 goto err_napi_del;
995
996 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
997 priv->params.rx_cq_moderation_usec,
998 priv->params.rx_cq_moderation_pkts);
999 if (err)
1000 goto err_close_tx_cqs;
f62b8bb8
AV		 1001
1002 napi_enable(&c->napi);
1003
1004 err = mlx5e_open_sqs(c, cparam);
1005 if (err)
1006 goto err_disable_napi;
1007
1008 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1009 if (err)
1010 goto err_close_sqs;
1011
1012 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1013 *cp = c;
1014
1015 return 0;
1016
1017err_close_sqs:
1018 mlx5e_close_sqs(c);
1019
1020err_disable_napi:
1021 napi_disable(&c->napi);
1022 mlx5e_close_cq(&c->rq.cq);
1023
1024err_close_tx_cqs:
1025 mlx5e_close_tx_cqs(c);
1026
1027err_napi_del:
1028 netif_napi_del(&c->napi);
7ae92ae5 1029 napi_hash_del(&c->napi);
f62b8bb8
AV		 1030 kfree(c);
1031
1032 return err;
1033}
1034
1035static void mlx5e_close_channel(struct mlx5e_channel *c)
1036{
1037 mlx5e_close_rq(&c->rq);
1038 mlx5e_close_sqs(c);
1039 napi_disable(&c->napi);
1040 mlx5e_close_cq(&c->rq.cq);
1041 mlx5e_close_tx_cqs(c);
1042 netif_napi_del(&c->napi);
7ae92ae5
ED		 1043
1044 napi_hash_del(&c->napi);
1045 synchronize_rcu();
1046
f62b8bb8
AV		 1047 kfree(c);
1048}
1049
1050static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1051 struct mlx5e_rq_param *param)
1052{
1053 void *rqc = param->rqc;
1054 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1055
1056 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1057 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1058 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1059 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1060 MLX5_SET(wq, wq, pd, priv->pdn);
1061
311c7c71 1062 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1063 param->wq.linear = 1;
1064}
1065
1066static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1067 struct mlx5e_sq_param *param)
1068{
1069 void *sqc = param->sqc;
1070 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1071
1072 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1073 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1074 MLX5_SET(wq, wq, pd, priv->pdn);
1075
311c7c71 1076 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
58d52291 1077 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1078}
1079
1080static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1081 struct mlx5e_cq_param *param)
1082{
1083 void *cqc = param->cqc;
1084
1085 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1086}
1087
1088static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1089 struct mlx5e_cq_param *param)
1090{
1091 void *cqc = param->cqc;
1092
1093 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1094
1095 mlx5e_build_common_cq_param(priv, param);
1096}
1097
1098static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1099 struct mlx5e_cq_param *param)
1100{
1101 void *cqc = param->cqc;
1102
1103 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1104
1105 mlx5e_build_common_cq_param(priv, param);
1106}
1107
1108static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1109 struct mlx5e_channel_param *cparam)
1110{
1111 memset(cparam, 0, sizeof(*cparam));
1112
1113 mlx5e_build_rq_param(priv, &cparam->rq);
1114 mlx5e_build_sq_param(priv, &cparam->sq);
1115 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1116 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1117}
1118
1119static int mlx5e_open_channels(struct mlx5e_priv *priv)
1120{
1121 struct mlx5e_channel_param cparam;
a4418a6c 1122 int nch = priv->params.num_channels;
03289b88 1123 int err = -ENOMEM;
f62b8bb8
AV		 1124 int i;
1125 int j;
1126
a4418a6c
AS		 1127 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1128 GFP_KERNEL);
03289b88 1129
a4418a6c 1130 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1131 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1132
1133 if (!priv->channel || !priv->txq_to_sq_map)
1134 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1135
1136 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1137 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1138 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1139 if (err)
1140 goto err_close_channels;
1141 }
1142
a4418a6c 1143 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1144 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1145 if (err)
1146 goto err_close_channels;
1147 }
1148
1149 return 0;
1150
1151err_close_channels:
1152 for (i--; i >= 0; i--)
1153 mlx5e_close_channel(priv->channel[i]);
1154
03289b88
SM		 1155err_free_txq_to_sq_map:
1156 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1157 kfree(priv->channel);
1158
1159 return err;
1160}
1161
1162static void mlx5e_close_channels(struct mlx5e_priv *priv)
1163{
1164 int i;
1165
1166 for (i = 0; i < priv->params.num_channels; i++)
1167 mlx5e_close_channel(priv->channel[i]);
1168
03289b88 1169 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1170 kfree(priv->channel);
1171}
1172
2be6967c
SM		 1173static int mlx5e_rx_hash_fn(int hfunc)
1174{
1175 return (hfunc == ETH_RSS_HASH_TOP) ?
1176 MLX5_RX_HASH_FN_TOEPLITZ :
1177 MLX5_RX_HASH_FN_INVERTED_XOR8;
1178}
1179
1180static int mlx5e_bits_invert(unsigned long a, int size)
1181{
1182 int inv = 0;
1183 int i;
1184
1185 for (i = 0; i < size; i++)
1186 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1187
1188 return inv;
1189}
1190
936896e9
AS		 1191static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1192{
1193 int i;
1194
1195 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1196 int ix = i;
1197
1198 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1199 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1200
2d75b2bc 1201 ix = priv->params.indirection_rqt[ix];
936896e9
AS		 1202 ix = ix % priv->params.num_channels;
1203 MLX5_SET(rqtc, rqtc, rq_num[i],
1204 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1205 priv->channel[ix]->rq.rqn :
1206 priv->drop_rq.rqn);
1207 }
1208}
1209
4cbeaff5
AS		 1210static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1211 enum mlx5e_rqt_ix rqt_ix)
1212{
4cbeaff5
AS		 1213
1214 switch (rqt_ix) {
1215 case MLX5E_INDIRECTION_RQT:
936896e9 1216 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
4cbeaff5
AS		 1217
1218 break;
1219
1220 default: /* MLX5E_SINGLE_RQ_RQT */
1221 MLX5_SET(rqtc, rqtc, rq_num[0],
5c50368f
AS		 1222 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1223 priv->channel[0]->rq.rqn :
1224 priv->drop_rq.rqn);
4cbeaff5
AS		 1225
1226 break;
1227 }
1228}
1229
40ab6a6e 1230static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1231{
1232 struct mlx5_core_dev *mdev = priv->mdev;
1233 u32 *in;
f62b8bb8
AV		 1234 void *rqtc;
1235 int inlen;
4cbeaff5 1236 int sz;
f62b8bb8 1237 int err;
4cbeaff5 1238
936896e9 1239 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
f62b8bb8 1240
f62b8bb8
AV		 1241 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1242 in = mlx5_vzalloc(inlen);
1243 if (!in)
1244 return -ENOMEM;
1245
1246 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1247
1248 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1249 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1250
4cbeaff5 1251 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1252
4cbeaff5 1253 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1254
1255 kvfree(in);
1256
1257 return err;
1258}
1259
2d75b2bc 1260int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
5c50368f
AS		 1261{
1262 struct mlx5_core_dev *mdev = priv->mdev;
1263 u32 *in;
1264 void *rqtc;
1265 int inlen;
5c50368f
AS		 1266 int sz;
1267 int err;
1268
936896e9 1269 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
5c50368f
AS		 1270
1271 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1272 in = mlx5_vzalloc(inlen);
1273 if (!in)
1274 return -ENOMEM;
1275
1276 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1277
1278 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1279
1280 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1281
1282 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1283
1284 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1285
1286 kvfree(in);
1287
1288 return err;
1289}
1290
40ab6a6e 1291static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1292{
4cbeaff5 1293 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1294}
1295
40ab6a6e
AS		 1296static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1297{
1298 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1299 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1300}
1301
5c50368f
AS		 1302static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1303{
1304 if (!priv->params.lro_en)
1305 return;
1306
1307#define ROUGH_MAX_L2_L3_HDR_SZ 256
1308
1309 MLX5_SET(tirc, tirc, lro_enable_mask,
1310 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1311 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1312 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1313 (priv->params.lro_wqe_sz -
1314 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1315 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1316 MLX5_CAP_ETH(priv->mdev,
d9a40271 1317 lro_timer_supported_periods[2]));
5c50368f
AS		 1318}
1319
1320static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1321{
1322 struct mlx5_core_dev *mdev = priv->mdev;
1323
1324 void *in;
1325 void *tirc;
1326 int inlen;
1327 int err;
1328
1329 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1330 in = mlx5_vzalloc(inlen);
1331 if (!in)
1332 return -ENOMEM;
1333
1334 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1335 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1336
1337 mlx5e_build_tir_ctx_lro(tirc, priv);
1338
1339 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1340
1341 kvfree(in);
1342
1343 return err;
1344}
1345
66189961
TT		 1346static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1347 u32 tirn)
1348{
1349 void *in;
1350 int inlen;
1351 int err;
1352
1353 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1354 in = mlx5_vzalloc(inlen);
1355 if (!in)
1356 return -ENOMEM;
1357
1358 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1359
1360 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1361
1362 kvfree(in);
1363
1364 return err;
1365}
1366
1367static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1368{
1369 int err;
1370 int i;
1371
1372 for (i = 0; i < MLX5E_NUM_TT; i++) {
1373 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1374 priv->tirn[i]);
1375 if (err)
1376 return err;
1377 }
1378
1379 return 0;
1380}
1381
40ab6a6e
AS		 1382static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1383{
1384 struct mlx5e_priv *priv = netdev_priv(netdev);
1385 struct mlx5_core_dev *mdev = priv->mdev;
1386 int hw_mtu;
1387 int err;
1388
1389 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1390 if (err)
1391 return err;
1392
1393 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1394
1395 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1396 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1397 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1398
1399 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1400 return 0;
1401}
1402
08fb1dac
SM		 1403static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1404{
1405 struct mlx5e_priv *priv = netdev_priv(netdev);
1406 int nch = priv->params.num_channels;
1407 int ntc = priv->params.num_tc;
1408 int tc;
1409
1410 netdev_reset_tc(netdev);
1411
1412 if (ntc == 1)
1413 return;
1414
1415 netdev_set_num_tc(netdev, ntc);
1416
1417 for (tc = 0; tc < ntc; tc++)
1418 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1419}
1420
40ab6a6e
AS		 1421int mlx5e_open_locked(struct net_device *netdev)
1422{
1423 struct mlx5e_priv *priv = netdev_priv(netdev);
1424 int num_txqs;
1425 int err;
1426
1427 set_bit(MLX5E_STATE_OPENED, &priv->state);
1428
08fb1dac
SM		 1429 mlx5e_netdev_set_tcs(netdev);
1430
40ab6a6e
AS		 1431 num_txqs = priv->params.num_channels * priv->params.num_tc;
1432 netif_set_real_num_tx_queues(netdev, num_txqs);
1433 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1434
1435 err = mlx5e_set_dev_port_mtu(netdev);
1436 if (err)
343b29f3 1437 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1438
1439 err = mlx5e_open_channels(priv);
1440 if (err) {
1441 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1442 __func__, err);
343b29f3 1443 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1444 }
1445
66189961
TT		 1446 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1447 if (err) {
1448 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1449 __func__, err);
1450 goto err_close_channels;
1451 }
1452
40ab6a6e
AS		 1453 mlx5e_update_carrier(priv);
1454 mlx5e_redirect_rqts(priv);
ef9814de 1455 mlx5e_timestamp_init(priv);
40ab6a6e
AS		 1456
1457 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1458
9b37b07f 1459 return 0;
343b29f3 1460
66189961
TT		 1461err_close_channels:
1462 mlx5e_close_channels(priv);
343b29f3
AS		 1463err_clear_state_opened_flag:
1464 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1465 return err;
40ab6a6e
AS		 1466}
1467
1468static int mlx5e_open(struct net_device *netdev)
1469{
1470 struct mlx5e_priv *priv = netdev_priv(netdev);
1471 int err;
1472
1473 mutex_lock(&priv->state_lock);
1474 err = mlx5e_open_locked(netdev);
1475 mutex_unlock(&priv->state_lock);
1476
1477 return err;
1478}
1479
1480int mlx5e_close_locked(struct net_device *netdev)
1481{
1482 struct mlx5e_priv *priv = netdev_priv(netdev);
1483
a1985740
AS		 1484 /* May already be CLOSED in case a previous configuration operation
1485 * (e.g RX/TX queue size change) that involves close&open failed.
1486 */
1487 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1488 return 0;
1489
40ab6a6e
AS		 1490 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1491
ef9814de 1492 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1493 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1494 netif_carrier_off(priv->netdev);
1495 mlx5e_close_channels(priv);
1496
1497 return 0;
1498}
1499
1500static int mlx5e_close(struct net_device *netdev)
1501{
1502 struct mlx5e_priv *priv = netdev_priv(netdev);
1503 int err;
1504
1505 mutex_lock(&priv->state_lock);
1506 err = mlx5e_close_locked(netdev);
1507 mutex_unlock(&priv->state_lock);
1508
1509 return err;
1510}
1511
1512static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1513 struct mlx5e_rq *rq,
1514 struct mlx5e_rq_param *param)
1515{
1516 struct mlx5_core_dev *mdev = priv->mdev;
1517 void *rqc = param->rqc;
1518 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1519 int err;
1520
1521 param->wq.db_numa_node = param->wq.buf_numa_node;
1522
1523 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1524 &rq->wq_ctrl);
1525 if (err)
1526 return err;
1527
1528 rq->priv = priv;
1529
1530 return 0;
1531}
1532
1533static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1534 struct mlx5e_cq *cq,
1535 struct mlx5e_cq_param *param)
1536{
1537 struct mlx5_core_dev *mdev = priv->mdev;
1538 struct mlx5_core_cq *mcq = &cq->mcq;
1539 int eqn_not_used;
0b6e26ce 1540 unsigned int irqn;
40ab6a6e
AS		 1541 int err;
1542
1543 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1544 &cq->wq_ctrl);
1545 if (err)
1546 return err;
1547
1548 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1549
1550 mcq->cqe_sz = 64;
1551 mcq->set_ci_db = cq->wq_ctrl.db.db;
1552 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1553 *mcq->set_ci_db = 0;
1554 *mcq->arm_db = 0;
1555 mcq->vector = param->eq_ix;
1556 mcq->comp = mlx5e_completion_event;
1557 mcq->event = mlx5e_cq_error_event;
1558 mcq->irqn = irqn;
1559 mcq->uar = &priv->cq_uar;
1560
1561 cq->priv = priv;
1562
1563 return 0;
1564}
1565
1566static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1567{
1568 struct mlx5e_cq_param cq_param;
1569 struct mlx5e_rq_param rq_param;
1570 struct mlx5e_rq *rq = &priv->drop_rq;
1571 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1572 int err;
1573
1574 memset(&cq_param, 0, sizeof(cq_param));
1575 memset(&rq_param, 0, sizeof(rq_param));
1576 mlx5e_build_rx_cq_param(priv, &cq_param);
1577 mlx5e_build_rq_param(priv, &rq_param);
1578
1579 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1580 if (err)
1581 return err;
1582
1583 err = mlx5e_enable_cq(cq, &cq_param);
1584 if (err)
1585 goto err_destroy_cq;
1586
1587 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1588 if (err)
1589 goto err_disable_cq;
1590
1591 err = mlx5e_enable_rq(rq, &rq_param);
1592 if (err)
1593 goto err_destroy_rq;
1594
1595 return 0;
1596
1597err_destroy_rq:
1598 mlx5e_destroy_rq(&priv->drop_rq);
1599
1600err_disable_cq:
1601 mlx5e_disable_cq(&priv->drop_rq.cq);
1602
1603err_destroy_cq:
1604 mlx5e_destroy_cq(&priv->drop_rq.cq);
1605
1606 return err;
1607}
1608
1609static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1610{
1611 mlx5e_disable_rq(&priv->drop_rq);
1612 mlx5e_destroy_rq(&priv->drop_rq);
1613 mlx5e_disable_cq(&priv->drop_rq.cq);
1614 mlx5e_destroy_cq(&priv->drop_rq.cq);
1615}
1616
1617static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1618{
1619 struct mlx5_core_dev *mdev = priv->mdev;
1620 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1621 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1622
1623 memset(in, 0, sizeof(in));
1624
08fb1dac 1625 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1626 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1627
1628 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1629}
1630
1631static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1632{
1633 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1634}
1635
1636static int mlx5e_create_tises(struct mlx5e_priv *priv)
1637{
1638 int err;
1639 int tc;
1640
08fb1dac 1641 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1642 err = mlx5e_create_tis(priv, tc);
1643 if (err)
1644 goto err_close_tises;
1645 }
1646
1647 return 0;
1648
1649err_close_tises:
1650 for (tc--; tc >= 0; tc--)
1651 mlx5e_destroy_tis(priv, tc);
1652
1653 return err;
1654}
1655
1656static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1657{
1658 int tc;
1659
08fb1dac 1660 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1661 mlx5e_destroy_tis(priv, tc);
1662}
1663
f62b8bb8
AV		 1664static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1665{
1666 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1667
3191e05f
AS		 1668 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1669
5a6f8aef
AS		 1670#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1671 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1672
5a6f8aef
AS		 1673#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1674 MLX5_HASH_FIELD_SEL_DST_IP |\
1675 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1676 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1677
a741749f
AS		 1678#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1679 MLX5_HASH_FIELD_SEL_DST_IP |\
1680 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1681
5c50368f 1682 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1683
4cbeaff5
AS		 1684 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1685
f62b8bb8
AV		 1686 switch (tt) {
1687 case MLX5E_TT_ANY:
4cbeaff5
AS		 1688 MLX5_SET(tirc, tirc, indirect_table,
1689 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1690 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1691 break;
1692 default:
f62b8bb8 1693 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1694 priv->rqtn[MLX5E_INDIRECTION_RQT]);
f62b8bb8 1695 MLX5_SET(tirc, tirc, rx_hash_fn,
2be6967c
SM		 1696 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1697 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1698 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1699 rx_hash_toeplitz_key);
1700 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1701 rx_hash_toeplitz_key);
1702
1703 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
57afead5 1704 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2be6967c 1705 }
f62b8bb8
AV		 1706 break;
1707 }
1708
1709 switch (tt) {
1710 case MLX5E_TT_IPV4_TCP:
1711 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1712 MLX5_L3_PROT_TYPE_IPV4);
1713 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1714 MLX5_L4_PROT_TYPE_TCP);
1715 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1716 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1717 break;
1718
1719 case MLX5E_TT_IPV6_TCP:
1720 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1721 MLX5_L3_PROT_TYPE_IPV6);
1722 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1723 MLX5_L4_PROT_TYPE_TCP);
1724 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1725 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1726 break;
1727
1728 case MLX5E_TT_IPV4_UDP:
1729 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1730 MLX5_L3_PROT_TYPE_IPV4);
1731 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1732 MLX5_L4_PROT_TYPE_UDP);
1733 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1734 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1735 break;
1736
1737 case MLX5E_TT_IPV6_UDP:
1738 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1739 MLX5_L3_PROT_TYPE_IPV6);
1740 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1741 MLX5_L4_PROT_TYPE_UDP);
1742 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1743 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1744 break;
1745
a741749f
AS		 1746 case MLX5E_TT_IPV4_IPSEC_AH:
1747 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1748 MLX5_L3_PROT_TYPE_IPV4);
1749 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1750 MLX5_HASH_IP_IPSEC_SPI);
1751 break;
1752
1753 case MLX5E_TT_IPV6_IPSEC_AH:
1754 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1755 MLX5_L3_PROT_TYPE_IPV6);
1756 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1757 MLX5_HASH_IP_IPSEC_SPI);
1758 break;
1759
1760 case MLX5E_TT_IPV4_IPSEC_ESP:
1761 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1762 MLX5_L3_PROT_TYPE_IPV4);
1763 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1764 MLX5_HASH_IP_IPSEC_SPI);
1765 break;
1766
1767 case MLX5E_TT_IPV6_IPSEC_ESP:
1768 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1769 MLX5_L3_PROT_TYPE_IPV6);
1770 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1771 MLX5_HASH_IP_IPSEC_SPI);
1772 break;
1773
f62b8bb8
AV		 1774 case MLX5E_TT_IPV4:
1775 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1776 MLX5_L3_PROT_TYPE_IPV4);
1777 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1778 MLX5_HASH_IP);
1779 break;
1780
1781 case MLX5E_TT_IPV6:
1782 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1783 MLX5_L3_PROT_TYPE_IPV6);
1784 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1785 MLX5_HASH_IP);
1786 break;
1787 }
1788}
1789
40ab6a6e 1790static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8
AV		 1791{
1792 struct mlx5_core_dev *mdev = priv->mdev;
1793 u32 *in;
1794 void *tirc;
1795 int inlen;
1796 int err;
1797
1798 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1799 in = mlx5_vzalloc(inlen);
1800 if (!in)
1801 return -ENOMEM;
1802
1803 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1804
1805 mlx5e_build_tir_ctx(priv, tirc, tt);
1806
7db22ffb 1807 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1808
1809 kvfree(in);
1810
1811 return err;
1812}
1813
40ab6a6e 1814static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8 1815{
7db22ffb 1816 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1817}
1818
40ab6a6e 1819static int mlx5e_create_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1820{
1821 int err;
1822 int i;
1823
1824 for (i = 0; i < MLX5E_NUM_TT; i++) {
40ab6a6e 1825 err = mlx5e_create_tir(priv, i);
f62b8bb8 1826 if (err)
40ab6a6e 1827 goto err_destroy_tirs;
f62b8bb8
AV		 1828 }
1829
1830 return 0;
1831
40ab6a6e 1832err_destroy_tirs:
f62b8bb8 1833 for (i--; i >= 0; i--)
40ab6a6e 1834 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1835
1836 return err;
1837}
1838
40ab6a6e 1839static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1840{
1841 int i;
1842
1843 for (i = 0; i < MLX5E_NUM_TT; i++)
40ab6a6e 1844 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1845}
1846
08fb1dac
SM		 1847static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1848{
1849 struct mlx5e_priv *priv = netdev_priv(netdev);
1850 bool was_opened;
1851 int err = 0;
1852
1853 if (tc && tc != MLX5E_MAX_NUM_TC)
1854 return -EINVAL;
1855
1856 mutex_lock(&priv->state_lock);
1857
1858 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1859 if (was_opened)
1860 mlx5e_close_locked(priv->netdev);
1861
1862 priv->params.num_tc = tc ? tc : 1;
1863
1864 if (was_opened)
1865 err = mlx5e_open_locked(priv->netdev);
1866
1867 mutex_unlock(&priv->state_lock);
1868
1869 return err;
1870}
1871
1872static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1873 __be16 proto, struct tc_to_netdev *tc)
1874{
1875 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
1876 return -EINVAL;
1877
1878 return mlx5e_setup_tc(dev, tc->tc);
1879}
1880
f62b8bb8
AV		 1881static struct rtnl_link_stats64 *
1882mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1883{
1884 struct mlx5e_priv *priv = netdev_priv(dev);
1885 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1886
1887 stats->rx_packets = vstats->rx_packets;
1888 stats->rx_bytes = vstats->rx_bytes;
1889 stats->tx_packets = vstats->tx_packets;
1890 stats->tx_bytes = vstats->tx_bytes;
1891 stats->multicast = vstats->rx_multicast_packets +
1892 vstats->tx_multicast_packets;
1893 stats->tx_errors = vstats->tx_error_packets;
1894 stats->rx_errors = vstats->rx_error_packets;
1895 stats->tx_dropped = vstats->tx_queue_dropped;
1896 stats->rx_crc_errors = 0;
1897 stats->rx_length_errors = 0;
1898
1899 return stats;
1900}
1901
1902static void mlx5e_set_rx_mode(struct net_device *dev)
1903{
1904 struct mlx5e_priv *priv = netdev_priv(dev);
1905
1906 schedule_work(&priv->set_rx_mode_work);
1907}
1908
1909static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1910{
1911 struct mlx5e_priv *priv = netdev_priv(netdev);
1912 struct sockaddr *saddr = addr;
1913
1914 if (!is_valid_ether_addr(saddr->sa_data))
1915 return -EADDRNOTAVAIL;
1916
1917 netif_addr_lock_bh(netdev);
1918 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1919 netif_addr_unlock_bh(netdev);
1920
1921 schedule_work(&priv->set_rx_mode_work);
1922
1923 return 0;
1924}
1925
1926static int mlx5e_set_features(struct net_device *netdev,
1927 netdev_features_t features)
1928{
1929 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 1930 int err = 0;
f62b8bb8 1931 netdev_features_t changes = features ^ netdev->features;
f62b8bb8
AV		 1932
1933 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 1934
1935 if (changes & NETIF_F_LRO) {
98e81b0a
AS		 1936 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1937
1938 if (was_opened)
1939 mlx5e_close_locked(priv->netdev);
f62b8bb8 1940
98e81b0a 1941 priv->params.lro_en = !!(features & NETIF_F_LRO);
5c50368f
AS		 1942 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1943 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
98e81b0a
AS		 1944
1945 if (was_opened)
1946 err = mlx5e_open_locked(priv->netdev);
1947 }
f62b8bb8 1948
9b37b07f
AS		 1949 mutex_unlock(&priv->state_lock);
1950
f62b8bb8
AV		 1951 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1952 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1953 mlx5e_enable_vlan_filter(priv);
1954 else
1955 mlx5e_disable_vlan_filter(priv);
1956 }
1957
fe9f4fe5 1958 return err;
f62b8bb8
AV		 1959}
1960
1961static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1962{
1963 struct mlx5e_priv *priv = netdev_priv(netdev);
1964 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1965 bool was_opened;
f62b8bb8 1966 int max_mtu;
98e81b0a 1967 int err = 0;
f62b8bb8 1968
facc9699 1969 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1970
50a9eea6
DT		 1971 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1972
facc9699
SM		 1973 if (new_mtu > max_mtu) {
1974 netdev_err(netdev,
1975 "%s: Bad MTU (%d) > (%d) Max\n",
1976 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1977 return -EINVAL;
1978 }
1979
1980 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1981
1982 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1983 if (was_opened)
1984 mlx5e_close_locked(netdev);
1985
f62b8bb8 1986 netdev->mtu = new_mtu;
98e81b0a
AS		 1987
1988 if (was_opened)
1989 err = mlx5e_open_locked(netdev);
1990
f62b8bb8
AV		 1991 mutex_unlock(&priv->state_lock);
1992
1993 return err;
1994}
1995
ef9814de
EBE		 1996static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1997{
1998 switch (cmd) {
1999 case SIOCSHWTSTAMP:
2000 return mlx5e_hwstamp_set(dev, ifr);
2001 case SIOCGHWTSTAMP:
2002 return mlx5e_hwstamp_get(dev, ifr);
2003 default:
2004 return -EOPNOTSUPP;
2005 }
2006}
2007
66e49ded
SM		 2008static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2009{
2010 struct mlx5e_priv *priv = netdev_priv(dev);
2011 struct mlx5_core_dev *mdev = priv->mdev;
2012
2013 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2014}
2015
2016static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2017{
2018 struct mlx5e_priv *priv = netdev_priv(dev);
2019 struct mlx5_core_dev *mdev = priv->mdev;
2020
2021 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2022 vlan, qos);
2023}
2024
2025static int mlx5_vport_link2ifla(u8 esw_link)
2026{
2027 switch (esw_link) {
2028 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2029 return IFLA_VF_LINK_STATE_DISABLE;
2030 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2031 return IFLA_VF_LINK_STATE_ENABLE;
2032 }
2033 return IFLA_VF_LINK_STATE_AUTO;
2034}
2035
2036static int mlx5_ifla_link2vport(u8 ifla_link)
2037{
2038 switch (ifla_link) {
2039 case IFLA_VF_LINK_STATE_DISABLE:
2040 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2041 case IFLA_VF_LINK_STATE_ENABLE:
2042 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2043 }
2044 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2045}
2046
2047static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2048 int link_state)
2049{
2050 struct mlx5e_priv *priv = netdev_priv(dev);
2051 struct mlx5_core_dev *mdev = priv->mdev;
2052
2053 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2054 mlx5_ifla_link2vport(link_state));
2055}
2056
2057static int mlx5e_get_vf_config(struct net_device *dev,
2058 int vf, struct ifla_vf_info *ivi)
2059{
2060 struct mlx5e_priv *priv = netdev_priv(dev);
2061 struct mlx5_core_dev *mdev = priv->mdev;
2062 int err;
2063
2064 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2065 if (err)
2066 return err;
2067 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2068 return 0;
2069}
2070
2071static int mlx5e_get_vf_stats(struct net_device *dev,
2072 int vf, struct ifla_vf_stats *vf_stats)
2073{
2074 struct mlx5e_priv *priv = netdev_priv(dev);
2075 struct mlx5_core_dev *mdev = priv->mdev;
2076
2077 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2078 vf_stats);
2079}
2080
b0eed40e 2081static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2082 .ndo_open = mlx5e_open,
2083 .ndo_stop = mlx5e_close,
2084 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2085 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2086 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2087 .ndo_get_stats64 = mlx5e_get_stats,
2088 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2089 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2090 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2091 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2092 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2093 .ndo_change_mtu = mlx5e_change_mtu,
2094 .ndo_do_ioctl = mlx5e_ioctl,
2095};
2096
2097static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2098 .ndo_open = mlx5e_open,
2099 .ndo_stop = mlx5e_close,
2100 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2101 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2102 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2103 .ndo_get_stats64 = mlx5e_get_stats,
2104 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2105 .ndo_set_mac_address = mlx5e_set_mac,
2106 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2107 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2108 .ndo_set_features = mlx5e_set_features,
2109 .ndo_change_mtu = mlx5e_change_mtu,
2110 .ndo_do_ioctl = mlx5e_ioctl,
2111 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2112 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2113 .ndo_get_vf_config = mlx5e_get_vf_config,
2114 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2115 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2116};
2117
2118static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2119{
2120 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2121 return -ENOTSUPP;
2122 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2123 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2124 !MLX5_CAP_ETH(mdev, csum_cap) ||
2125 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2126 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2127 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2128 MLX5_CAP_FLOWTABLE(mdev,
2129 flow_table_properties_nic_receive.max_ft_level)
2130 < 3) {
f62b8bb8
AV		 2131 mlx5_core_warn(mdev,
2132 "Not creating net device, some required device capabilities are missing\n");
2133 return -ENOTSUPP;
2134 }
66189961
TT		 2135 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2136 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2137
f62b8bb8
AV		 2138 return 0;
2139}
2140
58d52291
AS		 2141u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2142{
2143 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2144
2145 return bf_buf_size -
2146 sizeof(struct mlx5e_tx_wqe) +
2147 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2148}
2149
08fb1dac
SM		 2150#ifdef CONFIG_MLX5_CORE_EN_DCB
2151static void mlx5e_ets_init(struct mlx5e_priv *priv)
2152{
2153 int i;
2154
2155 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2156 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2157 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2158 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2159 priv->params.ets.prio_tc[i] = i;
2160 }
2161
2162 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2163 priv->params.ets.prio_tc[0] = 1;
2164 priv->params.ets.prio_tc[1] = 0;
2165}
2166#endif
2167
f62b8bb8
AV		 2168static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2169 struct net_device *netdev,
936896e9 2170 int num_channels)
f62b8bb8
AV		 2171{
2172 struct mlx5e_priv *priv = netdev_priv(netdev);
2d75b2bc 2173 int i;
f62b8bb8
AV		 2174
2175 priv->params.log_sq_size =
2176 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2177 priv->params.log_rq_size =
2178 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2179 priv->params.rx_cq_moderation_usec =
2180 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2181 priv->params.rx_cq_moderation_pkts =
2182 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2183 priv->params.tx_cq_moderation_usec =
2184 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2185 priv->params.tx_cq_moderation_pkts =
2186 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2187 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8
AV		 2188 priv->params.min_rx_wqes =
2189 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
f62b8bb8 2190 priv->params.num_tc = 1;
2be6967c 2191 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2192
57afead5
AS		 2193 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2194 sizeof(priv->params.toeplitz_hash_key));
2195
2d75b2bc
AS		 2196 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
2197 priv->params.indirection_rqt[i] = i % num_channels;
2198
f62b8bb8
AV		 2199 priv->params.lro_wqe_sz =
2200 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2201
2202 priv->mdev = mdev;
2203 priv->netdev = netdev;
936896e9 2204 priv->params.num_channels = num_channels;
08fb1dac
SM		 2205
2206#ifdef CONFIG_MLX5_CORE_EN_DCB
2207 mlx5e_ets_init(priv);
2208#endif
f62b8bb8
AV		 2209
2210 spin_lock_init(&priv->async_events_spinlock);
2211 mutex_init(&priv->state_lock);
2212
2213 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2214 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2215 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2216}
2217
2218static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2219{
2220 struct mlx5e_priv *priv = netdev_priv(netdev);
2221
e1d7d349 2222 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2223 if (is_zero_ether_addr(netdev->dev_addr) &&
2224 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2225 eth_hw_addr_random(netdev);
2226 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2227 }
f62b8bb8
AV		 2228}
2229
2230static void mlx5e_build_netdev(struct net_device *netdev)
2231{
2232 struct mlx5e_priv *priv = netdev_priv(netdev);
2233 struct mlx5_core_dev *mdev = priv->mdev;
2234
2235 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2236
08fb1dac 2237 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2238 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2239#ifdef CONFIG_MLX5_CORE_EN_DCB
2240 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2241#endif
2242 } else {
b0eed40e 2243 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2244 }
66e49ded 2245
f62b8bb8
AV		 2246 netdev->watchdog_timeo = 15 * HZ;
2247
2248 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2249
12be4b21 2250 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2251 netdev->vlan_features |= NETIF_F_IP_CSUM;
2252 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2253 netdev->vlan_features |= NETIF_F_GRO;
2254 netdev->vlan_features |= NETIF_F_TSO;
2255 netdev->vlan_features |= NETIF_F_TSO6;
2256 netdev->vlan_features |= NETIF_F_RXCSUM;
2257 netdev->vlan_features |= NETIF_F_RXHASH;
2258
2259 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2260 netdev->vlan_features |= NETIF_F_LRO;
2261
2262 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2263 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2264 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2265 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2266
2267 netdev->features = netdev->hw_features;
2268 if (!priv->params.lro_en)
2269 netdev->features &= ~NETIF_F_LRO;
2270
2271 netdev->features |= NETIF_F_HIGHDMA;
2272
2273 netdev->priv_flags |= IFF_UNICAST_FLT;
2274
2275 mlx5e_set_netdev_dev_addr(netdev);
2276}
2277
2278static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2279 struct mlx5_core_mr *mr)
2280{
2281 struct mlx5_core_dev *mdev = priv->mdev;
2282 struct mlx5_create_mkey_mbox_in *in;
2283 int err;
2284
2285 in = mlx5_vzalloc(sizeof(*in));
2286 if (!in)
2287 return -ENOMEM;
2288
2289 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2290 MLX5_PERM_LOCAL_READ |
2291 MLX5_ACCESS_MODE_PA;
2292 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2293 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2294
2295 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2296 NULL);
2297
2298 kvfree(in);
2299
2300 return err;
2301}
2302
2303static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2304{
2305 struct net_device *netdev;
2306 struct mlx5e_priv *priv;
3435ab59 2307 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2308 int err;
2309
2310 if (mlx5e_check_required_hca_cap(mdev))
2311 return NULL;
2312
08fb1dac
SM		 2313 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2314 nch * MLX5E_MAX_NUM_TC,
2315 nch);
f62b8bb8
AV		 2316 if (!netdev) {
2317 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2318 return NULL;
2319 }
2320
936896e9 2321 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2322 mlx5e_build_netdev(netdev);
2323
2324 netif_carrier_off(netdev);
2325
2326 priv = netdev_priv(netdev);
2327
2328 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2329 if (err) {
1f2a3003 2330 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2331 goto err_free_netdev;
2332 }
2333
2334 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2335 if (err) {
1f2a3003 2336 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2337 goto err_unmap_free_uar;
2338 }
2339
8d7f9ecb 2340 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 2341 if (err) {
1f2a3003 2342 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2343 goto err_dealloc_pd;
2344 }
2345
f62b8bb8
AV		 2346 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2347 if (err) {
1f2a3003 2348 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2349 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2350 }
2351
40ab6a6e 2352 err = mlx5e_create_tises(priv);
5c50368f 2353 if (err) {
40ab6a6e 2354 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
5c50368f
AS		 2355 goto err_destroy_mkey;
2356 }
2357
2358 err = mlx5e_open_drop_rq(priv);
2359 if (err) {
2360 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2361 goto err_destroy_tises;
5c50368f
AS		 2362 }
2363
40ab6a6e 2364 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2365 if (err) {
40ab6a6e 2366 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
5c50368f
AS		 2367 goto err_close_drop_rq;
2368 }
2369
40ab6a6e 2370 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2371 if (err) {
40ab6a6e
AS		 2372 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2373 goto err_destroy_rqt_indir;
5c50368f
AS		 2374 }
2375
40ab6a6e 2376 err = mlx5e_create_tirs(priv);
5c50368f 2377 if (err) {
40ab6a6e
AS		 2378 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2379 goto err_destroy_rqt_single;
5c50368f
AS		 2380 }
2381
40ab6a6e 2382 err = mlx5e_create_flow_tables(priv);
5c50368f 2383 if (err) {
40ab6a6e
AS		 2384 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2385 goto err_destroy_tirs;
5c50368f
AS		 2386 }
2387
2388 mlx5e_init_eth_addr(priv);
2389
08fb1dac
SM		 2390#ifdef CONFIG_MLX5_CORE_EN_DCB
2391 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2392#endif
2393
f62b8bb8
AV		 2394 err = register_netdev(netdev);
2395 if (err) {
1f2a3003 2396 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
40ab6a6e 2397 goto err_destroy_flow_tables;
f62b8bb8
AV		 2398 }
2399
2400 mlx5e_enable_async_events(priv);
9b37b07f 2401 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 2402
2403 return priv;
2404
40ab6a6e
AS		 2405err_destroy_flow_tables:
2406 mlx5e_destroy_flow_tables(priv);
5c50368f 2407
40ab6a6e
AS		 2408err_destroy_tirs:
2409 mlx5e_destroy_tirs(priv);
5c50368f 2410
40ab6a6e
AS		 2411err_destroy_rqt_single:
2412 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2413
40ab6a6e
AS		 2414err_destroy_rqt_indir:
2415 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f
AS		 2416
2417err_close_drop_rq:
2418 mlx5e_close_drop_rq(priv);
2419
40ab6a6e
AS		 2420err_destroy_tises:
2421 mlx5e_destroy_tises(priv);
5c50368f 2422
f62b8bb8
AV		 2423err_destroy_mkey:
2424 mlx5_core_destroy_mkey(mdev, &priv->mr);
2425
3191e05f 2426err_dealloc_transport_domain:
8d7f9ecb 2427 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 2428
f62b8bb8
AV		 2429err_dealloc_pd:
2430 mlx5_core_dealloc_pd(mdev, priv->pdn);
2431
2432err_unmap_free_uar:
2433 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2434
2435err_free_netdev:
2436 free_netdev(netdev);
2437
2438 return NULL;
2439}
2440
2441static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2442{
2443 struct mlx5e_priv *priv = vpriv;
2444 struct net_device *netdev = priv->netdev;
2445
9b37b07f
AS		 2446 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2447
2448 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 2449 mlx5e_disable_async_events(priv);
2450 flush_scheduled_work();
f62b8bb8 2451 unregister_netdev(netdev);
40ab6a6e
AS		 2452 mlx5e_destroy_flow_tables(priv);
2453 mlx5e_destroy_tirs(priv);
2454 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2455 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2456 mlx5e_close_drop_rq(priv);
40ab6a6e 2457 mlx5e_destroy_tises(priv);
f62b8bb8 2458 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
8d7f9ecb 2459 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 2460 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2461 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
f62b8bb8
AV		 2462 free_netdev(netdev);
2463}
2464
2465static void *mlx5e_get_netdev(void *vpriv)
2466{
2467 struct mlx5e_priv *priv = vpriv;
2468
2469 return priv->netdev;
2470}
2471
2472static struct mlx5_interface mlx5e_interface = {
2473 .add = mlx5e_create_netdev,
2474 .remove = mlx5e_destroy_netdev,
2475 .event = mlx5e_async_event,
2476 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2477 .get_dev = mlx5e_get_netdev,
2478};
2479
2480void mlx5e_init(void)
2481{
2482 mlx5_register_interface(&mlx5e_interface);
2483}
2484
2485void mlx5e_cleanup(void)
2486{
2487 mlx5_unregister_interface(&mlx5e_interface);
2488}
Linux kernel - Deliverables
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