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net/mlx5e: Add TXQ set max rate support
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8
AV		 41
42struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45};
46
47struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
58d52291 50 u16 max_inline;
d3c9bc27 51 bool icosq;
f62b8bb8
AV		 52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
58};
59
60struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
d3c9bc27 63 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
d3c9bc27 66 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 67};
68
69static void mlx5e_update_carrier(struct mlx5e_priv *priv)
70{
71 struct mlx5_core_dev *mdev = priv->mdev;
72 u8 port_state;
73
74 port_state = mlx5_query_vport_state(mdev,
e7546514 75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 76
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
79 else
80 netif_carrier_off(priv->netdev);
81}
82
83static void mlx5e_update_carrier_work(struct work_struct *work)
84{
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
86 update_carrier_work);
87
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
92}
93
9218b44d 94static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 95{
9218b44d 96 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
9218b44d 99 u64 tx_offload_none = 0;
f62b8bb8
AV		 100 int i, j;
101
9218b44d 102 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
105
faf4478b
GP		 106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
f62b8bb8
AV		 108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
bbceefce 111 s->rx_csum_sw += rq_stats->csum_sw;
1b223dd3 112 s->rx_csum_inner += rq_stats->csum_inner;
f62b8bb8 113 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 114 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 115 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 116 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 117 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
118 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
f62b8bb8 119
a4418a6c 120 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 121 sq_stats = &priv->channel[i]->sq[j].stats;
122
faf4478b
GP		 123 s->tx_packets += sq_stats->packets;
124 s->tx_bytes += sq_stats->bytes;
f62b8bb8
AV		 125 s->tso_packets += sq_stats->tso_packets;
126 s->tso_bytes += sq_stats->tso_bytes;
89db09eb
MF		 127 s->tso_inner_packets += sq_stats->tso_inner_packets;
128 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 129 s->tx_queue_stopped += sq_stats->stopped;
130 s->tx_queue_wake += sq_stats->wake;
131 s->tx_queue_dropped += sq_stats->dropped;
89db09eb 132 s->tx_csum_inner += sq_stats->csum_offload_inner;
f62b8bb8
AV		 133 tx_offload_none += sq_stats->csum_offload_none;
134 }
135 }
136
9218b44d
GP		 137 /* Update calculated offload counters */
138 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
139 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
140 s->rx_csum_sw;
121fcdc8
GP		 141
142 s->link_down_events = MLX5_GET(ppcnt_reg,
143 priv->stats.pport.phy_counters,
144 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 145}
146
147static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
148{
149 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
150 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
151 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
152 struct mlx5_core_dev *mdev = priv->mdev;
153
f62b8bb8
AV		 154 memset(in, 0, sizeof(in));
155
156 MLX5_SET(query_vport_counter_in, in, opcode,
157 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
158 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
159 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
160
161 memset(out, 0, outlen);
162
9218b44d
GP		 163 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
164}
165
166static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
167{
168 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
169 struct mlx5_core_dev *mdev = priv->mdev;
170 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 171 int prio;
9218b44d
GP		 172 void *out;
173 u32 *in;
174
175 in = mlx5_vzalloc(sz);
176 if (!in)
f62b8bb8
AV		 177 goto free_out;
178
9218b44d 179 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 180
9218b44d
GP		 181 out = pstats->IEEE_802_3_counters;
182 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
183 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 184
9218b44d
GP		 185 out = pstats->RFC_2863_counters;
186 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
187 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
188
189 out = pstats->RFC_2819_counters;
190 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
191 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 192
121fcdc8
GP		 193 out = pstats->phy_counters;
194 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
195 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
196
cf678570
GP		 197 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
198 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
199 out = pstats->per_prio_counters[prio];
200 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
201 mlx5_core_access_reg(mdev, in, sz, out, sz,
202 MLX5_REG_PPCNT, 0, 0);
203 }
204
f62b8bb8 205free_out:
9218b44d
GP		 206 kvfree(in);
207}
208
209static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
210{
211 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
212
213 if (!priv->q_counter)
214 return;
215
216 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
217 &qcnt->rx_out_of_buffer);
218}
219
220void mlx5e_update_stats(struct mlx5e_priv *priv)
221{
9218b44d
GP		 222 mlx5e_update_q_counter(priv);
223 mlx5e_update_vport_counters(priv);
224 mlx5e_update_pport_counters(priv);
121fcdc8 225 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 226}
227
228static void mlx5e_update_stats_work(struct work_struct *work)
229{
230 struct delayed_work *dwork = to_delayed_work(work);
231 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
232 update_stats_work);
233 mutex_lock(&priv->state_lock);
234 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
235 mlx5e_update_stats(priv);
7bb29755
MF		 236 queue_delayed_work(priv->wq, dwork,
237 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 238 }
239 mutex_unlock(&priv->state_lock);
240}
241
daa21560
TT		 242static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
243 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 244{
daa21560
TT		 245 struct mlx5e_priv *priv = vpriv;
246
247 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
248 return;
249
f62b8bb8
AV		 250 switch (event) {
251 case MLX5_DEV_EVENT_PORT_UP:
252 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 253 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 254 break;
255
256 default:
257 break;
258 }
259}
260
f62b8bb8
AV		 261static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
262{
263 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
264}
265
266static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
267{
f62b8bb8 268 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
daa21560 269 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 270}
271
facc9699
SM		 272#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
273#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
274
f62b8bb8
AV		 275static int mlx5e_create_rq(struct mlx5e_channel *c,
276 struct mlx5e_rq_param *param,
277 struct mlx5e_rq *rq)
278{
279 struct mlx5e_priv *priv = c->priv;
280 struct mlx5_core_dev *mdev = priv->mdev;
281 void *rqc = param->rqc;
282 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 283 u32 byte_count;
f62b8bb8
AV		 284 int wq_sz;
285 int err;
286 int i;
287
311c7c71
SM		 288 param->wq.db_numa_node = cpu_to_node(c->cpu);
289
f62b8bb8
AV		 290 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
291 &rq->wq_ctrl);
292 if (err)
293 return err;
294
295 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
296
297 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 298
461017cb
TT		 299 switch (priv->params.rq_wq_type) {
300 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
301 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
302 GFP_KERNEL, cpu_to_node(c->cpu));
303 if (!rq->wqe_info) {
304 err = -ENOMEM;
305 goto err_rq_wq_destroy;
306 }
307 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
308 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
309
d9d9f156
TT		 310 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
311 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
312 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
461017cb
TT		 313 byte_count = rq->wqe_sz;
314 break;
315 default: /* MLX5_WQ_TYPE_LINKED_LIST */
316 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
317 cpu_to_node(c->cpu));
318 if (!rq->skb) {
319 err = -ENOMEM;
320 goto err_rq_wq_destroy;
321 }
322 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
323 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
324
325 rq->wqe_sz = (priv->params.lro_en) ?
326 priv->params.lro_wqe_sz :
327 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 328 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
329 byte_count = rq->wqe_sz;
461017cb
TT		 330 byte_count |= MLX5_HW_START_PADDING;
331 }
f62b8bb8
AV		 332
333 for (i = 0; i < wq_sz; i++) {
334 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
335
461017cb 336 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 337 }
338
461017cb 339 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 340 rq->pdev = c->pdev;
341 rq->netdev = c->netdev;
ef9814de 342 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 343 rq->channel = c;
344 rq->ix = c->ix;
50cfa25a 345 rq->priv = c->priv;
bc77b240
TT		 346 rq->mkey_be = c->mkey_be;
347 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 348
349 return 0;
350
351err_rq_wq_destroy:
352 mlx5_wq_destroy(&rq->wq_ctrl);
353
354 return err;
355}
356
357static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
358{
461017cb
TT		 359 switch (rq->wq_type) {
360 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
361 kfree(rq->wqe_info);
362 break;
363 default: /* MLX5_WQ_TYPE_LINKED_LIST */
364 kfree(rq->skb);
365 }
366
f62b8bb8
AV		 367 mlx5_wq_destroy(&rq->wq_ctrl);
368}
369
370static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
371{
50cfa25a 372 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 373 struct mlx5_core_dev *mdev = priv->mdev;
374
375 void *in;
376 void *rqc;
377 void *wq;
378 int inlen;
379 int err;
380
381 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
382 sizeof(u64) * rq->wq_ctrl.buf.npages;
383 in = mlx5_vzalloc(inlen);
384 if (!in)
385 return -ENOMEM;
386
387 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
388 wq = MLX5_ADDR_OF(rqc, rqc, wq);
389
390 memcpy(rqc, param->rqc, sizeof(param->rqc));
391
97de9f31 392 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 393 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
394 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
36350114 395 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 396 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 397 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 398 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
399
400 mlx5_fill_page_array(&rq->wq_ctrl.buf,
401 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
402
7db22ffb 403 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 404
405 kvfree(in);
406
407 return err;
408}
409
36350114
GP		 410static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
411 int next_state)
f62b8bb8
AV		 412{
413 struct mlx5e_channel *c = rq->channel;
414 struct mlx5e_priv *priv = c->priv;
415 struct mlx5_core_dev *mdev = priv->mdev;
416
417 void *in;
418 void *rqc;
419 int inlen;
420 int err;
421
422 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
423 in = mlx5_vzalloc(inlen);
424 if (!in)
425 return -ENOMEM;
426
427 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
428
429 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
430 MLX5_SET(rqc, rqc, state, next_state);
431
7db22ffb 432 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 433
434 kvfree(in);
435
436 return err;
437}
438
36350114
GP		 439static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
440{
441 struct mlx5e_channel *c = rq->channel;
442 struct mlx5e_priv *priv = c->priv;
443 struct mlx5_core_dev *mdev = priv->mdev;
444
445 void *in;
446 void *rqc;
447 int inlen;
448 int err;
449
450 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
451 in = mlx5_vzalloc(inlen);
452 if (!in)
453 return -ENOMEM;
454
455 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
456
457 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
458 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
459 MLX5_SET(rqc, rqc, vsd, vsd);
460 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
461
462 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
463
464 kvfree(in);
465
466 return err;
467}
468
f62b8bb8
AV		 469static void mlx5e_disable_rq(struct mlx5e_rq *rq)
470{
50cfa25a 471 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 472}
473
474static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
475{
01c196a2 476 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 477 struct mlx5e_channel *c = rq->channel;
478 struct mlx5e_priv *priv = c->priv;
479 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 480
01c196a2 481 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 482 if (wq->cur_sz >= priv->params.min_rx_wqes)
483 return 0;
484
485 msleep(20);
486 }
487
488 return -ETIMEDOUT;
489}
490
491static int mlx5e_open_rq(struct mlx5e_channel *c,
492 struct mlx5e_rq_param *param,
493 struct mlx5e_rq *rq)
494{
d3c9bc27
TT		 495 struct mlx5e_sq *sq = &c->icosq;
496 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 497 int err;
498
499 err = mlx5e_create_rq(c, param, rq);
500 if (err)
501 return err;
502
503 err = mlx5e_enable_rq(rq, param);
504 if (err)
505 goto err_destroy_rq;
506
36350114 507 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 508 if (err)
509 goto err_disable_rq;
510
511 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 512
513 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
514 sq->ico_wqe_info[pi].num_wqebbs = 1;
515 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 516
517 return 0;
518
519err_disable_rq:
520 mlx5e_disable_rq(rq);
521err_destroy_rq:
522 mlx5e_destroy_rq(rq);
523
524 return err;
525}
526
527static void mlx5e_close_rq(struct mlx5e_rq *rq)
528{
529 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
530 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
531
36350114 532 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
f62b8bb8
AV		 533 while (!mlx5_wq_ll_is_empty(&rq->wq))
534 msleep(20);
535
536 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
537 napi_synchronize(&rq->channel->napi);
538
539 mlx5e_disable_rq(rq);
540 mlx5e_destroy_rq(rq);
541}
542
543static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
544{
34802a42 545 kfree(sq->wqe_info);
f62b8bb8
AV		 546 kfree(sq->dma_fifo);
547 kfree(sq->skb);
548}
549
550static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
551{
552 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
553 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
554
555 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
556 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
557 numa);
34802a42
AS		 558 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
559 numa);
f62b8bb8 560
34802a42 561 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 562 mlx5e_free_sq_db(sq);
563 return -ENOMEM;
564 }
565
566 sq->dma_fifo_mask = df_sz - 1;
567
568 return 0;
569}
570
571static int mlx5e_create_sq(struct mlx5e_channel *c,
572 int tc,
573 struct mlx5e_sq_param *param,
574 struct mlx5e_sq *sq)
575{
576 struct mlx5e_priv *priv = c->priv;
577 struct mlx5_core_dev *mdev = priv->mdev;
578
579 void *sqc = param->sqc;
580 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
581 int err;
582
0ba42241 583 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
f62b8bb8
AV		 584 if (err)
585 return err;
586
311c7c71
SM		 587 param->wq.db_numa_node = cpu_to_node(c->cpu);
588
f62b8bb8
AV		 589 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
590 &sq->wq_ctrl);
591 if (err)
592 goto err_unmap_free_uar;
593
594 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 595 if (sq->uar.bf_map) {
596 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
597 sq->uar_map = sq->uar.bf_map;
598 } else {
599 sq->uar_map = sq->uar.map;
600 }
f62b8bb8 601 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 602 sq->max_inline = param->max_inline;
f62b8bb8 603
7ec0bb22
DC		 604 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
605 if (err)
f62b8bb8
AV		 606 goto err_sq_wq_destroy;
607
d3c9bc27
TT		 608 if (param->icosq) {
609 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
610
611 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
612 wq_sz,
613 GFP_KERNEL,
614 cpu_to_node(c->cpu));
615 if (!sq->ico_wqe_info) {
616 err = -ENOMEM;
617 goto err_free_sq_db;
618 }
619 } else {
620 int txq_ix;
621
622 txq_ix = c->ix + tc * priv->params.num_channels;
623 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
624 priv->txq_to_sq_map[txq_ix] = sq;
625 }
f62b8bb8 626
88a85f99 627 sq->pdev = c->pdev;
ef9814de 628 sq->tstamp = &priv->tstamp;
88a85f99
AS		 629 sq->mkey_be = c->mkey_be;
630 sq->channel = c;
631 sq->tc = tc;
632 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
633 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 634
635 return 0;
636
d3c9bc27
TT		 637err_free_sq_db:
638 mlx5e_free_sq_db(sq);
639
f62b8bb8
AV		 640err_sq_wq_destroy:
641 mlx5_wq_destroy(&sq->wq_ctrl);
642
643err_unmap_free_uar:
644 mlx5_unmap_free_uar(mdev, &sq->uar);
645
646 return err;
647}
648
649static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
650{
651 struct mlx5e_channel *c = sq->channel;
652 struct mlx5e_priv *priv = c->priv;
653
d3c9bc27 654 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 655 mlx5e_free_sq_db(sq);
656 mlx5_wq_destroy(&sq->wq_ctrl);
657 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
658}
659
660static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
661{
662 struct mlx5e_channel *c = sq->channel;
663 struct mlx5e_priv *priv = c->priv;
664 struct mlx5_core_dev *mdev = priv->mdev;
665
666 void *in;
667 void *sqc;
668 void *wq;
669 int inlen;
670 int err;
671
672 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
673 sizeof(u64) * sq->wq_ctrl.buf.npages;
674 in = mlx5_vzalloc(inlen);
675 if (!in)
676 return -ENOMEM;
677
678 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
679 wq = MLX5_ADDR_OF(sqc, sqc, wq);
680
681 memcpy(sqc, param->sqc, sizeof(param->sqc));
682
d3c9bc27
TT		 683 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
684 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
f62b8bb8 685 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 686 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 687 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
688
689 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
690 MLX5_SET(wq, wq, uar_page, sq->uar.index);
691 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 692 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 693 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
694
695 mlx5_fill_page_array(&sq->wq_ctrl.buf,
696 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
697
7db22ffb 698 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 699
700 kvfree(in);
701
702 return err;
703}
704
507f0c81
YP		 705static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
706 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 707{
708 struct mlx5e_channel *c = sq->channel;
709 struct mlx5e_priv *priv = c->priv;
710 struct mlx5_core_dev *mdev = priv->mdev;
711
712 void *in;
713 void *sqc;
714 int inlen;
715 int err;
716
717 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
718 in = mlx5_vzalloc(inlen);
719 if (!in)
720 return -ENOMEM;
721
722 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
723
724 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
725 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 726 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
727 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
728 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
729 }
f62b8bb8 730
7db22ffb 731 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 732
733 kvfree(in);
734
735 return err;
736}
737
738static void mlx5e_disable_sq(struct mlx5e_sq *sq)
739{
740 struct mlx5e_channel *c = sq->channel;
741 struct mlx5e_priv *priv = c->priv;
742 struct mlx5_core_dev *mdev = priv->mdev;
743
7db22ffb 744 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 745 if (sq->rate_limit)
746 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 747}
748
749static int mlx5e_open_sq(struct mlx5e_channel *c,
750 int tc,
751 struct mlx5e_sq_param *param,
752 struct mlx5e_sq *sq)
753{
754 int err;
755
756 err = mlx5e_create_sq(c, tc, param, sq);
757 if (err)
758 return err;
759
760 err = mlx5e_enable_sq(sq, param);
761 if (err)
762 goto err_destroy_sq;
763
507f0c81
YP		 764 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
765 false, 0);
f62b8bb8
AV		 766 if (err)
767 goto err_disable_sq;
768
d3c9bc27
TT		 769 if (sq->txq) {
770 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
771 netdev_tx_reset_queue(sq->txq);
772 netif_tx_start_queue(sq->txq);
773 }
f62b8bb8
AV		 774
775 return 0;
776
777err_disable_sq:
778 mlx5e_disable_sq(sq);
779err_destroy_sq:
780 mlx5e_destroy_sq(sq);
781
782 return err;
783}
784
785static inline void netif_tx_disable_queue(struct netdev_queue *txq)
786{
787 __netif_tx_lock_bh(txq);
788 netif_tx_stop_queue(txq);
789 __netif_tx_unlock_bh(txq);
790}
791
792static void mlx5e_close_sq(struct mlx5e_sq *sq)
793{
d3c9bc27
TT		 794 if (sq->txq) {
795 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
796 /* prevent netif_tx_wake_queue */
797 napi_synchronize(&sq->channel->napi);
798 netif_tx_disable_queue(sq->txq);
f62b8bb8 799
d3c9bc27
TT		 800 /* ensure hw is notified of all pending wqes */
801 if (mlx5e_sq_has_room_for(sq, 1))
802 mlx5e_send_nop(sq, true);
803
507f0c81
YP		 804 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR,
805 false, 0);
d3c9bc27 806 }
f62b8bb8 807
f62b8bb8
AV		 808 while (sq->cc != sq->pc) /* wait till sq is empty */
809 msleep(20);
810
811 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
812 napi_synchronize(&sq->channel->napi);
813
814 mlx5e_disable_sq(sq);
815 mlx5e_destroy_sq(sq);
816}
817
818static int mlx5e_create_cq(struct mlx5e_channel *c,
819 struct mlx5e_cq_param *param,
820 struct mlx5e_cq *cq)
821{
822 struct mlx5e_priv *priv = c->priv;
823 struct mlx5_core_dev *mdev = priv->mdev;
824 struct mlx5_core_cq *mcq = &cq->mcq;
825 int eqn_not_used;
0b6e26ce 826 unsigned int irqn;
f62b8bb8
AV		 827 int err;
828 u32 i;
829
311c7c71
SM		 830 param->wq.buf_numa_node = cpu_to_node(c->cpu);
831 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 832 param->eq_ix = c->ix;
833
834 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
835 &cq->wq_ctrl);
836 if (err)
837 return err;
838
839 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
840
841 cq->napi = &c->napi;
842
843 mcq->cqe_sz = 64;
844 mcq->set_ci_db = cq->wq_ctrl.db.db;
845 mcq->arm_db = cq->wq_ctrl.db.db + 1;
846 *mcq->set_ci_db = 0;
847 *mcq->arm_db = 0;
848 mcq->vector = param->eq_ix;
849 mcq->comp = mlx5e_completion_event;
850 mcq->event = mlx5e_cq_error_event;
851 mcq->irqn = irqn;
852 mcq->uar = &priv->cq_uar;
853
854 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
855 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
856
857 cqe->op_own = 0xf1;
858 }
859
860 cq->channel = c;
50cfa25a 861 cq->priv = priv;
f62b8bb8
AV		 862
863 return 0;
864}
865
866static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
867{
868 mlx5_wq_destroy(&cq->wq_ctrl);
869}
870
871static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
872{
50cfa25a 873 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 874 struct mlx5_core_dev *mdev = priv->mdev;
875 struct mlx5_core_cq *mcq = &cq->mcq;
876
877 void *in;
878 void *cqc;
879 int inlen;
0b6e26ce 880 unsigned int irqn_not_used;
f62b8bb8
AV		 881 int eqn;
882 int err;
883
884 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
885 sizeof(u64) * cq->wq_ctrl.buf.npages;
886 in = mlx5_vzalloc(inlen);
887 if (!in)
888 return -ENOMEM;
889
890 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
891
892 memcpy(cqc, param->cqc, sizeof(param->cqc));
893
894 mlx5_fill_page_array(&cq->wq_ctrl.buf,
895 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
896
897 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
898
899 MLX5_SET(cqc, cqc, c_eqn, eqn);
900 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
901 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 902 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 903 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
904
905 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
906
907 kvfree(in);
908
909 if (err)
910 return err;
911
912 mlx5e_cq_arm(cq);
913
914 return 0;
915}
916
917static void mlx5e_disable_cq(struct mlx5e_cq *cq)
918{
50cfa25a 919 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 920 struct mlx5_core_dev *mdev = priv->mdev;
921
922 mlx5_core_destroy_cq(mdev, &cq->mcq);
923}
924
925static int mlx5e_open_cq(struct mlx5e_channel *c,
926 struct mlx5e_cq_param *param,
927 struct mlx5e_cq *cq,
928 u16 moderation_usecs,
929 u16 moderation_frames)
930{
931 int err;
932 struct mlx5e_priv *priv = c->priv;
933 struct mlx5_core_dev *mdev = priv->mdev;
934
935 err = mlx5e_create_cq(c, param, cq);
936 if (err)
937 return err;
938
939 err = mlx5e_enable_cq(cq, param);
940 if (err)
941 goto err_destroy_cq;
942
7524a5d8
GP		 943 if (MLX5_CAP_GEN(mdev, cq_moderation))
944 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
945 moderation_usecs,
946 moderation_frames);
f62b8bb8
AV		 947 return 0;
948
949err_destroy_cq:
950 mlx5e_destroy_cq(cq);
951
952 return err;
953}
954
955static void mlx5e_close_cq(struct mlx5e_cq *cq)
956{
957 mlx5e_disable_cq(cq);
958 mlx5e_destroy_cq(cq);
959}
960
961static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
962{
963 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
964}
965
966static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
967 struct mlx5e_channel_param *cparam)
968{
969 struct mlx5e_priv *priv = c->priv;
970 int err;
971 int tc;
972
973 for (tc = 0; tc < c->num_tc; tc++) {
974 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
975 priv->params.tx_cq_moderation_usec,
976 priv->params.tx_cq_moderation_pkts);
977 if (err)
978 goto err_close_tx_cqs;
f62b8bb8
AV		 979 }
980
981 return 0;
982
983err_close_tx_cqs:
984 for (tc--; tc >= 0; tc--)
985 mlx5e_close_cq(&c->sq[tc].cq);
986
987 return err;
988}
989
990static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
991{
992 int tc;
993
994 for (tc = 0; tc < c->num_tc; tc++)
995 mlx5e_close_cq(&c->sq[tc].cq);
996}
997
998static int mlx5e_open_sqs(struct mlx5e_channel *c,
999 struct mlx5e_channel_param *cparam)
1000{
1001 int err;
1002 int tc;
1003
1004 for (tc = 0; tc < c->num_tc; tc++) {
1005 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1006 if (err)
1007 goto err_close_sqs;
1008 }
1009
1010 return 0;
1011
1012err_close_sqs:
1013 for (tc--; tc >= 0; tc--)
1014 mlx5e_close_sq(&c->sq[tc]);
1015
1016 return err;
1017}
1018
1019static void mlx5e_close_sqs(struct mlx5e_channel *c)
1020{
1021 int tc;
1022
1023 for (tc = 0; tc < c->num_tc; tc++)
1024 mlx5e_close_sq(&c->sq[tc]);
1025}
1026
5283af89 1027static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1028{
1029 int i;
1030
1031 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 1032 priv->channeltc_to_txq_map[ix][i] =
1033 ix + i * priv->params.num_channels;
03289b88
SM		 1034}
1035
507f0c81
YP		 1036static int mlx5e_set_sq_maxrate(struct net_device *dev,
1037 struct mlx5e_sq *sq, u32 rate)
1038{
1039 struct mlx5e_priv *priv = netdev_priv(dev);
1040 struct mlx5_core_dev *mdev = priv->mdev;
1041 u16 rl_index = 0;
1042 int err;
1043
1044 if (rate == sq->rate_limit)
1045 /* nothing to do */
1046 return 0;
1047
1048 if (sq->rate_limit)
1049 /* remove current rl index to free space to next ones */
1050 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1051
1052 sq->rate_limit = 0;
1053
1054 if (rate) {
1055 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1056 if (err) {
1057 netdev_err(dev, "Failed configuring rate %u: %d\n",
1058 rate, err);
1059 return err;
1060 }
1061 }
1062
1063 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1064 MLX5_SQC_STATE_RDY, true, rl_index);
1065 if (err) {
1066 netdev_err(dev, "Failed configuring rate %u: %d\n",
1067 rate, err);
1068 /* remove the rate from the table */
1069 if (rate)
1070 mlx5_rl_remove_rate(mdev, rate);
1071 return err;
1072 }
1073
1074 sq->rate_limit = rate;
1075 return 0;
1076}
1077
1078static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1079{
1080 struct mlx5e_priv *priv = netdev_priv(dev);
1081 struct mlx5_core_dev *mdev = priv->mdev;
1082 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1083 int err = 0;
1084
1085 if (!mlx5_rl_is_supported(mdev)) {
1086 netdev_err(dev, "Rate limiting is not supported on this device\n");
1087 return -EINVAL;
1088 }
1089
1090 /* rate is given in Mb/sec, HW config is in Kb/sec */
1091 rate = rate << 10;
1092
1093 /* Check whether rate in valid range, 0 is always valid */
1094 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1095 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1096 return -ERANGE;
1097 }
1098
1099 mutex_lock(&priv->state_lock);
1100 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1101 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1102 if (!err)
1103 priv->tx_rates[index] = rate;
1104 mutex_unlock(&priv->state_lock);
1105
1106 return err;
1107}
1108
f62b8bb8
AV		 1109static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1110 struct mlx5e_channel_param *cparam,
1111 struct mlx5e_channel **cp)
1112{
1113 struct net_device *netdev = priv->netdev;
1114 int cpu = mlx5e_get_cpu(priv, ix);
1115 struct mlx5e_channel *c;
507f0c81 1116 struct mlx5e_sq *sq;
f62b8bb8 1117 int err;
507f0c81 1118 int i;
f62b8bb8
AV		 1119
1120 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1121 if (!c)
1122 return -ENOMEM;
1123
1124 c->priv = priv;
1125 c->ix = ix;
1126 c->cpu = cpu;
1127 c->pdev = &priv->mdev->pdev->dev;
1128 c->netdev = priv->netdev;
a606b0f6 1129 c->mkey_be = cpu_to_be32(priv->mkey.key);
a4418a6c 1130 c->num_tc = priv->params.num_tc;
f62b8bb8 1131
5283af89 1132 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1133
f62b8bb8
AV		 1134 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1135
d3c9bc27 1136 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
f62b8bb8
AV		 1137 if (err)
1138 goto err_napi_del;
1139
d3c9bc27
TT		 1140 err = mlx5e_open_tx_cqs(c, cparam);
1141 if (err)
1142 goto err_close_icosq_cq;
1143
f62b8bb8
AV		 1144 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1145 priv->params.rx_cq_moderation_usec,
1146 priv->params.rx_cq_moderation_pkts);
1147 if (err)
1148 goto err_close_tx_cqs;
f62b8bb8
AV		 1149
1150 napi_enable(&c->napi);
1151
d3c9bc27 1152 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1153 if (err)
1154 goto err_disable_napi;
1155
d3c9bc27
TT		 1156 err = mlx5e_open_sqs(c, cparam);
1157 if (err)
1158 goto err_close_icosq;
1159
507f0c81
YP		 1160 for (i = 0; i < priv->params.num_tc; i++) {
1161 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1162
1163 if (priv->tx_rates[txq_ix]) {
1164 sq = priv->txq_to_sq_map[txq_ix];
1165 mlx5e_set_sq_maxrate(priv->netdev, sq,
1166 priv->tx_rates[txq_ix]);
1167 }
1168 }
1169
f62b8bb8
AV		 1170 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1171 if (err)
1172 goto err_close_sqs;
1173
1174 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1175 *cp = c;
1176
1177 return 0;
1178
1179err_close_sqs:
1180 mlx5e_close_sqs(c);
1181
d3c9bc27
TT		 1182err_close_icosq:
1183 mlx5e_close_sq(&c->icosq);
1184
f62b8bb8
AV		 1185err_disable_napi:
1186 napi_disable(&c->napi);
1187 mlx5e_close_cq(&c->rq.cq);
1188
1189err_close_tx_cqs:
1190 mlx5e_close_tx_cqs(c);
1191
d3c9bc27
TT		 1192err_close_icosq_cq:
1193 mlx5e_close_cq(&c->icosq.cq);
1194
f62b8bb8
AV		 1195err_napi_del:
1196 netif_napi_del(&c->napi);
7ae92ae5 1197 napi_hash_del(&c->napi);
f62b8bb8
AV		 1198 kfree(c);
1199
1200 return err;
1201}
1202
1203static void mlx5e_close_channel(struct mlx5e_channel *c)
1204{
1205 mlx5e_close_rq(&c->rq);
1206 mlx5e_close_sqs(c);
d3c9bc27 1207 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1208 napi_disable(&c->napi);
1209 mlx5e_close_cq(&c->rq.cq);
1210 mlx5e_close_tx_cqs(c);
d3c9bc27 1211 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1212 netif_napi_del(&c->napi);
7ae92ae5
ED		 1213
1214 napi_hash_del(&c->napi);
1215 synchronize_rcu();
1216
f62b8bb8
AV		 1217 kfree(c);
1218}
1219
1220static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1221 struct mlx5e_rq_param *param)
1222{
1223 void *rqc = param->rqc;
1224 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1225
461017cb
TT		 1226 switch (priv->params.rq_wq_type) {
1227 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1228 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1229 priv->params.mpwqe_log_num_strides - 9);
461017cb 1230 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1231 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1232 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1233 break;
1234 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1235 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1236 }
1237
f62b8bb8
AV		 1238 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1239 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1240 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1241 MLX5_SET(wq, wq, pd, priv->pdn);
593cf338 1242 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1243
311c7c71 1244 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1245 param->wq.linear = 1;
1246}
1247
556dd1b9
TT		 1248static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1249{
1250 void *rqc = param->rqc;
1251 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1252
1253 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1254 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1255}
1256
d3c9bc27
TT		 1257static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1258 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1259{
1260 void *sqc = param->sqc;
1261 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1262
f62b8bb8
AV		 1263 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1264 MLX5_SET(wq, wq, pd, priv->pdn);
1265
311c7c71 1266 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1267}
1268
1269static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1270 struct mlx5e_sq_param *param)
1271{
1272 void *sqc = param->sqc;
1273 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1274
1275 mlx5e_build_sq_param_common(priv, param);
1276 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1277
58d52291 1278 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1279}
1280
1281static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1282 struct mlx5e_cq_param *param)
1283{
1284 void *cqc = param->cqc;
1285
1286 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1287}
1288
1289static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1290 struct mlx5e_cq_param *param)
1291{
1292 void *cqc = param->cqc;
461017cb 1293 u8 log_cq_size;
f62b8bb8 1294
461017cb
TT		 1295 switch (priv->params.rq_wq_type) {
1296 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1297 log_cq_size = priv->params.log_rq_size +
d9d9f156 1298 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1299 break;
1300 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1301 log_cq_size = priv->params.log_rq_size;
1302 }
1303
1304 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1305 if (priv->params.rx_cqe_compress) {
1306 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1307 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1308 }
f62b8bb8
AV		 1309
1310 mlx5e_build_common_cq_param(priv, param);
1311}
1312
1313static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1314 struct mlx5e_cq_param *param)
1315{
1316 void *cqc = param->cqc;
1317
d3c9bc27 1318 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1319
1320 mlx5e_build_common_cq_param(priv, param);
1321}
1322
d3c9bc27
TT		 1323static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1324 struct mlx5e_cq_param *param,
1325 u8 log_wq_size)
1326{
1327 void *cqc = param->cqc;
1328
1329 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1330
1331 mlx5e_build_common_cq_param(priv, param);
1332}
1333
1334static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1335 struct mlx5e_sq_param *param,
1336 u8 log_wq_size)
1337{
1338 void *sqc = param->sqc;
1339 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1340
1341 mlx5e_build_sq_param_common(priv, param);
1342
1343 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1344 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1345
1346 param->icosq = true;
1347}
1348
6b87663f 1349static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1350{
bc77b240 1351 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1352
f62b8bb8
AV		 1353 mlx5e_build_rq_param(priv, &cparam->rq);
1354 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1355 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1356 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1357 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1358 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1359}
1360
1361static int mlx5e_open_channels(struct mlx5e_priv *priv)
1362{
6b87663f 1363 struct mlx5e_channel_param *cparam;
a4418a6c 1364 int nch = priv->params.num_channels;
03289b88 1365 int err = -ENOMEM;
f62b8bb8
AV		 1366 int i;
1367 int j;
1368
a4418a6c
AS		 1369 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1370 GFP_KERNEL);
03289b88 1371
a4418a6c 1372 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1373 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1374
6b87663f
AB		 1375 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1376
1377 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1378 goto err_free_txq_to_sq_map;
f62b8bb8 1379
6b87663f
AB		 1380 mlx5e_build_channel_param(priv, cparam);
1381
a4418a6c 1382 for (i = 0; i < nch; i++) {
6b87663f 1383 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1384 if (err)
1385 goto err_close_channels;
1386 }
1387
a4418a6c 1388 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1389 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1390 if (err)
1391 goto err_close_channels;
1392 }
1393
6b87663f 1394 kfree(cparam);
f62b8bb8
AV		 1395 return 0;
1396
1397err_close_channels:
1398 for (i--; i >= 0; i--)
1399 mlx5e_close_channel(priv->channel[i]);
1400
03289b88
SM		 1401err_free_txq_to_sq_map:
1402 kfree(priv->txq_to_sq_map);
f62b8bb8 1403 kfree(priv->channel);
6b87663f 1404 kfree(cparam);
f62b8bb8
AV		 1405
1406 return err;
1407}
1408
1409static void mlx5e_close_channels(struct mlx5e_priv *priv)
1410{
1411 int i;
1412
1413 for (i = 0; i < priv->params.num_channels; i++)
1414 mlx5e_close_channel(priv->channel[i]);
1415
03289b88 1416 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1417 kfree(priv->channel);
1418}
1419
2be6967c
SM		 1420static int mlx5e_rx_hash_fn(int hfunc)
1421{
1422 return (hfunc == ETH_RSS_HASH_TOP) ?
1423 MLX5_RX_HASH_FN_TOEPLITZ :
1424 MLX5_RX_HASH_FN_INVERTED_XOR8;
1425}
1426
1427static int mlx5e_bits_invert(unsigned long a, int size)
1428{
1429 int inv = 0;
1430 int i;
1431
1432 for (i = 0; i < size; i++)
1433 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1434
1435 return inv;
1436}
1437
936896e9
AS		 1438static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1439{
1440 int i;
1441
1442 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1443 int ix = i;
1da36696 1444 u32 rqn;
936896e9
AS		 1445
1446 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1447 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1448
2d75b2bc 1449 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1450 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1451 priv->channel[ix]->rq.rqn :
1452 priv->drop_rq.rqn;
1453 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1454 }
1455}
1456
1da36696
TT		 1457static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1458 int ix)
4cbeaff5 1459{
1da36696
TT		 1460 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1461 priv->channel[ix]->rq.rqn :
1462 priv->drop_rq.rqn;
4cbeaff5 1463
1da36696 1464 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1465}
1466
1da36696 1467static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
f62b8bb8
AV		 1468{
1469 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1470 void *rqtc;
1471 int inlen;
1472 int err;
1da36696 1473 u32 *in;
f62b8bb8 1474
f62b8bb8
AV		 1475 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1476 in = mlx5_vzalloc(inlen);
1477 if (!in)
1478 return -ENOMEM;
1479
1480 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1481
1482 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1483 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1484
1da36696
TT		 1485 if (sz > 1) /* RSS */
1486 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1487 else
1488 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1489
1da36696 1490 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
f62b8bb8
AV		 1491
1492 kvfree(in);
1da36696
TT		 1493 return err;
1494}
1495
1496static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1497{
1498 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1499}
1500
1501static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1502{
1503 int nch = mlx5e_get_max_num_channels(priv->mdev);
1504 u32 *rqtn;
1505 int err;
1506 int ix;
1507
1508 /* Indirect RQT */
1509 rqtn = &priv->indir_rqtn;
1510 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1511 if (err)
1512 return err;
1513
1514 /* Direct RQTs */
1515 for (ix = 0; ix < nch; ix++) {
1516 rqtn = &priv->direct_tir[ix].rqtn;
1517 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1518 if (err)
1519 goto err_destroy_rqts;
1520 }
1521
1522 return 0;
1523
1524err_destroy_rqts:
1525 for (ix--; ix >= 0; ix--)
1526 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1527
1528 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
f62b8bb8
AV		 1529
1530 return err;
1531}
1532
1da36696
TT		 1533static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1534{
1535 int nch = mlx5e_get_max_num_channels(priv->mdev);
1536 int i;
1537
1538 for (i = 0; i < nch; i++)
1539 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1540
1541 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1542}
1543
1544int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1545{
1546 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1547 void *rqtc;
1548 int inlen;
1da36696 1549 u32 *in;
5c50368f
AS		 1550 int err;
1551
5c50368f
AS		 1552 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1553 in = mlx5_vzalloc(inlen);
1554 if (!in)
1555 return -ENOMEM;
1556
1557 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1558
1559 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1560 if (sz > 1) /* RSS */
1561 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1562 else
1563 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1564
1565 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1566
1da36696 1567 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1568
1569 kvfree(in);
1570
1571 return err;
1572}
1573
40ab6a6e
AS		 1574static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1575{
1da36696
TT		 1576 u32 rqtn;
1577 int ix;
1578
1579 rqtn = priv->indir_rqtn;
1580 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1581 for (ix = 0; ix < priv->params.num_channels; ix++) {
1582 rqtn = priv->direct_tir[ix].rqtn;
1583 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1584 }
40ab6a6e
AS		 1585}
1586
5c50368f
AS		 1587static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1588{
1589 if (!priv->params.lro_en)
1590 return;
1591
1592#define ROUGH_MAX_L2_L3_HDR_SZ 256
1593
1594 MLX5_SET(tirc, tirc, lro_enable_mask,
1595 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1596 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1597 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1598 (priv->params.lro_wqe_sz -
1599 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1600 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1601 MLX5_CAP_ETH(priv->mdev,
d9a40271 1602 lro_timer_supported_periods[2]));
5c50368f
AS		 1603}
1604
bdfc028d
TT		 1605void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1606{
1607 MLX5_SET(tirc, tirc, rx_hash_fn,
1608 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1609 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1610 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1611 rx_hash_toeplitz_key);
1612 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1613 rx_hash_toeplitz_key);
1614
1615 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1616 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1617 }
1618}
1619
ab0394fe 1620static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1621{
1622 struct mlx5_core_dev *mdev = priv->mdev;
1623
1624 void *in;
1625 void *tirc;
1626 int inlen;
1627 int err;
ab0394fe 1628 int tt;
1da36696 1629 int ix;
5c50368f
AS		 1630
1631 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1632 in = mlx5_vzalloc(inlen);
1633 if (!in)
1634 return -ENOMEM;
1635
1636 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1637 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1638
1639 mlx5e_build_tir_ctx_lro(tirc, priv);
1640
1da36696
TT		 1641 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1642 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1643 inlen);
ab0394fe 1644 if (err)
1da36696 1645 goto free_in;
ab0394fe 1646 }
5c50368f 1647
1da36696
TT		 1648 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1649 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1650 in, inlen);
1651 if (err)
1652 goto free_in;
1653 }
1654
1655free_in:
5c50368f
AS		 1656 kvfree(in);
1657
1658 return err;
1659}
1660
1da36696 1661static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
66189961
TT		 1662{
1663 void *in;
1664 int inlen;
1665 int err;
1da36696 1666 int i;
66189961
TT		 1667
1668 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1669 in = mlx5_vzalloc(inlen);
1670 if (!in)
1671 return -ENOMEM;
1672
1673 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1674
1da36696
TT		 1675 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1676 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1677 inlen);
1678 if (err)
1679 return err;
1680 }
66189961 1681
1da36696
TT		 1682 for (i = 0; i < priv->params.num_channels; i++) {
1683 err = mlx5_core_modify_tir(priv->mdev,
1684 priv->direct_tir[i].tirn, in,
1685 inlen);
66189961
TT		 1686 if (err)
1687 return err;
1688 }
1689
1da36696
TT		 1690 kvfree(in);
1691
66189961
TT		 1692 return 0;
1693}
1694
cd255eff 1695static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1696{
40ab6a6e 1697 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1698 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1699 int err;
1700
cd255eff 1701 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1702 if (err)
1703 return err;
1704
cd255eff
SM		 1705 /* Update vport context MTU */
1706 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1707 return 0;
1708}
40ab6a6e 1709
cd255eff
SM		 1710static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1711{
1712 struct mlx5_core_dev *mdev = priv->mdev;
1713 u16 hw_mtu = 0;
1714 int err;
40ab6a6e 1715
cd255eff
SM		 1716 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1717 if (err || !hw_mtu) /* fallback to port oper mtu */
1718 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1719
1720 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1721}
1722
1723static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1724{
1725 struct mlx5e_priv *priv = netdev_priv(netdev);
1726 u16 mtu;
1727 int err;
1728
1729 err = mlx5e_set_mtu(priv, netdev->mtu);
1730 if (err)
1731 return err;
40ab6a6e 1732
cd255eff
SM		 1733 mlx5e_query_mtu(priv, &mtu);
1734 if (mtu != netdev->mtu)
1735 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1736 __func__, mtu, netdev->mtu);
40ab6a6e 1737
cd255eff 1738 netdev->mtu = mtu;
40ab6a6e
AS		 1739 return 0;
1740}
1741
08fb1dac
SM		 1742static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1743{
1744 struct mlx5e_priv *priv = netdev_priv(netdev);
1745 int nch = priv->params.num_channels;
1746 int ntc = priv->params.num_tc;
1747 int tc;
1748
1749 netdev_reset_tc(netdev);
1750
1751 if (ntc == 1)
1752 return;
1753
1754 netdev_set_num_tc(netdev, ntc);
1755
1756 for (tc = 0; tc < ntc; tc++)
1757 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1758}
1759
40ab6a6e
AS		 1760int mlx5e_open_locked(struct net_device *netdev)
1761{
1762 struct mlx5e_priv *priv = netdev_priv(netdev);
1763 int num_txqs;
1764 int err;
1765
1766 set_bit(MLX5E_STATE_OPENED, &priv->state);
1767
08fb1dac
SM		 1768 mlx5e_netdev_set_tcs(netdev);
1769
40ab6a6e
AS		 1770 num_txqs = priv->params.num_channels * priv->params.num_tc;
1771 netif_set_real_num_tx_queues(netdev, num_txqs);
1772 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1773
1774 err = mlx5e_set_dev_port_mtu(netdev);
1775 if (err)
343b29f3 1776 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1777
1778 err = mlx5e_open_channels(priv);
1779 if (err) {
1780 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1781 __func__, err);
343b29f3 1782 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1783 }
1784
66189961
TT		 1785 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1786 if (err) {
1787 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1788 __func__, err);
1789 goto err_close_channels;
1790 }
1791
40ab6a6e 1792 mlx5e_redirect_rqts(priv);
ce89ef36 1793 mlx5e_update_carrier(priv);
ef9814de 1794 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 1795#ifdef CONFIG_RFS_ACCEL
1796 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1797#endif
40ab6a6e 1798
7bb29755 1799 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 1800
9b37b07f 1801 return 0;
343b29f3 1802
66189961
TT		 1803err_close_channels:
1804 mlx5e_close_channels(priv);
343b29f3
AS		 1805err_clear_state_opened_flag:
1806 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1807 return err;
40ab6a6e
AS		 1808}
1809
1810static int mlx5e_open(struct net_device *netdev)
1811{
1812 struct mlx5e_priv *priv = netdev_priv(netdev);
1813 int err;
1814
1815 mutex_lock(&priv->state_lock);
1816 err = mlx5e_open_locked(netdev);
1817 mutex_unlock(&priv->state_lock);
1818
1819 return err;
1820}
1821
1822int mlx5e_close_locked(struct net_device *netdev)
1823{
1824 struct mlx5e_priv *priv = netdev_priv(netdev);
1825
a1985740
AS		 1826 /* May already be CLOSED in case a previous configuration operation
1827 * (e.g RX/TX queue size change) that involves close&open failed.
1828 */
1829 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1830 return 0;
1831
40ab6a6e
AS		 1832 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1833
ef9814de 1834 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1835 netif_carrier_off(priv->netdev);
ce89ef36 1836 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1837 mlx5e_close_channels(priv);
1838
1839 return 0;
1840}
1841
1842static int mlx5e_close(struct net_device *netdev)
1843{
1844 struct mlx5e_priv *priv = netdev_priv(netdev);
1845 int err;
1846
1847 mutex_lock(&priv->state_lock);
1848 err = mlx5e_close_locked(netdev);
1849 mutex_unlock(&priv->state_lock);
1850
1851 return err;
1852}
1853
1854static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1855 struct mlx5e_rq *rq,
1856 struct mlx5e_rq_param *param)
1857{
1858 struct mlx5_core_dev *mdev = priv->mdev;
1859 void *rqc = param->rqc;
1860 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1861 int err;
1862
1863 param->wq.db_numa_node = param->wq.buf_numa_node;
1864
1865 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1866 &rq->wq_ctrl);
1867 if (err)
1868 return err;
1869
1870 rq->priv = priv;
1871
1872 return 0;
1873}
1874
1875static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1876 struct mlx5e_cq *cq,
1877 struct mlx5e_cq_param *param)
1878{
1879 struct mlx5_core_dev *mdev = priv->mdev;
1880 struct mlx5_core_cq *mcq = &cq->mcq;
1881 int eqn_not_used;
0b6e26ce 1882 unsigned int irqn;
40ab6a6e
AS		 1883 int err;
1884
1885 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1886 &cq->wq_ctrl);
1887 if (err)
1888 return err;
1889
1890 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1891
1892 mcq->cqe_sz = 64;
1893 mcq->set_ci_db = cq->wq_ctrl.db.db;
1894 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1895 *mcq->set_ci_db = 0;
1896 *mcq->arm_db = 0;
1897 mcq->vector = param->eq_ix;
1898 mcq->comp = mlx5e_completion_event;
1899 mcq->event = mlx5e_cq_error_event;
1900 mcq->irqn = irqn;
1901 mcq->uar = &priv->cq_uar;
1902
1903 cq->priv = priv;
1904
1905 return 0;
1906}
1907
1908static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1909{
1910 struct mlx5e_cq_param cq_param;
1911 struct mlx5e_rq_param rq_param;
1912 struct mlx5e_rq *rq = &priv->drop_rq;
1913 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1914 int err;
1915
1916 memset(&cq_param, 0, sizeof(cq_param));
1917 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1918 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1919
1920 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1921 if (err)
1922 return err;
1923
1924 err = mlx5e_enable_cq(cq, &cq_param);
1925 if (err)
1926 goto err_destroy_cq;
1927
1928 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1929 if (err)
1930 goto err_disable_cq;
1931
1932 err = mlx5e_enable_rq(rq, &rq_param);
1933 if (err)
1934 goto err_destroy_rq;
1935
1936 return 0;
1937
1938err_destroy_rq:
1939 mlx5e_destroy_rq(&priv->drop_rq);
1940
1941err_disable_cq:
1942 mlx5e_disable_cq(&priv->drop_rq.cq);
1943
1944err_destroy_cq:
1945 mlx5e_destroy_cq(&priv->drop_rq.cq);
1946
1947 return err;
1948}
1949
1950static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1951{
1952 mlx5e_disable_rq(&priv->drop_rq);
1953 mlx5e_destroy_rq(&priv->drop_rq);
1954 mlx5e_disable_cq(&priv->drop_rq.cq);
1955 mlx5e_destroy_cq(&priv->drop_rq.cq);
1956}
1957
1958static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1959{
1960 struct mlx5_core_dev *mdev = priv->mdev;
1961 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1962 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1963
1964 memset(in, 0, sizeof(in));
1965
08fb1dac 1966 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1967 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1968
1969 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1970}
1971
1972static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1973{
1974 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1975}
1976
1977static int mlx5e_create_tises(struct mlx5e_priv *priv)
1978{
1979 int err;
1980 int tc;
1981
08fb1dac 1982 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1983 err = mlx5e_create_tis(priv, tc);
1984 if (err)
1985 goto err_close_tises;
1986 }
1987
1988 return 0;
1989
1990err_close_tises:
1991 for (tc--; tc >= 0; tc--)
1992 mlx5e_destroy_tis(priv, tc);
1993
1994 return err;
1995}
1996
1997static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1998{
1999 int tc;
2000
08fb1dac 2001 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 2002 mlx5e_destroy_tis(priv, tc);
2003}
2004
1da36696
TT		 2005static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2006 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2007{
2008 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2009
3191e05f
AS		 2010 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2011
5a6f8aef
AS		 2012#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2013 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2014
5a6f8aef
AS		 2015#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2016 MLX5_HASH_FIELD_SEL_DST_IP |\
2017 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2018 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2019
a741749f
AS		 2020#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2021 MLX5_HASH_FIELD_SEL_DST_IP |\
2022 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2023
5c50368f 2024 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2025
4cbeaff5 2026 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1da36696
TT		 2027 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
2028 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2029
2030 switch (tt) {
2031 case MLX5E_TT_IPV4_TCP:
2032 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2033 MLX5_L3_PROT_TYPE_IPV4);
2034 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2035 MLX5_L4_PROT_TYPE_TCP);
2036 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2037 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2038 break;
2039
2040 case MLX5E_TT_IPV6_TCP:
2041 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2042 MLX5_L3_PROT_TYPE_IPV6);
2043 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2044 MLX5_L4_PROT_TYPE_TCP);
2045 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2046 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2047 break;
2048
2049 case MLX5E_TT_IPV4_UDP:
2050 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2051 MLX5_L3_PROT_TYPE_IPV4);
2052 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2053 MLX5_L4_PROT_TYPE_UDP);
2054 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2055 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2056 break;
2057
2058 case MLX5E_TT_IPV6_UDP:
2059 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2060 MLX5_L3_PROT_TYPE_IPV6);
2061 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2062 MLX5_L4_PROT_TYPE_UDP);
2063 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2064 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2065 break;
2066
a741749f
AS		 2067 case MLX5E_TT_IPV4_IPSEC_AH:
2068 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2069 MLX5_L3_PROT_TYPE_IPV4);
2070 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2071 MLX5_HASH_IP_IPSEC_SPI);
2072 break;
2073
2074 case MLX5E_TT_IPV6_IPSEC_AH:
2075 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2076 MLX5_L3_PROT_TYPE_IPV6);
2077 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2078 MLX5_HASH_IP_IPSEC_SPI);
2079 break;
2080
2081 case MLX5E_TT_IPV4_IPSEC_ESP:
2082 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2083 MLX5_L3_PROT_TYPE_IPV4);
2084 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2085 MLX5_HASH_IP_IPSEC_SPI);
2086 break;
2087
2088 case MLX5E_TT_IPV6_IPSEC_ESP:
2089 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2090 MLX5_L3_PROT_TYPE_IPV6);
2091 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2092 MLX5_HASH_IP_IPSEC_SPI);
2093 break;
2094
f62b8bb8
AV		 2095 case MLX5E_TT_IPV4:
2096 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2097 MLX5_L3_PROT_TYPE_IPV4);
2098 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2099 MLX5_HASH_IP);
2100 break;
2101
2102 case MLX5E_TT_IPV6:
2103 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2104 MLX5_L3_PROT_TYPE_IPV6);
2105 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2106 MLX5_HASH_IP);
2107 break;
1da36696
TT		 2108 default:
2109 WARN_ONCE(true,
2110 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2111 }
2112}
2113
1da36696
TT		 2114static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2115 u32 rqtn)
f62b8bb8 2116{
1da36696
TT		 2117 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2118
2119 mlx5e_build_tir_ctx_lro(tirc, priv);
2120
2121 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2122 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2123 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2124}
2125
2126static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2127{
2128 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2129 void *tirc;
2130 int inlen;
1da36696 2131 u32 *tirn;
f62b8bb8 2132 int err;
1da36696
TT		 2133 u32 *in;
2134 int ix;
2135 int tt;
f62b8bb8
AV		 2136
2137 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2138 in = mlx5_vzalloc(inlen);
2139 if (!in)
2140 return -ENOMEM;
2141
1da36696
TT		 2142 /* indirect tirs */
2143 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2144 memset(in, 0, inlen);
2145 tirn = &priv->indir_tirn[tt];
2146 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2147 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2148 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
f62b8bb8 2149 if (err)
40ab6a6e 2150 goto err_destroy_tirs;
f62b8bb8
AV		 2151 }
2152
1da36696
TT		 2153 /* direct tirs */
2154 for (ix = 0; ix < nch; ix++) {
2155 memset(in, 0, inlen);
2156 tirn = &priv->direct_tir[ix].tirn;
2157 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2158 mlx5e_build_direct_tir_ctx(priv, tirc,
2159 priv->direct_tir[ix].rqtn);
2160 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2161 if (err)
2162 goto err_destroy_ch_tirs;
2163 }
2164
2165 kvfree(in);
2166
f62b8bb8
AV		 2167 return 0;
2168
1da36696
TT		 2169err_destroy_ch_tirs:
2170 for (ix--; ix >= 0; ix--)
2171 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2172
40ab6a6e 2173err_destroy_tirs:
1da36696
TT		 2174 for (tt--; tt >= 0; tt--)
2175 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2176
2177 kvfree(in);
f62b8bb8
AV		 2178
2179 return err;
2180}
2181
40ab6a6e 2182static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8 2183{
1da36696 2184 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2185 int i;
2186
1da36696
TT		 2187 for (i = 0; i < nch; i++)
2188 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2189
2190 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2191 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
f62b8bb8
AV		 2192}
2193
36350114
GP		 2194int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2195{
2196 int err = 0;
2197 int i;
2198
2199 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2200 return 0;
2201
2202 for (i = 0; i < priv->params.num_channels; i++) {
2203 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2204 if (err)
2205 return err;
2206 }
2207
2208 return 0;
2209}
2210
08fb1dac
SM		 2211static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2212{
2213 struct mlx5e_priv *priv = netdev_priv(netdev);
2214 bool was_opened;
2215 int err = 0;
2216
2217 if (tc && tc != MLX5E_MAX_NUM_TC)
2218 return -EINVAL;
2219
2220 mutex_lock(&priv->state_lock);
2221
2222 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2223 if (was_opened)
2224 mlx5e_close_locked(priv->netdev);
2225
2226 priv->params.num_tc = tc ? tc : 1;
2227
2228 if (was_opened)
2229 err = mlx5e_open_locked(priv->netdev);
2230
2231 mutex_unlock(&priv->state_lock);
2232
2233 return err;
2234}
2235
2236static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2237 __be16 proto, struct tc_to_netdev *tc)
2238{
e8f887ac
AV		 2239 struct mlx5e_priv *priv = netdev_priv(dev);
2240
2241 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2242 goto mqprio;
2243
2244 switch (tc->type) {
e3a2b7ed
AV		 2245 case TC_SETUP_CLSFLOWER:
2246 switch (tc->cls_flower->command) {
2247 case TC_CLSFLOWER_REPLACE:
2248 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2249 case TC_CLSFLOWER_DESTROY:
2250 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2251 case TC_CLSFLOWER_STATS:
2252 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2253 }
e8f887ac
AV		 2254 default:
2255 return -EOPNOTSUPP;
2256 }
2257
2258mqprio:
67ba422e 2259 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2260 return -EINVAL;
2261
2262 return mlx5e_setup_tc(dev, tc->tc);
2263}
2264
f62b8bb8
AV		 2265static struct rtnl_link_stats64 *
2266mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2267{
2268 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2269 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2270 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2271 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2272
9218b44d
GP		 2273 stats->rx_packets = sstats->rx_packets;
2274 stats->rx_bytes = sstats->rx_bytes;
2275 stats->tx_packets = sstats->tx_packets;
2276 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2277
2278 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2279 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2280
2281 stats->rx_length_errors =
9218b44d
GP		 2282 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2283 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2284 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2285 stats->rx_crc_errors =
9218b44d
GP		 2286 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2287 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2288 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2289 stats->tx_carrier_errors =
9218b44d 2290 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2291 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2292 stats->rx_frame_errors;
2293 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2294
2295 /* vport multicast also counts packets that are dropped due to steering
2296 * or rx out of buffer
2297 */
9218b44d
GP		 2298 stats->multicast =
2299 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2300
2301 return stats;
2302}
2303
2304static void mlx5e_set_rx_mode(struct net_device *dev)
2305{
2306 struct mlx5e_priv *priv = netdev_priv(dev);
2307
7bb29755 2308 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2309}
2310
2311static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2312{
2313 struct mlx5e_priv *priv = netdev_priv(netdev);
2314 struct sockaddr *saddr = addr;
2315
2316 if (!is_valid_ether_addr(saddr->sa_data))
2317 return -EADDRNOTAVAIL;
2318
2319 netif_addr_lock_bh(netdev);
2320 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2321 netif_addr_unlock_bh(netdev);
2322
7bb29755 2323 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2324
2325 return 0;
2326}
2327
0e405443
GP		 2328#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2329 do { \
2330 if (enable) \
2331 netdev->features |= feature; \
2332 else \
2333 netdev->features &= ~feature; \
2334 } while (0)
2335
2336typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2337
2338static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2339{
2340 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2341 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2342 int err;
f62b8bb8
AV		 2343
2344 mutex_lock(&priv->state_lock);
f62b8bb8 2345
0e405443
GP		 2346 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2347 mlx5e_close_locked(priv->netdev);
98e81b0a 2348
0e405443
GP		 2349 priv->params.lro_en = enable;
2350 err = mlx5e_modify_tirs_lro(priv);
2351 if (err) {
2352 netdev_err(netdev, "lro modify failed, %d\n", err);
2353 priv->params.lro_en = !enable;
98e81b0a 2354 }
f62b8bb8 2355
0e405443
GP		 2356 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2357 mlx5e_open_locked(priv->netdev);
2358
9b37b07f
AS		 2359 mutex_unlock(&priv->state_lock);
2360
0e405443
GP		 2361 return err;
2362}
2363
2364static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2365{
2366 struct mlx5e_priv *priv = netdev_priv(netdev);
2367
2368 if (enable)
2369 mlx5e_enable_vlan_filter(priv);
2370 else
2371 mlx5e_disable_vlan_filter(priv);
2372
2373 return 0;
2374}
2375
2376static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2377{
2378 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2379
0e405443 2380 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2381 netdev_err(netdev,
2382 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2383 return -EINVAL;
2384 }
2385
0e405443
GP		 2386 return 0;
2387}
2388
94cb1ebb
EBE		 2389static int set_feature_rx_all(struct net_device *netdev, bool enable)
2390{
2391 struct mlx5e_priv *priv = netdev_priv(netdev);
2392 struct mlx5_core_dev *mdev = priv->mdev;
2393
2394 return mlx5_set_port_fcs(mdev, !enable);
2395}
2396
36350114
GP		 2397static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2398{
2399 struct mlx5e_priv *priv = netdev_priv(netdev);
2400 int err;
2401
2402 mutex_lock(&priv->state_lock);
2403
2404 priv->params.vlan_strip_disable = !enable;
2405 err = mlx5e_modify_rqs_vsd(priv, !enable);
2406 if (err)
2407 priv->params.vlan_strip_disable = enable;
2408
2409 mutex_unlock(&priv->state_lock);
2410
2411 return err;
2412}
2413
45bf454a
MG		 2414#ifdef CONFIG_RFS_ACCEL
2415static int set_feature_arfs(struct net_device *netdev, bool enable)
2416{
2417 struct mlx5e_priv *priv = netdev_priv(netdev);
2418 int err;
2419
2420 if (enable)
2421 err = mlx5e_arfs_enable(priv);
2422 else
2423 err = mlx5e_arfs_disable(priv);
2424
2425 return err;
2426}
2427#endif
2428
0e405443
GP		 2429static int mlx5e_handle_feature(struct net_device *netdev,
2430 netdev_features_t wanted_features,
2431 netdev_features_t feature,
2432 mlx5e_feature_handler feature_handler)
2433{
2434 netdev_features_t changes = wanted_features ^ netdev->features;
2435 bool enable = !!(wanted_features & feature);
2436 int err;
2437
2438 if (!(changes & feature))
2439 return 0;
2440
2441 err = feature_handler(netdev, enable);
2442 if (err) {
2443 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2444 enable ? "Enable" : "Disable", feature, err);
2445 return err;
2446 }
2447
2448 MLX5E_SET_FEATURE(netdev, feature, enable);
2449 return 0;
2450}
2451
2452static int mlx5e_set_features(struct net_device *netdev,
2453 netdev_features_t features)
2454{
2455 int err;
2456
2457 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2458 set_feature_lro);
2459 err |= mlx5e_handle_feature(netdev, features,
2460 NETIF_F_HW_VLAN_CTAG_FILTER,
2461 set_feature_vlan_filter);
2462 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2463 set_feature_tc_num_filters);
94cb1ebb
EBE		 2464 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2465 set_feature_rx_all);
36350114
GP		 2466 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2467 set_feature_rx_vlan);
45bf454a
MG		 2468#ifdef CONFIG_RFS_ACCEL
2469 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2470 set_feature_arfs);
2471#endif
0e405443
GP		 2472
2473 return err ? -EINVAL : 0;
f62b8bb8
AV		 2474}
2475
d8edd246
SM		 2476#define MXL5_HW_MIN_MTU 64
2477#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2478
f62b8bb8
AV		 2479static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2480{
2481 struct mlx5e_priv *priv = netdev_priv(netdev);
2482 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2483 bool was_opened;
046339ea 2484 u16 max_mtu;
d8edd246 2485 u16 min_mtu;
98e81b0a 2486 int err = 0;
f62b8bb8 2487
facc9699 2488 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2489
50a9eea6 2490 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2491 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2492
d8edd246 2493 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2494 netdev_err(netdev,
d8edd246
SM		 2495 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2496 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2497 return -EINVAL;
2498 }
2499
2500 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2501
2502 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2503 if (was_opened)
2504 mlx5e_close_locked(netdev);
2505
f62b8bb8 2506 netdev->mtu = new_mtu;
98e81b0a
AS		 2507
2508 if (was_opened)
2509 err = mlx5e_open_locked(netdev);
2510
f62b8bb8
AV		 2511 mutex_unlock(&priv->state_lock);
2512
2513 return err;
2514}
2515
ef9814de
EBE		 2516static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2517{
2518 switch (cmd) {
2519 case SIOCSHWTSTAMP:
2520 return mlx5e_hwstamp_set(dev, ifr);
2521 case SIOCGHWTSTAMP:
2522 return mlx5e_hwstamp_get(dev, ifr);
2523 default:
2524 return -EOPNOTSUPP;
2525 }
2526}
2527
66e49ded
SM		 2528static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2529{
2530 struct mlx5e_priv *priv = netdev_priv(dev);
2531 struct mlx5_core_dev *mdev = priv->mdev;
2532
2533 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2534}
2535
2536static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2537{
2538 struct mlx5e_priv *priv = netdev_priv(dev);
2539 struct mlx5_core_dev *mdev = priv->mdev;
2540
2541 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2542 vlan, qos);
2543}
2544
f942380c
MHY		 2545static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2546{
2547 struct mlx5e_priv *priv = netdev_priv(dev);
2548 struct mlx5_core_dev *mdev = priv->mdev;
2549
2550 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2551}
2552
1edc57e2
MHY		 2553static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2554{
2555 struct mlx5e_priv *priv = netdev_priv(dev);
2556 struct mlx5_core_dev *mdev = priv->mdev;
2557
2558 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2559}
66e49ded
SM		 2560static int mlx5_vport_link2ifla(u8 esw_link)
2561{
2562 switch (esw_link) {
2563 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2564 return IFLA_VF_LINK_STATE_DISABLE;
2565 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2566 return IFLA_VF_LINK_STATE_ENABLE;
2567 }
2568 return IFLA_VF_LINK_STATE_AUTO;
2569}
2570
2571static int mlx5_ifla_link2vport(u8 ifla_link)
2572{
2573 switch (ifla_link) {
2574 case IFLA_VF_LINK_STATE_DISABLE:
2575 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2576 case IFLA_VF_LINK_STATE_ENABLE:
2577 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2578 }
2579 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2580}
2581
2582static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2583 int link_state)
2584{
2585 struct mlx5e_priv *priv = netdev_priv(dev);
2586 struct mlx5_core_dev *mdev = priv->mdev;
2587
2588 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2589 mlx5_ifla_link2vport(link_state));
2590}
2591
2592static int mlx5e_get_vf_config(struct net_device *dev,
2593 int vf, struct ifla_vf_info *ivi)
2594{
2595 struct mlx5e_priv *priv = netdev_priv(dev);
2596 struct mlx5_core_dev *mdev = priv->mdev;
2597 int err;
2598
2599 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2600 if (err)
2601 return err;
2602 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2603 return 0;
2604}
2605
2606static int mlx5e_get_vf_stats(struct net_device *dev,
2607 int vf, struct ifla_vf_stats *vf_stats)
2608{
2609 struct mlx5e_priv *priv = netdev_priv(dev);
2610 struct mlx5_core_dev *mdev = priv->mdev;
2611
2612 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2613 vf_stats);
2614}
2615
b3f63c3d 2616static void mlx5e_add_vxlan_port(struct net_device *netdev,
974c3f30 2617 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2618{
2619 struct mlx5e_priv *priv = netdev_priv(netdev);
2620
974c3f30
AD		 2621 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2622 return;
2623
b3f63c3d
MF		 2624 if (!mlx5e_vxlan_allowed(priv->mdev))
2625 return;
2626
974c3f30 2627 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 2628}
2629
2630static void mlx5e_del_vxlan_port(struct net_device *netdev,
974c3f30 2631 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2632{
2633 struct mlx5e_priv *priv = netdev_priv(netdev);
2634
974c3f30
AD		 2635 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2636 return;
2637
b3f63c3d
MF		 2638 if (!mlx5e_vxlan_allowed(priv->mdev))
2639 return;
2640
974c3f30 2641 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 2642}
2643
2644static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2645 struct sk_buff *skb,
2646 netdev_features_t features)
2647{
2648 struct udphdr *udph;
2649 u16 proto;
2650 u16 port = 0;
2651
2652 switch (vlan_get_protocol(skb)) {
2653 case htons(ETH_P_IP):
2654 proto = ip_hdr(skb)->protocol;
2655 break;
2656 case htons(ETH_P_IPV6):
2657 proto = ipv6_hdr(skb)->nexthdr;
2658 break;
2659 default:
2660 goto out;
2661 }
2662
2663 if (proto == IPPROTO_UDP) {
2664 udph = udp_hdr(skb);
2665 port = be16_to_cpu(udph->dest);
2666 }
2667
2668 /* Verify if UDP port is being offloaded by HW */
2669 if (port && mlx5e_vxlan_lookup_port(priv, port))
2670 return features;
2671
2672out:
2673 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2674 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2675}
2676
2677static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2678 struct net_device *netdev,
2679 netdev_features_t features)
2680{
2681 struct mlx5e_priv *priv = netdev_priv(netdev);
2682
2683 features = vlan_features_check(skb, features);
2684 features = vxlan_features_check(skb, features);
2685
2686 /* Validate if the tunneled packet is being offloaded by HW */
2687 if (skb->encapsulation &&
2688 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2689 return mlx5e_vxlan_features_check(priv, skb, features);
2690
2691 return features;
2692}
2693
b0eed40e 2694static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2695 .ndo_open = mlx5e_open,
2696 .ndo_stop = mlx5e_close,
2697 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2698 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2699 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2700 .ndo_get_stats64 = mlx5e_get_stats,
2701 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2702 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2703 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2704 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2705 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2706 .ndo_change_mtu = mlx5e_change_mtu,
2707 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 2708 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 2709#ifdef CONFIG_RFS_ACCEL
2710 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2711#endif
b0eed40e
SM		 2712};
2713
2714static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2715 .ndo_open = mlx5e_open,
2716 .ndo_stop = mlx5e_close,
2717 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2718 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2719 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2720 .ndo_get_stats64 = mlx5e_get_stats,
2721 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2722 .ndo_set_mac_address = mlx5e_set_mac,
2723 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2724 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2725 .ndo_set_features = mlx5e_set_features,
2726 .ndo_change_mtu = mlx5e_change_mtu,
2727 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 2728 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
2729 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 2730 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 2731 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 2732#ifdef CONFIG_RFS_ACCEL
2733 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2734#endif
b0eed40e
SM		 2735 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2736 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 2737 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 2738 .ndo_set_vf_trust = mlx5e_set_vf_trust,
b0eed40e
SM		 2739 .ndo_get_vf_config = mlx5e_get_vf_config,
2740 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2741 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2742};
2743
2744static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2745{
2746 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2747 return -ENOTSUPP;
2748 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2749 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2750 !MLX5_CAP_ETH(mdev, csum_cap) ||
2751 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2752 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2753 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2754 MLX5_CAP_FLOWTABLE(mdev,
2755 flow_table_properties_nic_receive.max_ft_level)
2756 < 3) {
f62b8bb8
AV		 2757 mlx5_core_warn(mdev,
2758 "Not creating net device, some required device capabilities are missing\n");
2759 return -ENOTSUPP;
2760 }
66189961
TT		 2761 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2762 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2763 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2764 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2765
f62b8bb8
AV		 2766 return 0;
2767}
2768
58d52291
AS		 2769u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2770{
2771 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2772
2773 return bf_buf_size -
2774 sizeof(struct mlx5e_tx_wqe) +
2775 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2776}
2777
08fb1dac
SM		 2778#ifdef CONFIG_MLX5_CORE_EN_DCB
2779static void mlx5e_ets_init(struct mlx5e_priv *priv)
2780{
2781 int i;
2782
2783 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2784 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2785 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2786 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2787 priv->params.ets.prio_tc[i] = i;
2788 }
2789
2790 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2791 priv->params.ets.prio_tc[0] = 1;
2792 priv->params.ets.prio_tc[1] = 0;
2793}
2794#endif
2795
d8c9660d
TT		 2796void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2797 u32 *indirection_rqt, int len,
85082dba
TT		 2798 int num_channels)
2799{
d8c9660d
TT		 2800 int node = mdev->priv.numa_node;
2801 int node_num_of_cores;
85082dba
TT		 2802 int i;
2803
d8c9660d
TT		 2804 if (node == -1)
2805 node = first_online_node;
2806
2807 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2808
2809 if (node_num_of_cores)
2810 num_channels = min_t(int, num_channels, node_num_of_cores);
2811
85082dba
TT		 2812 for (i = 0; i < len; i++)
2813 indirection_rqt[i] = i % num_channels;
2814}
2815
bc77b240
TT		 2816static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2817{
2818 return MLX5_CAP_GEN(mdev, striding_rq) &&
2819 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2820 MLX5_CAP_ETH(mdev, reg_umr_sq);
2821}
2822
b797a684
SM		 2823static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2824{
2825 enum pcie_link_width width;
2826 enum pci_bus_speed speed;
2827 int err = 0;
2828
2829 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2830 if (err)
2831 return err;
2832
2833 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2834 return -EINVAL;
2835
2836 switch (speed) {
2837 case PCIE_SPEED_2_5GT:
2838 *pci_bw = 2500 * width;
2839 break;
2840 case PCIE_SPEED_5_0GT:
2841 *pci_bw = 5000 * width;
2842 break;
2843 case PCIE_SPEED_8_0GT:
2844 *pci_bw = 8000 * width;
2845 break;
2846 default:
2847 return -EINVAL;
2848 }
2849
2850 return 0;
2851}
2852
2853static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2854{
2855 return (link_speed && pci_bw &&
2856 (pci_bw < 40000) && (pci_bw < link_speed));
2857}
2858
f62b8bb8
AV		 2859static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2860 struct net_device *netdev,
936896e9 2861 int num_channels)
f62b8bb8
AV		 2862{
2863 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 2864 u32 link_speed = 0;
2865 u32 pci_bw = 0;
f62b8bb8
AV		 2866
2867 priv->params.log_sq_size =
2868 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 2869 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 2870 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2871 MLX5_WQ_TYPE_LINKED_LIST;
2872
b797a684
SM		 2873 /* set CQE compression */
2874 priv->params.rx_cqe_compress_admin = false;
2875 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2876 MLX5_CAP_GEN(mdev, vport_group_manager)) {
2877 mlx5e_get_max_linkspeed(mdev, &link_speed);
2878 mlx5e_get_pci_bw(mdev, &pci_bw);
2879 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2880 link_speed, pci_bw);
2881 priv->params.rx_cqe_compress_admin =
2882 cqe_compress_heuristic(link_speed, pci_bw);
2883 }
2884
2885 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2886
461017cb
TT		 2887 switch (priv->params.rq_wq_type) {
2888 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2889 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
d9d9f156
TT		 2890 priv->params.mpwqe_log_stride_sz =
2891 priv->params.rx_cqe_compress ?
2892 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2893 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2894 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2895 priv->params.mpwqe_log_stride_sz;
461017cb
TT		 2896 priv->params.lro_en = true;
2897 break;
2898 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2899 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2900 }
2901
d9d9f156
TT		 2902 mlx5_core_info(mdev,
2903 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2904 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2905 BIT(priv->params.log_rq_size),
2906 BIT(priv->params.mpwqe_log_stride_sz),
2907 priv->params.rx_cqe_compress_admin);
2908
461017cb
TT		 2909 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2910 BIT(priv->params.log_rq_size));
f62b8bb8
AV		 2911 priv->params.rx_cq_moderation_usec =
2912 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2913 priv->params.rx_cq_moderation_pkts =
2914 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2915 priv->params.tx_cq_moderation_usec =
2916 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2917 priv->params.tx_cq_moderation_pkts =
2918 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2919 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8 2920 priv->params.num_tc = 1;
2be6967c 2921 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2922
57afead5
AS		 2923 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2924 sizeof(priv->params.toeplitz_hash_key));
2925
d8c9660d 2926 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
85082dba 2927 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2928
f62b8bb8
AV		 2929 priv->params.lro_wqe_sz =
2930 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2931
2932 priv->mdev = mdev;
2933 priv->netdev = netdev;
936896e9 2934 priv->params.num_channels = num_channels;
f62b8bb8 2935
08fb1dac
SM		 2936#ifdef CONFIG_MLX5_CORE_EN_DCB
2937 mlx5e_ets_init(priv);
2938#endif
f62b8bb8 2939
f62b8bb8
AV		 2940 mutex_init(&priv->state_lock);
2941
2942 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2943 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2944 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2945}
2946
2947static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2948{
2949 struct mlx5e_priv *priv = netdev_priv(netdev);
2950
e1d7d349 2951 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2952 if (is_zero_ether_addr(netdev->dev_addr) &&
2953 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2954 eth_hw_addr_random(netdev);
2955 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2956 }
f62b8bb8
AV		 2957}
2958
2959static void mlx5e_build_netdev(struct net_device *netdev)
2960{
2961 struct mlx5e_priv *priv = netdev_priv(netdev);
2962 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 2963 bool fcs_supported;
2964 bool fcs_enabled;
f62b8bb8
AV		 2965
2966 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2967
08fb1dac 2968 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2969 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2970#ifdef CONFIG_MLX5_CORE_EN_DCB
2971 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2972#endif
2973 } else {
b0eed40e 2974 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2975 }
66e49ded 2976
f62b8bb8
AV		 2977 netdev->watchdog_timeo = 15 * HZ;
2978
2979 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2980
12be4b21 2981 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2982 netdev->vlan_features |= NETIF_F_IP_CSUM;
2983 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2984 netdev->vlan_features |= NETIF_F_GRO;
2985 netdev->vlan_features |= NETIF_F_TSO;
2986 netdev->vlan_features |= NETIF_F_TSO6;
2987 netdev->vlan_features |= NETIF_F_RXCSUM;
2988 netdev->vlan_features |= NETIF_F_RXHASH;
2989
2990 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2991 netdev->vlan_features |= NETIF_F_LRO;
2992
2993 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2994 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2995 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2996 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2997
b3f63c3d 2998 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 2999 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3000 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3001 NETIF_F_GSO_PARTIAL;
b3f63c3d 3002 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3003 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3004 netdev->hw_enc_features |= NETIF_F_TSO;
3005 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3006 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3007 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3008 NETIF_F_GSO_PARTIAL;
3009 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3010 }
3011
94cb1ebb
EBE		 3012 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3013
3014 if (fcs_supported)
3015 netdev->hw_features |= NETIF_F_RXALL;
3016
f62b8bb8
AV		 3017 netdev->features = netdev->hw_features;
3018 if (!priv->params.lro_en)
3019 netdev->features &= ~NETIF_F_LRO;
3020
94cb1ebb
EBE		 3021 if (fcs_enabled)
3022 netdev->features &= ~NETIF_F_RXALL;
3023
e8f887ac
AV		 3024#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3025 if (FT_CAP(flow_modify_en) &&
3026 FT_CAP(modify_root) &&
3027 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3028 FT_CAP(flow_table_modify)) {
3029 netdev->hw_features |= NETIF_F_HW_TC;
3030#ifdef CONFIG_RFS_ACCEL
3031 netdev->hw_features |= NETIF_F_NTUPLE;
3032#endif
3033 }
e8f887ac 3034
f62b8bb8
AV		 3035 netdev->features |= NETIF_F_HIGHDMA;
3036
3037 netdev->priv_flags |= IFF_UNICAST_FLT;
3038
3039 mlx5e_set_netdev_dev_addr(netdev);
3040}
3041
3042static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
a606b0f6 3043 struct mlx5_core_mkey *mkey)
f62b8bb8
AV		 3044{
3045 struct mlx5_core_dev *mdev = priv->mdev;
3046 struct mlx5_create_mkey_mbox_in *in;
3047 int err;
3048
3049 in = mlx5_vzalloc(sizeof(*in));
3050 if (!in)
3051 return -ENOMEM;
3052
3053 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
3054 MLX5_PERM_LOCAL_READ |
3055 MLX5_ACCESS_MODE_PA;
3056 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
3057 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3058
a606b0f6 3059 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
f62b8bb8
AV		 3060 NULL);
3061
3062 kvfree(in);
3063
3064 return err;
3065}
3066
593cf338
RS		 3067static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3068{
3069 struct mlx5_core_dev *mdev = priv->mdev;
3070 int err;
3071
3072 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3073 if (err) {
3074 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3075 priv->q_counter = 0;
3076 }
3077}
3078
3079static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3080{
3081 if (!priv->q_counter)
3082 return;
3083
3084 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3085}
3086
bc77b240
TT		 3087static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3088{
3089 struct mlx5_core_dev *mdev = priv->mdev;
3090 struct mlx5_create_mkey_mbox_in *in;
3091 struct mlx5_mkey_seg *mkc;
3092 int inlen = sizeof(*in);
3093 u64 npages =
3094 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3095 int err;
3096
3097 in = mlx5_vzalloc(inlen);
3098 if (!in)
3099 return -ENOMEM;
3100
3101 mkc = &in->seg;
3102 mkc->status = MLX5_MKEY_STATUS_FREE;
3103 mkc->flags = MLX5_PERM_UMR_EN |
3104 MLX5_PERM_LOCAL_READ |
3105 MLX5_PERM_LOCAL_WRITE |
3106 MLX5_ACCESS_MODE_MTT;
3107
3108 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3109 mkc->flags_pd = cpu_to_be32(priv->pdn);
3110 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3111 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3112 mkc->log2_page_size = PAGE_SHIFT;
3113
3114 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3115 NULL, NULL);
3116
3117 kvfree(in);
3118
3119 return err;
3120}
3121
f62b8bb8
AV		 3122static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3123{
3124 struct net_device *netdev;
3125 struct mlx5e_priv *priv;
3435ab59 3126 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 3127 int err;
3128
3129 if (mlx5e_check_required_hca_cap(mdev))
3130 return NULL;
3131
08fb1dac
SM		 3132 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3133 nch * MLX5E_MAX_NUM_TC,
3134 nch);
f62b8bb8
AV		 3135 if (!netdev) {
3136 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3137 return NULL;
3138 }
3139
936896e9 3140 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 3141 mlx5e_build_netdev(netdev);
3142
3143 netif_carrier_off(netdev);
3144
3145 priv = netdev_priv(netdev);
3146
7bb29755
MF		 3147 priv->wq = create_singlethread_workqueue("mlx5e");
3148 if (!priv->wq)
3149 goto err_free_netdev;
3150
0ba42241 3151 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
f62b8bb8 3152 if (err) {
1f2a3003 3153 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
7bb29755 3154 goto err_destroy_wq;
f62b8bb8
AV		 3155 }
3156
3157 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3158 if (err) {
1f2a3003 3159 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 3160 goto err_unmap_free_uar;
3161 }
3162
8d7f9ecb 3163 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 3164 if (err) {
1f2a3003 3165 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 3166 goto err_dealloc_pd;
3167 }
3168
a606b0f6 3169 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
f62b8bb8 3170 if (err) {
1f2a3003 3171 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 3172 goto err_dealloc_transport_domain;
f62b8bb8
AV		 3173 }
3174
bc77b240
TT		 3175 err = mlx5e_create_umr_mkey(priv);
3176 if (err) {
3177 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3178 goto err_destroy_mkey;
3179 }
3180
40ab6a6e 3181 err = mlx5e_create_tises(priv);
5c50368f 3182 if (err) {
40ab6a6e 3183 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
bc77b240 3184 goto err_destroy_umr_mkey;
5c50368f
AS		 3185 }
3186
3187 err = mlx5e_open_drop_rq(priv);
3188 if (err) {
3189 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 3190 goto err_destroy_tises;
5c50368f
AS		 3191 }
3192
1da36696 3193 err = mlx5e_create_rqts(priv);
5c50368f 3194 if (err) {
1da36696 3195 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
5c50368f
AS		 3196 goto err_close_drop_rq;
3197 }
3198
40ab6a6e 3199 err = mlx5e_create_tirs(priv);
5c50368f 3200 if (err) {
40ab6a6e 3201 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
1da36696 3202 goto err_destroy_rqts;
5c50368f
AS		 3203 }
3204
acff797c 3205 err = mlx5e_create_flow_steering(priv);
5c50368f 3206 if (err) {
acff797c 3207 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
40ab6a6e 3208 goto err_destroy_tirs;
5c50368f
AS		 3209 }
3210
593cf338
RS		 3211 mlx5e_create_q_counter(priv);
3212
33cfaaa8 3213 mlx5e_init_l2_addr(priv);
5c50368f 3214
b3f63c3d
MF		 3215 mlx5e_vxlan_init(priv);
3216
e8f887ac
AV		 3217 err = mlx5e_tc_init(priv);
3218 if (err)
593cf338 3219 goto err_dealloc_q_counters;
e8f887ac 3220
08fb1dac
SM		 3221#ifdef CONFIG_MLX5_CORE_EN_DCB
3222 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3223#endif
3224
f62b8bb8
AV		 3225 err = register_netdev(netdev);
3226 if (err) {
1f2a3003 3227 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
e8f887ac 3228 goto err_tc_cleanup;
f62b8bb8
AV		 3229 }
3230
01a14098
MF		 3231 if (mlx5e_vxlan_allowed(mdev)) {
3232 rtnl_lock();
974c3f30 3233 udp_tunnel_get_rx_info(netdev);
01a14098
MF		 3234 rtnl_unlock();
3235 }
b3f63c3d 3236
f62b8bb8 3237 mlx5e_enable_async_events(priv);
7bb29755 3238 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3239
3240 return priv;
3241
e8f887ac
AV		 3242err_tc_cleanup:
3243 mlx5e_tc_cleanup(priv);
3244
593cf338
RS		 3245err_dealloc_q_counters:
3246 mlx5e_destroy_q_counter(priv);
acff797c 3247 mlx5e_destroy_flow_steering(priv);
5c50368f 3248
40ab6a6e
AS		 3249err_destroy_tirs:
3250 mlx5e_destroy_tirs(priv);
5c50368f 3251
1da36696
TT		 3252err_destroy_rqts:
3253 mlx5e_destroy_rqts(priv);
5c50368f
AS		 3254
3255err_close_drop_rq:
3256 mlx5e_close_drop_rq(priv);
3257
40ab6a6e
AS		 3258err_destroy_tises:
3259 mlx5e_destroy_tises(priv);
5c50368f 3260
bc77b240
TT		 3261err_destroy_umr_mkey:
3262 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3263
f62b8bb8 3264err_destroy_mkey:
a606b0f6 3265 mlx5_core_destroy_mkey(mdev, &priv->mkey);
f62b8bb8 3266
3191e05f 3267err_dealloc_transport_domain:
8d7f9ecb 3268 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 3269
f62b8bb8
AV		 3270err_dealloc_pd:
3271 mlx5_core_dealloc_pd(mdev, priv->pdn);
3272
3273err_unmap_free_uar:
3274 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3275
7bb29755
MF		 3276err_destroy_wq:
3277 destroy_workqueue(priv->wq);
3278
f62b8bb8
AV		 3279err_free_netdev:
3280 free_netdev(netdev);
3281
3282 return NULL;
3283}
3284
3285static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3286{
3287 struct mlx5e_priv *priv = vpriv;
3288 struct net_device *netdev = priv->netdev;
3289
9b37b07f
AS		 3290 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3291
7bb29755 3292 queue_work(priv->wq, &priv->set_rx_mode_work);
1cefa326 3293 mlx5e_disable_async_events(priv);
7bb29755 3294 flush_workqueue(priv->wq);
5fc7197d
MD		 3295 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3296 netif_device_detach(netdev);
811afeaa 3297 mlx5e_close(netdev);
5fc7197d
MD		 3298 } else {
3299 unregister_netdev(netdev);
3300 }
3301
e8f887ac 3302 mlx5e_tc_cleanup(priv);
b3f63c3d 3303 mlx5e_vxlan_cleanup(priv);
593cf338 3304 mlx5e_destroy_q_counter(priv);
acff797c 3305 mlx5e_destroy_flow_steering(priv);
40ab6a6e 3306 mlx5e_destroy_tirs(priv);
1da36696 3307 mlx5e_destroy_rqts(priv);
5c50368f 3308 mlx5e_close_drop_rq(priv);
40ab6a6e 3309 mlx5e_destroy_tises(priv);
bc77b240 3310 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
a606b0f6 3311 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
8d7f9ecb 3312 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 3313 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3314 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
7bb29755
MF		 3315 cancel_delayed_work_sync(&priv->update_stats_work);
3316 destroy_workqueue(priv->wq);
5fc7197d
MD		 3317
3318 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3319 free_netdev(netdev);
f62b8bb8
AV		 3320}
3321
3322static void *mlx5e_get_netdev(void *vpriv)
3323{
3324 struct mlx5e_priv *priv = vpriv;
3325
3326 return priv->netdev;
3327}
3328
3329static struct mlx5_interface mlx5e_interface = {
3330 .add = mlx5e_create_netdev,
3331 .remove = mlx5e_destroy_netdev,
3332 .event = mlx5e_async_event,
3333 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3334 .get_dev = mlx5e_get_netdev,
3335};
3336
3337void mlx5e_init(void)
3338{
3339 mlx5_register_interface(&mlx5e_interface);
3340}
3341
3342void mlx5e_cleanup(void)
3343{
3344 mlx5_unregister_interface(&mlx5e_interface);
3345}
Linux kernel - Deliverables
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