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net/mlx5e: Correctly handle RSS indirection table when changing number of channels
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
86d722ad 33#include <linux/mlx5/fs.h>
f62b8bb8 34#include "en.h"
66e49ded 35#include "eswitch.h"
f62b8bb8
AV		 36
37struct mlx5e_rq_param {
38 u32 rqc[MLX5_ST_SZ_DW(rqc)];
39 struct mlx5_wq_param wq;
40};
41
42struct mlx5e_sq_param {
43 u32 sqc[MLX5_ST_SZ_DW(sqc)];
44 struct mlx5_wq_param wq;
58d52291 45 u16 max_inline;
f62b8bb8
AV		 46};
47
48struct mlx5e_cq_param {
49 u32 cqc[MLX5_ST_SZ_DW(cqc)];
50 struct mlx5_wq_param wq;
51 u16 eq_ix;
52};
53
54struct mlx5e_channel_param {
55 struct mlx5e_rq_param rq;
56 struct mlx5e_sq_param sq;
57 struct mlx5e_cq_param rx_cq;
58 struct mlx5e_cq_param tx_cq;
59};
60
61static void mlx5e_update_carrier(struct mlx5e_priv *priv)
62{
63 struct mlx5_core_dev *mdev = priv->mdev;
64 u8 port_state;
65
66 port_state = mlx5_query_vport_state(mdev,
e7546514 67 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 68
69 if (port_state == VPORT_STATE_UP)
70 netif_carrier_on(priv->netdev);
71 else
72 netif_carrier_off(priv->netdev);
73}
74
75static void mlx5e_update_carrier_work(struct work_struct *work)
76{
77 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
78 update_carrier_work);
79
80 mutex_lock(&priv->state_lock);
81 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
82 mlx5e_update_carrier(priv);
83 mutex_unlock(&priv->state_lock);
84}
85
efea389d
GP		 86static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
87{
88 struct mlx5_core_dev *mdev = priv->mdev;
89 struct mlx5e_pport_stats *s = &priv->stats.pport;
90 u32 *in;
91 u32 *out;
92 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
93
94 in = mlx5_vzalloc(sz);
95 out = mlx5_vzalloc(sz);
96 if (!in || !out)
97 goto free_out;
98
99 MLX5_SET(ppcnt_reg, in, local_port, 1);
100
101 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
102 mlx5_core_access_reg(mdev, in, sz, out,
103 sz, MLX5_REG_PPCNT, 0, 0);
104 memcpy(s->IEEE_802_3_counters,
105 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
106 sizeof(s->IEEE_802_3_counters));
107
108 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
109 mlx5_core_access_reg(mdev, in, sz, out,
110 sz, MLX5_REG_PPCNT, 0, 0);
111 memcpy(s->RFC_2863_counters,
112 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
113 sizeof(s->RFC_2863_counters));
114
115 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
116 mlx5_core_access_reg(mdev, in, sz, out,
117 sz, MLX5_REG_PPCNT, 0, 0);
118 memcpy(s->RFC_2819_counters,
119 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
120 sizeof(s->RFC_2819_counters));
121
122free_out:
123 kvfree(in);
124 kvfree(out);
125}
126
f62b8bb8
AV		 127void mlx5e_update_stats(struct mlx5e_priv *priv)
128{
129 struct mlx5_core_dev *mdev = priv->mdev;
130 struct mlx5e_vport_stats *s = &priv->stats.vport;
131 struct mlx5e_rq_stats *rq_stats;
132 struct mlx5e_sq_stats *sq_stats;
133 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
134 u32 *out;
135 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
136 u64 tx_offload_none;
137 int i, j;
138
139 out = mlx5_vzalloc(outlen);
140 if (!out)
141 return;
142
143 /* Collect firts the SW counters and then HW for consistency */
144 s->tso_packets = 0;
145 s->tso_bytes = 0;
146 s->tx_queue_stopped = 0;
147 s->tx_queue_wake = 0;
148 s->tx_queue_dropped = 0;
149 tx_offload_none = 0;
150 s->lro_packets = 0;
151 s->lro_bytes = 0;
152 s->rx_csum_none = 0;
bbceefce 153 s->rx_csum_sw = 0;
f62b8bb8
AV		 154 s->rx_wqe_err = 0;
155 for (i = 0; i < priv->params.num_channels; i++) {
156 rq_stats = &priv->channel[i]->rq.stats;
157
158 s->lro_packets += rq_stats->lro_packets;
159 s->lro_bytes += rq_stats->lro_bytes;
160 s->rx_csum_none += rq_stats->csum_none;
bbceefce 161 s->rx_csum_sw += rq_stats->csum_sw;
f62b8bb8
AV		 162 s->rx_wqe_err += rq_stats->wqe_err;
163
a4418a6c 164 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 165 sq_stats = &priv->channel[i]->sq[j].stats;
166
167 s->tso_packets += sq_stats->tso_packets;
168 s->tso_bytes += sq_stats->tso_bytes;
169 s->tx_queue_stopped += sq_stats->stopped;
170 s->tx_queue_wake += sq_stats->wake;
171 s->tx_queue_dropped += sq_stats->dropped;
172 tx_offload_none += sq_stats->csum_offload_none;
173 }
174 }
175
176 /* HW counters */
177 memset(in, 0, sizeof(in));
178
179 MLX5_SET(query_vport_counter_in, in, opcode,
180 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
181 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
182 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
183
184 memset(out, 0, outlen);
185
186 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
187 goto free_out;
188
189#define MLX5_GET_CTR(p, x) \
190 MLX5_GET64(query_vport_counter_out, p, x)
191
192 s->rx_error_packets =
193 MLX5_GET_CTR(out, received_errors.packets);
194 s->rx_error_bytes =
195 MLX5_GET_CTR(out, received_errors.octets);
196 s->tx_error_packets =
197 MLX5_GET_CTR(out, transmit_errors.packets);
198 s->tx_error_bytes =
199 MLX5_GET_CTR(out, transmit_errors.octets);
200
201 s->rx_unicast_packets =
202 MLX5_GET_CTR(out, received_eth_unicast.packets);
203 s->rx_unicast_bytes =
204 MLX5_GET_CTR(out, received_eth_unicast.octets);
205 s->tx_unicast_packets =
206 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
207 s->tx_unicast_bytes =
208 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
209
210 s->rx_multicast_packets =
211 MLX5_GET_CTR(out, received_eth_multicast.packets);
212 s->rx_multicast_bytes =
213 MLX5_GET_CTR(out, received_eth_multicast.octets);
214 s->tx_multicast_packets =
215 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
216 s->tx_multicast_bytes =
217 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
218
219 s->rx_broadcast_packets =
220 MLX5_GET_CTR(out, received_eth_broadcast.packets);
221 s->rx_broadcast_bytes =
222 MLX5_GET_CTR(out, received_eth_broadcast.octets);
223 s->tx_broadcast_packets =
224 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
225 s->tx_broadcast_bytes =
226 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
227
228 s->rx_packets =
229 s->rx_unicast_packets +
230 s->rx_multicast_packets +
231 s->rx_broadcast_packets;
232 s->rx_bytes =
233 s->rx_unicast_bytes +
234 s->rx_multicast_bytes +
235 s->rx_broadcast_bytes;
236 s->tx_packets =
237 s->tx_unicast_packets +
238 s->tx_multicast_packets +
239 s->tx_broadcast_packets;
240 s->tx_bytes =
241 s->tx_unicast_bytes +
242 s->tx_multicast_bytes +
243 s->tx_broadcast_bytes;
244
245 /* Update calculated offload counters */
246 s->tx_csum_offload = s->tx_packets - tx_offload_none;
bbceefce
AS		 247 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
248 s->rx_csum_sw;
f62b8bb8 249
efea389d 250 mlx5e_update_pport_counters(priv);
f62b8bb8
AV		 251free_out:
252 kvfree(out);
253}
254
255static void mlx5e_update_stats_work(struct work_struct *work)
256{
257 struct delayed_work *dwork = to_delayed_work(work);
258 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
259 update_stats_work);
260 mutex_lock(&priv->state_lock);
261 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
262 mlx5e_update_stats(priv);
263 schedule_delayed_work(dwork,
264 msecs_to_jiffies(
265 MLX5E_UPDATE_STATS_INTERVAL));
266 }
267 mutex_unlock(&priv->state_lock);
268}
269
270static void __mlx5e_async_event(struct mlx5e_priv *priv,
271 enum mlx5_dev_event event)
272{
273 switch (event) {
274 case MLX5_DEV_EVENT_PORT_UP:
275 case MLX5_DEV_EVENT_PORT_DOWN:
276 schedule_work(&priv->update_carrier_work);
277 break;
278
279 default:
280 break;
281 }
282}
283
284static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
285 enum mlx5_dev_event event, unsigned long param)
286{
287 struct mlx5e_priv *priv = vpriv;
288
289 spin_lock(&priv->async_events_spinlock);
290 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
291 __mlx5e_async_event(priv, event);
292 spin_unlock(&priv->async_events_spinlock);
293}
294
295static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
296{
297 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
298}
299
300static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
301{
302 spin_lock_irq(&priv->async_events_spinlock);
303 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
304 spin_unlock_irq(&priv->async_events_spinlock);
305}
306
facc9699
SM		 307#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
308#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
309
f62b8bb8
AV		 310static int mlx5e_create_rq(struct mlx5e_channel *c,
311 struct mlx5e_rq_param *param,
312 struct mlx5e_rq *rq)
313{
314 struct mlx5e_priv *priv = c->priv;
315 struct mlx5_core_dev *mdev = priv->mdev;
316 void *rqc = param->rqc;
317 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
318 int wq_sz;
319 int err;
320 int i;
321
311c7c71
SM		 322 param->wq.db_numa_node = cpu_to_node(c->cpu);
323
f62b8bb8
AV		 324 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
325 &rq->wq_ctrl);
326 if (err)
327 return err;
328
329 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
330
331 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
332 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
333 cpu_to_node(c->cpu));
334 if (!rq->skb) {
335 err = -ENOMEM;
336 goto err_rq_wq_destroy;
337 }
338
339 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 340 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 341 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 342
343 for (i = 0; i < wq_sz; i++) {
344 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 345 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 346
347 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 348 wqe->data.byte_count =
349 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 350 }
351
352 rq->pdev = c->pdev;
353 rq->netdev = c->netdev;
ef9814de 354 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 355 rq->channel = c;
356 rq->ix = c->ix;
50cfa25a 357 rq->priv = c->priv;
f62b8bb8
AV		 358
359 return 0;
360
361err_rq_wq_destroy:
362 mlx5_wq_destroy(&rq->wq_ctrl);
363
364 return err;
365}
366
367static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
368{
369 kfree(rq->skb);
370 mlx5_wq_destroy(&rq->wq_ctrl);
371}
372
373static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
374{
50cfa25a 375 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 376 struct mlx5_core_dev *mdev = priv->mdev;
377
378 void *in;
379 void *rqc;
380 void *wq;
381 int inlen;
382 int err;
383
384 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
385 sizeof(u64) * rq->wq_ctrl.buf.npages;
386 in = mlx5_vzalloc(inlen);
387 if (!in)
388 return -ENOMEM;
389
390 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
391 wq = MLX5_ADDR_OF(rqc, rqc, wq);
392
393 memcpy(rqc, param->rqc, sizeof(param->rqc));
394
97de9f31 395 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 396 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
397 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8 398 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 399 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 400 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
401
402 mlx5_fill_page_array(&rq->wq_ctrl.buf,
403 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
404
7db22ffb 405 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 406
407 kvfree(in);
408
409 return err;
410}
411
412static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
413{
414 struct mlx5e_channel *c = rq->channel;
415 struct mlx5e_priv *priv = c->priv;
416 struct mlx5_core_dev *mdev = priv->mdev;
417
418 void *in;
419 void *rqc;
420 int inlen;
421 int err;
422
423 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
424 in = mlx5_vzalloc(inlen);
425 if (!in)
426 return -ENOMEM;
427
428 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
429
430 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
431 MLX5_SET(rqc, rqc, state, next_state);
432
7db22ffb 433 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 434
435 kvfree(in);
436
437 return err;
438}
439
440static void mlx5e_disable_rq(struct mlx5e_rq *rq)
441{
50cfa25a 442 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 443}
444
445static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
446{
01c196a2 447 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 448 struct mlx5e_channel *c = rq->channel;
449 struct mlx5e_priv *priv = c->priv;
450 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 451
01c196a2 452 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 453 if (wq->cur_sz >= priv->params.min_rx_wqes)
454 return 0;
455
456 msleep(20);
457 }
458
459 return -ETIMEDOUT;
460}
461
462static int mlx5e_open_rq(struct mlx5e_channel *c,
463 struct mlx5e_rq_param *param,
464 struct mlx5e_rq *rq)
465{
466 int err;
467
468 err = mlx5e_create_rq(c, param, rq);
469 if (err)
470 return err;
471
472 err = mlx5e_enable_rq(rq, param);
473 if (err)
474 goto err_destroy_rq;
475
476 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
477 if (err)
478 goto err_disable_rq;
479
480 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 481 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 482
483 return 0;
484
485err_disable_rq:
486 mlx5e_disable_rq(rq);
487err_destroy_rq:
488 mlx5e_destroy_rq(rq);
489
490 return err;
491}
492
493static void mlx5e_close_rq(struct mlx5e_rq *rq)
494{
495 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
496 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
497
498 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
499 while (!mlx5_wq_ll_is_empty(&rq->wq))
500 msleep(20);
501
502 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
503 napi_synchronize(&rq->channel->napi);
504
505 mlx5e_disable_rq(rq);
506 mlx5e_destroy_rq(rq);
507}
508
509static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
510{
34802a42 511 kfree(sq->wqe_info);
f62b8bb8
AV		 512 kfree(sq->dma_fifo);
513 kfree(sq->skb);
514}
515
516static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
517{
518 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
519 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
520
521 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
522 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
523 numa);
34802a42
AS		 524 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
525 numa);
f62b8bb8 526
34802a42 527 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 528 mlx5e_free_sq_db(sq);
529 return -ENOMEM;
530 }
531
532 sq->dma_fifo_mask = df_sz - 1;
533
534 return 0;
535}
536
537static int mlx5e_create_sq(struct mlx5e_channel *c,
538 int tc,
539 struct mlx5e_sq_param *param,
540 struct mlx5e_sq *sq)
541{
542 struct mlx5e_priv *priv = c->priv;
543 struct mlx5_core_dev *mdev = priv->mdev;
544
545 void *sqc = param->sqc;
546 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
03289b88 547 int txq_ix;
f62b8bb8
AV		 548 int err;
549
550 err = mlx5_alloc_map_uar(mdev, &sq->uar);
551 if (err)
552 return err;
553
311c7c71
SM		 554 param->wq.db_numa_node = cpu_to_node(c->cpu);
555
f62b8bb8
AV		 556 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
557 &sq->wq_ctrl);
558 if (err)
559 goto err_unmap_free_uar;
560
561 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
562 sq->uar_map = sq->uar.map;
88a85f99 563 sq->uar_bf_map = sq->uar.bf_map;
f62b8bb8 564 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 565 sq->max_inline = param->max_inline;
f62b8bb8 566
7ec0bb22
DC		 567 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
568 if (err)
f62b8bb8
AV		 569 goto err_sq_wq_destroy;
570
03289b88
SM		 571 txq_ix = c->ix + tc * priv->params.num_channels;
572 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
f62b8bb8 573
88a85f99 574 sq->pdev = c->pdev;
ef9814de 575 sq->tstamp = &priv->tstamp;
88a85f99
AS		 576 sq->mkey_be = c->mkey_be;
577 sq->channel = c;
578 sq->tc = tc;
579 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
580 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
03289b88 581 priv->txq_to_sq_map[txq_ix] = sq;
f62b8bb8
AV		 582
583 return 0;
584
585err_sq_wq_destroy:
586 mlx5_wq_destroy(&sq->wq_ctrl);
587
588err_unmap_free_uar:
589 mlx5_unmap_free_uar(mdev, &sq->uar);
590
591 return err;
592}
593
594static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
595{
596 struct mlx5e_channel *c = sq->channel;
597 struct mlx5e_priv *priv = c->priv;
598
599 mlx5e_free_sq_db(sq);
600 mlx5_wq_destroy(&sq->wq_ctrl);
601 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
602}
603
604static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
605{
606 struct mlx5e_channel *c = sq->channel;
607 struct mlx5e_priv *priv = c->priv;
608 struct mlx5_core_dev *mdev = priv->mdev;
609
610 void *in;
611 void *sqc;
612 void *wq;
613 int inlen;
614 int err;
615
616 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
617 sizeof(u64) * sq->wq_ctrl.buf.npages;
618 in = mlx5_vzalloc(inlen);
619 if (!in)
620 return -ENOMEM;
621
622 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
623 wq = MLX5_ADDR_OF(sqc, sqc, wq);
624
625 memcpy(sqc, param->sqc, sizeof(param->sqc));
626
f62b8bb8
AV		 627 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
628 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
629 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
630 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
631 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
632
633 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
634 MLX5_SET(wq, wq, uar_page, sq->uar.index);
635 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 636 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 637 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
638
639 mlx5_fill_page_array(&sq->wq_ctrl.buf,
640 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
641
7db22ffb 642 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 643
644 kvfree(in);
645
646 return err;
647}
648
649static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
650{
651 struct mlx5e_channel *c = sq->channel;
652 struct mlx5e_priv *priv = c->priv;
653 struct mlx5_core_dev *mdev = priv->mdev;
654
655 void *in;
656 void *sqc;
657 int inlen;
658 int err;
659
660 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
661 in = mlx5_vzalloc(inlen);
662 if (!in)
663 return -ENOMEM;
664
665 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
666
667 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
668 MLX5_SET(sqc, sqc, state, next_state);
669
7db22ffb 670 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 671
672 kvfree(in);
673
674 return err;
675}
676
677static void mlx5e_disable_sq(struct mlx5e_sq *sq)
678{
679 struct mlx5e_channel *c = sq->channel;
680 struct mlx5e_priv *priv = c->priv;
681 struct mlx5_core_dev *mdev = priv->mdev;
682
7db22ffb 683 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 684}
685
686static int mlx5e_open_sq(struct mlx5e_channel *c,
687 int tc,
688 struct mlx5e_sq_param *param,
689 struct mlx5e_sq *sq)
690{
691 int err;
692
693 err = mlx5e_create_sq(c, tc, param, sq);
694 if (err)
695 return err;
696
697 err = mlx5e_enable_sq(sq, param);
698 if (err)
699 goto err_destroy_sq;
700
701 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
702 if (err)
703 goto err_disable_sq;
704
705 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
706 netdev_tx_reset_queue(sq->txq);
707 netif_tx_start_queue(sq->txq);
708
709 return 0;
710
711err_disable_sq:
712 mlx5e_disable_sq(sq);
713err_destroy_sq:
714 mlx5e_destroy_sq(sq);
715
716 return err;
717}
718
719static inline void netif_tx_disable_queue(struct netdev_queue *txq)
720{
721 __netif_tx_lock_bh(txq);
722 netif_tx_stop_queue(txq);
723 __netif_tx_unlock_bh(txq);
724}
725
726static void mlx5e_close_sq(struct mlx5e_sq *sq)
727{
728 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
729 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
730 netif_tx_disable_queue(sq->txq);
731
732 /* ensure hw is notified of all pending wqes */
733 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 734 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 735
736 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
737 while (sq->cc != sq->pc) /* wait till sq is empty */
738 msleep(20);
739
740 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
741 napi_synchronize(&sq->channel->napi);
742
743 mlx5e_disable_sq(sq);
744 mlx5e_destroy_sq(sq);
745}
746
747static int mlx5e_create_cq(struct mlx5e_channel *c,
748 struct mlx5e_cq_param *param,
749 struct mlx5e_cq *cq)
750{
751 struct mlx5e_priv *priv = c->priv;
752 struct mlx5_core_dev *mdev = priv->mdev;
753 struct mlx5_core_cq *mcq = &cq->mcq;
754 int eqn_not_used;
0b6e26ce 755 unsigned int irqn;
f62b8bb8
AV		 756 int err;
757 u32 i;
758
311c7c71
SM		 759 param->wq.buf_numa_node = cpu_to_node(c->cpu);
760 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 761 param->eq_ix = c->ix;
762
763 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
764 &cq->wq_ctrl);
765 if (err)
766 return err;
767
768 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
769
770 cq->napi = &c->napi;
771
772 mcq->cqe_sz = 64;
773 mcq->set_ci_db = cq->wq_ctrl.db.db;
774 mcq->arm_db = cq->wq_ctrl.db.db + 1;
775 *mcq->set_ci_db = 0;
776 *mcq->arm_db = 0;
777 mcq->vector = param->eq_ix;
778 mcq->comp = mlx5e_completion_event;
779 mcq->event = mlx5e_cq_error_event;
780 mcq->irqn = irqn;
781 mcq->uar = &priv->cq_uar;
782
783 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
784 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
785
786 cqe->op_own = 0xf1;
787 }
788
789 cq->channel = c;
50cfa25a 790 cq->priv = priv;
f62b8bb8
AV		 791
792 return 0;
793}
794
795static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
796{
797 mlx5_wq_destroy(&cq->wq_ctrl);
798}
799
800static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
801{
50cfa25a 802 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 803 struct mlx5_core_dev *mdev = priv->mdev;
804 struct mlx5_core_cq *mcq = &cq->mcq;
805
806 void *in;
807 void *cqc;
808 int inlen;
0b6e26ce 809 unsigned int irqn_not_used;
f62b8bb8
AV		 810 int eqn;
811 int err;
812
813 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
814 sizeof(u64) * cq->wq_ctrl.buf.npages;
815 in = mlx5_vzalloc(inlen);
816 if (!in)
817 return -ENOMEM;
818
819 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
820
821 memcpy(cqc, param->cqc, sizeof(param->cqc));
822
823 mlx5_fill_page_array(&cq->wq_ctrl.buf,
824 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
825
826 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
827
828 MLX5_SET(cqc, cqc, c_eqn, eqn);
829 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
830 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 831 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 832 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
833
834 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
835
836 kvfree(in);
837
838 if (err)
839 return err;
840
841 mlx5e_cq_arm(cq);
842
843 return 0;
844}
845
846static void mlx5e_disable_cq(struct mlx5e_cq *cq)
847{
50cfa25a 848 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 849 struct mlx5_core_dev *mdev = priv->mdev;
850
851 mlx5_core_destroy_cq(mdev, &cq->mcq);
852}
853
854static int mlx5e_open_cq(struct mlx5e_channel *c,
855 struct mlx5e_cq_param *param,
856 struct mlx5e_cq *cq,
857 u16 moderation_usecs,
858 u16 moderation_frames)
859{
860 int err;
861 struct mlx5e_priv *priv = c->priv;
862 struct mlx5_core_dev *mdev = priv->mdev;
863
864 err = mlx5e_create_cq(c, param, cq);
865 if (err)
866 return err;
867
868 err = mlx5e_enable_cq(cq, param);
869 if (err)
870 goto err_destroy_cq;
871
872 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
873 moderation_usecs,
874 moderation_frames);
875 if (err)
876 goto err_destroy_cq;
877
878 return 0;
879
880err_destroy_cq:
881 mlx5e_destroy_cq(cq);
882
883 return err;
884}
885
886static void mlx5e_close_cq(struct mlx5e_cq *cq)
887{
888 mlx5e_disable_cq(cq);
889 mlx5e_destroy_cq(cq);
890}
891
892static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
893{
894 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
895}
896
897static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
898 struct mlx5e_channel_param *cparam)
899{
900 struct mlx5e_priv *priv = c->priv;
901 int err;
902 int tc;
903
904 for (tc = 0; tc < c->num_tc; tc++) {
905 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
906 priv->params.tx_cq_moderation_usec,
907 priv->params.tx_cq_moderation_pkts);
908 if (err)
909 goto err_close_tx_cqs;
f62b8bb8
AV		 910 }
911
912 return 0;
913
914err_close_tx_cqs:
915 for (tc--; tc >= 0; tc--)
916 mlx5e_close_cq(&c->sq[tc].cq);
917
918 return err;
919}
920
921static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
922{
923 int tc;
924
925 for (tc = 0; tc < c->num_tc; tc++)
926 mlx5e_close_cq(&c->sq[tc].cq);
927}
928
929static int mlx5e_open_sqs(struct mlx5e_channel *c,
930 struct mlx5e_channel_param *cparam)
931{
932 int err;
933 int tc;
934
935 for (tc = 0; tc < c->num_tc; tc++) {
936 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
937 if (err)
938 goto err_close_sqs;
939 }
940
941 return 0;
942
943err_close_sqs:
944 for (tc--; tc >= 0; tc--)
945 mlx5e_close_sq(&c->sq[tc]);
946
947 return err;
948}
949
950static void mlx5e_close_sqs(struct mlx5e_channel *c)
951{
952 int tc;
953
954 for (tc = 0; tc < c->num_tc; tc++)
955 mlx5e_close_sq(&c->sq[tc]);
956}
957
5283af89 958static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 959{
960 int i;
961
962 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 963 priv->channeltc_to_txq_map[ix][i] =
964 ix + i * priv->params.num_channels;
03289b88
SM		 965}
966
f62b8bb8
AV		 967static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
968 struct mlx5e_channel_param *cparam,
969 struct mlx5e_channel **cp)
970{
971 struct net_device *netdev = priv->netdev;
972 int cpu = mlx5e_get_cpu(priv, ix);
973 struct mlx5e_channel *c;
974 int err;
975
976 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
977 if (!c)
978 return -ENOMEM;
979
980 c->priv = priv;
981 c->ix = ix;
982 c->cpu = cpu;
983 c->pdev = &priv->mdev->pdev->dev;
984 c->netdev = priv->netdev;
985 c->mkey_be = cpu_to_be32(priv->mr.key);
a4418a6c 986 c->num_tc = priv->params.num_tc;
f62b8bb8 987
5283af89 988 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 989
f62b8bb8
AV		 990 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
991
992 err = mlx5e_open_tx_cqs(c, cparam);
993 if (err)
994 goto err_napi_del;
995
996 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
997 priv->params.rx_cq_moderation_usec,
998 priv->params.rx_cq_moderation_pkts);
999 if (err)
1000 goto err_close_tx_cqs;
f62b8bb8
AV		 1001
1002 napi_enable(&c->napi);
1003
1004 err = mlx5e_open_sqs(c, cparam);
1005 if (err)
1006 goto err_disable_napi;
1007
1008 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1009 if (err)
1010 goto err_close_sqs;
1011
1012 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1013 *cp = c;
1014
1015 return 0;
1016
1017err_close_sqs:
1018 mlx5e_close_sqs(c);
1019
1020err_disable_napi:
1021 napi_disable(&c->napi);
1022 mlx5e_close_cq(&c->rq.cq);
1023
1024err_close_tx_cqs:
1025 mlx5e_close_tx_cqs(c);
1026
1027err_napi_del:
1028 netif_napi_del(&c->napi);
7ae92ae5 1029 napi_hash_del(&c->napi);
f62b8bb8
AV		 1030 kfree(c);
1031
1032 return err;
1033}
1034
1035static void mlx5e_close_channel(struct mlx5e_channel *c)
1036{
1037 mlx5e_close_rq(&c->rq);
1038 mlx5e_close_sqs(c);
1039 napi_disable(&c->napi);
1040 mlx5e_close_cq(&c->rq.cq);
1041 mlx5e_close_tx_cqs(c);
1042 netif_napi_del(&c->napi);
7ae92ae5
ED		 1043
1044 napi_hash_del(&c->napi);
1045 synchronize_rcu();
1046
f62b8bb8
AV		 1047 kfree(c);
1048}
1049
1050static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1051 struct mlx5e_rq_param *param)
1052{
1053 void *rqc = param->rqc;
1054 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1055
1056 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1057 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1058 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1059 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1060 MLX5_SET(wq, wq, pd, priv->pdn);
1061
311c7c71 1062 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1063 param->wq.linear = 1;
1064}
1065
1066static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1067 struct mlx5e_sq_param *param)
1068{
1069 void *sqc = param->sqc;
1070 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1071
1072 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1073 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1074 MLX5_SET(wq, wq, pd, priv->pdn);
1075
311c7c71 1076 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
58d52291 1077 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1078}
1079
1080static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1081 struct mlx5e_cq_param *param)
1082{
1083 void *cqc = param->cqc;
1084
1085 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1086}
1087
1088static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1089 struct mlx5e_cq_param *param)
1090{
1091 void *cqc = param->cqc;
1092
1093 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1094
1095 mlx5e_build_common_cq_param(priv, param);
1096}
1097
1098static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1099 struct mlx5e_cq_param *param)
1100{
1101 void *cqc = param->cqc;
1102
1103 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1104
1105 mlx5e_build_common_cq_param(priv, param);
1106}
1107
1108static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1109 struct mlx5e_channel_param *cparam)
1110{
1111 memset(cparam, 0, sizeof(*cparam));
1112
1113 mlx5e_build_rq_param(priv, &cparam->rq);
1114 mlx5e_build_sq_param(priv, &cparam->sq);
1115 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1116 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1117}
1118
1119static int mlx5e_open_channels(struct mlx5e_priv *priv)
1120{
1121 struct mlx5e_channel_param cparam;
a4418a6c 1122 int nch = priv->params.num_channels;
03289b88 1123 int err = -ENOMEM;
f62b8bb8
AV		 1124 int i;
1125 int j;
1126
a4418a6c
AS		 1127 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1128 GFP_KERNEL);
03289b88 1129
a4418a6c 1130 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1131 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1132
1133 if (!priv->channel || !priv->txq_to_sq_map)
1134 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1135
1136 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1137 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1138 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1139 if (err)
1140 goto err_close_channels;
1141 }
1142
a4418a6c 1143 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1144 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1145 if (err)
1146 goto err_close_channels;
1147 }
1148
1149 return 0;
1150
1151err_close_channels:
1152 for (i--; i >= 0; i--)
1153 mlx5e_close_channel(priv->channel[i]);
1154
03289b88
SM		 1155err_free_txq_to_sq_map:
1156 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1157 kfree(priv->channel);
1158
1159 return err;
1160}
1161
1162static void mlx5e_close_channels(struct mlx5e_priv *priv)
1163{
1164 int i;
1165
1166 for (i = 0; i < priv->params.num_channels; i++)
1167 mlx5e_close_channel(priv->channel[i]);
1168
03289b88 1169 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1170 kfree(priv->channel);
1171}
1172
2be6967c
SM		 1173static int mlx5e_rx_hash_fn(int hfunc)
1174{
1175 return (hfunc == ETH_RSS_HASH_TOP) ?
1176 MLX5_RX_HASH_FN_TOEPLITZ :
1177 MLX5_RX_HASH_FN_INVERTED_XOR8;
1178}
1179
1180static int mlx5e_bits_invert(unsigned long a, int size)
1181{
1182 int inv = 0;
1183 int i;
1184
1185 for (i = 0; i < size; i++)
1186 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1187
1188 return inv;
1189}
1190
936896e9
AS		 1191static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1192{
1193 int i;
1194
1195 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1196 int ix = i;
1197
1198 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1199 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1200
2d75b2bc 1201 ix = priv->params.indirection_rqt[ix];
936896e9
AS		 1202 MLX5_SET(rqtc, rqtc, rq_num[i],
1203 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1204 priv->channel[ix]->rq.rqn :
1205 priv->drop_rq.rqn);
1206 }
1207}
1208
4cbeaff5
AS		 1209static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1210 enum mlx5e_rqt_ix rqt_ix)
1211{
4cbeaff5
AS		 1212
1213 switch (rqt_ix) {
1214 case MLX5E_INDIRECTION_RQT:
936896e9 1215 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
4cbeaff5
AS		 1216
1217 break;
1218
1219 default: /* MLX5E_SINGLE_RQ_RQT */
1220 MLX5_SET(rqtc, rqtc, rq_num[0],
5c50368f
AS		 1221 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1222 priv->channel[0]->rq.rqn :
1223 priv->drop_rq.rqn);
4cbeaff5
AS		 1224
1225 break;
1226 }
1227}
1228
40ab6a6e 1229static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1230{
1231 struct mlx5_core_dev *mdev = priv->mdev;
1232 u32 *in;
f62b8bb8
AV		 1233 void *rqtc;
1234 int inlen;
4cbeaff5 1235 int sz;
f62b8bb8 1236 int err;
4cbeaff5 1237
936896e9 1238 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
f62b8bb8 1239
f62b8bb8
AV		 1240 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1241 in = mlx5_vzalloc(inlen);
1242 if (!in)
1243 return -ENOMEM;
1244
1245 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1246
1247 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1248 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1249
4cbeaff5 1250 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1251
4cbeaff5 1252 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1253
1254 kvfree(in);
1255
1256 return err;
1257}
1258
2d75b2bc 1259int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
5c50368f
AS		 1260{
1261 struct mlx5_core_dev *mdev = priv->mdev;
1262 u32 *in;
1263 void *rqtc;
1264 int inlen;
5c50368f
AS		 1265 int sz;
1266 int err;
1267
936896e9 1268 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
5c50368f
AS		 1269
1270 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1271 in = mlx5_vzalloc(inlen);
1272 if (!in)
1273 return -ENOMEM;
1274
1275 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1276
1277 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1278
1279 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1280
1281 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1282
1283 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1284
1285 kvfree(in);
1286
1287 return err;
1288}
1289
40ab6a6e 1290static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1291{
4cbeaff5 1292 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1293}
1294
40ab6a6e
AS		 1295static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1296{
1297 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1298 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1299}
1300
5c50368f
AS		 1301static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1302{
1303 if (!priv->params.lro_en)
1304 return;
1305
1306#define ROUGH_MAX_L2_L3_HDR_SZ 256
1307
1308 MLX5_SET(tirc, tirc, lro_enable_mask,
1309 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1310 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1311 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1312 (priv->params.lro_wqe_sz -
1313 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1314 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1315 MLX5_CAP_ETH(priv->mdev,
d9a40271 1316 lro_timer_supported_periods[2]));
5c50368f
AS		 1317}
1318
bdfc028d
TT		 1319void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1320{
1321 MLX5_SET(tirc, tirc, rx_hash_fn,
1322 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1323 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1324 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1325 rx_hash_toeplitz_key);
1326 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1327 rx_hash_toeplitz_key);
1328
1329 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1330 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1331 }
1332}
1333
ab0394fe 1334static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1335{
1336 struct mlx5_core_dev *mdev = priv->mdev;
1337
1338 void *in;
1339 void *tirc;
1340 int inlen;
1341 int err;
ab0394fe 1342 int tt;
5c50368f
AS		 1343
1344 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1345 in = mlx5_vzalloc(inlen);
1346 if (!in)
1347 return -ENOMEM;
1348
1349 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1350 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1351
1352 mlx5e_build_tir_ctx_lro(tirc, priv);
1353
ab0394fe
TT		 1354 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1355 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1356 if (err)
1357 break;
1358 }
5c50368f
AS		 1359
1360 kvfree(in);
1361
1362 return err;
1363}
1364
66189961
TT		 1365static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1366 u32 tirn)
1367{
1368 void *in;
1369 int inlen;
1370 int err;
1371
1372 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1373 in = mlx5_vzalloc(inlen);
1374 if (!in)
1375 return -ENOMEM;
1376
1377 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1378
1379 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1380
1381 kvfree(in);
1382
1383 return err;
1384}
1385
1386static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1387{
1388 int err;
1389 int i;
1390
1391 for (i = 0; i < MLX5E_NUM_TT; i++) {
1392 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1393 priv->tirn[i]);
1394 if (err)
1395 return err;
1396 }
1397
1398 return 0;
1399}
1400
40ab6a6e
AS		 1401static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1402{
1403 struct mlx5e_priv *priv = netdev_priv(netdev);
1404 struct mlx5_core_dev *mdev = priv->mdev;
1405 int hw_mtu;
1406 int err;
1407
1408 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1409 if (err)
1410 return err;
1411
1412 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1413
1414 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1415 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1416 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1417
1418 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1419 return 0;
1420}
1421
1422int mlx5e_open_locked(struct net_device *netdev)
1423{
1424 struct mlx5e_priv *priv = netdev_priv(netdev);
1425 int num_txqs;
1426 int err;
1427
1428 set_bit(MLX5E_STATE_OPENED, &priv->state);
1429
1430 num_txqs = priv->params.num_channels * priv->params.num_tc;
1431 netif_set_real_num_tx_queues(netdev, num_txqs);
1432 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1433
1434 err = mlx5e_set_dev_port_mtu(netdev);
1435 if (err)
343b29f3 1436 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1437
1438 err = mlx5e_open_channels(priv);
1439 if (err) {
1440 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1441 __func__, err);
343b29f3 1442 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1443 }
1444
66189961
TT		 1445 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1446 if (err) {
1447 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1448 __func__, err);
1449 goto err_close_channels;
1450 }
1451
40ab6a6e
AS		 1452 mlx5e_update_carrier(priv);
1453 mlx5e_redirect_rqts(priv);
ef9814de 1454 mlx5e_timestamp_init(priv);
40ab6a6e
AS		 1455
1456 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1457
9b37b07f 1458 return 0;
343b29f3 1459
66189961
TT		 1460err_close_channels:
1461 mlx5e_close_channels(priv);
343b29f3
AS		 1462err_clear_state_opened_flag:
1463 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1464 return err;
40ab6a6e
AS		 1465}
1466
1467static int mlx5e_open(struct net_device *netdev)
1468{
1469 struct mlx5e_priv *priv = netdev_priv(netdev);
1470 int err;
1471
1472 mutex_lock(&priv->state_lock);
1473 err = mlx5e_open_locked(netdev);
1474 mutex_unlock(&priv->state_lock);
1475
1476 return err;
1477}
1478
1479int mlx5e_close_locked(struct net_device *netdev)
1480{
1481 struct mlx5e_priv *priv = netdev_priv(netdev);
1482
a1985740
AS		 1483 /* May already be CLOSED in case a previous configuration operation
1484 * (e.g RX/TX queue size change) that involves close&open failed.
1485 */
1486 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1487 return 0;
1488
40ab6a6e
AS		 1489 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1490
ef9814de 1491 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1492 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1493 netif_carrier_off(priv->netdev);
1494 mlx5e_close_channels(priv);
1495
1496 return 0;
1497}
1498
1499static int mlx5e_close(struct net_device *netdev)
1500{
1501 struct mlx5e_priv *priv = netdev_priv(netdev);
1502 int err;
1503
1504 mutex_lock(&priv->state_lock);
1505 err = mlx5e_close_locked(netdev);
1506 mutex_unlock(&priv->state_lock);
1507
1508 return err;
1509}
1510
1511static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1512 struct mlx5e_rq *rq,
1513 struct mlx5e_rq_param *param)
1514{
1515 struct mlx5_core_dev *mdev = priv->mdev;
1516 void *rqc = param->rqc;
1517 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1518 int err;
1519
1520 param->wq.db_numa_node = param->wq.buf_numa_node;
1521
1522 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1523 &rq->wq_ctrl);
1524 if (err)
1525 return err;
1526
1527 rq->priv = priv;
1528
1529 return 0;
1530}
1531
1532static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1533 struct mlx5e_cq *cq,
1534 struct mlx5e_cq_param *param)
1535{
1536 struct mlx5_core_dev *mdev = priv->mdev;
1537 struct mlx5_core_cq *mcq = &cq->mcq;
1538 int eqn_not_used;
0b6e26ce 1539 unsigned int irqn;
40ab6a6e
AS		 1540 int err;
1541
1542 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1543 &cq->wq_ctrl);
1544 if (err)
1545 return err;
1546
1547 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1548
1549 mcq->cqe_sz = 64;
1550 mcq->set_ci_db = cq->wq_ctrl.db.db;
1551 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1552 *mcq->set_ci_db = 0;
1553 *mcq->arm_db = 0;
1554 mcq->vector = param->eq_ix;
1555 mcq->comp = mlx5e_completion_event;
1556 mcq->event = mlx5e_cq_error_event;
1557 mcq->irqn = irqn;
1558 mcq->uar = &priv->cq_uar;
1559
1560 cq->priv = priv;
1561
1562 return 0;
1563}
1564
1565static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1566{
1567 struct mlx5e_cq_param cq_param;
1568 struct mlx5e_rq_param rq_param;
1569 struct mlx5e_rq *rq = &priv->drop_rq;
1570 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1571 int err;
1572
1573 memset(&cq_param, 0, sizeof(cq_param));
1574 memset(&rq_param, 0, sizeof(rq_param));
1575 mlx5e_build_rx_cq_param(priv, &cq_param);
1576 mlx5e_build_rq_param(priv, &rq_param);
1577
1578 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1579 if (err)
1580 return err;
1581
1582 err = mlx5e_enable_cq(cq, &cq_param);
1583 if (err)
1584 goto err_destroy_cq;
1585
1586 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1587 if (err)
1588 goto err_disable_cq;
1589
1590 err = mlx5e_enable_rq(rq, &rq_param);
1591 if (err)
1592 goto err_destroy_rq;
1593
1594 return 0;
1595
1596err_destroy_rq:
1597 mlx5e_destroy_rq(&priv->drop_rq);
1598
1599err_disable_cq:
1600 mlx5e_disable_cq(&priv->drop_rq.cq);
1601
1602err_destroy_cq:
1603 mlx5e_destroy_cq(&priv->drop_rq.cq);
1604
1605 return err;
1606}
1607
1608static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1609{
1610 mlx5e_disable_rq(&priv->drop_rq);
1611 mlx5e_destroy_rq(&priv->drop_rq);
1612 mlx5e_disable_cq(&priv->drop_rq.cq);
1613 mlx5e_destroy_cq(&priv->drop_rq.cq);
1614}
1615
1616static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1617{
1618 struct mlx5_core_dev *mdev = priv->mdev;
1619 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1620 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1621
1622 memset(in, 0, sizeof(in));
1623
1624 MLX5_SET(tisc, tisc, prio, tc);
1625 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1626
1627 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1628}
1629
1630static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1631{
1632 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1633}
1634
1635static int mlx5e_create_tises(struct mlx5e_priv *priv)
1636{
1637 int err;
1638 int tc;
1639
1640 for (tc = 0; tc < priv->params.num_tc; tc++) {
1641 err = mlx5e_create_tis(priv, tc);
1642 if (err)
1643 goto err_close_tises;
1644 }
1645
1646 return 0;
1647
1648err_close_tises:
1649 for (tc--; tc >= 0; tc--)
1650 mlx5e_destroy_tis(priv, tc);
1651
1652 return err;
1653}
1654
1655static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1656{
1657 int tc;
1658
1659 for (tc = 0; tc < priv->params.num_tc; tc++)
1660 mlx5e_destroy_tis(priv, tc);
1661}
1662
f62b8bb8
AV		 1663static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1664{
1665 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1666
3191e05f
AS		 1667 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1668
5a6f8aef
AS		 1669#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1670 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1671
5a6f8aef
AS		 1672#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1673 MLX5_HASH_FIELD_SEL_DST_IP |\
1674 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1675 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1676
a741749f
AS		 1677#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1678 MLX5_HASH_FIELD_SEL_DST_IP |\
1679 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1680
5c50368f 1681 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1682
4cbeaff5
AS		 1683 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1684
f62b8bb8
AV		 1685 switch (tt) {
1686 case MLX5E_TT_ANY:
4cbeaff5
AS		 1687 MLX5_SET(tirc, tirc, indirect_table,
1688 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1689 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1690 break;
1691 default:
f62b8bb8 1692 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1693 priv->rqtn[MLX5E_INDIRECTION_RQT]);
bdfc028d 1694 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 1695 break;
1696 }
1697
1698 switch (tt) {
1699 case MLX5E_TT_IPV4_TCP:
1700 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1701 MLX5_L3_PROT_TYPE_IPV4);
1702 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1703 MLX5_L4_PROT_TYPE_TCP);
1704 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1705 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1706 break;
1707
1708 case MLX5E_TT_IPV6_TCP:
1709 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1710 MLX5_L3_PROT_TYPE_IPV6);
1711 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1712 MLX5_L4_PROT_TYPE_TCP);
1713 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1714 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1715 break;
1716
1717 case MLX5E_TT_IPV4_UDP:
1718 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1719 MLX5_L3_PROT_TYPE_IPV4);
1720 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1721 MLX5_L4_PROT_TYPE_UDP);
1722 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1723 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1724 break;
1725
1726 case MLX5E_TT_IPV6_UDP:
1727 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1728 MLX5_L3_PROT_TYPE_IPV6);
1729 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1730 MLX5_L4_PROT_TYPE_UDP);
1731 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1732 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1733 break;
1734
a741749f
AS		 1735 case MLX5E_TT_IPV4_IPSEC_AH:
1736 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1737 MLX5_L3_PROT_TYPE_IPV4);
1738 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1739 MLX5_HASH_IP_IPSEC_SPI);
1740 break;
1741
1742 case MLX5E_TT_IPV6_IPSEC_AH:
1743 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1744 MLX5_L3_PROT_TYPE_IPV6);
1745 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1746 MLX5_HASH_IP_IPSEC_SPI);
1747 break;
1748
1749 case MLX5E_TT_IPV4_IPSEC_ESP:
1750 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1751 MLX5_L3_PROT_TYPE_IPV4);
1752 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1753 MLX5_HASH_IP_IPSEC_SPI);
1754 break;
1755
1756 case MLX5E_TT_IPV6_IPSEC_ESP:
1757 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1758 MLX5_L3_PROT_TYPE_IPV6);
1759 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1760 MLX5_HASH_IP_IPSEC_SPI);
1761 break;
1762
f62b8bb8
AV		 1763 case MLX5E_TT_IPV4:
1764 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1765 MLX5_L3_PROT_TYPE_IPV4);
1766 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1767 MLX5_HASH_IP);
1768 break;
1769
1770 case MLX5E_TT_IPV6:
1771 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1772 MLX5_L3_PROT_TYPE_IPV6);
1773 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1774 MLX5_HASH_IP);
1775 break;
1776 }
1777}
1778
40ab6a6e 1779static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8
AV		 1780{
1781 struct mlx5_core_dev *mdev = priv->mdev;
1782 u32 *in;
1783 void *tirc;
1784 int inlen;
1785 int err;
1786
1787 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1788 in = mlx5_vzalloc(inlen);
1789 if (!in)
1790 return -ENOMEM;
1791
1792 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1793
1794 mlx5e_build_tir_ctx(priv, tirc, tt);
1795
7db22ffb 1796 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1797
1798 kvfree(in);
1799
1800 return err;
1801}
1802
40ab6a6e 1803static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8 1804{
7db22ffb 1805 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1806}
1807
40ab6a6e 1808static int mlx5e_create_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1809{
1810 int err;
1811 int i;
1812
1813 for (i = 0; i < MLX5E_NUM_TT; i++) {
40ab6a6e 1814 err = mlx5e_create_tir(priv, i);
f62b8bb8 1815 if (err)
40ab6a6e 1816 goto err_destroy_tirs;
f62b8bb8
AV		 1817 }
1818
1819 return 0;
1820
40ab6a6e 1821err_destroy_tirs:
f62b8bb8 1822 for (i--; i >= 0; i--)
40ab6a6e 1823 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1824
1825 return err;
1826}
1827
40ab6a6e 1828static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1829{
1830 int i;
1831
1832 for (i = 0; i < MLX5E_NUM_TT; i++)
40ab6a6e 1833 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1834}
1835
f62b8bb8
AV		 1836static struct rtnl_link_stats64 *
1837mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1838{
1839 struct mlx5e_priv *priv = netdev_priv(dev);
1840 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1841
1842 stats->rx_packets = vstats->rx_packets;
1843 stats->rx_bytes = vstats->rx_bytes;
1844 stats->tx_packets = vstats->tx_packets;
1845 stats->tx_bytes = vstats->tx_bytes;
1846 stats->multicast = vstats->rx_multicast_packets +
1847 vstats->tx_multicast_packets;
1848 stats->tx_errors = vstats->tx_error_packets;
1849 stats->rx_errors = vstats->rx_error_packets;
1850 stats->tx_dropped = vstats->tx_queue_dropped;
1851 stats->rx_crc_errors = 0;
1852 stats->rx_length_errors = 0;
1853
1854 return stats;
1855}
1856
1857static void mlx5e_set_rx_mode(struct net_device *dev)
1858{
1859 struct mlx5e_priv *priv = netdev_priv(dev);
1860
1861 schedule_work(&priv->set_rx_mode_work);
1862}
1863
1864static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1865{
1866 struct mlx5e_priv *priv = netdev_priv(netdev);
1867 struct sockaddr *saddr = addr;
1868
1869 if (!is_valid_ether_addr(saddr->sa_data))
1870 return -EADDRNOTAVAIL;
1871
1872 netif_addr_lock_bh(netdev);
1873 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1874 netif_addr_unlock_bh(netdev);
1875
1876 schedule_work(&priv->set_rx_mode_work);
1877
1878 return 0;
1879}
1880
1881static int mlx5e_set_features(struct net_device *netdev,
1882 netdev_features_t features)
1883{
1884 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 1885 int err = 0;
f62b8bb8 1886 netdev_features_t changes = features ^ netdev->features;
f62b8bb8
AV		 1887
1888 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 1889
1890 if (changes & NETIF_F_LRO) {
98e81b0a
AS		 1891 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1892
1893 if (was_opened)
1894 mlx5e_close_locked(priv->netdev);
f62b8bb8 1895
98e81b0a 1896 priv->params.lro_en = !!(features & NETIF_F_LRO);
ab0394fe
TT		 1897 err = mlx5e_modify_tirs_lro(priv);
1898 if (err)
1899 mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1900 err);
98e81b0a
AS		 1901
1902 if (was_opened)
1903 err = mlx5e_open_locked(priv->netdev);
1904 }
f62b8bb8 1905
9b37b07f
AS		 1906 mutex_unlock(&priv->state_lock);
1907
f62b8bb8
AV		 1908 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1909 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1910 mlx5e_enable_vlan_filter(priv);
1911 else
1912 mlx5e_disable_vlan_filter(priv);
1913 }
1914
fe9f4fe5 1915 return err;
f62b8bb8
AV		 1916}
1917
1918static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1919{
1920 struct mlx5e_priv *priv = netdev_priv(netdev);
1921 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1922 bool was_opened;
f62b8bb8 1923 int max_mtu;
98e81b0a 1924 int err = 0;
f62b8bb8 1925
facc9699 1926 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1927
50a9eea6
DT		 1928 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1929
facc9699
SM		 1930 if (new_mtu > max_mtu) {
1931 netdev_err(netdev,
1932 "%s: Bad MTU (%d) > (%d) Max\n",
1933 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1934 return -EINVAL;
1935 }
1936
1937 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1938
1939 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1940 if (was_opened)
1941 mlx5e_close_locked(netdev);
1942
f62b8bb8 1943 netdev->mtu = new_mtu;
98e81b0a
AS		 1944
1945 if (was_opened)
1946 err = mlx5e_open_locked(netdev);
1947
f62b8bb8
AV		 1948 mutex_unlock(&priv->state_lock);
1949
1950 return err;
1951}
1952
ef9814de
EBE		 1953static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1954{
1955 switch (cmd) {
1956 case SIOCSHWTSTAMP:
1957 return mlx5e_hwstamp_set(dev, ifr);
1958 case SIOCGHWTSTAMP:
1959 return mlx5e_hwstamp_get(dev, ifr);
1960 default:
1961 return -EOPNOTSUPP;
1962 }
1963}
1964
66e49ded
SM		 1965static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
1966{
1967 struct mlx5e_priv *priv = netdev_priv(dev);
1968 struct mlx5_core_dev *mdev = priv->mdev;
1969
1970 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
1971}
1972
1973static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
1974{
1975 struct mlx5e_priv *priv = netdev_priv(dev);
1976 struct mlx5_core_dev *mdev = priv->mdev;
1977
1978 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
1979 vlan, qos);
1980}
1981
1982static int mlx5_vport_link2ifla(u8 esw_link)
1983{
1984 switch (esw_link) {
1985 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
1986 return IFLA_VF_LINK_STATE_DISABLE;
1987 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
1988 return IFLA_VF_LINK_STATE_ENABLE;
1989 }
1990 return IFLA_VF_LINK_STATE_AUTO;
1991}
1992
1993static int mlx5_ifla_link2vport(u8 ifla_link)
1994{
1995 switch (ifla_link) {
1996 case IFLA_VF_LINK_STATE_DISABLE:
1997 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
1998 case IFLA_VF_LINK_STATE_ENABLE:
1999 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2000 }
2001 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2002}
2003
2004static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2005 int link_state)
2006{
2007 struct mlx5e_priv *priv = netdev_priv(dev);
2008 struct mlx5_core_dev *mdev = priv->mdev;
2009
2010 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2011 mlx5_ifla_link2vport(link_state));
2012}
2013
2014static int mlx5e_get_vf_config(struct net_device *dev,
2015 int vf, struct ifla_vf_info *ivi)
2016{
2017 struct mlx5e_priv *priv = netdev_priv(dev);
2018 struct mlx5_core_dev *mdev = priv->mdev;
2019 int err;
2020
2021 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2022 if (err)
2023 return err;
2024 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2025 return 0;
2026}
2027
2028static int mlx5e_get_vf_stats(struct net_device *dev,
2029 int vf, struct ifla_vf_stats *vf_stats)
2030{
2031 struct mlx5e_priv *priv = netdev_priv(dev);
2032 struct mlx5_core_dev *mdev = priv->mdev;
2033
2034 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2035 vf_stats);
2036}
2037
b0eed40e 2038static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2039 .ndo_open = mlx5e_open,
2040 .ndo_stop = mlx5e_close,
2041 .ndo_start_xmit = mlx5e_xmit,
2042 .ndo_get_stats64 = mlx5e_get_stats,
2043 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2044 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2045 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2046 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2047 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2048 .ndo_change_mtu = mlx5e_change_mtu,
2049 .ndo_do_ioctl = mlx5e_ioctl,
2050};
2051
2052static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2053 .ndo_open = mlx5e_open,
2054 .ndo_stop = mlx5e_close,
2055 .ndo_start_xmit = mlx5e_xmit,
2056 .ndo_get_stats64 = mlx5e_get_stats,
2057 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2058 .ndo_set_mac_address = mlx5e_set_mac,
2059 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2060 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2061 .ndo_set_features = mlx5e_set_features,
2062 .ndo_change_mtu = mlx5e_change_mtu,
2063 .ndo_do_ioctl = mlx5e_ioctl,
2064 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2065 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2066 .ndo_get_vf_config = mlx5e_get_vf_config,
2067 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2068 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2069};
2070
2071static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2072{
2073 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2074 return -ENOTSUPP;
2075 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2076 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2077 !MLX5_CAP_ETH(mdev, csum_cap) ||
2078 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2079 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2080 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2081 MLX5_CAP_FLOWTABLE(mdev,
2082 flow_table_properties_nic_receive.max_ft_level)
2083 < 3) {
f62b8bb8
AV		 2084 mlx5_core_warn(mdev,
2085 "Not creating net device, some required device capabilities are missing\n");
2086 return -ENOTSUPP;
2087 }
66189961
TT		 2088 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2089 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2090
f62b8bb8
AV		 2091 return 0;
2092}
2093
58d52291
AS		 2094u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2095{
2096 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2097
2098 return bf_buf_size -
2099 sizeof(struct mlx5e_tx_wqe) +
2100 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2101}
2102
85082dba
TT		 2103void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
2104 int num_channels)
2105{
2106 int i;
2107
2108 for (i = 0; i < len; i++)
2109 indirection_rqt[i] = i % num_channels;
2110}
2111
f62b8bb8
AV		 2112static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2113 struct net_device *netdev,
936896e9 2114 int num_channels)
f62b8bb8
AV		 2115{
2116 struct mlx5e_priv *priv = netdev_priv(netdev);
2117
2118 priv->params.log_sq_size =
2119 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2120 priv->params.log_rq_size =
2121 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2122 priv->params.rx_cq_moderation_usec =
2123 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2124 priv->params.rx_cq_moderation_pkts =
2125 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2126 priv->params.tx_cq_moderation_usec =
2127 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2128 priv->params.tx_cq_moderation_pkts =
2129 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2130 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8
AV		 2131 priv->params.min_rx_wqes =
2132 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
f62b8bb8
AV		 2133 priv->params.num_tc = 1;
2134 priv->params.default_vlan_prio = 0;
2be6967c 2135 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2136
57afead5
AS		 2137 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2138 sizeof(priv->params.toeplitz_hash_key));
2139
85082dba
TT		 2140 mlx5e_build_default_indir_rqt(priv->params.indirection_rqt,
2141 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2142
f62b8bb8
AV		 2143 priv->params.lro_wqe_sz =
2144 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2145
2146 priv->mdev = mdev;
2147 priv->netdev = netdev;
936896e9 2148 priv->params.num_channels = num_channels;
f62b8bb8
AV		 2149 priv->default_vlan_prio = priv->params.default_vlan_prio;
2150
2151 spin_lock_init(&priv->async_events_spinlock);
2152 mutex_init(&priv->state_lock);
2153
2154 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2155 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2156 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2157}
2158
2159static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2160{
2161 struct mlx5e_priv *priv = netdev_priv(netdev);
2162
e1d7d349 2163 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2164 if (is_zero_ether_addr(netdev->dev_addr) &&
2165 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2166 eth_hw_addr_random(netdev);
2167 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2168 }
f62b8bb8
AV		 2169}
2170
2171static void mlx5e_build_netdev(struct net_device *netdev)
2172{
2173 struct mlx5e_priv *priv = netdev_priv(netdev);
2174 struct mlx5_core_dev *mdev = priv->mdev;
2175
2176 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2177
b0eed40e
SM		 2178 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2179 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2180 else
2181 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
66e49ded 2182
f62b8bb8
AV		 2183 netdev->watchdog_timeo = 15 * HZ;
2184
2185 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2186
12be4b21 2187 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2188 netdev->vlan_features |= NETIF_F_IP_CSUM;
2189 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2190 netdev->vlan_features |= NETIF_F_GRO;
2191 netdev->vlan_features |= NETIF_F_TSO;
2192 netdev->vlan_features |= NETIF_F_TSO6;
2193 netdev->vlan_features |= NETIF_F_RXCSUM;
2194 netdev->vlan_features |= NETIF_F_RXHASH;
2195
2196 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2197 netdev->vlan_features |= NETIF_F_LRO;
2198
2199 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2200 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2201 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2202 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2203
2204 netdev->features = netdev->hw_features;
2205 if (!priv->params.lro_en)
2206 netdev->features &= ~NETIF_F_LRO;
2207
2208 netdev->features |= NETIF_F_HIGHDMA;
2209
2210 netdev->priv_flags |= IFF_UNICAST_FLT;
2211
2212 mlx5e_set_netdev_dev_addr(netdev);
2213}
2214
2215static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2216 struct mlx5_core_mr *mr)
2217{
2218 struct mlx5_core_dev *mdev = priv->mdev;
2219 struct mlx5_create_mkey_mbox_in *in;
2220 int err;
2221
2222 in = mlx5_vzalloc(sizeof(*in));
2223 if (!in)
2224 return -ENOMEM;
2225
2226 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2227 MLX5_PERM_LOCAL_READ |
2228 MLX5_ACCESS_MODE_PA;
2229 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2230 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2231
2232 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2233 NULL);
2234
2235 kvfree(in);
2236
2237 return err;
2238}
2239
2240static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2241{
2242 struct net_device *netdev;
2243 struct mlx5e_priv *priv;
3435ab59 2244 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2245 int err;
2246
2247 if (mlx5e_check_required_hca_cap(mdev))
2248 return NULL;
2249
936896e9 2250 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), nch, nch);
f62b8bb8
AV		 2251 if (!netdev) {
2252 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2253 return NULL;
2254 }
2255
936896e9 2256 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2257 mlx5e_build_netdev(netdev);
2258
2259 netif_carrier_off(netdev);
2260
2261 priv = netdev_priv(netdev);
2262
2263 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2264 if (err) {
1f2a3003 2265 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2266 goto err_free_netdev;
2267 }
2268
2269 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2270 if (err) {
1f2a3003 2271 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2272 goto err_unmap_free_uar;
2273 }
2274
8d7f9ecb 2275 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 2276 if (err) {
1f2a3003 2277 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2278 goto err_dealloc_pd;
2279 }
2280
f62b8bb8
AV		 2281 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2282 if (err) {
1f2a3003 2283 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2284 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2285 }
2286
40ab6a6e 2287 err = mlx5e_create_tises(priv);
5c50368f 2288 if (err) {
40ab6a6e 2289 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
5c50368f
AS		 2290 goto err_destroy_mkey;
2291 }
2292
2293 err = mlx5e_open_drop_rq(priv);
2294 if (err) {
2295 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2296 goto err_destroy_tises;
5c50368f
AS		 2297 }
2298
40ab6a6e 2299 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2300 if (err) {
40ab6a6e 2301 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
5c50368f
AS		 2302 goto err_close_drop_rq;
2303 }
2304
40ab6a6e 2305 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2306 if (err) {
40ab6a6e
AS		 2307 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2308 goto err_destroy_rqt_indir;
5c50368f
AS		 2309 }
2310
40ab6a6e 2311 err = mlx5e_create_tirs(priv);
5c50368f 2312 if (err) {
40ab6a6e
AS		 2313 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2314 goto err_destroy_rqt_single;
5c50368f
AS		 2315 }
2316
40ab6a6e 2317 err = mlx5e_create_flow_tables(priv);
5c50368f 2318 if (err) {
40ab6a6e
AS		 2319 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2320 goto err_destroy_tirs;
5c50368f
AS		 2321 }
2322
2323 mlx5e_init_eth_addr(priv);
2324
f62b8bb8
AV		 2325 err = register_netdev(netdev);
2326 if (err) {
1f2a3003 2327 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
40ab6a6e 2328 goto err_destroy_flow_tables;
f62b8bb8
AV		 2329 }
2330
2331 mlx5e_enable_async_events(priv);
9b37b07f 2332 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 2333
2334 return priv;
2335
40ab6a6e
AS		 2336err_destroy_flow_tables:
2337 mlx5e_destroy_flow_tables(priv);
5c50368f 2338
40ab6a6e
AS		 2339err_destroy_tirs:
2340 mlx5e_destroy_tirs(priv);
5c50368f 2341
40ab6a6e
AS		 2342err_destroy_rqt_single:
2343 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2344
40ab6a6e
AS		 2345err_destroy_rqt_indir:
2346 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f
AS		 2347
2348err_close_drop_rq:
2349 mlx5e_close_drop_rq(priv);
2350
40ab6a6e
AS		 2351err_destroy_tises:
2352 mlx5e_destroy_tises(priv);
5c50368f 2353
f62b8bb8
AV		 2354err_destroy_mkey:
2355 mlx5_core_destroy_mkey(mdev, &priv->mr);
2356
3191e05f 2357err_dealloc_transport_domain:
8d7f9ecb 2358 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 2359
f62b8bb8
AV		 2360err_dealloc_pd:
2361 mlx5_core_dealloc_pd(mdev, priv->pdn);
2362
2363err_unmap_free_uar:
2364 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2365
2366err_free_netdev:
2367 free_netdev(netdev);
2368
2369 return NULL;
2370}
2371
2372static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2373{
2374 struct mlx5e_priv *priv = vpriv;
2375 struct net_device *netdev = priv->netdev;
2376
9b37b07f
AS		 2377 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2378
2379 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 2380 mlx5e_disable_async_events(priv);
2381 flush_scheduled_work();
f62b8bb8 2382 unregister_netdev(netdev);
40ab6a6e
AS		 2383 mlx5e_destroy_flow_tables(priv);
2384 mlx5e_destroy_tirs(priv);
2385 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2386 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2387 mlx5e_close_drop_rq(priv);
40ab6a6e 2388 mlx5e_destroy_tises(priv);
f62b8bb8 2389 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
8d7f9ecb 2390 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 2391 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2392 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
f62b8bb8
AV		 2393 free_netdev(netdev);
2394}
2395
2396static void *mlx5e_get_netdev(void *vpriv)
2397{
2398 struct mlx5e_priv *priv = vpriv;
2399
2400 return priv->netdev;
2401}
2402
2403static struct mlx5_interface mlx5e_interface = {
2404 .add = mlx5e_create_netdev,
2405 .remove = mlx5e_destroy_netdev,
2406 .event = mlx5e_async_event,
2407 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2408 .get_dev = mlx5e_get_netdev,
2409};
2410
2411void mlx5e_init(void)
2412{
2413 mlx5_register_interface(&mlx5e_interface);
2414}
2415
2416void mlx5e_cleanup(void)
2417{
2418 mlx5_unregister_interface(&mlx5e_interface);
2419}
Linux kernel - Deliverables
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