Commit | Line | Data |
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e586b3b0 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/ip.h> | |
34 | #include <linux/ipv6.h> | |
35 | #include <linux/tcp.h> | |
7ae92ae5 | 36 | #include <net/busy_poll.h> |
e586b3b0 | 37 | #include "en.h" |
12185a9f | 38 | #include "en_tc.h" |
e586b3b0 | 39 | |
ef9814de EBE |
40 | static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) |
41 | { | |
42 | return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; | |
43 | } | |
44 | ||
2f48af12 | 45 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) |
e586b3b0 AV |
46 | { |
47 | struct sk_buff *skb; | |
48 | dma_addr_t dma_addr; | |
49 | ||
c5adb96f | 50 | skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz); |
e586b3b0 AV |
51 | if (unlikely(!skb)) |
52 | return -ENOMEM; | |
53 | ||
e586b3b0 AV |
54 | dma_addr = dma_map_single(rq->pdev, |
55 | /* hw start padding */ | |
fc11fbf9 SM |
56 | skb->data, |
57 | /* hw end padding */ | |
e586b3b0 AV |
58 | rq->wqe_sz, |
59 | DMA_FROM_DEVICE); | |
60 | ||
61 | if (unlikely(dma_mapping_error(rq->pdev, dma_addr))) | |
62 | goto err_free_skb; | |
63 | ||
64 | *((dma_addr_t *)skb->cb) = dma_addr; | |
c5adb96f | 65 | wqe->data.addr = cpu_to_be64(dma_addr); |
bc77b240 | 66 | wqe->data.lkey = rq->mkey_be; |
e586b3b0 AV |
67 | |
68 | rq->skb[ix] = skb; | |
69 | ||
70 | return 0; | |
71 | ||
72 | err_free_skb: | |
73 | dev_kfree_skb(skb); | |
74 | ||
75 | return -ENOMEM; | |
76 | } | |
77 | ||
bc77b240 TT |
78 | static inline void |
79 | mlx5e_dma_pre_sync_linear_mpwqe(struct device *pdev, | |
80 | struct mlx5e_mpw_info *wi, | |
81 | u32 wqe_offset, u32 len) | |
82 | { | |
83 | dma_sync_single_for_cpu(pdev, wi->dma_info.addr + wqe_offset, | |
84 | len, DMA_FROM_DEVICE); | |
85 | } | |
86 | ||
87 | static inline void | |
88 | mlx5e_dma_pre_sync_fragmented_mpwqe(struct device *pdev, | |
89 | struct mlx5e_mpw_info *wi, | |
90 | u32 wqe_offset, u32 len) | |
91 | { | |
92 | /* No dma pre sync for fragmented MPWQE */ | |
93 | } | |
94 | ||
95 | static inline void | |
96 | mlx5e_add_skb_frag_linear_mpwqe(struct device *pdev, | |
97 | struct sk_buff *skb, | |
98 | struct mlx5e_mpw_info *wi, | |
99 | u32 page_idx, u32 frag_offset, | |
100 | u32 len) | |
101 | { | |
102 | unsigned int truesize = ALIGN(len, MLX5_MPWRQ_STRIDE_SIZE); | |
103 | ||
104 | wi->skbs_frags[page_idx]++; | |
105 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
106 | &wi->dma_info.page[page_idx], frag_offset, | |
107 | len, truesize); | |
108 | } | |
109 | ||
110 | static inline void | |
111 | mlx5e_add_skb_frag_fragmented_mpwqe(struct device *pdev, | |
112 | struct sk_buff *skb, | |
113 | struct mlx5e_mpw_info *wi, | |
114 | u32 page_idx, u32 frag_offset, | |
115 | u32 len) | |
116 | { | |
117 | unsigned int truesize = ALIGN(len, MLX5_MPWRQ_STRIDE_SIZE); | |
118 | ||
119 | dma_sync_single_for_cpu(pdev, | |
120 | wi->umr.dma_info[page_idx].addr + frag_offset, | |
121 | len, DMA_FROM_DEVICE); | |
122 | wi->skbs_frags[page_idx]++; | |
123 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
124 | wi->umr.dma_info[page_idx].page, frag_offset, | |
125 | len, truesize); | |
126 | } | |
127 | ||
128 | static inline void | |
129 | mlx5e_copy_skb_header_linear_mpwqe(struct device *pdev, | |
130 | struct sk_buff *skb, | |
131 | struct mlx5e_mpw_info *wi, | |
132 | u32 page_idx, u32 offset, | |
133 | u32 headlen) | |
134 | { | |
135 | struct page *page = &wi->dma_info.page[page_idx]; | |
136 | ||
137 | skb_copy_to_linear_data(skb, page_address(page) + offset, | |
138 | ALIGN(headlen, sizeof(long))); | |
139 | } | |
140 | ||
141 | static inline void | |
142 | mlx5e_copy_skb_header_fragmented_mpwqe(struct device *pdev, | |
143 | struct sk_buff *skb, | |
144 | struct mlx5e_mpw_info *wi, | |
145 | u32 page_idx, u32 offset, | |
146 | u32 headlen) | |
147 | { | |
148 | u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); | |
149 | struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; | |
150 | unsigned int len; | |
151 | ||
152 | /* Aligning len to sizeof(long) optimizes memcpy performance */ | |
153 | len = ALIGN(headlen_pg, sizeof(long)); | |
154 | dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, | |
155 | DMA_FROM_DEVICE); | |
156 | skb_copy_to_linear_data_offset(skb, 0, | |
157 | page_address(dma_info->page) + offset, | |
158 | len); | |
159 | #if (MLX5_MPWRQ_SMALL_PACKET_THRESHOLD >= MLX5_MPWRQ_STRIDE_SIZE) | |
160 | if (unlikely(offset + headlen > PAGE_SIZE)) { | |
161 | dma_info++; | |
162 | headlen_pg = len; | |
163 | len = ALIGN(headlen - headlen_pg, sizeof(long)); | |
164 | dma_sync_single_for_cpu(pdev, dma_info->addr, len, | |
165 | DMA_FROM_DEVICE); | |
166 | skb_copy_to_linear_data_offset(skb, headlen_pg, | |
167 | page_address(dma_info->page), | |
168 | len); | |
169 | } | |
170 | #endif | |
171 | } | |
172 | ||
173 | static u16 mlx5e_get_wqe_mtt_offset(u16 rq_ix, u16 wqe_ix) | |
174 | { | |
175 | return rq_ix * MLX5_CHANNEL_MAX_NUM_MTTS + | |
176 | wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); | |
177 | } | |
178 | ||
179 | static void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, | |
180 | struct mlx5e_sq *sq, | |
181 | struct mlx5e_umr_wqe *wqe, | |
182 | u16 ix) | |
183 | { | |
184 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
185 | struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; | |
186 | struct mlx5_wqe_data_seg *dseg = &wqe->data; | |
187 | struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; | |
188 | u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS); | |
189 | u16 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix); | |
190 | ||
191 | memset(wqe, 0, sizeof(*wqe)); | |
192 | cseg->opmod_idx_opcode = | |
193 | cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | | |
194 | MLX5_OPCODE_UMR); | |
195 | cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | | |
196 | ds_cnt); | |
197 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
198 | cseg->imm = rq->umr_mkey_be; | |
199 | ||
200 | ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN; | |
201 | ucseg->klm_octowords = | |
202 | cpu_to_be16(mlx5e_get_mtt_octw(MLX5_MPWRQ_PAGES_PER_WQE)); | |
203 | ucseg->bsf_octowords = | |
204 | cpu_to_be16(mlx5e_get_mtt_octw(umr_wqe_mtt_offset)); | |
205 | ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); | |
206 | ||
207 | dseg->lkey = sq->mkey_be; | |
208 | dseg->addr = cpu_to_be64(wi->umr.mtt_addr); | |
209 | } | |
210 | ||
211 | static void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) | |
212 | { | |
213 | struct mlx5e_sq *sq = &rq->channel->icosq; | |
214 | struct mlx5_wq_cyc *wq = &sq->wq; | |
215 | struct mlx5e_umr_wqe *wqe; | |
216 | u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); | |
217 | u16 pi; | |
218 | ||
219 | /* fill sq edge with nops to avoid wqe wrap around */ | |
220 | while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { | |
221 | sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP; | |
222 | sq->ico_wqe_info[pi].num_wqebbs = 1; | |
223 | mlx5e_send_nop(sq, true); | |
224 | } | |
225 | ||
226 | wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
227 | mlx5e_build_umr_wqe(rq, sq, wqe, ix); | |
228 | sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR; | |
229 | sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs; | |
230 | sq->pc += num_wqebbs; | |
231 | mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0); | |
232 | } | |
233 | ||
234 | static inline int mlx5e_get_wqe_mtt_sz(void) | |
235 | { | |
236 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes. | |
237 | * To avoid copying garbage after the mtt array, we allocate | |
238 | * a little more. | |
239 | */ | |
240 | return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64), | |
241 | MLX5_UMR_MTT_ALIGNMENT); | |
242 | } | |
243 | ||
244 | static int mlx5e_alloc_and_map_page(struct mlx5e_rq *rq, | |
245 | struct mlx5e_mpw_info *wi, | |
246 | int i) | |
247 | { | |
248 | struct page *page; | |
249 | ||
250 | page = dev_alloc_page(); | |
251 | if (unlikely(!page)) | |
252 | return -ENOMEM; | |
253 | ||
254 | wi->umr.dma_info[i].page = page; | |
255 | wi->umr.dma_info[i].addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE, | |
256 | PCI_DMA_FROMDEVICE); | |
257 | if (unlikely(dma_mapping_error(rq->pdev, wi->umr.dma_info[i].addr))) { | |
258 | put_page(page); | |
259 | return -ENOMEM; | |
260 | } | |
261 | wi->umr.mtt[i] = cpu_to_be64(wi->umr.dma_info[i].addr | MLX5_EN_WR); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static int mlx5e_alloc_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
267 | struct mlx5e_rx_wqe *wqe, | |
268 | u16 ix) | |
269 | { | |
270 | struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; | |
271 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); | |
272 | u32 dma_offset = mlx5e_get_wqe_mtt_offset(rq->ix, ix) << PAGE_SHIFT; | |
273 | int i; | |
274 | ||
275 | wi->umr.dma_info = kmalloc(sizeof(*wi->umr.dma_info) * | |
276 | MLX5_MPWRQ_PAGES_PER_WQE, | |
277 | GFP_ATOMIC); | |
278 | if (unlikely(!wi->umr.dma_info)) | |
279 | goto err_out; | |
280 | ||
281 | /* We allocate more than mtt_sz as we will align the pointer */ | |
282 | wi->umr.mtt_no_align = kzalloc(mtt_sz + MLX5_UMR_ALIGN - 1, | |
283 | GFP_ATOMIC); | |
284 | if (unlikely(!wi->umr.mtt_no_align)) | |
285 | goto err_free_umr; | |
286 | ||
287 | wi->umr.mtt = PTR_ALIGN(wi->umr.mtt_no_align, MLX5_UMR_ALIGN); | |
288 | wi->umr.mtt_addr = dma_map_single(rq->pdev, wi->umr.mtt, mtt_sz, | |
289 | PCI_DMA_TODEVICE); | |
290 | if (unlikely(dma_mapping_error(rq->pdev, wi->umr.mtt_addr))) | |
291 | goto err_free_mtt; | |
292 | ||
293 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { | |
294 | if (unlikely(mlx5e_alloc_and_map_page(rq, wi, i))) | |
295 | goto err_unmap; | |
296 | atomic_add(MLX5_MPWRQ_STRIDES_PER_PAGE, | |
297 | &wi->umr.dma_info[i].page->_count); | |
298 | wi->skbs_frags[i] = 0; | |
299 | } | |
300 | ||
301 | wi->consumed_strides = 0; | |
302 | wi->dma_pre_sync = mlx5e_dma_pre_sync_fragmented_mpwqe; | |
303 | wi->add_skb_frag = mlx5e_add_skb_frag_fragmented_mpwqe; | |
304 | wi->copy_skb_header = mlx5e_copy_skb_header_fragmented_mpwqe; | |
305 | wi->free_wqe = mlx5e_free_rx_fragmented_mpwqe; | |
306 | wqe->data.lkey = rq->umr_mkey_be; | |
307 | wqe->data.addr = cpu_to_be64(dma_offset); | |
308 | ||
309 | return 0; | |
310 | ||
311 | err_unmap: | |
312 | while (--i >= 0) { | |
313 | dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE, | |
314 | PCI_DMA_FROMDEVICE); | |
315 | atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE, | |
316 | &wi->umr.dma_info[i].page->_count); | |
317 | put_page(wi->umr.dma_info[i].page); | |
318 | } | |
319 | dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE); | |
320 | ||
321 | err_free_mtt: | |
322 | kfree(wi->umr.mtt_no_align); | |
323 | ||
324 | err_free_umr: | |
325 | kfree(wi->umr.dma_info); | |
326 | ||
327 | err_out: | |
328 | return -ENOMEM; | |
329 | } | |
330 | ||
331 | void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
332 | struct mlx5e_mpw_info *wi) | |
333 | { | |
334 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); | |
335 | int i; | |
336 | ||
337 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { | |
338 | dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE, | |
339 | PCI_DMA_FROMDEVICE); | |
340 | atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE - wi->skbs_frags[i], | |
341 | &wi->umr.dma_info[i].page->_count); | |
342 | put_page(wi->umr.dma_info[i].page); | |
343 | } | |
344 | dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE); | |
345 | kfree(wi->umr.mtt_no_align); | |
346 | kfree(wi->umr.dma_info); | |
347 | } | |
348 | ||
349 | void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq) | |
350 | { | |
351 | struct mlx5_wq_ll *wq = &rq->wq; | |
352 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); | |
353 | ||
354 | clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); | |
355 | mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); | |
356 | rq->stats.mpwqe_frag++; | |
357 | ||
358 | /* ensure wqes are visible to device before updating doorbell record */ | |
359 | dma_wmb(); | |
360 | ||
361 | mlx5_wq_ll_update_db_record(wq); | |
362 | } | |
363 | ||
364 | static int mlx5e_alloc_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
365 | struct mlx5e_rx_wqe *wqe, | |
366 | u16 ix) | |
461017cb TT |
367 | { |
368 | struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; | |
369 | gfp_t gfp_mask; | |
370 | int i; | |
371 | ||
372 | gfp_mask = GFP_ATOMIC | __GFP_COLD | __GFP_MEMALLOC; | |
373 | wi->dma_info.page = alloc_pages_node(NUMA_NO_NODE, gfp_mask, | |
374 | MLX5_MPWRQ_WQE_PAGE_ORDER); | |
375 | if (unlikely(!wi->dma_info.page)) | |
376 | return -ENOMEM; | |
377 | ||
378 | wi->dma_info.addr = dma_map_page(rq->pdev, wi->dma_info.page, 0, | |
379 | rq->wqe_sz, PCI_DMA_FROMDEVICE); | |
380 | if (unlikely(dma_mapping_error(rq->pdev, wi->dma_info.addr))) { | |
381 | put_page(wi->dma_info.page); | |
382 | return -ENOMEM; | |
383 | } | |
384 | ||
385 | /* We split the high-order page into order-0 ones and manage their | |
386 | * reference counter to minimize the memory held by small skb fragments | |
387 | */ | |
388 | split_page(wi->dma_info.page, MLX5_MPWRQ_WQE_PAGE_ORDER); | |
389 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { | |
390 | atomic_add(MLX5_MPWRQ_STRIDES_PER_PAGE, | |
391 | &wi->dma_info.page[i]._count); | |
392 | wi->skbs_frags[i] = 0; | |
393 | } | |
394 | ||
395 | wi->consumed_strides = 0; | |
bc77b240 TT |
396 | wi->dma_pre_sync = mlx5e_dma_pre_sync_linear_mpwqe; |
397 | wi->add_skb_frag = mlx5e_add_skb_frag_linear_mpwqe; | |
398 | wi->copy_skb_header = mlx5e_copy_skb_header_linear_mpwqe; | |
399 | wi->free_wqe = mlx5e_free_rx_linear_mpwqe; | |
400 | wqe->data.lkey = rq->mkey_be; | |
401 | wqe->data.addr = cpu_to_be64(wi->dma_info.addr); | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
407 | struct mlx5e_mpw_info *wi) | |
408 | { | |
409 | int i; | |
410 | ||
411 | dma_unmap_page(rq->pdev, wi->dma_info.addr, rq->wqe_sz, | |
412 | PCI_DMA_FROMDEVICE); | |
413 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { | |
414 | atomic_sub(MLX5_MPWRQ_STRIDES_PER_PAGE - wi->skbs_frags[i], | |
415 | &wi->dma_info.page[i]._count); | |
416 | put_page(&wi->dma_info.page[i]); | |
417 | } | |
418 | } | |
419 | ||
420 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) | |
421 | { | |
422 | int err; | |
423 | ||
424 | err = mlx5e_alloc_rx_linear_mpwqe(rq, wqe, ix); | |
425 | if (unlikely(err)) { | |
426 | err = mlx5e_alloc_rx_fragmented_mpwqe(rq, wqe, ix); | |
427 | if (unlikely(err)) | |
428 | return err; | |
429 | set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); | |
430 | mlx5e_post_umr_wqe(rq, ix); | |
431 | return -EBUSY; | |
432 | } | |
461017cb TT |
433 | |
434 | return 0; | |
435 | } | |
436 | ||
bc77b240 TT |
437 | #define RQ_CANNOT_POST(rq) \ |
438 | (!test_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state) || \ | |
439 | test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state)) | |
440 | ||
e586b3b0 AV |
441 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) |
442 | { | |
443 | struct mlx5_wq_ll *wq = &rq->wq; | |
444 | ||
bc77b240 | 445 | if (unlikely(RQ_CANNOT_POST(rq))) |
e586b3b0 AV |
446 | return false; |
447 | ||
448 | while (!mlx5_wq_ll_is_full(wq)) { | |
449 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); | |
54984407 | 450 | int err; |
e586b3b0 | 451 | |
54984407 TT |
452 | err = rq->alloc_wqe(rq, wqe, wq->head); |
453 | if (unlikely(err)) { | |
454 | if (err != -EBUSY) | |
455 | rq->stats.buff_alloc_err++; | |
e586b3b0 | 456 | break; |
54984407 | 457 | } |
e586b3b0 AV |
458 | |
459 | mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); | |
460 | } | |
461 | ||
462 | /* ensure wqes are visible to device before updating doorbell record */ | |
463 | dma_wmb(); | |
464 | ||
465 | mlx5_wq_ll_update_db_record(wq); | |
466 | ||
467 | return !mlx5_wq_ll_is_full(wq); | |
468 | } | |
469 | ||
461017cb TT |
470 | static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, |
471 | u32 cqe_bcnt) | |
e586b3b0 AV |
472 | { |
473 | struct ethhdr *eth = (struct ethhdr *)(skb->data); | |
474 | struct iphdr *ipv4 = (struct iphdr *)(skb->data + ETH_HLEN); | |
475 | struct ipv6hdr *ipv6 = (struct ipv6hdr *)(skb->data + ETH_HLEN); | |
476 | struct tcphdr *tcp; | |
477 | ||
478 | u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); | |
479 | int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || | |
480 | (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); | |
481 | ||
461017cb | 482 | u16 tot_len = cqe_bcnt - ETH_HLEN; |
e586b3b0 AV |
483 | |
484 | if (eth->h_proto == htons(ETH_P_IP)) { | |
485 | tcp = (struct tcphdr *)(skb->data + ETH_HLEN + | |
486 | sizeof(struct iphdr)); | |
487 | ipv6 = NULL; | |
d9a40271 | 488 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; |
e586b3b0 AV |
489 | } else { |
490 | tcp = (struct tcphdr *)(skb->data + ETH_HLEN + | |
491 | sizeof(struct ipv6hdr)); | |
492 | ipv4 = NULL; | |
d9a40271 | 493 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; |
e586b3b0 AV |
494 | } |
495 | ||
496 | if (get_cqe_lro_tcppsh(cqe)) | |
497 | tcp->psh = 1; | |
498 | ||
499 | if (tcp_ack) { | |
500 | tcp->ack = 1; | |
501 | tcp->ack_seq = cqe->lro_ack_seq_num; | |
502 | tcp->window = cqe->lro_tcp_win; | |
503 | } | |
504 | ||
505 | if (ipv4) { | |
506 | ipv4->ttl = cqe->lro_min_ttl; | |
507 | ipv4->tot_len = cpu_to_be16(tot_len); | |
508 | ipv4->check = 0; | |
509 | ipv4->check = ip_fast_csum((unsigned char *)ipv4, | |
510 | ipv4->ihl); | |
511 | } else { | |
512 | ipv6->hop_limit = cqe->lro_min_ttl; | |
513 | ipv6->payload_len = cpu_to_be16(tot_len - | |
514 | sizeof(struct ipv6hdr)); | |
515 | } | |
516 | } | |
517 | ||
518 | static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, | |
519 | struct sk_buff *skb) | |
520 | { | |
521 | u8 cht = cqe->rss_hash_type; | |
522 | int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : | |
523 | (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : | |
524 | PKT_HASH_TYPE_NONE; | |
525 | skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); | |
526 | } | |
527 | ||
bbceefce AS |
528 | static inline bool is_first_ethertype_ip(struct sk_buff *skb) |
529 | { | |
530 | __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; | |
531 | ||
532 | return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); | |
533 | } | |
534 | ||
535 | static inline void mlx5e_handle_csum(struct net_device *netdev, | |
536 | struct mlx5_cqe64 *cqe, | |
537 | struct mlx5e_rq *rq, | |
5f6d12d1 MF |
538 | struct sk_buff *skb, |
539 | bool lro) | |
bbceefce AS |
540 | { |
541 | if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) | |
542 | goto csum_none; | |
543 | ||
5f6d12d1 | 544 | if (lro) { |
bbceefce | 545 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
5f6d12d1 | 546 | } else if (likely(is_first_ethertype_ip(skb))) { |
bbceefce | 547 | skb->ip_summed = CHECKSUM_COMPLETE; |
ecf842f6 | 548 | skb->csum = csum_unfold((__force __sum16)cqe->check_sum); |
bbceefce AS |
549 | rq->stats.csum_sw++; |
550 | } else { | |
551 | goto csum_none; | |
552 | } | |
553 | ||
554 | return; | |
555 | ||
556 | csum_none: | |
557 | skb->ip_summed = CHECKSUM_NONE; | |
558 | rq->stats.csum_none++; | |
559 | } | |
560 | ||
e586b3b0 | 561 | static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, |
461017cb | 562 | u32 cqe_bcnt, |
e586b3b0 AV |
563 | struct mlx5e_rq *rq, |
564 | struct sk_buff *skb) | |
565 | { | |
566 | struct net_device *netdev = rq->netdev; | |
ef9814de | 567 | struct mlx5e_tstamp *tstamp = rq->tstamp; |
e586b3b0 AV |
568 | int lro_num_seg; |
569 | ||
e586b3b0 AV |
570 | lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; |
571 | if (lro_num_seg > 1) { | |
461017cb | 572 | mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); |
d9a40271 | 573 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); |
e586b3b0 AV |
574 | rq->stats.lro_packets++; |
575 | rq->stats.lro_bytes += cqe_bcnt; | |
576 | } | |
577 | ||
ef9814de EBE |
578 | if (unlikely(mlx5e_rx_hw_stamp(tstamp))) |
579 | mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); | |
580 | ||
e586b3b0 AV |
581 | skb_record_rx_queue(skb, rq->ix); |
582 | ||
583 | if (likely(netdev->features & NETIF_F_RXHASH)) | |
584 | mlx5e_skb_set_hash(cqe, skb); | |
585 | ||
586 | if (cqe_has_vlan(cqe)) | |
587 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
588 | be16_to_cpu(cqe->vlan_info)); | |
12185a9f AV |
589 | |
590 | skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; | |
e20a0db3 SM |
591 | |
592 | mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); | |
593 | skb->protocol = eth_type_trans(skb, netdev); | |
e586b3b0 AV |
594 | } |
595 | ||
461017cb TT |
596 | static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, |
597 | struct mlx5_cqe64 *cqe, | |
598 | u32 cqe_bcnt, | |
599 | struct sk_buff *skb) | |
600 | { | |
601 | rq->stats.packets++; | |
602 | rq->stats.bytes += cqe_bcnt; | |
603 | mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); | |
604 | napi_gro_receive(rq->cq.napi, skb); | |
605 | } | |
606 | ||
2f48af12 TT |
607 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) |
608 | { | |
609 | struct mlx5e_rx_wqe *wqe; | |
610 | struct sk_buff *skb; | |
611 | __be16 wqe_counter_be; | |
612 | u16 wqe_counter; | |
461017cb | 613 | u32 cqe_bcnt; |
2f48af12 TT |
614 | |
615 | wqe_counter_be = cqe->wqe_counter; | |
616 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
617 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
618 | skb = rq->skb[wqe_counter]; | |
619 | prefetch(skb->data); | |
620 | rq->skb[wqe_counter] = NULL; | |
621 | ||
622 | dma_unmap_single(rq->pdev, | |
623 | *((dma_addr_t *)skb->cb), | |
624 | rq->wqe_sz, | |
625 | DMA_FROM_DEVICE); | |
626 | ||
627 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { | |
628 | rq->stats.wqe_err++; | |
629 | dev_kfree_skb(skb); | |
630 | goto wq_ll_pop; | |
631 | } | |
632 | ||
461017cb TT |
633 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); |
634 | skb_put(skb, cqe_bcnt); | |
635 | ||
636 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); | |
2f48af12 TT |
637 | |
638 | wq_ll_pop: | |
639 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, | |
640 | &wqe->next.next_wqe_index); | |
641 | } | |
642 | ||
bc77b240 TT |
643 | static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, |
644 | struct mlx5_cqe64 *cqe, | |
645 | struct mlx5e_mpw_info *wi, | |
646 | u32 cqe_bcnt, | |
647 | struct sk_buff *skb) | |
648 | { | |
649 | u32 consumed_bytes = ALIGN(cqe_bcnt, MLX5_MPWRQ_STRIDE_SIZE); | |
650 | u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); | |
651 | u32 wqe_offset = stride_ix * MLX5_MPWRQ_STRIDE_SIZE; | |
652 | u32 head_offset = wqe_offset & (PAGE_SIZE - 1); | |
653 | u32 page_idx = wqe_offset >> PAGE_SHIFT; | |
654 | u32 head_page_idx = page_idx; | |
655 | u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); | |
656 | u32 frag_offset = head_offset + headlen; | |
657 | u16 byte_cnt = cqe_bcnt - headlen; | |
658 | ||
659 | #if (MLX5_MPWRQ_SMALL_PACKET_THRESHOLD >= MLX5_MPWRQ_STRIDE_SIZE) | |
660 | if (unlikely(frag_offset >= PAGE_SIZE)) { | |
661 | page_idx++; | |
662 | frag_offset -= PAGE_SIZE; | |
663 | } | |
664 | #endif | |
665 | wi->dma_pre_sync(rq->pdev, wi, wqe_offset, consumed_bytes); | |
666 | ||
667 | while (byte_cnt) { | |
668 | u32 pg_consumed_bytes = | |
669 | min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); | |
670 | ||
671 | wi->add_skb_frag(rq->pdev, skb, wi, page_idx, frag_offset, | |
672 | pg_consumed_bytes); | |
673 | byte_cnt -= pg_consumed_bytes; | |
674 | frag_offset = 0; | |
675 | page_idx++; | |
676 | } | |
677 | /* copy header */ | |
678 | wi->copy_skb_header(rq->pdev, skb, wi, head_page_idx, head_offset, | |
679 | headlen); | |
680 | /* skb linear part was allocated with headlen and aligned to long */ | |
681 | skb->tail += headlen; | |
682 | skb->len += headlen; | |
683 | } | |
684 | ||
461017cb TT |
685 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) |
686 | { | |
687 | u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); | |
461017cb TT |
688 | u16 wqe_id = be16_to_cpu(cqe->wqe_id); |
689 | struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id]; | |
690 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); | |
691 | struct sk_buff *skb; | |
461017cb | 692 | u16 cqe_bcnt; |
461017cb TT |
693 | |
694 | wi->consumed_strides += cstrides; | |
695 | ||
696 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { | |
697 | rq->stats.wqe_err++; | |
698 | goto mpwrq_cqe_out; | |
699 | } | |
700 | ||
701 | if (unlikely(mpwrq_is_filler_cqe(cqe))) { | |
702 | rq->stats.mpwqe_filler++; | |
703 | goto mpwrq_cqe_out; | |
704 | } | |
705 | ||
c5adb96f TT |
706 | skb = napi_alloc_skb(rq->cq.napi, |
707 | ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, | |
708 | sizeof(long))); | |
54984407 TT |
709 | if (unlikely(!skb)) { |
710 | rq->stats.buff_alloc_err++; | |
461017cb | 711 | goto mpwrq_cqe_out; |
54984407 | 712 | } |
461017cb TT |
713 | |
714 | prefetch(skb->data); | |
461017cb | 715 | cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); |
461017cb | 716 | |
bc77b240 | 717 | mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); |
461017cb TT |
718 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); |
719 | ||
720 | mpwrq_cqe_out: | |
721 | if (likely(wi->consumed_strides < MLX5_MPWRQ_NUM_STRIDES)) | |
722 | return; | |
723 | ||
bc77b240 | 724 | wi->free_wqe(rq, wi); |
461017cb TT |
725 | mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); |
726 | } | |
727 | ||
44fb6fbb | 728 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) |
e586b3b0 | 729 | { |
e3391054 | 730 | struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); |
44fb6fbb | 731 | int work_done; |
e586b3b0 | 732 | |
44fb6fbb | 733 | for (work_done = 0; work_done < budget; work_done++) { |
2f48af12 | 734 | struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq); |
e586b3b0 | 735 | |
e586b3b0 AV |
736 | if (!cqe) |
737 | break; | |
738 | ||
a1f5a1a8 AS |
739 | mlx5_cqwq_pop(&cq->wq); |
740 | ||
2f48af12 | 741 | rq->handle_rx_cqe(rq, cqe); |
e586b3b0 AV |
742 | } |
743 | ||
744 | mlx5_cqwq_update_db_record(&cq->wq); | |
745 | ||
746 | /* ensure cq space is freed before enabling more cqes */ | |
747 | wmb(); | |
748 | ||
44fb6fbb | 749 | return work_done; |
e586b3b0 | 750 | } |