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net/mlx5e: Don't wait for RQ completions on close
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
CommitLineData
e586b3b0
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/ip.h>
34#include <linux/ipv6.h>
35#include <linux/tcp.h>
7ae92ae5 36#include <net/busy_poll.h>
e586b3b0 37#include "en.h"
12185a9f 38#include "en_tc.h"
e586b3b0 39
ef9814de
EBE		 40static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
41{
42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
43}
44
7219ab34
TT		 45static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
46 void *data)
47{
48 u32 ci = cqcc & cq->wq.sz_m1;
49
50 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
51}
52
53static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
54 struct mlx5e_cq *cq, u32 cqcc)
55{
56 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
57 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
58 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
59 rq->stats.cqe_compress_blks++;
60}
61
62static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
63{
64 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
65 cq->mini_arr_idx = 0;
66}
67
68static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
69{
70 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
71 u32 wq_sz = 1 << cq->wq.log_sz;
72 u32 ci = cqcc & cq->wq.sz_m1;
73 u32 ci_top = min_t(u32, wq_sz, ci + n);
74
75 for (; ci < ci_top; ci++, n--) {
76 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
77
78 cqe->op_own = op_own;
79 }
80
81 if (unlikely(ci == wq_sz)) {
82 op_own = !op_own;
83 for (ci = 0; ci < n; ci++) {
84 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
85
86 cqe->op_own = op_own;
87 }
88 }
89}
90
91static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
92 struct mlx5e_cq *cq, u32 cqcc)
93{
94 u16 wqe_cnt_step;
95
96 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
97 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
98 cq->title.op_own &= 0xf0;
99 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
100 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
101
102 wqe_cnt_step =
103 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
104 mpwrq_get_cqe_consumed_strides(&cq->title) : 1;
105 cq->decmprs_wqe_counter =
106 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1;
107}
108
109static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
110 struct mlx5e_cq *cq, u32 cqcc)
111{
112 mlx5e_decompress_cqe(rq, cq, cqcc);
113 cq->title.rss_hash_type = 0;
114 cq->title.rss_hash_result = 0;
115}
116
117static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
118 struct mlx5e_cq *cq,
119 int update_owner_only,
120 int budget_rem)
121{
122 u32 cqcc = cq->wq.cc + update_owner_only;
123 u32 cqe_count;
124 u32 i;
125
126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
127
128 for (i = update_owner_only; i < cqe_count;
129 i++, cq->mini_arr_idx++, cqcc++) {
d9d9f156 130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
7219ab34
TT		 131 mlx5e_read_mini_arr_slot(cq, cqcc);
132
133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
134 rq->handle_rx_cqe(rq, &cq->title);
135 }
136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
137 cq->wq.cc = cqcc;
138 cq->decmprs_left -= cqe_count;
139 rq->stats.cqe_compress_pkts += cqe_count;
140
141 return cqe_count;
142}
143
144static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
145 struct mlx5e_cq *cq,
146 int budget_rem)
147{
148 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
151 rq->handle_rx_cqe(rq, &cq->title);
152 cq->mini_arr_idx++;
153
154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
155}
156
157void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val)
158{
159 bool was_opened;
160
161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
162 return;
163
164 mutex_lock(&priv->state_lock);
165
166 if (priv->params.rx_cqe_compress == val)
167 goto unlock;
168
169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
170 if (was_opened)
171 mlx5e_close_locked(priv->netdev);
172
173 priv->params.rx_cqe_compress = val;
174
175 if (was_opened)
176 mlx5e_open_locked(priv->netdev);
177
178unlock:
179 mutex_unlock(&priv->state_lock);
180}
181
2f48af12 182int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
e586b3b0
AV		 183{
184 struct sk_buff *skb;
185 dma_addr_t dma_addr;
186
c5adb96f 187 skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz);
e586b3b0
AV		 188 if (unlikely(!skb))
189 return -ENOMEM;
190
e586b3b0
AV		 191 dma_addr = dma_map_single(rq->pdev,
192 /* hw start padding */
fc11fbf9
SM		 193 skb->data,
194 /* hw end padding */
e586b3b0
AV		 195 rq->wqe_sz,
196 DMA_FROM_DEVICE);
197
198 if (unlikely(dma_mapping_error(rq->pdev, dma_addr)))
199 goto err_free_skb;
200
201 *((dma_addr_t *)skb->cb) = dma_addr;
c5adb96f 202 wqe->data.addr = cpu_to_be64(dma_addr);
bc77b240 203 wqe->data.lkey = rq->mkey_be;
e586b3b0
AV		 204
205 rq->skb[ix] = skb;
206
207 return 0;
208
209err_free_skb:
210 dev_kfree_skb(skb);
211
212 return -ENOMEM;
213}
214
6cd392a0
DJ		 215void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
216{
217 struct sk_buff *skb = rq->skb[ix];
218
219 if (skb) {
220 rq->skb[ix] = NULL;
221 dma_unmap_single(rq->pdev,
222 *((dma_addr_t *)skb->cb),
223 rq->wqe_sz,
224 DMA_FROM_DEVICE);
225 dev_kfree_skb(skb);
226 }
227}
228
d9d9f156
TT		 229static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
230{
231 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
232}
233
bc77b240
TT		 234static inline void
235mlx5e_dma_pre_sync_linear_mpwqe(struct device *pdev,
236 struct mlx5e_mpw_info *wi,
237 u32 wqe_offset, u32 len)
238{
239 dma_sync_single_for_cpu(pdev, wi->dma_info.addr + wqe_offset,
240 len, DMA_FROM_DEVICE);
241}
242
243static inline void
244mlx5e_dma_pre_sync_fragmented_mpwqe(struct device *pdev,
245 struct mlx5e_mpw_info *wi,
246 u32 wqe_offset, u32 len)
247{
248 /* No dma pre sync for fragmented MPWQE */
249}
250
251static inline void
d9d9f156 252mlx5e_add_skb_frag_linear_mpwqe(struct mlx5e_rq *rq,
bc77b240
TT		 253 struct sk_buff *skb,
254 struct mlx5e_mpw_info *wi,
255 u32 page_idx, u32 frag_offset,
256 u32 len)
257{
d9d9f156 258 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
bc77b240
TT		 259
260 wi->skbs_frags[page_idx]++;
261 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
262 &wi->dma_info.page[page_idx], frag_offset,
263 len, truesize);
264}
265
266static inline void
d9d9f156 267mlx5e_add_skb_frag_fragmented_mpwqe(struct mlx5e_rq *rq,
bc77b240
TT		 268 struct sk_buff *skb,
269 struct mlx5e_mpw_info *wi,
270 u32 page_idx, u32 frag_offset,
271 u32 len)
272{
d9d9f156 273 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
bc77b240 274
d9d9f156 275 dma_sync_single_for_cpu(rq->pdev,
bc77b240
TT		 276 wi->umr.dma_info[page_idx].addr + frag_offset,
277 len, DMA_FROM_DEVICE);
278 wi->skbs_frags[page_idx]++;
279 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
280 wi->umr.dma_info[page_idx].page, frag_offset,
281 len, truesize);
282}
283
284static inline void
285mlx5e_copy_skb_header_linear_mpwqe(struct device *pdev,
286 struct sk_buff *skb,
287 struct mlx5e_mpw_info *wi,
288 u32 page_idx, u32 offset,
289 u32 headlen)
290{
291 struct page *page = &wi->dma_info.page[page_idx];
292
293 skb_copy_to_linear_data(skb, page_address(page) + offset,
294 ALIGN(headlen, sizeof(long)));
295}
296
297static inline void
298mlx5e_copy_skb_header_fragmented_mpwqe(struct device *pdev,
299 struct sk_buff *skb,
300 struct mlx5e_mpw_info *wi,
301 u32 page_idx, u32 offset,
302 u32 headlen)
303{
304 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
305 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
306 unsigned int len;
307
308 /* Aligning len to sizeof(long) optimizes memcpy performance */
309 len = ALIGN(headlen_pg, sizeof(long));
310 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
311 DMA_FROM_DEVICE);
312 skb_copy_to_linear_data_offset(skb, 0,
313 page_address(dma_info->page) + offset,
314 len);
bc77b240
TT		 315 if (unlikely(offset + headlen > PAGE_SIZE)) {
316 dma_info++;
317 headlen_pg = len;
318 len = ALIGN(headlen - headlen_pg, sizeof(long));
319 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
320 DMA_FROM_DEVICE);
321 skb_copy_to_linear_data_offset(skb, headlen_pg,
322 page_address(dma_info->page),
323 len);
324 }
bc77b240
TT		 325}
326
fe4c988b 327static u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
bc77b240 328{
fe4c988b 329 return rq->mpwqe_mtt_offset +
bc77b240
TT		 330 wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
331}
332
333static void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
334 struct mlx5e_sq *sq,
335 struct mlx5e_umr_wqe *wqe,
336 u16 ix)
337{
338 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
339 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
340 struct mlx5_wqe_data_seg *dseg = &wqe->data;
341 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
342 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
fe4c988b 343 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
bc77b240
TT		 344
345 memset(wqe, 0, sizeof(*wqe));
346 cseg->opmod_idx_opcode =
347 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
348 MLX5_OPCODE_UMR);
349 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
350 ds_cnt);
351 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
352 cseg->imm = rq->umr_mkey_be;
353
354 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
355 ucseg->klm_octowords =
fe4c988b 356 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
bc77b240 357 ucseg->bsf_octowords =
fe4c988b 358 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
bc77b240
TT		 359 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
360
361 dseg->lkey = sq->mkey_be;
362 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
363}
364
365static void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
366{
367 struct mlx5e_sq *sq = &rq->channel->icosq;
368 struct mlx5_wq_cyc *wq = &sq->wq;
369 struct mlx5e_umr_wqe *wqe;
370 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
371 u16 pi;
372
373 /* fill sq edge with nops to avoid wqe wrap around */
374 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
375 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
376 sq->ico_wqe_info[pi].num_wqebbs = 1;
377 mlx5e_send_nop(sq, true);
378 }
379
380 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
381 mlx5e_build_umr_wqe(rq, sq, wqe, ix);
382 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR;
383 sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs;
384 sq->pc += num_wqebbs;
385 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
386}
387
388static inline int mlx5e_get_wqe_mtt_sz(void)
389{
390 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
391 * To avoid copying garbage after the mtt array, we allocate
392 * a little more.
393 */
394 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
395 MLX5_UMR_MTT_ALIGNMENT);
396}
397
398static int mlx5e_alloc_and_map_page(struct mlx5e_rq *rq,
399 struct mlx5e_mpw_info *wi,
400 int i)
401{
402 struct page *page;
403
404 page = dev_alloc_page();
405 if (unlikely(!page))
406 return -ENOMEM;
407
408 wi->umr.dma_info[i].page = page;
409 wi->umr.dma_info[i].addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE,
410 PCI_DMA_FROMDEVICE);
411 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.dma_info[i].addr))) {
412 put_page(page);
413 return -ENOMEM;
414 }
415 wi->umr.mtt[i] = cpu_to_be64(wi->umr.dma_info[i].addr | MLX5_EN_WR);
416
417 return 0;
418}
419
420static int mlx5e_alloc_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
421 struct mlx5e_rx_wqe *wqe,
422 u16 ix)
423{
424 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
425 int mtt_sz = mlx5e_get_wqe_mtt_sz();
fe4c988b 426 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
bc77b240
TT		 427 int i;
428
429 wi->umr.dma_info = kmalloc(sizeof(*wi->umr.dma_info) *
430 MLX5_MPWRQ_PAGES_PER_WQE,
431 GFP_ATOMIC);
432 if (unlikely(!wi->umr.dma_info))
433 goto err_out;
434
435 /* We allocate more than mtt_sz as we will align the pointer */
436 wi->umr.mtt_no_align = kzalloc(mtt_sz + MLX5_UMR_ALIGN - 1,
437 GFP_ATOMIC);
438 if (unlikely(!wi->umr.mtt_no_align))
439 goto err_free_umr;
440
441 wi->umr.mtt = PTR_ALIGN(wi->umr.mtt_no_align, MLX5_UMR_ALIGN);
442 wi->umr.mtt_addr = dma_map_single(rq->pdev, wi->umr.mtt, mtt_sz,
443 PCI_DMA_TODEVICE);
444 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.mtt_addr)))
445 goto err_free_mtt;
446
447 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
448 if (unlikely(mlx5e_alloc_and_map_page(rq, wi, i)))
449 goto err_unmap;
0139aa7b
JK		 450 page_ref_add(wi->umr.dma_info[i].page,
451 mlx5e_mpwqe_strides_per_page(rq));
bc77b240
TT		 452 wi->skbs_frags[i] = 0;
453 }
454
455 wi->consumed_strides = 0;
456 wi->dma_pre_sync = mlx5e_dma_pre_sync_fragmented_mpwqe;
457 wi->add_skb_frag = mlx5e_add_skb_frag_fragmented_mpwqe;
458 wi->copy_skb_header = mlx5e_copy_skb_header_fragmented_mpwqe;
459 wi->free_wqe = mlx5e_free_rx_fragmented_mpwqe;
460 wqe->data.lkey = rq->umr_mkey_be;
461 wqe->data.addr = cpu_to_be64(dma_offset);
462
463 return 0;
464
465err_unmap:
466 while (--i >= 0) {
467 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
468 PCI_DMA_FROMDEVICE);
0139aa7b
JK		 469 page_ref_sub(wi->umr.dma_info[i].page,
470 mlx5e_mpwqe_strides_per_page(rq));
bc77b240
TT		 471 put_page(wi->umr.dma_info[i].page);
472 }
473 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
474
475err_free_mtt:
476 kfree(wi->umr.mtt_no_align);
477
478err_free_umr:
479 kfree(wi->umr.dma_info);
480
481err_out:
482 return -ENOMEM;
483}
484
485void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
486 struct mlx5e_mpw_info *wi)
487{
488 int mtt_sz = mlx5e_get_wqe_mtt_sz();
489 int i;
490
491 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
492 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
493 PCI_DMA_FROMDEVICE);
0139aa7b
JK		 494 page_ref_sub(wi->umr.dma_info[i].page,
495 mlx5e_mpwqe_strides_per_page(rq) - wi->skbs_frags[i]);
bc77b240
TT		 496 put_page(wi->umr.dma_info[i].page);
497 }
498 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
499 kfree(wi->umr.mtt_no_align);
500 kfree(wi->umr.dma_info);
501}
502
503void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq)
504{
505 struct mlx5_wq_ll *wq = &rq->wq;
506 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
507
508 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
509 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
510 rq->stats.mpwqe_frag++;
511
512 /* ensure wqes are visible to device before updating doorbell record */
513 dma_wmb();
514
515 mlx5_wq_ll_update_db_record(wq);
516}
517
518static int mlx5e_alloc_rx_linear_mpwqe(struct mlx5e_rq *rq,
519 struct mlx5e_rx_wqe *wqe,
520 u16 ix)
461017cb
TT		 521{
522 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
523 gfp_t gfp_mask;
524 int i;
525
526 gfp_mask = GFP_ATOMIC | __GFP_COLD | __GFP_MEMALLOC;
527 wi->dma_info.page = alloc_pages_node(NUMA_NO_NODE, gfp_mask,
528 MLX5_MPWRQ_WQE_PAGE_ORDER);
529 if (unlikely(!wi->dma_info.page))
530 return -ENOMEM;
531
532 wi->dma_info.addr = dma_map_page(rq->pdev, wi->dma_info.page, 0,
533 rq->wqe_sz, PCI_DMA_FROMDEVICE);
534 if (unlikely(dma_mapping_error(rq->pdev, wi->dma_info.addr))) {
535 put_page(wi->dma_info.page);
536 return -ENOMEM;
537 }
538
539 /* We split the high-order page into order-0 ones and manage their
540 * reference counter to minimize the memory held by small skb fragments
541 */
542 split_page(wi->dma_info.page, MLX5_MPWRQ_WQE_PAGE_ORDER);
543 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
0139aa7b
JK		 544 page_ref_add(&wi->dma_info.page[i],
545 mlx5e_mpwqe_strides_per_page(rq));
461017cb
TT		 546 wi->skbs_frags[i] = 0;
547 }
548
549 wi->consumed_strides = 0;
bc77b240
TT		 550 wi->dma_pre_sync = mlx5e_dma_pre_sync_linear_mpwqe;
551 wi->add_skb_frag = mlx5e_add_skb_frag_linear_mpwqe;
552 wi->copy_skb_header = mlx5e_copy_skb_header_linear_mpwqe;
553 wi->free_wqe = mlx5e_free_rx_linear_mpwqe;
554 wqe->data.lkey = rq->mkey_be;
555 wqe->data.addr = cpu_to_be64(wi->dma_info.addr);
556
557 return 0;
558}
559
560void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
561 struct mlx5e_mpw_info *wi)
562{
563 int i;
564
565 dma_unmap_page(rq->pdev, wi->dma_info.addr, rq->wqe_sz,
566 PCI_DMA_FROMDEVICE);
567 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
0139aa7b
JK		 568 page_ref_sub(&wi->dma_info.page[i],
569 mlx5e_mpwqe_strides_per_page(rq) - wi->skbs_frags[i]);
bc77b240
TT		 570 put_page(&wi->dma_info.page[i]);
571 }
572}
573
574int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
575{
576 int err;
577
578 err = mlx5e_alloc_rx_linear_mpwqe(rq, wqe, ix);
579 if (unlikely(err)) {
580 err = mlx5e_alloc_rx_fragmented_mpwqe(rq, wqe, ix);
581 if (unlikely(err))
582 return err;
583 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
584 mlx5e_post_umr_wqe(rq, ix);
585 return -EBUSY;
586 }
461017cb
TT		 587
588 return 0;
589}
590
6cd392a0
DJ		 591void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
592{
593 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
594
595 wi->free_wqe(rq, wi);
596}
597
bc77b240 598#define RQ_CANNOT_POST(rq) \
f2fde18c
SM		 599 (test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state) || \
600 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
bc77b240 601
e586b3b0
AV		 602bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
603{
604 struct mlx5_wq_ll *wq = &rq->wq;
605
bc77b240 606 if (unlikely(RQ_CANNOT_POST(rq)))
e586b3b0
AV		 607 return false;
608
609 while (!mlx5_wq_ll_is_full(wq)) {
610 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
54984407 611 int err;
e586b3b0 612
54984407
TT		 613 err = rq->alloc_wqe(rq, wqe, wq->head);
614 if (unlikely(err)) {
615 if (err != -EBUSY)
616 rq->stats.buff_alloc_err++;
e586b3b0 617 break;
54984407 618 }
e586b3b0
AV		 619
620 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
621 }
622
623 /* ensure wqes are visible to device before updating doorbell record */
624 dma_wmb();
625
626 mlx5_wq_ll_update_db_record(wq);
627
628 return !mlx5_wq_ll_is_full(wq);
629}
630
461017cb
TT		 631static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
632 u32 cqe_bcnt)
e586b3b0
AV		 633{
634 struct ethhdr *eth = (struct ethhdr *)(skb->data);
635 struct iphdr *ipv4 = (struct iphdr *)(skb->data + ETH_HLEN);
636 struct ipv6hdr *ipv6 = (struct ipv6hdr *)(skb->data + ETH_HLEN);
637 struct tcphdr *tcp;
638
639 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
640 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
641 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
642
461017cb 643 u16 tot_len = cqe_bcnt - ETH_HLEN;
e586b3b0
AV		 644
645 if (eth->h_proto == htons(ETH_P_IP)) {
646 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
647 sizeof(struct iphdr));
648 ipv6 = NULL;
d9a40271 649 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
e586b3b0
AV		 650 } else {
651 tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
652 sizeof(struct ipv6hdr));
653 ipv4 = NULL;
d9a40271 654 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
e586b3b0
AV		 655 }
656
657 if (get_cqe_lro_tcppsh(cqe))
658 tcp->psh = 1;
659
660 if (tcp_ack) {
661 tcp->ack = 1;
662 tcp->ack_seq = cqe->lro_ack_seq_num;
663 tcp->window = cqe->lro_tcp_win;
664 }
665
666 if (ipv4) {
667 ipv4->ttl = cqe->lro_min_ttl;
668 ipv4->tot_len = cpu_to_be16(tot_len);
669 ipv4->check = 0;
670 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
671 ipv4->ihl);
672 } else {
673 ipv6->hop_limit = cqe->lro_min_ttl;
674 ipv6->payload_len = cpu_to_be16(tot_len -
675 sizeof(struct ipv6hdr));
676 }
677}
678
679static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
680 struct sk_buff *skb)
681{
682 u8 cht = cqe->rss_hash_type;
683 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
684 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
685 PKT_HASH_TYPE_NONE;
686 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
687}
688
bbceefce
AS		 689static inline bool is_first_ethertype_ip(struct sk_buff *skb)
690{
691 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
692
693 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
694}
695
696static inline void mlx5e_handle_csum(struct net_device *netdev,
697 struct mlx5_cqe64 *cqe,
698 struct mlx5e_rq *rq,
5f6d12d1
MF		 699 struct sk_buff *skb,
700 bool lro)
bbceefce
AS		 701{
702 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
703 goto csum_none;
704
5f6d12d1 705 if (lro) {
bbceefce 706 skb->ip_summed = CHECKSUM_UNNECESSARY;
1b223dd3
SM		 707 return;
708 }
709
710 if (is_first_ethertype_ip(skb)) {
bbceefce 711 skb->ip_summed = CHECKSUM_COMPLETE;
ecf842f6 712 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
bfe6d8d1 713 rq->stats.csum_complete++;
1b223dd3 714 return;
bbceefce
AS		 715 }
716
1b223dd3
SM		 717 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
718 (cqe->hds_ip_ext & CQE_L4_OK))) {
719 skb->ip_summed = CHECKSUM_UNNECESSARY;
720 if (cqe_is_tunneled(cqe)) {
721 skb->csum_level = 1;
722 skb->encapsulation = 1;
bfe6d8d1 723 rq->stats.csum_unnecessary_inner++;
1b223dd3
SM		 724 }
725 return;
726 }
bbceefce
AS		 727csum_none:
728 skb->ip_summed = CHECKSUM_NONE;
729 rq->stats.csum_none++;
730}
731
e586b3b0 732static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
461017cb 733 u32 cqe_bcnt,
e586b3b0
AV		 734 struct mlx5e_rq *rq,
735 struct sk_buff *skb)
736{
737 struct net_device *netdev = rq->netdev;
ef9814de 738 struct mlx5e_tstamp *tstamp = rq->tstamp;
e586b3b0
AV		 739 int lro_num_seg;
740
e586b3b0
AV		 741 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
742 if (lro_num_seg > 1) {
461017cb 743 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
d9a40271 744 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
e586b3b0
AV		 745 rq->stats.lro_packets++;
746 rq->stats.lro_bytes += cqe_bcnt;
747 }
748
ef9814de
EBE		 749 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
750 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
751
e586b3b0
AV		 752 skb_record_rx_queue(skb, rq->ix);
753
754 if (likely(netdev->features & NETIF_F_RXHASH))
755 mlx5e_skb_set_hash(cqe, skb);
756
757 if (cqe_has_vlan(cqe))
758 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
759 be16_to_cpu(cqe->vlan_info));
12185a9f
AV		 760
761 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
e20a0db3
SM		 762
763 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
764 skb->protocol = eth_type_trans(skb, netdev);
e586b3b0
AV		 765}
766
461017cb
TT		 767static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
768 struct mlx5_cqe64 *cqe,
769 u32 cqe_bcnt,
770 struct sk_buff *skb)
771{
772 rq->stats.packets++;
773 rq->stats.bytes += cqe_bcnt;
774 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
775 napi_gro_receive(rq->cq.napi, skb);
776}
777
2f48af12
TT		 778void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
779{
780 struct mlx5e_rx_wqe *wqe;
781 struct sk_buff *skb;
782 __be16 wqe_counter_be;
783 u16 wqe_counter;
461017cb 784 u32 cqe_bcnt;
2f48af12
TT		 785
786 wqe_counter_be = cqe->wqe_counter;
787 wqe_counter = be16_to_cpu(wqe_counter_be);
788 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
789 skb = rq->skb[wqe_counter];
790 prefetch(skb->data);
791 rq->skb[wqe_counter] = NULL;
792
793 dma_unmap_single(rq->pdev,
794 *((dma_addr_t *)skb->cb),
795 rq->wqe_sz,
796 DMA_FROM_DEVICE);
797
798 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
799 rq->stats.wqe_err++;
800 dev_kfree_skb(skb);
801 goto wq_ll_pop;
802 }
803
461017cb
TT		 804 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
805 skb_put(skb, cqe_bcnt);
806
807 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
2f48af12
TT		 808
809wq_ll_pop:
810 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
811 &wqe->next.next_wqe_index);
812}
813
bc77b240
TT		 814static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
815 struct mlx5_cqe64 *cqe,
816 struct mlx5e_mpw_info *wi,
817 u32 cqe_bcnt,
818 struct sk_buff *skb)
819{
d9d9f156 820 u32 consumed_bytes = ALIGN(cqe_bcnt, rq->mpwqe_stride_sz);
bc77b240 821 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
d9d9f156 822 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
bc77b240
TT		 823 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
824 u32 page_idx = wqe_offset >> PAGE_SHIFT;
825 u32 head_page_idx = page_idx;
826 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
827 u32 frag_offset = head_offset + headlen;
828 u16 byte_cnt = cqe_bcnt - headlen;
829
bc77b240
TT		 830 if (unlikely(frag_offset >= PAGE_SIZE)) {
831 page_idx++;
832 frag_offset -= PAGE_SIZE;
833 }
bc77b240
TT		 834 wi->dma_pre_sync(rq->pdev, wi, wqe_offset, consumed_bytes);
835
836 while (byte_cnt) {
837 u32 pg_consumed_bytes =
838 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
839
d9d9f156 840 wi->add_skb_frag(rq, skb, wi, page_idx, frag_offset,
bc77b240
TT		 841 pg_consumed_bytes);
842 byte_cnt -= pg_consumed_bytes;
843 frag_offset = 0;
844 page_idx++;
845 }
846 /* copy header */
847 wi->copy_skb_header(rq->pdev, skb, wi, head_page_idx, head_offset,
848 headlen);
849 /* skb linear part was allocated with headlen and aligned to long */
850 skb->tail += headlen;
851 skb->len += headlen;
852}
853
461017cb
TT		 854void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
855{
856 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
461017cb
TT		 857 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
858 struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id];
859 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
860 struct sk_buff *skb;
461017cb 861 u16 cqe_bcnt;
461017cb
TT		 862
863 wi->consumed_strides += cstrides;
864
865 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
866 rq->stats.wqe_err++;
867 goto mpwrq_cqe_out;
868 }
869
870 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
871 rq->stats.mpwqe_filler++;
872 goto mpwrq_cqe_out;
873 }
874
c5adb96f
TT		 875 skb = napi_alloc_skb(rq->cq.napi,
876 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
877 sizeof(long)));
54984407
TT		 878 if (unlikely(!skb)) {
879 rq->stats.buff_alloc_err++;
461017cb 880 goto mpwrq_cqe_out;
54984407 881 }
461017cb
TT		 882
883 prefetch(skb->data);
461017cb 884 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
461017cb 885
bc77b240 886 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
461017cb
TT		 887 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
888
889mpwrq_cqe_out:
d9d9f156 890 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
461017cb
TT		 891 return;
892
bc77b240 893 wi->free_wqe(rq, wi);
461017cb
TT		 894 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
895}
896
44fb6fbb 897int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
e586b3b0 898{
e3391054 899 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
7219ab34 900 int work_done = 0;
e586b3b0 901
f2fde18c 902 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state)))
6cd392a0
DJ		 903 return 0;
904
7219ab34
TT		 905 if (cq->decmprs_left)
906 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
907
908 for (; work_done < budget; work_done++) {
2f48af12 909 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
e586b3b0 910
e586b3b0
AV		 911 if (!cqe)
912 break;
913
7219ab34
TT		 914 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
915 work_done +=
916 mlx5e_decompress_cqes_start(rq, cq,
917 budget - work_done);
918 continue;
919 }
920
a1f5a1a8
AS		 921 mlx5_cqwq_pop(&cq->wq);
922
2f48af12 923 rq->handle_rx_cqe(rq, cqe);
e586b3b0
AV		 924 }
925
926 mlx5_cqwq_update_db_record(&cq->wq);
927
928 /* ensure cq space is freed before enabling more cqes */
929 wmb();
930
44fb6fbb 931 return work_done;
e586b3b0 932}
Linux kernel - Deliverables
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