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net/mlx5: Add devlink interface
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.c
CommitLineData
073bb189
SM		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
86d722ad 37#include <linux/mlx5/fs.h>
073bb189
SM		 38#include "mlx5_core.h"
39#include "eswitch.h"
40
81848731
SM		 41#define UPLINK_VPORT 0xFFFF
42
073bb189
SM		 43enum {
44 MLX5_ACTION_NONE = 0,
45 MLX5_ACTION_ADD = 1,
46 MLX5_ACTION_DEL = 2,
47};
48
81848731
SM		 49/* E-Switch UC L2 table hash node */
50struct esw_uc_addr {
073bb189 51 struct l2addr_node node;
073bb189
SM		 52 u32 table_index;
53 u32 vport;
54};
55
81848731
SM		 56/* E-Switch MC FDB table hash node */
57struct esw_mc_addr { /* SRIOV only */
58 struct l2addr_node node;
59 struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */
60 u32 refcnt;
61};
62
63/* Vport UC/MC hash node */
64struct vport_addr {
65 struct l2addr_node node;
66 u8 action;
67 u32 vport;
68 struct mlx5_flow_rule *flow_rule; /* SRIOV only */
a35f71f2
MHY		 69 /* A flag indicating that mac was added due to mc promiscuous vport */
70 bool mc_promisc;
073bb189
SM		 71};
72
73enum {
74 UC_ADDR_CHANGE = BIT(0),
75 MC_ADDR_CHANGE = BIT(1),
a35f71f2 76 PROMISC_CHANGE = BIT(3),
073bb189
SM		 77};
78
81848731
SM		 79/* Vport context events */
80#define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
a35f71f2
MHY		 81 MC_ADDR_CHANGE | \
82 PROMISC_CHANGE)
81848731 83
69697b6e
OG		 84int esw_create_offloads_fdb_table(struct mlx5_eswitch *esw, int nvports);
85void esw_destroy_offloads_fdb_table(struct mlx5_eswitch *esw);
86
81848731 87static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
073bb189
SM		 88 u32 events_mask)
89{
90 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)];
91 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)];
92 void *nic_vport_ctx;
93 int err;
94
95 memset(out, 0, sizeof(out));
96 memset(in, 0, sizeof(in));
97
98 MLX5_SET(modify_nic_vport_context_in, in,
99 opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
100 MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
101 MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
102 if (vport)
103 MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
104 nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
105 in, nic_vport_context);
106
107 MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
108
109 if (events_mask & UC_ADDR_CHANGE)
110 MLX5_SET(nic_vport_context, nic_vport_ctx,
111 event_on_uc_address_change, 1);
112 if (events_mask & MC_ADDR_CHANGE)
113 MLX5_SET(nic_vport_context, nic_vport_ctx,
114 event_on_mc_address_change, 1);
a35f71f2
MHY		 115 if (events_mask & PROMISC_CHANGE)
116 MLX5_SET(nic_vport_context, nic_vport_ctx,
117 event_on_promisc_change, 1);
073bb189
SM		 118
119 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
120 if (err)
121 goto ex;
122 err = mlx5_cmd_status_to_err_v2(out);
123 if (err)
124 goto ex;
125 return 0;
126ex:
127 return err;
128}
129
9e7ea352
SM		 130/* E-Switch vport context HW commands */
131static int query_esw_vport_context_cmd(struct mlx5_core_dev *mdev, u32 vport,
132 u32 *out, int outlen)
133{
134 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)];
135
136 memset(in, 0, sizeof(in));
137
138 MLX5_SET(query_nic_vport_context_in, in, opcode,
139 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
140
141 MLX5_SET(query_esw_vport_context_in, in, vport_number, vport);
142 if (vport)
143 MLX5_SET(query_esw_vport_context_in, in, other_vport, 1);
144
145 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in), out, outlen);
146}
147
148static int query_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
149 u16 *vlan, u8 *qos)
150{
151 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)];
152 int err;
153 bool cvlan_strip;
154 bool cvlan_insert;
155
156 memset(out, 0, sizeof(out));
157
158 *vlan = 0;
159 *qos = 0;
160
161 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
162 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
163 return -ENOTSUPP;
164
165 err = query_esw_vport_context_cmd(dev, vport, out, sizeof(out));
166 if (err)
167 goto out;
168
169 cvlan_strip = MLX5_GET(query_esw_vport_context_out, out,
170 esw_vport_context.vport_cvlan_strip);
171
172 cvlan_insert = MLX5_GET(query_esw_vport_context_out, out,
173 esw_vport_context.vport_cvlan_insert);
174
175 if (cvlan_strip || cvlan_insert) {
176 *vlan = MLX5_GET(query_esw_vport_context_out, out,
177 esw_vport_context.cvlan_id);
178 *qos = MLX5_GET(query_esw_vport_context_out, out,
179 esw_vport_context.cvlan_pcp);
180 }
181
182 esw_debug(dev, "Query Vport[%d] cvlan: VLAN %d qos=%d\n",
183 vport, *vlan, *qos);
184out:
185 return err;
186}
187
188static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport,
189 void *in, int inlen)
190{
191 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)];
192
193 memset(out, 0, sizeof(out));
194
195 MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport);
196 if (vport)
197 MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1);
198
199 MLX5_SET(modify_esw_vport_context_in, in, opcode,
200 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT);
201
202 return mlx5_cmd_exec_check_status(dev, in, inlen,
203 out, sizeof(out));
204}
205
206static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
207 u16 vlan, u8 qos, bool set)
208{
209 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)];
210
211 memset(in, 0, sizeof(in));
212
213 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
214 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
215 return -ENOTSUPP;
216
217 esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%d\n",
218 vport, vlan, qos, set);
219
220 if (set) {
221 MLX5_SET(modify_esw_vport_context_in, in,
222 esw_vport_context.vport_cvlan_strip, 1);
223 /* insert only if no vlan in packet */
224 MLX5_SET(modify_esw_vport_context_in, in,
225 esw_vport_context.vport_cvlan_insert, 1);
226 MLX5_SET(modify_esw_vport_context_in, in,
227 esw_vport_context.cvlan_pcp, qos);
228 MLX5_SET(modify_esw_vport_context_in, in,
229 esw_vport_context.cvlan_id, vlan);
230 }
231
232 MLX5_SET(modify_esw_vport_context_in, in,
233 field_select.vport_cvlan_strip, 1);
234 MLX5_SET(modify_esw_vport_context_in, in,
235 field_select.vport_cvlan_insert, 1);
236
237 return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in));
238}
239
073bb189
SM		 240/* HW L2 Table (MPFS) management */
241static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
242 u8 *mac, u8 vlan_valid, u16 vlan)
243{
244 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)];
245 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)];
246 u8 *in_mac_addr;
247
248 memset(in, 0, sizeof(in));
249 memset(out, 0, sizeof(out));
250
251 MLX5_SET(set_l2_table_entry_in, in, opcode,
252 MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
253 MLX5_SET(set_l2_table_entry_in, in, table_index, index);
254 MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
255 MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
256
257 in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
258 ether_addr_copy(&in_mac_addr[2], mac);
259
260 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
261 out, sizeof(out));
262}
263
264static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
265{
266 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)];
267 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)];
268
269 memset(in, 0, sizeof(in));
270 memset(out, 0, sizeof(out));
271
272 MLX5_SET(delete_l2_table_entry_in, in, opcode,
273 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
274 MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
275 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
276 out, sizeof(out));
277}
278
279static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
280{
281 int err = 0;
282
283 *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
284 if (*ix >= l2_table->size)
285 err = -ENOSPC;
286 else
287 __set_bit(*ix, l2_table->bitmap);
288
289 return err;
290}
291
292static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
293{
294 __clear_bit(ix, l2_table->bitmap);
295}
296
297static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
298 u8 vlan_valid, u16 vlan,
299 u32 *index)
300{
301 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
302 int err;
303
304 err = alloc_l2_table_index(l2_table, index);
305 if (err)
306 return err;
307
308 err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
309 if (err)
310 free_l2_table_index(l2_table, *index);
311
312 return err;
313}
314
315static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
316{
317 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
318
319 del_l2_table_entry_cmd(dev, index);
320 free_l2_table_index(l2_table, index);
321}
322
81848731
SM		 323/* E-Switch FDB */
324static struct mlx5_flow_rule *
a35f71f2 325__esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule,
78a9199b 326 u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN])
81848731 327{
78a9199b
MHY		 328 int match_header = (is_zero_ether_addr(mac_c) ? 0 :
329 MLX5_MATCH_OUTER_HEADERS);
81848731 330 struct mlx5_flow_rule *flow_rule = NULL;
78a9199b 331 struct mlx5_flow_destination dest;
a35f71f2
MHY		 332 void *mv_misc = NULL;
333 void *mc_misc = NULL;
78a9199b
MHY		 334 u8 *dmac_v = NULL;
335 u8 *dmac_c = NULL;
81848731
SM		 336 u32 *match_v;
337 u32 *match_c;
81848731 338
a35f71f2
MHY		 339 if (rx_rule)
340 match_header |= MLX5_MATCH_MISC_PARAMETERS;
81848731
SM		 341 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
342 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
343 if (!match_v || !match_c) {
344 pr_warn("FDB: Failed to alloc match parameters\n");
345 goto out;
346 }
78a9199b 347
81848731
SM		 348 dmac_v = MLX5_ADDR_OF(fte_match_param, match_v,
349 outer_headers.dmac_47_16);
350 dmac_c = MLX5_ADDR_OF(fte_match_param, match_c,
351 outer_headers.dmac_47_16);
352
a35f71f2 353 if (match_header & MLX5_MATCH_OUTER_HEADERS) {
78a9199b
MHY		 354 ether_addr_copy(dmac_v, mac_v);
355 ether_addr_copy(dmac_c, mac_c);
356 }
81848731 357
a35f71f2
MHY		 358 if (match_header & MLX5_MATCH_MISC_PARAMETERS) {
359 mv_misc = MLX5_ADDR_OF(fte_match_param, match_v, misc_parameters);
360 mc_misc = MLX5_ADDR_OF(fte_match_param, match_c, misc_parameters);
361 MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT);
362 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port);
363 }
364
81848731
SM		 365 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
366 dest.vport_num = vport;
367
368 esw_debug(esw->dev,
369 "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
370 dmac_v, dmac_c, vport);
371 flow_rule =
86d722ad 372 mlx5_add_flow_rule(esw->fdb_table.fdb,
81848731
SM		 373 match_header,
374 match_c,
375 match_v,
376 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
377 0, &dest);
3f42ac66 378 if (IS_ERR(flow_rule)) {
81848731
SM		 379 pr_warn(
380 "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
381 dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
382 flow_rule = NULL;
383 }
384out:
385 kfree(match_v);
386 kfree(match_c);
387 return flow_rule;
388}
389
78a9199b
MHY		 390static struct mlx5_flow_rule *
391esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
392{
393 u8 mac_c[ETH_ALEN];
394
395 eth_broadcast_addr(mac_c);
a35f71f2
MHY		 396 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac);
397}
398
399static struct mlx5_flow_rule *
400esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport)
401{
402 u8 mac_c[ETH_ALEN];
403 u8 mac_v[ETH_ALEN];
404
405 eth_zero_addr(mac_c);
406 eth_zero_addr(mac_v);
407 mac_c[0] = 0x01;
408 mac_v[0] = 0x01;
409 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v);
410}
411
412static struct mlx5_flow_rule *
413esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport)
414{
415 u8 mac_c[ETH_ALEN];
416 u8 mac_v[ETH_ALEN];
417
418 eth_zero_addr(mac_c);
419 eth_zero_addr(mac_v);
420 return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v);
78a9199b
MHY		 421}
422
6ab36e35 423static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw, int nvports)
81848731 424{
86d722ad 425 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
81848731 426 struct mlx5_core_dev *dev = esw->dev;
86d722ad 427 struct mlx5_flow_namespace *root_ns;
81848731 428 struct mlx5_flow_table *fdb;
86d722ad
MG		 429 struct mlx5_flow_group *g;
430 void *match_criteria;
431 int table_size;
432 u32 *flow_group_in;
81848731 433 u8 *dmac;
86d722ad 434 int err = 0;
81848731
SM		 435
436 esw_debug(dev, "Create FDB log_max_size(%d)\n",
437 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
438
86d722ad
MG		 439 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
440 if (!root_ns) {
441 esw_warn(dev, "Failed to get FDB flow namespace\n");
442 return -ENOMEM;
443 }
81848731 444
86d722ad
MG		 445 flow_group_in = mlx5_vzalloc(inlen);
446 if (!flow_group_in)
447 return -ENOMEM;
448 memset(flow_group_in, 0, inlen);
449
450 table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
d63cd286 451 fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0);
3f42ac66 452 if (IS_ERR(fdb)) {
86d722ad
MG		 453 err = PTR_ERR(fdb);
454 esw_warn(dev, "Failed to create FDB Table err %d\n", err);
455 goto out;
456 }
78a9199b 457 esw->fdb_table.fdb = fdb;
81848731 458
78a9199b 459 /* Addresses group : Full match unicast/multicast addresses */
86d722ad
MG		 460 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
461 MLX5_MATCH_OUTER_HEADERS);
462 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
463 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16);
464 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
78a9199b
MHY		 465 /* Preserve 2 entries for allmulti and promisc rules*/
466 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3);
86d722ad 467 eth_broadcast_addr(dmac);
86d722ad 468 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 469 if (IS_ERR(g)) {
86d722ad
MG		 470 err = PTR_ERR(g);
471 esw_warn(dev, "Failed to create flow group err(%d)\n", err);
472 goto out;
473 }
6ab36e35 474 esw->fdb_table.legacy.addr_grp = g;
78a9199b
MHY		 475
476 /* Allmulti group : One rule that forwards any mcast traffic */
477 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
478 MLX5_MATCH_OUTER_HEADERS);
479 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2);
480 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2);
481 eth_zero_addr(dmac);
482 dmac[0] = 0x01;
483 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 484 if (IS_ERR(g)) {
78a9199b
MHY		 485 err = PTR_ERR(g);
486 esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err);
487 goto out;
488 }
6ab36e35 489 esw->fdb_table.legacy.allmulti_grp = g;
78a9199b
MHY		 490
491 /* Promiscuous group :
492 * One rule that forward all unmatched traffic from previous groups
493 */
494 eth_zero_addr(dmac);
495 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
496 MLX5_MATCH_MISC_PARAMETERS);
497 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
498 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1);
499 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1);
500 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 501 if (IS_ERR(g)) {
78a9199b
MHY		 502 err = PTR_ERR(g);
503 esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err);
504 goto out;
505 }
6ab36e35 506 esw->fdb_table.legacy.promisc_grp = g;
78a9199b 507
86d722ad 508out:
78a9199b 509 if (err) {
6ab36e35
OG		 510 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.allmulti_grp)) {
511 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
512 esw->fdb_table.legacy.allmulti_grp = NULL;
78a9199b 513 }
6ab36e35
OG		 514 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.addr_grp)) {
515 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
516 esw->fdb_table.legacy.addr_grp = NULL;
78a9199b
MHY		 517 }
518 if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) {
519 mlx5_destroy_flow_table(esw->fdb_table.fdb);
520 esw->fdb_table.fdb = NULL;
521 }
522 }
523
3fe3d819 524 kvfree(flow_group_in);
86d722ad 525 return err;
81848731
SM		 526}
527
6ab36e35 528static void esw_destroy_legacy_fdb_table(struct mlx5_eswitch *esw)
81848731
SM		 529{
530 if (!esw->fdb_table.fdb)
531 return;
532
86d722ad 533 esw_debug(esw->dev, "Destroy FDB Table\n");
6ab36e35
OG		 534 mlx5_destroy_flow_group(esw->fdb_table.legacy.promisc_grp);
535 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
536 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
81848731
SM		 537 mlx5_destroy_flow_table(esw->fdb_table.fdb);
538 esw->fdb_table.fdb = NULL;
6ab36e35
OG		 539 esw->fdb_table.legacy.addr_grp = NULL;
540 esw->fdb_table.legacy.allmulti_grp = NULL;
541 esw->fdb_table.legacy.promisc_grp = NULL;
81848731
SM		 542}
543
544/* E-Switch vport UC/MC lists management */
545typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
546 struct vport_addr *vaddr);
547
548static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
549{
550 struct hlist_head *hash = esw->l2_table.l2_hash;
551 struct esw_uc_addr *esw_uc;
552 u8 *mac = vaddr->node.addr;
553 u32 vport = vaddr->vport;
554 int err;
555
556 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
557 if (esw_uc) {
073bb189
SM		 558 esw_warn(esw->dev,
559 "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
81848731 560 mac, vport, esw_uc->vport);
073bb189
SM		 561 return -EEXIST;
562 }
563
81848731
SM		 564 esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
565 if (!esw_uc)
073bb189 566 return -ENOMEM;
81848731 567 esw_uc->vport = vport;
073bb189 568
81848731 569 err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
073bb189 570 if (err)
81848731
SM		 571 goto abort;
572
69697b6e
OG		 573 /* SRIOV is enabled: Forward UC MAC to vport */
574 if (esw->fdb_table.fdb && esw->mode == SRIOV_LEGACY)
81848731
SM		 575 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
576
577 esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
578 vport, mac, esw_uc->table_index, vaddr->flow_rule);
579 return err;
580abort:
581 l2addr_hash_del(esw_uc);
073bb189
SM		 582 return err;
583}
584
81848731 585static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
073bb189 586{
81848731
SM		 587 struct hlist_head *hash = esw->l2_table.l2_hash;
588 struct esw_uc_addr *esw_uc;
589 u8 *mac = vaddr->node.addr;
590 u32 vport = vaddr->vport;
591
592 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
593 if (!esw_uc || esw_uc->vport != vport) {
594 esw_debug(esw->dev,
595 "MAC(%pM) doesn't belong to vport (%d)\n",
596 mac, vport);
597 return -EINVAL;
598 }
599 esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
600 vport, mac, esw_uc->table_index, vaddr->flow_rule);
601
602 del_l2_table_entry(esw->dev, esw_uc->table_index);
603
604 if (vaddr->flow_rule)
86d722ad 605 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 606 vaddr->flow_rule = NULL;
607
608 l2addr_hash_del(esw_uc);
609 return 0;
610}
611
a35f71f2
MHY		 612static void update_allmulti_vports(struct mlx5_eswitch *esw,
613 struct vport_addr *vaddr,
614 struct esw_mc_addr *esw_mc)
615{
616 u8 *mac = vaddr->node.addr;
617 u32 vport_idx = 0;
618
619 for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) {
620 struct mlx5_vport *vport = &esw->vports[vport_idx];
621 struct hlist_head *vport_hash = vport->mc_list;
622 struct vport_addr *iter_vaddr =
623 l2addr_hash_find(vport_hash,
624 mac,
625 struct vport_addr);
626 if (IS_ERR_OR_NULL(vport->allmulti_rule) ||
627 vaddr->vport == vport_idx)
628 continue;
629 switch (vaddr->action) {
630 case MLX5_ACTION_ADD:
631 if (iter_vaddr)
632 continue;
633 iter_vaddr = l2addr_hash_add(vport_hash, mac,
634 struct vport_addr,
635 GFP_KERNEL);
636 if (!iter_vaddr) {
637 esw_warn(esw->dev,
638 "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n",
639 mac, vport_idx);
640 continue;
641 }
642 iter_vaddr->vport = vport_idx;
643 iter_vaddr->flow_rule =
644 esw_fdb_set_vport_rule(esw,
645 mac,
646 vport_idx);
62e3c24a 647 iter_vaddr->mc_promisc = true;
a35f71f2
MHY		 648 break;
649 case MLX5_ACTION_DEL:
650 if (!iter_vaddr)
651 continue;
652 mlx5_del_flow_rule(iter_vaddr->flow_rule);
653 l2addr_hash_del(iter_vaddr);
654 break;
655 }
656 }
657}
658
81848731
SM		 659static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
660{
661 struct hlist_head *hash = esw->mc_table;
662 struct esw_mc_addr *esw_mc;
663 u8 *mac = vaddr->node.addr;
664 u32 vport = vaddr->vport;
665
666 if (!esw->fdb_table.fdb)
667 return 0;
668
669 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
670 if (esw_mc)
671 goto add;
672
673 esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
674 if (!esw_mc)
675 return -ENOMEM;
676
677 esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
678 esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
a35f71f2
MHY		 679
680 /* Add this multicast mac to all the mc promiscuous vports */
681 update_allmulti_vports(esw, vaddr, esw_mc);
682
81848731 683add:
a35f71f2
MHY		 684 /* If the multicast mac is added as a result of mc promiscuous vport,
685 * don't increment the multicast ref count
686 */
687 if (!vaddr->mc_promisc)
688 esw_mc->refcnt++;
689
81848731
SM		 690 /* Forward MC MAC to vport */
691 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
692 esw_debug(esw->dev,
693 "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
694 vport, mac, vaddr->flow_rule,
695 esw_mc->refcnt, esw_mc->uplink_rule);
696 return 0;
697}
698
699static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
700{
701 struct hlist_head *hash = esw->mc_table;
702 struct esw_mc_addr *esw_mc;
703 u8 *mac = vaddr->node.addr;
704 u32 vport = vaddr->vport;
073bb189 705
81848731
SM		 706 if (!esw->fdb_table.fdb)
707 return 0;
708
709 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
710 if (!esw_mc) {
711 esw_warn(esw->dev,
712 "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
073bb189
SM		 713 mac, vport);
714 return -EINVAL;
715 }
81848731
SM		 716 esw_debug(esw->dev,
717 "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
718 vport, mac, vaddr->flow_rule, esw_mc->refcnt,
719 esw_mc->uplink_rule);
720
721 if (vaddr->flow_rule)
86d722ad 722 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 723 vaddr->flow_rule = NULL;
724
a35f71f2
MHY		 725 /* If the multicast mac is added as a result of mc promiscuous vport,
726 * don't decrement the multicast ref count.
727 */
728 if (vaddr->mc_promisc || (--esw_mc->refcnt > 0))
81848731 729 return 0;
073bb189 730
a35f71f2
MHY		 731 /* Remove this multicast mac from all the mc promiscuous vports */
732 update_allmulti_vports(esw, vaddr, esw_mc);
733
81848731 734 if (esw_mc->uplink_rule)
86d722ad 735 mlx5_del_flow_rule(esw_mc->uplink_rule);
81848731
SM		 736
737 l2addr_hash_del(esw_mc);
073bb189
SM		 738 return 0;
739}
740
81848731
SM		 741/* Apply vport UC/MC list to HW l2 table and FDB table */
742static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
743 u32 vport_num, int list_type)
073bb189
SM		 744{
745 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731
SM		 746 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
747 vport_addr_action vport_addr_add;
748 vport_addr_action vport_addr_del;
749 struct vport_addr *addr;
073bb189
SM		 750 struct l2addr_node *node;
751 struct hlist_head *hash;
752 struct hlist_node *tmp;
753 int hi;
754
81848731
SM		 755 vport_addr_add = is_uc ? esw_add_uc_addr :
756 esw_add_mc_addr;
757 vport_addr_del = is_uc ? esw_del_uc_addr :
758 esw_del_mc_addr;
759
760 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189 761 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 762 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 763 switch (addr->action) {
764 case MLX5_ACTION_ADD:
81848731 765 vport_addr_add(esw, addr);
073bb189
SM		 766 addr->action = MLX5_ACTION_NONE;
767 break;
768 case MLX5_ACTION_DEL:
81848731 769 vport_addr_del(esw, addr);
073bb189
SM		 770 l2addr_hash_del(addr);
771 break;
772 }
773 }
774}
775
81848731
SM		 776/* Sync vport UC/MC list from vport context */
777static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
778 u32 vport_num, int list_type)
073bb189
SM		 779{
780 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731 781 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
073bb189 782 u8 (*mac_list)[ETH_ALEN];
81848731
SM		 783 struct l2addr_node *node;
784 struct vport_addr *addr;
073bb189
SM		 785 struct hlist_head *hash;
786 struct hlist_node *tmp;
787 int size;
788 int err;
789 int hi;
790 int i;
791
81848731
SM		 792 size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
793 MLX5_MAX_MC_PER_VPORT(esw->dev);
073bb189
SM		 794
795 mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
796 if (!mac_list)
797 return;
798
81848731 799 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189
SM		 800
801 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 802 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 803 addr->action = MLX5_ACTION_DEL;
804 }
805
586cfa7f
MHY		 806 if (!vport->enabled)
807 goto out;
808
81848731 809 err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
073bb189
SM		 810 mac_list, &size);
811 if (err)
761e205b 812 goto out;
81848731
SM		 813 esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
814 vport_num, is_uc ? "UC" : "MC", size);
073bb189
SM		 815
816 for (i = 0; i < size; i++) {
81848731 817 if (is_uc && !is_valid_ether_addr(mac_list[i]))
073bb189
SM		 818 continue;
819
81848731
SM		 820 if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
821 continue;
822
823 addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
073bb189
SM		 824 if (addr) {
825 addr->action = MLX5_ACTION_NONE;
a35f71f2
MHY		 826 /* If this mac was previously added because of allmulti
827 * promiscuous rx mode, its now converted to be original
828 * vport mac.
829 */
830 if (addr->mc_promisc) {
831 struct esw_mc_addr *esw_mc =
832 l2addr_hash_find(esw->mc_table,
833 mac_list[i],
834 struct esw_mc_addr);
835 if (!esw_mc) {
836 esw_warn(esw->dev,
837 "Failed to MAC(%pM) in mcast DB\n",
838 mac_list[i]);
839 continue;
840 }
841 esw_mc->refcnt++;
842 addr->mc_promisc = false;
843 }
073bb189
SM		 844 continue;
845 }
846
81848731 847 addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
073bb189
SM		 848 GFP_KERNEL);
849 if (!addr) {
850 esw_warn(esw->dev,
851 "Failed to add MAC(%pM) to vport[%d] DB\n",
852 mac_list[i], vport_num);
853 continue;
854 }
81848731 855 addr->vport = vport_num;
073bb189
SM		 856 addr->action = MLX5_ACTION_ADD;
857 }
761e205b 858out:
073bb189
SM		 859 kfree(mac_list);
860}
861
a35f71f2
MHY		 862/* Sync vport UC/MC list from vport context
863 * Must be called after esw_update_vport_addr_list
864 */
865static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num)
866{
867 struct mlx5_vport *vport = &esw->vports[vport_num];
868 struct l2addr_node *node;
869 struct vport_addr *addr;
870 struct hlist_head *hash;
871 struct hlist_node *tmp;
872 int hi;
873
874 hash = vport->mc_list;
875
876 for_each_l2hash_node(node, tmp, esw->mc_table, hi) {
877 u8 *mac = node->addr;
878
879 addr = l2addr_hash_find(hash, mac, struct vport_addr);
880 if (addr) {
881 if (addr->action == MLX5_ACTION_DEL)
882 addr->action = MLX5_ACTION_NONE;
883 continue;
884 }
885 addr = l2addr_hash_add(hash, mac, struct vport_addr,
886 GFP_KERNEL);
887 if (!addr) {
888 esw_warn(esw->dev,
889 "Failed to add allmulti MAC(%pM) to vport[%d] DB\n",
890 mac, vport_num);
891 continue;
892 }
893 addr->vport = vport_num;
894 addr->action = MLX5_ACTION_ADD;
895 addr->mc_promisc = true;
896 }
897}
898
899/* Apply vport rx mode to HW FDB table */
900static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num,
901 bool promisc, bool mc_promisc)
902{
903 struct esw_mc_addr *allmulti_addr = esw->mc_promisc;
904 struct mlx5_vport *vport = &esw->vports[vport_num];
905
906 if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc)
907 goto promisc;
908
909 if (mc_promisc) {
910 vport->allmulti_rule =
911 esw_fdb_set_vport_allmulti_rule(esw, vport_num);
912 if (!allmulti_addr->uplink_rule)
913 allmulti_addr->uplink_rule =
914 esw_fdb_set_vport_allmulti_rule(esw,
915 UPLINK_VPORT);
916 allmulti_addr->refcnt++;
917 } else if (vport->allmulti_rule) {
918 mlx5_del_flow_rule(vport->allmulti_rule);
919 vport->allmulti_rule = NULL;
920
921 if (--allmulti_addr->refcnt > 0)
922 goto promisc;
923
924 if (allmulti_addr->uplink_rule)
925 mlx5_del_flow_rule(allmulti_addr->uplink_rule);
926 allmulti_addr->uplink_rule = NULL;
927 }
928
929promisc:
930 if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc)
931 return;
932
933 if (promisc) {
934 vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw,
935 vport_num);
936 } else if (vport->promisc_rule) {
937 mlx5_del_flow_rule(vport->promisc_rule);
938 vport->promisc_rule = NULL;
939 }
940}
941
942/* Sync vport rx mode from vport context */
943static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num)
944{
945 struct mlx5_vport *vport = &esw->vports[vport_num];
946 int promisc_all = 0;
947 int promisc_uc = 0;
948 int promisc_mc = 0;
949 int err;
950
951 err = mlx5_query_nic_vport_promisc(esw->dev,
952 vport_num,
953 &promisc_uc,
954 &promisc_mc,
955 &promisc_all);
956 if (err)
957 return;
958 esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n",
959 vport_num, promisc_all, promisc_mc);
960
961 if (!vport->trusted || !vport->enabled) {
962 promisc_uc = 0;
963 promisc_mc = 0;
964 promisc_all = 0;
965 }
966
967 esw_apply_vport_rx_mode(esw, vport_num, promisc_all,
968 (promisc_all || promisc_mc));
969}
970
1edc57e2 971static void esw_vport_change_handle_locked(struct mlx5_vport *vport)
073bb189 972{
073bb189 973 struct mlx5_core_dev *dev = vport->dev;
81848731 974 struct mlx5_eswitch *esw = dev->priv.eswitch;
073bb189
SM		 975 u8 mac[ETH_ALEN];
976
977 mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
81848731
SM		 978 esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
979 vport->vport, mac);
980
981 if (vport->enabled_events & UC_ADDR_CHANGE) {
982 esw_update_vport_addr_list(esw, vport->vport,
983 MLX5_NVPRT_LIST_TYPE_UC);
984 esw_apply_vport_addr_list(esw, vport->vport,
985 MLX5_NVPRT_LIST_TYPE_UC);
986 }
073bb189 987
81848731
SM		 988 if (vport->enabled_events & MC_ADDR_CHANGE) {
989 esw_update_vport_addr_list(esw, vport->vport,
990 MLX5_NVPRT_LIST_TYPE_MC);
a35f71f2
MHY		 991 }
992
993 if (vport->enabled_events & PROMISC_CHANGE) {
994 esw_update_vport_rx_mode(esw, vport->vport);
995 if (!IS_ERR_OR_NULL(vport->allmulti_rule))
996 esw_update_vport_mc_promisc(esw, vport->vport);
997 }
998
999 if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) {
81848731
SM		 1000 esw_apply_vport_addr_list(esw, vport->vport,
1001 MLX5_NVPRT_LIST_TYPE_MC);
1002 }
073bb189 1003
81848731 1004 esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
073bb189
SM		 1005 if (vport->enabled)
1006 arm_vport_context_events_cmd(dev, vport->vport,
81848731 1007 vport->enabled_events);
073bb189
SM		 1008}
1009
1edc57e2
MHY		 1010static void esw_vport_change_handler(struct work_struct *work)
1011{
1012 struct mlx5_vport *vport =
1013 container_of(work, struct mlx5_vport, vport_change_handler);
1014 struct mlx5_eswitch *esw = vport->dev->priv.eswitch;
1015
1016 mutex_lock(&esw->state_lock);
1017 esw_vport_change_handle_locked(vport);
1018 mutex_unlock(&esw->state_lock);
1019}
1020
5742df0f
MHY		 1021static void esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
1022 struct mlx5_vport *vport)
1023{
1024 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1025 struct mlx5_flow_group *vlan_grp = NULL;
1026 struct mlx5_flow_group *drop_grp = NULL;
1027 struct mlx5_core_dev *dev = esw->dev;
1028 struct mlx5_flow_namespace *root_ns;
1029 struct mlx5_flow_table *acl;
1030 void *match_criteria;
1031 u32 *flow_group_in;
1032 /* The egress acl table contains 2 rules:
1033 * 1)Allow traffic with vlan_tag=vst_vlan_id
1034 * 2)Drop all other traffic.
1035 */
1036 int table_size = 2;
1037 int err = 0;
1038
01f51f22
MHY		 1039 if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support) ||
1040 !IS_ERR_OR_NULL(vport->egress.acl))
5742df0f
MHY		 1041 return;
1042
1043 esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n",
1044 vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size));
1045
1046 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS);
1047 if (!root_ns) {
1048 esw_warn(dev, "Failed to get E-Switch egress flow namespace\n");
1049 return;
1050 }
1051
1052 flow_group_in = mlx5_vzalloc(inlen);
1053 if (!flow_group_in)
1054 return;
1055
1056 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1057 if (IS_ERR(acl)) {
5742df0f
MHY		 1058 err = PTR_ERR(acl);
1059 esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n",
1060 vport->vport, err);
1061 goto out;
1062 }
1063
1064 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1065 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1066 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1067 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
1068 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1069 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1070
1071 vlan_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1072 if (IS_ERR(vlan_grp)) {
5742df0f
MHY		 1073 err = PTR_ERR(vlan_grp);
1074 esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n",
1075 vport->vport, err);
1076 goto out;
1077 }
1078
1079 memset(flow_group_in, 0, inlen);
1080 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1081 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1082 drop_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1083 if (IS_ERR(drop_grp)) {
5742df0f
MHY		 1084 err = PTR_ERR(drop_grp);
1085 esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n",
1086 vport->vport, err);
1087 goto out;
1088 }
1089
1090 vport->egress.acl = acl;
1091 vport->egress.drop_grp = drop_grp;
1092 vport->egress.allowed_vlans_grp = vlan_grp;
1093out:
3fe3d819 1094 kvfree(flow_group_in);
5742df0f
MHY		 1095 if (err && !IS_ERR_OR_NULL(vlan_grp))
1096 mlx5_destroy_flow_group(vlan_grp);
1097 if (err && !IS_ERR_OR_NULL(acl))
1098 mlx5_destroy_flow_table(acl);
1099}
1100
dfcb1ed3
MHY		 1101static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
1102 struct mlx5_vport *vport)
1103{
1104 if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan))
1105 mlx5_del_flow_rule(vport->egress.allowed_vlan);
1106
1107 if (!IS_ERR_OR_NULL(vport->egress.drop_rule))
1108 mlx5_del_flow_rule(vport->egress.drop_rule);
1109
1110 vport->egress.allowed_vlan = NULL;
1111 vport->egress.drop_rule = NULL;
1112}
1113
5742df0f
MHY		 1114static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
1115 struct mlx5_vport *vport)
1116{
1117 if (IS_ERR_OR_NULL(vport->egress.acl))
1118 return;
1119
1120 esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport);
1121
dfcb1ed3 1122 esw_vport_cleanup_egress_rules(esw, vport);
5742df0f
MHY		 1123 mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp);
1124 mlx5_destroy_flow_group(vport->egress.drop_grp);
1125 mlx5_destroy_flow_table(vport->egress.acl);
1126 vport->egress.allowed_vlans_grp = NULL;
1127 vport->egress.drop_grp = NULL;
1128 vport->egress.acl = NULL;
1129}
1130
1131static void esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
1132 struct mlx5_vport *vport)
1133{
1134 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1135 struct mlx5_core_dev *dev = esw->dev;
1136 struct mlx5_flow_namespace *root_ns;
1137 struct mlx5_flow_table *acl;
1138 struct mlx5_flow_group *g;
1139 void *match_criteria;
1140 u32 *flow_group_in;
1141 /* The ingress acl table contains 4 groups
1142 * (2 active rules at the same time -
1143 * 1 allow rule from one of the first 3 groups.
1144 * 1 drop rule from the last group):
1145 * 1)Allow untagged traffic with smac=original mac.
1146 * 2)Allow untagged traffic.
1147 * 3)Allow traffic with smac=original mac.
1148 * 4)Drop all other traffic.
1149 */
1150 int table_size = 4;
1151 int err = 0;
1152
01f51f22
MHY		 1153 if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support) ||
1154 !IS_ERR_OR_NULL(vport->ingress.acl))
5742df0f
MHY		 1155 return;
1156
1157 esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n",
1158 vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size));
1159
1160 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS);
1161 if (!root_ns) {
1162 esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n");
1163 return;
1164 }
1165
1166 flow_group_in = mlx5_vzalloc(inlen);
1167 if (!flow_group_in)
1168 return;
1169
1170 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1171 if (IS_ERR(acl)) {
5742df0f
MHY		 1172 err = PTR_ERR(acl);
1173 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n",
1174 vport->vport, err);
1175 goto out;
1176 }
1177 vport->ingress.acl = acl;
1178
1179 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1180
1181 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1182 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1183 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1184 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1185 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1186 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1187
1188 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1189 if (IS_ERR(g)) {
5742df0f
MHY		 1190 err = PTR_ERR(g);
1191 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n",
1192 vport->vport, err);
1193 goto out;
1194 }
1195 vport->ingress.allow_untagged_spoofchk_grp = g;
1196
1197 memset(flow_group_in, 0, inlen);
1198 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1199 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1200 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1201 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1202
1203 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1204 if (IS_ERR(g)) {
5742df0f
MHY		 1205 err = PTR_ERR(g);
1206 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n",
1207 vport->vport, err);
1208 goto out;
1209 }
1210 vport->ingress.allow_untagged_only_grp = g;
1211
1212 memset(flow_group_in, 0, inlen);
1213 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1214 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1215 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1216 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2);
1217 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2);
1218
1219 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1220 if (IS_ERR(g)) {
5742df0f
MHY		 1221 err = PTR_ERR(g);
1222 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n",
1223 vport->vport, err);
1224 goto out;
1225 }
1226 vport->ingress.allow_spoofchk_only_grp = g;
1227
1228 memset(flow_group_in, 0, inlen);
1229 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3);
1230 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3);
1231
1232 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1233 if (IS_ERR(g)) {
5742df0f
MHY		 1234 err = PTR_ERR(g);
1235 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n",
1236 vport->vport, err);
1237 goto out;
1238 }
1239 vport->ingress.drop_grp = g;
1240
1241out:
1242 if (err) {
1243 if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp))
1244 mlx5_destroy_flow_group(
1245 vport->ingress.allow_spoofchk_only_grp);
1246 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp))
1247 mlx5_destroy_flow_group(
1248 vport->ingress.allow_untagged_only_grp);
1249 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp))
1250 mlx5_destroy_flow_group(
1251 vport->ingress.allow_untagged_spoofchk_grp);
1252 if (!IS_ERR_OR_NULL(vport->ingress.acl))
1253 mlx5_destroy_flow_table(vport->ingress.acl);
1254 }
1255
3fe3d819 1256 kvfree(flow_group_in);
5742df0f
MHY		 1257}
1258
dfcb1ed3
MHY		 1259static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
1260 struct mlx5_vport *vport)
1261{
1262 if (!IS_ERR_OR_NULL(vport->ingress.drop_rule))
1263 mlx5_del_flow_rule(vport->ingress.drop_rule);
f942380c
MHY		 1264
1265 if (!IS_ERR_OR_NULL(vport->ingress.allow_rule))
1266 mlx5_del_flow_rule(vport->ingress.allow_rule);
1267
dfcb1ed3 1268 vport->ingress.drop_rule = NULL;
f942380c 1269 vport->ingress.allow_rule = NULL;
dfcb1ed3
MHY		 1270}
1271
5742df0f
MHY		 1272static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
1273 struct mlx5_vport *vport)
1274{
1275 if (IS_ERR_OR_NULL(vport->ingress.acl))
1276 return;
1277
1278 esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport);
1279
dfcb1ed3 1280 esw_vport_cleanup_ingress_rules(esw, vport);
5742df0f
MHY		 1281 mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp);
1282 mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp);
1283 mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp);
1284 mlx5_destroy_flow_group(vport->ingress.drop_grp);
1285 mlx5_destroy_flow_table(vport->ingress.acl);
1286 vport->ingress.acl = NULL;
1287 vport->ingress.drop_grp = NULL;
1288 vport->ingress.allow_spoofchk_only_grp = NULL;
1289 vport->ingress.allow_untagged_only_grp = NULL;
1290 vport->ingress.allow_untagged_spoofchk_grp = NULL;
1291}
1292
dfcb1ed3
MHY		 1293static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
1294 struct mlx5_vport *vport)
1295{
f942380c 1296 u8 smac[ETH_ALEN];
dfcb1ed3
MHY		 1297 u32 *match_v;
1298 u32 *match_c;
1299 int err = 0;
f942380c 1300 u8 *smac_v;
dfcb1ed3 1301
f942380c
MHY		 1302 if (vport->spoofchk) {
1303 err = mlx5_query_nic_vport_mac_address(esw->dev, vport->vport, smac);
1304 if (err) {
1305 esw_warn(esw->dev,
1306 "vport[%d] configure ingress rules failed, query smac failed, err(%d)\n",
1307 vport->vport, err);
1308 return err;
1309 }
1310
1311 if (!is_valid_ether_addr(smac)) {
1312 mlx5_core_warn(esw->dev,
1313 "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n",
1314 vport->vport);
1315 return -EPERM;
1316 }
1317 }
1318
dfcb1ed3
MHY		 1319 esw_vport_cleanup_ingress_rules(esw, vport);
1320
01f51f22
MHY		 1321 if (!vport->vlan && !vport->qos && !vport->spoofchk) {
1322 esw_vport_disable_ingress_acl(esw, vport);
dfcb1ed3 1323 return 0;
01f51f22
MHY		 1324 }
1325
1326 esw_vport_enable_ingress_acl(esw, vport);
dfcb1ed3
MHY		 1327
1328 esw_debug(esw->dev,
1329 "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n",
1330 vport->vport, vport->vlan, vport->qos);
1331
1332 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1333 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1334 if (!match_v || !match_c) {
1335 err = -ENOMEM;
1336 esw_warn(esw->dev, "vport[%d] configure ingress rules failed, err(%d)\n",
1337 vport->vport, err);
1338 goto out;
1339 }
dfcb1ed3 1340
f942380c
MHY		 1341 if (vport->vlan || vport->qos)
1342 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.vlan_tag);
1343
1344 if (vport->spoofchk) {
1345 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.smac_47_16);
1346 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.smac_15_0);
1347 smac_v = MLX5_ADDR_OF(fte_match_param,
1348 match_v,
1349 outer_headers.smac_47_16);
1350 ether_addr_copy(smac_v, smac);
1351 }
1352
1353 vport->ingress.allow_rule =
dfcb1ed3
MHY		 1354 mlx5_add_flow_rule(vport->ingress.acl,
1355 MLX5_MATCH_OUTER_HEADERS,
1356 match_c,
1357 match_v,
f942380c
MHY		 1358 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1359 0, NULL);
3f42ac66 1360 if (IS_ERR(vport->ingress.allow_rule)) {
f942380c
MHY		 1361 err = PTR_ERR(vport->ingress.allow_rule);
1362 pr_warn("vport[%d] configure ingress allow rule, err(%d)\n",
1363 vport->vport, err);
1364 vport->ingress.allow_rule = NULL;
1365 goto out;
1366 }
1367
1368 memset(match_c, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1369 memset(match_v, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1370 vport->ingress.drop_rule =
1371 mlx5_add_flow_rule(vport->ingress.acl,
1372 0,
1373 match_c,
1374 match_v,
dfcb1ed3
MHY		 1375 MLX5_FLOW_CONTEXT_ACTION_DROP,
1376 0, NULL);
3f42ac66 1377 if (IS_ERR(vport->ingress.drop_rule)) {
dfcb1ed3 1378 err = PTR_ERR(vport->ingress.drop_rule);
f942380c 1379 pr_warn("vport[%d] configure ingress drop rule, err(%d)\n",
dfcb1ed3
MHY		 1380 vport->vport, err);
1381 vport->ingress.drop_rule = NULL;
f942380c 1382 goto out;
dfcb1ed3 1383 }
f942380c 1384
dfcb1ed3 1385out:
f942380c
MHY		 1386 if (err)
1387 esw_vport_cleanup_ingress_rules(esw, vport);
1388
dfcb1ed3
MHY		 1389 kfree(match_v);
1390 kfree(match_c);
1391 return err;
1392}
1393
1394static int esw_vport_egress_config(struct mlx5_eswitch *esw,
1395 struct mlx5_vport *vport)
1396{
1397 u32 *match_v;
1398 u32 *match_c;
1399 int err = 0;
1400
dfcb1ed3
MHY		 1401 esw_vport_cleanup_egress_rules(esw, vport);
1402
01f51f22
MHY		 1403 if (!vport->vlan && !vport->qos) {
1404 esw_vport_disable_egress_acl(esw, vport);
dfcb1ed3 1405 return 0;
01f51f22
MHY		 1406 }
1407
1408 esw_vport_enable_egress_acl(esw, vport);
dfcb1ed3
MHY		 1409
1410 esw_debug(esw->dev,
1411 "vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
1412 vport->vport, vport->vlan, vport->qos);
1413
1414 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1415 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1416 if (!match_v || !match_c) {
1417 err = -ENOMEM;
1418 esw_warn(esw->dev, "vport[%d] configure egress rules failed, err(%d)\n",
1419 vport->vport, err);
1420 goto out;
1421 }
1422
1423 /* Allowed vlan rule */
1424 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.vlan_tag);
1425 MLX5_SET_TO_ONES(fte_match_param, match_v, outer_headers.vlan_tag);
1426 MLX5_SET_TO_ONES(fte_match_param, match_c, outer_headers.first_vid);
1427 MLX5_SET(fte_match_param, match_v, outer_headers.first_vid, vport->vlan);
1428
1429 vport->egress.allowed_vlan =
1430 mlx5_add_flow_rule(vport->egress.acl,
1431 MLX5_MATCH_OUTER_HEADERS,
1432 match_c,
1433 match_v,
1434 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1435 0, NULL);
3f42ac66 1436 if (IS_ERR(vport->egress.allowed_vlan)) {
dfcb1ed3
MHY		 1437 err = PTR_ERR(vport->egress.allowed_vlan);
1438 pr_warn("vport[%d] configure egress allowed vlan rule failed, err(%d)\n",
1439 vport->vport, err);
1440 vport->egress.allowed_vlan = NULL;
1441 goto out;
1442 }
1443
1444 /* Drop others rule (star rule) */
1445 memset(match_c, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1446 memset(match_v, 0, MLX5_ST_SZ_BYTES(fte_match_param));
1447 vport->egress.drop_rule =
1448 mlx5_add_flow_rule(vport->egress.acl,
1449 0,
1450 match_c,
1451 match_v,
1452 MLX5_FLOW_CONTEXT_ACTION_DROP,
1453 0, NULL);
3f42ac66 1454 if (IS_ERR(vport->egress.drop_rule)) {
dfcb1ed3
MHY		 1455 err = PTR_ERR(vport->egress.drop_rule);
1456 pr_warn("vport[%d] configure egress drop rule failed, err(%d)\n",
1457 vport->vport, err);
1458 vport->egress.drop_rule = NULL;
1459 }
1460out:
1461 kfree(match_v);
1462 kfree(match_c);
1463 return err;
1464}
1465
81848731
SM		 1466static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
1467 int enable_events)
073bb189
SM		 1468{
1469 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189 1470
dfcb1ed3 1471 mutex_lock(&esw->state_lock);
81848731
SM		 1472 WARN_ON(vport->enabled);
1473
1474 esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
5742df0f
MHY		 1475
1476 if (vport_num) { /* Only VFs need ACLs for VST and spoofchk filtering */
dfcb1ed3
MHY		 1477 esw_vport_ingress_config(esw, vport);
1478 esw_vport_egress_config(esw, vport);
5742df0f
MHY		 1479 }
1480
81848731
SM		 1481 mlx5_modify_vport_admin_state(esw->dev,
1482 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1483 vport_num,
1484 MLX5_ESW_VPORT_ADMIN_STATE_AUTO);
1485
1486 /* Sync with current vport context */
1487 vport->enabled_events = enable_events;
073bb189 1488 vport->enabled = true;
073bb189 1489
a35f71f2
MHY		 1490 /* only PF is trusted by default */
1491 vport->trusted = (vport_num) ? false : true;
25fff58c 1492 esw_vport_change_handle_locked(vport);
81848731
SM		 1493
1494 esw->enabled_vports++;
1495 esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
dfcb1ed3 1496 mutex_unlock(&esw->state_lock);
81848731
SM		 1497}
1498
073bb189
SM		 1499static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
1500{
1501 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189
SM		 1502
1503 if (!vport->enabled)
1504 return;
1505
81848731 1506 esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
073bb189 1507 /* Mark this vport as disabled to discard new events */
073bb189 1508 vport->enabled = false;
831cae1d
MHY		 1509
1510 synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
073bb189 1511
81848731
SM		 1512 mlx5_modify_vport_admin_state(esw->dev,
1513 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1514 vport_num,
1515 MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
073bb189
SM		 1516 /* Wait for current already scheduled events to complete */
1517 flush_workqueue(esw->work_queue);
073bb189
SM		 1518 /* Disable events from this vport */
1519 arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
dfcb1ed3 1520 mutex_lock(&esw->state_lock);
586cfa7f
MHY		 1521 /* We don't assume VFs will cleanup after themselves.
1522 * Calling vport change handler while vport is disabled will cleanup
1523 * the vport resources.
1524 */
1edc57e2 1525 esw_vport_change_handle_locked(vport);
586cfa7f 1526 vport->enabled_events = 0;
5742df0f
MHY		 1527 if (vport_num) {
1528 esw_vport_disable_egress_acl(esw, vport);
1529 esw_vport_disable_ingress_acl(esw, vport);
1530 }
81848731 1531 esw->enabled_vports--;
dfcb1ed3 1532 mutex_unlock(&esw->state_lock);
073bb189
SM		 1533}
1534
1535/* Public E-Switch API */
6ab36e35 1536int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode)
81848731
SM		 1537{
1538 int err;
69697b6e 1539 int i, enabled_events;
81848731
SM		 1540
1541 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1542 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1543 return 0;
1544
1545 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
1546 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
1547 esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
1548 return -ENOTSUPP;
1549 }
1550
5742df0f
MHY		 1551 if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support))
1552 esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n");
1553
1554 if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support))
1555 esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n");
1556
6ab36e35 1557 esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d) mode (%d)\n", nvfs, mode);
6ab36e35 1558 esw->mode = mode;
81848731
SM		 1559 esw_disable_vport(esw, 0);
1560
69697b6e
OG		 1561 if (mode == SRIOV_LEGACY)
1562 err = esw_create_legacy_fdb_table(esw, nvfs + 1);
1563 else
1564 err = esw_create_offloads_fdb_table(esw, nvfs + 1);
81848731
SM		 1565 if (err)
1566 goto abort;
1567
69697b6e 1568 enabled_events = (mode == SRIOV_LEGACY) ? SRIOV_VPORT_EVENTS : UC_ADDR_CHANGE;
81848731 1569 for (i = 0; i <= nvfs; i++)
69697b6e 1570 esw_enable_vport(esw, i, enabled_events);
81848731
SM		 1571
1572 esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
1573 esw->enabled_vports);
1574 return 0;
1575
1576abort:
1577 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1578 return err;
1579}
1580
1581void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
1582{
a35f71f2 1583 struct esw_mc_addr *mc_promisc;
81848731
SM		 1584 int i;
1585
1586 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1587 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1588 return;
1589
6ab36e35
OG		 1590 esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n",
1591 esw->enabled_vports, esw->mode);
81848731 1592
a35f71f2
MHY		 1593 mc_promisc = esw->mc_promisc;
1594
81848731
SM		 1595 for (i = 0; i < esw->total_vports; i++)
1596 esw_disable_vport(esw, i);
1597
a35f71f2
MHY		 1598 if (mc_promisc && mc_promisc->uplink_rule)
1599 mlx5_del_flow_rule(mc_promisc->uplink_rule);
1600
69697b6e
OG		 1601 if (esw->mode == SRIOV_LEGACY)
1602 esw_destroy_legacy_fdb_table(esw);
1603 else
1604 esw_destroy_offloads_fdb_table(esw);
81848731 1605
6ab36e35 1606 esw->mode = SRIOV_NONE;
81848731
SM		 1607 /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
1608 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1609}
1610
073bb189
SM		 1611int mlx5_eswitch_init(struct mlx5_core_dev *dev)
1612{
1613 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
efdc810b 1614 int total_vports = MLX5_TOTAL_VPORTS(dev);
a35f71f2 1615 struct esw_mc_addr *mc_promisc;
073bb189
SM		 1616 struct mlx5_eswitch *esw;
1617 int vport_num;
1618 int err;
1619
1620 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
1621 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1622 return 0;
1623
1624 esw_info(dev,
1625 "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
1626 total_vports, l2_table_size,
1627 MLX5_MAX_UC_PER_VPORT(dev),
1628 MLX5_MAX_MC_PER_VPORT(dev));
1629
1630 esw = kzalloc(sizeof(*esw), GFP_KERNEL);
1631 if (!esw)
1632 return -ENOMEM;
1633
1634 esw->dev = dev;
1635
1636 esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
1637 sizeof(uintptr_t), GFP_KERNEL);
1638 if (!esw->l2_table.bitmap) {
1639 err = -ENOMEM;
1640 goto abort;
1641 }
1642 esw->l2_table.size = l2_table_size;
1643
a35f71f2
MHY		 1644 mc_promisc = kzalloc(sizeof(*mc_promisc), GFP_KERNEL);
1645 if (!mc_promisc) {
1646 err = -ENOMEM;
1647 goto abort;
1648 }
1649 esw->mc_promisc = mc_promisc;
1650
073bb189
SM		 1651 esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
1652 if (!esw->work_queue) {
1653 err = -ENOMEM;
1654 goto abort;
1655 }
1656
1657 esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
1658 GFP_KERNEL);
1659 if (!esw->vports) {
1660 err = -ENOMEM;
1661 goto abort;
1662 }
1663
dfcb1ed3
MHY		 1664 mutex_init(&esw->state_lock);
1665
073bb189
SM		 1666 for (vport_num = 0; vport_num < total_vports; vport_num++) {
1667 struct mlx5_vport *vport = &esw->vports[vport_num];
1668
1669 vport->vport = vport_num;
1670 vport->dev = dev;
1671 INIT_WORK(&vport->vport_change_handler,
1672 esw_vport_change_handler);
073bb189
SM		 1673 }
1674
81848731
SM		 1675 esw->total_vports = total_vports;
1676 esw->enabled_vports = 0;
6ab36e35 1677 esw->mode = SRIOV_NONE;
073bb189 1678
81848731
SM		 1679 dev->priv.eswitch = esw;
1680 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
073bb189
SM		 1681 /* VF Vports will be enabled when SRIOV is enabled */
1682 return 0;
1683abort:
1684 if (esw->work_queue)
1685 destroy_workqueue(esw->work_queue);
1686 kfree(esw->l2_table.bitmap);
1687 kfree(esw->vports);
1688 kfree(esw);
1689 return err;
1690}
1691
1692void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
1693{
1694 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1695 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1696 return;
1697
1698 esw_info(esw->dev, "cleanup\n");
1699 esw_disable_vport(esw, 0);
1700
1701 esw->dev->priv.eswitch = NULL;
1702 destroy_workqueue(esw->work_queue);
1703 kfree(esw->l2_table.bitmap);
a35f71f2 1704 kfree(esw->mc_promisc);
073bb189
SM		 1705 kfree(esw->vports);
1706 kfree(esw);
1707}
1708
1709void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
1710{
1711 struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
1712 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
1713 struct mlx5_vport *vport;
1714
1715 if (!esw) {
1716 pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
1717 vport_num);
1718 return;
1719 }
1720
1721 vport = &esw->vports[vport_num];
073bb189
SM		 1722 if (vport->enabled)
1723 queue_work(esw->work_queue, &vport->vport_change_handler);
073bb189 1724}
77256579
SM		 1725
1726/* Vport Administration */
1727#define ESW_ALLOWED(esw) \
1728 (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev))
1729#define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports)
1730
23898c76
NO		 1731static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN])
1732{
1733 ((u8 *)node_guid)[7] = mac[0];
1734 ((u8 *)node_guid)[6] = mac[1];
1735 ((u8 *)node_guid)[5] = mac[2];
1736 ((u8 *)node_guid)[4] = 0xff;
1737 ((u8 *)node_guid)[3] = 0xfe;
1738 ((u8 *)node_guid)[2] = mac[3];
1739 ((u8 *)node_guid)[1] = mac[4];
1740 ((u8 *)node_guid)[0] = mac[5];
1741}
1742
77256579
SM		 1743int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
1744 int vport, u8 mac[ETH_ALEN])
1745{
f942380c 1746 struct mlx5_vport *evport;
23898c76
NO		 1747 u64 node_guid;
1748 int err = 0;
77256579
SM		 1749
1750 if (!ESW_ALLOWED(esw))
1751 return -EPERM;
1752 if (!LEGAL_VPORT(esw, vport))
1753 return -EINVAL;
1754
f942380c
MHY		 1755 evport = &esw->vports[vport];
1756
1757 if (evport->spoofchk && !is_valid_ether_addr(mac)) {
1758 mlx5_core_warn(esw->dev,
1759 "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n",
1760 vport);
1761 return -EPERM;
1762 }
1763
77256579
SM		 1764 err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac);
1765 if (err) {
1766 mlx5_core_warn(esw->dev,
1767 "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n",
1768 vport, err);
1769 return err;
1770 }
1771
23898c76
NO		 1772 node_guid_gen_from_mac(&node_guid, mac);
1773 err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid);
1774 if (err)
1775 mlx5_core_warn(esw->dev,
1776 "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n",
1777 vport, err);
1778
f942380c
MHY		 1779 mutex_lock(&esw->state_lock);
1780 if (evport->enabled)
1781 err = esw_vport_ingress_config(esw, evport);
1782 mutex_unlock(&esw->state_lock);
77256579
SM		 1783 return err;
1784}
1785
1786int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
1787 int vport, int link_state)
1788{
1789 if (!ESW_ALLOWED(esw))
1790 return -EPERM;
1791 if (!LEGAL_VPORT(esw, vport))
1792 return -EINVAL;
1793
1794 return mlx5_modify_vport_admin_state(esw->dev,
1795 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1796 vport, link_state);
1797}
1798
1799int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
1800 int vport, struct ifla_vf_info *ivi)
1801{
f942380c 1802 struct mlx5_vport *evport;
9e7ea352
SM		 1803 u16 vlan;
1804 u8 qos;
1805
77256579
SM		 1806 if (!ESW_ALLOWED(esw))
1807 return -EPERM;
1808 if (!LEGAL_VPORT(esw, vport))
1809 return -EINVAL;
1810
f942380c
MHY		 1811 evport = &esw->vports[vport];
1812
77256579
SM		 1813 memset(ivi, 0, sizeof(*ivi));
1814 ivi->vf = vport - 1;
1815
1816 mlx5_query_nic_vport_mac_address(esw->dev, vport, ivi->mac);
1817 ivi->linkstate = mlx5_query_vport_admin_state(esw->dev,
1818 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1819 vport);
9e7ea352
SM		 1820 query_esw_vport_cvlan(esw->dev, vport, &vlan, &qos);
1821 ivi->vlan = vlan;
1822 ivi->qos = qos;
f942380c 1823 ivi->spoofchk = evport->spoofchk;
77256579
SM		 1824
1825 return 0;
1826}
9e7ea352
SM		 1827
1828int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1829 int vport, u16 vlan, u8 qos)
1830{
dfcb1ed3
MHY		 1831 struct mlx5_vport *evport;
1832 int err = 0;
9e7ea352
SM		 1833 int set = 0;
1834
1835 if (!ESW_ALLOWED(esw))
1836 return -EPERM;
1837 if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7))
1838 return -EINVAL;
1839
1840 if (vlan || qos)
1841 set = 1;
1842
dfcb1ed3
MHY		 1843 evport = &esw->vports[vport];
1844
1845 err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set);
1846 if (err)
1847 return err;
1848
1849 mutex_lock(&esw->state_lock);
1850 evport->vlan = vlan;
1851 evport->qos = qos;
1852 if (evport->enabled) {
1853 err = esw_vport_ingress_config(esw, evport);
1854 if (err)
1855 goto out;
1856 err = esw_vport_egress_config(esw, evport);
1857 }
1858
1859out:
1860 mutex_unlock(&esw->state_lock);
1861 return err;
9e7ea352 1862}
3b751a2a 1863
f942380c
MHY		 1864int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
1865 int vport, bool spoofchk)
1866{
1867 struct mlx5_vport *evport;
1868 bool pschk;
1869 int err = 0;
1870
1871 if (!ESW_ALLOWED(esw))
1872 return -EPERM;
1873 if (!LEGAL_VPORT(esw, vport))
1874 return -EINVAL;
1875
1876 evport = &esw->vports[vport];
1877
1878 mutex_lock(&esw->state_lock);
1879 pschk = evport->spoofchk;
1880 evport->spoofchk = spoofchk;
1881 if (evport->enabled)
1882 err = esw_vport_ingress_config(esw, evport);
1883 if (err)
1884 evport->spoofchk = pschk;
1885 mutex_unlock(&esw->state_lock);
1886
1887 return err;
1888}
1889
1edc57e2
MHY		 1890int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1891 int vport, bool setting)
1892{
1893 struct mlx5_vport *evport;
1894
1895 if (!ESW_ALLOWED(esw))
1896 return -EPERM;
1897 if (!LEGAL_VPORT(esw, vport))
1898 return -EINVAL;
1899
1900 evport = &esw->vports[vport];
1901
1902 mutex_lock(&esw->state_lock);
1903 evport->trusted = setting;
1904 if (evport->enabled)
1905 esw_vport_change_handle_locked(evport);
1906 mutex_unlock(&esw->state_lock);
1907
1908 return 0;
1909}
1910
3b751a2a
SM		 1911int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
1912 int vport,
1913 struct ifla_vf_stats *vf_stats)
1914{
1915 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
1916 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
1917 int err = 0;
1918 u32 *out;
1919
1920 if (!ESW_ALLOWED(esw))
1921 return -EPERM;
1922 if (!LEGAL_VPORT(esw, vport))
1923 return -EINVAL;
1924
1925 out = mlx5_vzalloc(outlen);
1926 if (!out)
1927 return -ENOMEM;
1928
1929 memset(in, 0, sizeof(in));
1930
1931 MLX5_SET(query_vport_counter_in, in, opcode,
1932 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
1933 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
1934 MLX5_SET(query_vport_counter_in, in, vport_number, vport);
1935 if (vport)
1936 MLX5_SET(query_vport_counter_in, in, other_vport, 1);
1937
1938 memset(out, 0, outlen);
1939 err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen);
1940 if (err)
1941 goto free_out;
1942
1943 #define MLX5_GET_CTR(p, x) \
1944 MLX5_GET64(query_vport_counter_out, p, x)
1945
1946 memset(vf_stats, 0, sizeof(*vf_stats));
1947 vf_stats->rx_packets =
1948 MLX5_GET_CTR(out, received_eth_unicast.packets) +
1949 MLX5_GET_CTR(out, received_eth_multicast.packets) +
1950 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1951
1952 vf_stats->rx_bytes =
1953 MLX5_GET_CTR(out, received_eth_unicast.octets) +
1954 MLX5_GET_CTR(out, received_eth_multicast.octets) +
1955 MLX5_GET_CTR(out, received_eth_broadcast.octets);
1956
1957 vf_stats->tx_packets =
1958 MLX5_GET_CTR(out, transmitted_eth_unicast.packets) +
1959 MLX5_GET_CTR(out, transmitted_eth_multicast.packets) +
1960 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
1961
1962 vf_stats->tx_bytes =
1963 MLX5_GET_CTR(out, transmitted_eth_unicast.octets) +
1964 MLX5_GET_CTR(out, transmitted_eth_multicast.octets) +
1965 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
1966
1967 vf_stats->multicast =
1968 MLX5_GET_CTR(out, received_eth_multicast.packets);
1969
1970 vf_stats->broadcast =
1971 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1972
1973free_out:
1974 kvfree(out);
1975 return err;
1976}
Linux kernel - Deliverables
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