net/mlx5e: Support DCBNL IEEE ETS
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / fw.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/mlx5/driver.h>
34#include <linux/mlx5/cmd.h>
35#include <linux/module.h>
36#include "mlx5_core.h"
37
7cf7fa52
MD
38static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
39 int outlen)
e126ba97 40{
211e6c80
MD
41 u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
42
43 memset(in, 0, sizeof(in));
44
45 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
46
47 return mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, outlen);
48}
49
50int mlx5_query_board_id(struct mlx5_core_dev *dev)
51{
52 u32 *out;
53 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
e126ba97
EC
54 int err;
55
211e6c80 56 out = kzalloc(outlen, GFP_KERNEL);
e126ba97
EC
57 if (!out)
58 return -ENOMEM;
59
211e6c80 60 err = mlx5_cmd_query_adapter(dev, out, outlen);
e126ba97 61 if (err)
211e6c80 62 goto out;
e126ba97 63
211e6c80
MD
64 memcpy(dev->board_id,
65 MLX5_ADDR_OF(query_adapter_out, out,
66 query_adapter_struct.vsd_contd_psid),
67 MLX5_FLD_SZ_BYTES(query_adapter_out,
68 query_adapter_struct.vsd_contd_psid));
e126ba97 69
211e6c80 70out:
e126ba97 71 kfree(out);
211e6c80
MD
72 return err;
73}
e126ba97 74
211e6c80
MD
75int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
76{
77 u32 *out;
78 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
79 int err;
80
81 out = kzalloc(outlen, GFP_KERNEL);
82 if (!out)
83 return -ENOMEM;
84
85 err = mlx5_cmd_query_adapter(mdev, out, outlen);
86 if (err)
87 goto out;
88
89 *vendor_id = MLX5_GET(query_adapter_out, out,
90 query_adapter_struct.ieee_vendor_id);
91out:
92 kfree(out);
e126ba97
EC
93 return err;
94}
211e6c80 95EXPORT_SYMBOL(mlx5_core_query_vendor_id);
e126ba97 96
938fe83c 97int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
e126ba97 98{
e420f0c0
HE
99 int err;
100
938fe83c
SM
101 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
102 if (err)
103 return err;
e420f0c0 104
938fe83c 105 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
e420f0c0 106 if (err)
938fe83c 107 return err;
e420f0c0 108
938fe83c
SM
109 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
110 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS,
111 HCA_CAP_OPMOD_GET_CUR);
112 if (err)
113 return err;
114 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS,
115 HCA_CAP_OPMOD_GET_MAX);
116 if (err)
117 return err;
e420f0c0
HE
118 }
119
938fe83c
SM
120 if (MLX5_CAP_GEN(dev, pg)) {
121 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP,
122 HCA_CAP_OPMOD_GET_CUR);
123 if (err)
124 return err;
125 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP,
126 HCA_CAP_OPMOD_GET_MAX);
127 if (err)
128 return err;
129 }
e420f0c0 130
938fe83c
SM
131 if (MLX5_CAP_GEN(dev, atomic)) {
132 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
133 HCA_CAP_OPMOD_GET_CUR);
134 if (err)
135 return err;
136 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
137 HCA_CAP_OPMOD_GET_MAX);
138 if (err)
139 return err;
140 }
e420f0c0 141
938fe83c
SM
142 if (MLX5_CAP_GEN(dev, roce)) {
143 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE,
144 HCA_CAP_OPMOD_GET_CUR);
145 if (err)
146 return err;
147 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE,
148 HCA_CAP_OPMOD_GET_MAX);
149 if (err)
150 return err;
151 }
152
153 if (MLX5_CAP_GEN(dev, nic_flow_table)) {
154 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE,
155 HCA_CAP_OPMOD_GET_CUR);
156 if (err)
157 return err;
158 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE,
159 HCA_CAP_OPMOD_GET_MAX);
160 if (err)
161 return err;
162 }
495716b1
SM
163
164 if (MLX5_CAP_GEN(dev, vport_group_manager) &&
165 MLX5_CAP_GEN(dev, eswitch_flow_table)) {
166 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE,
167 HCA_CAP_OPMOD_GET_CUR);
168 if (err)
169 return err;
170 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE,
171 HCA_CAP_OPMOD_GET_MAX);
172 if (err)
173 return err;
174 }
175
9bd0a185 176 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) {
d6666753
SM
177 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH,
178 HCA_CAP_OPMOD_GET_CUR);
179 if (err)
180 return err;
181 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH,
182 HCA_CAP_OPMOD_GET_MAX);
183 if (err)
184 return err;
185 }
186
938fe83c 187 return 0;
e420f0c0 188}
e420f0c0 189
e126ba97
EC
190int mlx5_cmd_init_hca(struct mlx5_core_dev *dev)
191{
192 struct mlx5_cmd_init_hca_mbox_in in;
193 struct mlx5_cmd_init_hca_mbox_out out;
194 int err;
195
196 memset(&in, 0, sizeof(in));
197 memset(&out, 0, sizeof(out));
198 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_INIT_HCA);
199 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
200 if (err)
201 return err;
202
203 if (out.hdr.status)
204 err = mlx5_cmd_status_to_err(&out.hdr);
205
206 return err;
207}
208
209int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
210{
211 struct mlx5_cmd_teardown_hca_mbox_in in;
212 struct mlx5_cmd_teardown_hca_mbox_out out;
213 int err;
214
215 memset(&in, 0, sizeof(in));
216 memset(&out, 0, sizeof(out));
217 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_TEARDOWN_HCA);
218 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
219 if (err)
220 return err;
221
222 if (out.hdr.status)
223 err = mlx5_cmd_status_to_err(&out.hdr);
224
225 return err;
226}
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