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net/mlx4_core: Fix misleading debug print on CQE stride support
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/mlx5/driver.h>
42#include <linux/mlx5/cq.h>
43#include <linux/mlx5/qp.h>
44#include <linux/mlx5/srq.h>
45#include <linux/debugfs.h>
f66f049f 46#include <linux/kmod.h>
b775516b 47#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 48#include "mlx5_core.h"
49
50#define DRIVER_NAME "mlx5_core"
169a1d85
AV		 51#define DRIVER_VERSION "2.2-1"
52#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 53
54MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
56MODULE_LICENSE("Dual BSD/GPL");
57MODULE_VERSION(DRIVER_VERSION);
58
59int mlx5_core_debug_mask;
60module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
61MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
62
9603b61d
JM		 63#define MLX5_DEFAULT_PROF 2
64static int prof_sel = MLX5_DEFAULT_PROF;
65module_param_named(prof_sel, prof_sel, int, 0444);
66MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
67
e126ba97 68struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 69static LIST_HEAD(intf_list);
70static LIST_HEAD(dev_list);
71static DEFINE_MUTEX(intf_mutex);
72
73struct mlx5_device_context {
74 struct list_head list;
75 struct mlx5_interface *intf;
76 void *context;
77};
78
79static struct mlx5_profile profile[] = {
80 [0] = {
81 .mask = 0,
82 },
83 [1] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .log_max_qp = 12,
86 },
87 [2] = {
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
90 .log_max_qp = 17,
91 .mr_cache[0] = {
92 .size = 500,
93 .limit = 250
94 },
95 .mr_cache[1] = {
96 .size = 500,
97 .limit = 250
98 },
99 .mr_cache[2] = {
100 .size = 500,
101 .limit = 250
102 },
103 .mr_cache[3] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[4] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[5] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[6] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[7] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[8] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[9] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[10] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[11] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[12] = {
140 .size = 64,
141 .limit = 32
142 },
143 .mr_cache[13] = {
144 .size = 32,
145 .limit = 16
146 },
147 .mr_cache[14] = {
148 .size = 16,
149 .limit = 8
150 },
151 .mr_cache[15] = {
152 .size = 8,
153 .limit = 4
154 },
155 },
156};
e126ba97
EC		 157
158static int set_dma_caps(struct pci_dev *pdev)
159{
160 int err;
161
162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
163 if (err) {
1a91de28 164 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 165 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
166 if (err) {
1a91de28 167 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 168 return err;
169 }
170 }
171
172 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
173 if (err) {
174 dev_warn(&pdev->dev,
1a91de28 175 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 176 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
177 if (err) {
178 dev_err(&pdev->dev,
1a91de28 179 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 180 return err;
181 }
182 }
183
184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
185 return err;
186}
187
188static int request_bar(struct pci_dev *pdev)
189{
190 int err = 0;
191
192 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 193 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 194 return -ENODEV;
195 }
196
197 err = pci_request_regions(pdev, DRIVER_NAME);
198 if (err)
199 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
200
201 return err;
202}
203
204static void release_bar(struct pci_dev *pdev)
205{
206 pci_release_regions(pdev);
207}
208
209static int mlx5_enable_msix(struct mlx5_core_dev *dev)
210{
211 struct mlx5_eq_table *table = &dev->priv.eq_table;
c7a08ac7 212 int num_eqs = 1 << dev->caps.gen.log_max_eq;
e126ba97 213 int nvec;
e126ba97
EC		 214 int i;
215
c7a08ac7 216 nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 217 nvec = min_t(int, nvec, num_eqs);
218 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
219 return -ENOMEM;
220
221 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
222 if (!table->msix_arr)
223 return -ENOMEM;
224
225 for (i = 0; i < nvec; i++)
226 table->msix_arr[i].entry = i;
227
f3c9407b 228 nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
3a9e161a 229 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 230 if (nvec < 0)
231 return nvec;
e126ba97 232
f3c9407b 233 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 234
235 return 0;
236}
237
238static void mlx5_disable_msix(struct mlx5_core_dev *dev)
239{
240 struct mlx5_eq_table *table = &dev->priv.eq_table;
241
242 pci_disable_msix(dev->pdev);
243 kfree(table->msix_arr);
244}
245
246struct mlx5_reg_host_endianess {
247 u8 he;
248 u8 rsvd[15];
249};
250
87b8de49
EC		 251
252#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
253
254enum {
c7a08ac7
EC		 255 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
256 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 257};
258
c7a08ac7
EC		 259static u16 to_fw_pkey_sz(u32 size)
260{
261 switch (size) {
262 case 128:
263 return 0;
264 case 256:
265 return 1;
266 case 512:
267 return 2;
268 case 1024:
269 return 3;
270 case 2048:
271 return 4;
272 case 4096:
273 return 5;
274 default:
275 pr_warn("invalid pkey table size %d\n", size);
276 return 0;
277 }
278}
279
87b8de49
EC		 280/* selectively copy writable fields clearing any reserved area
281 */
b775516b 282static void copy_rw_fields(void *to, struct mlx5_caps *from)
87b8de49 283{
b775516b 284 __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
87b8de49
EC		 285 u64 v64;
286
b775516b
EC		 287 MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
288 MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
289 MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
290 MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
291 MLX5_SET(cmd_hca_cap, to, log_max_ra_req_dc, from->gen.log_max_ra_req_dc);
292 MLX5_SET(cmd_hca_cap, to, log_max_ra_res_dc, from->gen.log_max_ra_res_dc);
293 MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
294 v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
295 *flags_off = cpu_to_be64(v64);
87b8de49
EC		 296}
297
c7a08ac7
EC		 298static u16 get_pkey_table_size(int pkey)
299{
300 if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
301 return 0;
87b8de49 302
c7a08ac7
EC		 303 return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
304}
305
b775516b 306static void fw2drv_caps(struct mlx5_caps *caps, void *out)
e126ba97 307{
c7a08ac7 308 struct mlx5_general_caps *gen = &caps->gen;
b775516b
EC		 309
310 gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
311 gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
312 gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
313 gen->log_max_strq = MLX5_GET_PR(cmd_hca_cap, out, log_max_strq_sz);
314 gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srqs);
315 gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
316 gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
317 gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
318 gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
319 gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
320 gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
321 gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
322 gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
323 gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
324 gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
325 gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
326 gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
327 gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
328 gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
329 gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
330 gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
331 gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
332 gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
333 gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
334 gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
c7a08ac7 335 pr_debug("flags = 0x%llx\n", gen->flags);
b775516b
EC		 336 gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
337 gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
338 gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
339 gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
340 gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
341 gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
342 gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
343 gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
344 gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
345 gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
346 gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
c7a08ac7
EC		 347}
348
349static const char *caps_opmod_str(u16 opmod)
350{
351 switch (opmod) {
352 case HCA_CAP_OPMOD_GET_MAX:
353 return "GET_MAX";
354 case HCA_CAP_OPMOD_GET_CUR:
355 return "GET_CUR";
356 default:
357 return "Invalid";
358 }
359}
360
361int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
362 u16 opmod)
363{
b775516b
EC		 364 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
365 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
366 void *out;
e126ba97
EC		 367 int err;
368
b775516b
EC		 369 memset(in, 0, sizeof(in));
370 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 371 if (!out)
e126ba97 372 return -ENOMEM;
b775516b
EC		 373 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
374 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
375 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
376 if (err)
377 goto query_ex;
e126ba97 378
b775516b 379 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 380 if (err) {
381 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
e126ba97
EC		 382 goto query_ex;
383 }
c7a08ac7 384 mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
b775516b 385 fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct));
c7a08ac7
EC		 386
387query_ex:
388 kfree(out);
389 return err;
390}
391
b775516b 392static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 393{
b775516b 394 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 395 int err;
396
b775516b 397 memset(out, 0, sizeof(out));
e126ba97 398
b775516b
EC		 399 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
400 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 401 if (err)
c7a08ac7 402 return err;
e126ba97 403
b775516b 404 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 405
406 return err;
407}
408
409static int handle_hca_cap(struct mlx5_core_dev *dev)
410{
b775516b 411 void *set_ctx = NULL;
c7a08ac7
EC		 412 struct mlx5_profile *prof = dev->profile;
413 struct mlx5_caps *cur_caps = NULL;
414 struct mlx5_caps *max_caps = NULL;
415 int err = -ENOMEM;
b775516b 416 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
c7a08ac7 417
b775516b 418 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 419 if (!set_ctx)
e126ba97 420 goto query_ex;
e126ba97 421
c7a08ac7
EC		 422 max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
423 if (!max_caps)
424 goto query_ex;
e126ba97 425
c7a08ac7
EC		 426 cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
427 if (!cur_caps)
428 goto query_ex;
e126ba97 429
c7a08ac7
EC		 430 err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
431 if (err)
e126ba97 432 goto query_ex;
e126ba97 433
c7a08ac7 434 err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 435 if (err)
436 goto query_ex;
437
c7a08ac7
EC		 438 /* we limit the size of the pkey table to 128 entries for now */
439 cur_caps->gen.pkey_table_size = 128;
440
441 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
442 cur_caps->gen.log_max_qp = prof->log_max_qp;
443
444 /* disable checksum */
445 cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
446
b775516b
EC		 447 copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, hca_capability_struct),
448 cur_caps);
449 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 450
e126ba97 451query_ex:
c7a08ac7
EC		 452 kfree(cur_caps);
453 kfree(max_caps);
e126ba97
EC		 454 kfree(set_ctx);
455
456 return err;
457}
458
459static int set_hca_ctrl(struct mlx5_core_dev *dev)
460{
461 struct mlx5_reg_host_endianess he_in;
462 struct mlx5_reg_host_endianess he_out;
463 int err;
464
465 memset(&he_in, 0, sizeof(he_in));
466 he_in.he = MLX5_SET_HOST_ENDIANNESS;
467 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
468 &he_out, sizeof(he_out),
469 MLX5_REG_HOST_ENDIANNESS, 0, 1);
470 return err;
471}
472
cd23b14b
EC		 473static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
474{
475 int err;
476 struct mlx5_enable_hca_mbox_in in;
477 struct mlx5_enable_hca_mbox_out out;
478
479 memset(&in, 0, sizeof(in));
480 memset(&out, 0, sizeof(out));
481 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
482 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
483 if (err)
484 return err;
485
486 if (out.hdr.status)
487 return mlx5_cmd_status_to_err(&out.hdr);
488
489 return 0;
490}
491
492static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
493{
494 int err;
495 struct mlx5_disable_hca_mbox_in in;
496 struct mlx5_disable_hca_mbox_out out;
497
498 memset(&in, 0, sizeof(in));
499 memset(&out, 0, sizeof(out));
500 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
501 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
502 if (err)
503 return err;
504
505 if (out.hdr.status)
506 return mlx5_cmd_status_to_err(&out.hdr);
507
508 return 0;
509}
510
9603b61d 511static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 512{
513 struct mlx5_priv *priv = &dev->priv;
514 int err;
515
516 dev->pdev = pdev;
517 pci_set_drvdata(dev->pdev, dev);
518 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
519 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
520
521 mutex_init(&priv->pgdir_mutex);
522 INIT_LIST_HEAD(&priv->pgdir_list);
523 spin_lock_init(&priv->mkey_lock);
524
525 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
526 if (!priv->dbg_root)
527 return -ENOMEM;
528
529 err = pci_enable_device(pdev);
530 if (err) {
1a91de28 531 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 532 goto err_dbg;
533 }
534
535 err = request_bar(pdev);
536 if (err) {
1a91de28 537 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 538 goto err_disable;
539 }
540
541 pci_set_master(pdev);
542
543 err = set_dma_caps(pdev);
544 if (err) {
545 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
546 goto err_clr_master;
547 }
548
549 dev->iseg_base = pci_resource_start(dev->pdev, 0);
550 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
551 if (!dev->iseg) {
552 err = -ENOMEM;
553 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
554 goto err_clr_master;
555 }
556 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
557 fw_rev_min(dev), fw_rev_sub(dev));
558
559 err = mlx5_cmd_init(dev);
560 if (err) {
561 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
562 goto err_unmap;
563 }
564
565 mlx5_pagealloc_init(dev);
cd23b14b
EC		 566
567 err = mlx5_core_enable_hca(dev);
568 if (err) {
569 dev_err(&pdev->dev, "enable hca failed\n");
570 goto err_pagealloc_cleanup;
571 }
572
573 err = mlx5_satisfy_startup_pages(dev, 1);
574 if (err) {
575 dev_err(&pdev->dev, "failed to allocate boot pages\n");
576 goto err_disable_hca;
577 }
578
e126ba97
EC		 579 err = set_hca_ctrl(dev);
580 if (err) {
581 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 582 goto reclaim_boot_pages;
e126ba97
EC		 583 }
584
585 err = handle_hca_cap(dev);
586 if (err) {
587 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 588 goto reclaim_boot_pages;
e126ba97
EC		 589 }
590
cd23b14b 591 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 592 if (err) {
cd23b14b
EC		 593 dev_err(&pdev->dev, "failed to allocate init pages\n");
594 goto reclaim_boot_pages;
e126ba97
EC		 595 }
596
597 err = mlx5_pagealloc_start(dev);
598 if (err) {
599 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 600 goto reclaim_boot_pages;
e126ba97
EC		 601 }
602
603 err = mlx5_cmd_init_hca(dev);
604 if (err) {
605 dev_err(&pdev->dev, "init hca failed\n");
606 goto err_pagealloc_stop;
607 }
608
609 mlx5_start_health_poll(dev);
610
611 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
612 if (err) {
613 dev_err(&pdev->dev, "query hca failed\n");
614 goto err_stop_poll;
615 }
616
617 err = mlx5_cmd_query_adapter(dev);
618 if (err) {
619 dev_err(&pdev->dev, "query adapter failed\n");
620 goto err_stop_poll;
621 }
622
623 err = mlx5_enable_msix(dev);
624 if (err) {
625 dev_err(&pdev->dev, "enable msix failed\n");
626 goto err_stop_poll;
627 }
628
629 err = mlx5_eq_init(dev);
630 if (err) {
631 dev_err(&pdev->dev, "failed to initialize eq\n");
632 goto disable_msix;
633 }
634
635 err = mlx5_alloc_uuars(dev, &priv->uuari);
636 if (err) {
637 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
638 goto err_eq_cleanup;
639 }
640
641 err = mlx5_start_eqs(dev);
642 if (err) {
643 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
644 goto err_free_uar;
645 }
646
647 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
648
649 mlx5_init_cq_table(dev);
650 mlx5_init_qp_table(dev);
651 mlx5_init_srq_table(dev);
3bcdb17a 652 mlx5_init_mr_table(dev);
e126ba97
EC		 653
654 return 0;
655
656err_free_uar:
657 mlx5_free_uuars(dev, &priv->uuari);
658
659err_eq_cleanup:
660 mlx5_eq_cleanup(dev);
661
662disable_msix:
663 mlx5_disable_msix(dev);
664
665err_stop_poll:
666 mlx5_stop_health_poll(dev);
1bde6e30
EC		 667 if (mlx5_cmd_teardown_hca(dev)) {
668 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
669 return err;
670 }
e126ba97
EC		 671
672err_pagealloc_stop:
673 mlx5_pagealloc_stop(dev);
674
cd23b14b 675reclaim_boot_pages:
e126ba97
EC		 676 mlx5_reclaim_startup_pages(dev);
677
cd23b14b
EC		 678err_disable_hca:
679 mlx5_core_disable_hca(dev);
680
e126ba97
EC		 681err_pagealloc_cleanup:
682 mlx5_pagealloc_cleanup(dev);
683 mlx5_cmd_cleanup(dev);
684
685err_unmap:
686 iounmap(dev->iseg);
687
688err_clr_master:
689 pci_clear_master(dev->pdev);
690 release_bar(dev->pdev);
691
692err_disable:
693 pci_disable_device(dev->pdev);
694
695err_dbg:
696 debugfs_remove(priv->dbg_root);
697 return err;
698}
699EXPORT_SYMBOL(mlx5_dev_init);
700
9603b61d 701static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 702{
703 struct mlx5_priv *priv = &dev->priv;
704
705 mlx5_cleanup_srq_table(dev);
706 mlx5_cleanup_qp_table(dev);
707 mlx5_cleanup_cq_table(dev);
708 mlx5_stop_eqs(dev);
709 mlx5_free_uuars(dev, &priv->uuari);
710 mlx5_eq_cleanup(dev);
711 mlx5_disable_msix(dev);
712 mlx5_stop_health_poll(dev);
1bde6e30
EC		 713 if (mlx5_cmd_teardown_hca(dev)) {
714 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
715 return;
716 }
e126ba97
EC		 717 mlx5_pagealloc_stop(dev);
718 mlx5_reclaim_startup_pages(dev);
cd23b14b 719 mlx5_core_disable_hca(dev);
e126ba97
EC		 720 mlx5_pagealloc_cleanup(dev);
721 mlx5_cmd_cleanup(dev);
722 iounmap(dev->iseg);
723 pci_clear_master(dev->pdev);
724 release_bar(dev->pdev);
725 pci_disable_device(dev->pdev);
726 debugfs_remove(priv->dbg_root);
727}
9603b61d
JM		 728
729static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
730{
731 struct mlx5_device_context *dev_ctx;
732 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
733
734 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
735 if (!dev_ctx) {
736 pr_warn("mlx5_add_device: alloc context failed\n");
737 return;
738 }
739
740 dev_ctx->intf = intf;
741 dev_ctx->context = intf->add(dev);
742
743 if (dev_ctx->context) {
744 spin_lock_irq(&priv->ctx_lock);
745 list_add_tail(&dev_ctx->list, &priv->ctx_list);
746 spin_unlock_irq(&priv->ctx_lock);
747 } else {
748 kfree(dev_ctx);
749 }
750}
751
752static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
753{
754 struct mlx5_device_context *dev_ctx;
755 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
756
757 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
758 if (dev_ctx->intf == intf) {
759 spin_lock_irq(&priv->ctx_lock);
760 list_del(&dev_ctx->list);
761 spin_unlock_irq(&priv->ctx_lock);
762
763 intf->remove(dev, dev_ctx->context);
764 kfree(dev_ctx);
765 return;
766 }
767}
768static int mlx5_register_device(struct mlx5_core_dev *dev)
769{
770 struct mlx5_priv *priv = &dev->priv;
771 struct mlx5_interface *intf;
772
773 mutex_lock(&intf_mutex);
774 list_add_tail(&priv->dev_list, &dev_list);
775 list_for_each_entry(intf, &intf_list, list)
776 mlx5_add_device(intf, priv);
777 mutex_unlock(&intf_mutex);
778
779 return 0;
780}
781static void mlx5_unregister_device(struct mlx5_core_dev *dev)
782{
783 struct mlx5_priv *priv = &dev->priv;
784 struct mlx5_interface *intf;
785
786 mutex_lock(&intf_mutex);
787 list_for_each_entry(intf, &intf_list, list)
788 mlx5_remove_device(intf, priv);
789 list_del(&priv->dev_list);
790 mutex_unlock(&intf_mutex);
791}
792
793int mlx5_register_interface(struct mlx5_interface *intf)
794{
795 struct mlx5_priv *priv;
796
797 if (!intf->add || !intf->remove)
798 return -EINVAL;
799
800 mutex_lock(&intf_mutex);
801 list_add_tail(&intf->list, &intf_list);
802 list_for_each_entry(priv, &dev_list, dev_list)
803 mlx5_add_device(intf, priv);
804 mutex_unlock(&intf_mutex);
805
806 return 0;
807}
808EXPORT_SYMBOL(mlx5_register_interface);
809
810void mlx5_unregister_interface(struct mlx5_interface *intf)
811{
812 struct mlx5_priv *priv;
813
814 mutex_lock(&intf_mutex);
815 list_for_each_entry(priv, &dev_list, dev_list)
816 mlx5_remove_device(intf, priv);
817 list_del(&intf->list);
818 mutex_unlock(&intf_mutex);
819}
820EXPORT_SYMBOL(mlx5_unregister_interface);
821
822static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 823 unsigned long param)
9603b61d
JM		 824{
825 struct mlx5_priv *priv = &dev->priv;
826 struct mlx5_device_context *dev_ctx;
827 unsigned long flags;
828
829 spin_lock_irqsave(&priv->ctx_lock, flags);
830
831 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
832 if (dev_ctx->intf->event)
4d2f9bbb 833 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 834
835 spin_unlock_irqrestore(&priv->ctx_lock, flags);
836}
837
838struct mlx5_core_event_handler {
839 void (*event)(struct mlx5_core_dev *dev,
840 enum mlx5_dev_event event,
841 void *data);
842};
843
f66f049f
EC		 844#define MLX5_IB_MOD "mlx5_ib"
845
9603b61d
JM		 846static int init_one(struct pci_dev *pdev,
847 const struct pci_device_id *id)
848{
849 struct mlx5_core_dev *dev;
850 struct mlx5_priv *priv;
851 int err;
852
853 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
854 if (!dev) {
855 dev_err(&pdev->dev, "kzalloc failed\n");
856 return -ENOMEM;
857 }
858 priv = &dev->priv;
859
860 pci_set_drvdata(pdev, dev);
861
862 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
863 pr_warn("selected profile out of range, selecting default (%d)\n",
864 MLX5_DEFAULT_PROF);
865 prof_sel = MLX5_DEFAULT_PROF;
866 }
867 dev->profile = &profile[prof_sel];
868 dev->event = mlx5_core_event;
869
364d1798
EC		 870 INIT_LIST_HEAD(&priv->ctx_list);
871 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 872 err = mlx5_dev_init(dev, pdev);
873 if (err) {
874 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
875 goto out;
876 }
877
9603b61d
JM		 878 err = mlx5_register_device(dev);
879 if (err) {
880 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
881 goto out_init;
882 }
883
f66f049f
EC		 884 err = request_module_nowait(MLX5_IB_MOD);
885 if (err)
886 pr_info("failed request module on %s\n", MLX5_IB_MOD);
887
9603b61d
JM		 888 return 0;
889
890out_init:
891 mlx5_dev_cleanup(dev);
892out:
893 kfree(dev);
894 return err;
895}
896static void remove_one(struct pci_dev *pdev)
897{
898 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
899
900 mlx5_unregister_device(dev);
901 mlx5_dev_cleanup(dev);
902 kfree(dev);
903}
904
905static const struct pci_device_id mlx5_core_pci_table[] = {
28c167fa
EC		 906 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
907 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
f832dc82 908 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
28c167fa
EC		 909 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
910 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
911 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
9603b61d
JM		 912 { 0, }
913};
914
915MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
916
917static struct pci_driver mlx5_core_driver = {
918 .name = DRIVER_NAME,
919 .id_table = mlx5_core_pci_table,
920 .probe = init_one,
921 .remove = remove_one
922};
e126ba97
EC		 923
924static int __init init(void)
925{
926 int err;
927
928 mlx5_register_debugfs();
929 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
930 if (!mlx5_core_wq) {
931 err = -ENOMEM;
932 goto err_debug;
933 }
934 mlx5_health_init();
935
9603b61d
JM		 936 err = pci_register_driver(&mlx5_core_driver);
937 if (err)
938 goto err_health;
939
e126ba97
EC		 940 return 0;
941
9603b61d
JM		 942err_health:
943 mlx5_health_cleanup();
944 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 945err_debug:
946 mlx5_unregister_debugfs();
947 return err;
948}
949
950static void __exit cleanup(void)
951{
9603b61d 952 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 953 mlx5_health_cleanup();
954 destroy_workqueue(mlx5_core_wq);
955 mlx5_unregister_debugfs();
956}
957
958module_init(init);
959module_exit(cleanup);
Linux kernel - Deliverables
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