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net/mlx5_core: Move completion eqs from mlx5_ib to mlx5_core
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/mlx5/driver.h>
42#include <linux/mlx5/cq.h>
43#include <linux/mlx5/qp.h>
44#include <linux/mlx5/srq.h>
45#include <linux/debugfs.h>
f66f049f 46#include <linux/kmod.h>
b775516b 47#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 48#include "mlx5_core.h"
49
50#define DRIVER_NAME "mlx5_core"
4ae6c18c
AS		 51#define DRIVER_VERSION "3.0"
52#define DRIVER_RELDATE "January 2015"
e126ba97
EC		 53
54MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 55MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 56MODULE_LICENSE("Dual BSD/GPL");
57MODULE_VERSION(DRIVER_VERSION);
58
59int mlx5_core_debug_mask;
60module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
61MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
62
9603b61d
JM		 63#define MLX5_DEFAULT_PROF 2
64static int prof_sel = MLX5_DEFAULT_PROF;
65module_param_named(prof_sel, prof_sel, int, 0444);
66MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
67
e126ba97 68struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 69static LIST_HEAD(intf_list);
70static LIST_HEAD(dev_list);
71static DEFINE_MUTEX(intf_mutex);
72
73struct mlx5_device_context {
74 struct list_head list;
75 struct mlx5_interface *intf;
76 void *context;
77};
78
79static struct mlx5_profile profile[] = {
80 [0] = {
81 .mask = 0,
82 },
83 [1] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .log_max_qp = 12,
86 },
87 [2] = {
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
90 .log_max_qp = 17,
91 .mr_cache[0] = {
92 .size = 500,
93 .limit = 250
94 },
95 .mr_cache[1] = {
96 .size = 500,
97 .limit = 250
98 },
99 .mr_cache[2] = {
100 .size = 500,
101 .limit = 250
102 },
103 .mr_cache[3] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[4] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[5] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[6] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[7] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[8] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[9] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[10] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[11] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[12] = {
140 .size = 64,
141 .limit = 32
142 },
143 .mr_cache[13] = {
144 .size = 32,
145 .limit = 16
146 },
147 .mr_cache[14] = {
148 .size = 16,
149 .limit = 8
150 },
151 .mr_cache[15] = {
152 .size = 8,
153 .limit = 4
154 },
155 },
156};
e126ba97
EC		 157
158static int set_dma_caps(struct pci_dev *pdev)
159{
160 int err;
161
162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
163 if (err) {
1a91de28 164 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 165 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
166 if (err) {
1a91de28 167 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 168 return err;
169 }
170 }
171
172 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
173 if (err) {
174 dev_warn(&pdev->dev,
1a91de28 175 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 176 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
177 if (err) {
178 dev_err(&pdev->dev,
1a91de28 179 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 180 return err;
181 }
182 }
183
184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
185 return err;
186}
187
188static int request_bar(struct pci_dev *pdev)
189{
190 int err = 0;
191
192 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 193 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 194 return -ENODEV;
195 }
196
197 err = pci_request_regions(pdev, DRIVER_NAME);
198 if (err)
199 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
200
201 return err;
202}
203
204static void release_bar(struct pci_dev *pdev)
205{
206 pci_release_regions(pdev);
207}
208
209static int mlx5_enable_msix(struct mlx5_core_dev *dev)
210{
211 struct mlx5_eq_table *table = &dev->priv.eq_table;
c7a08ac7 212 int num_eqs = 1 << dev->caps.gen.log_max_eq;
e126ba97 213 int nvec;
e126ba97
EC		 214 int i;
215
c7a08ac7 216 nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 217 nvec = min_t(int, nvec, num_eqs);
218 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
219 return -ENOMEM;
220
221 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
222 if (!table->msix_arr)
223 return -ENOMEM;
224
225 for (i = 0; i < nvec; i++)
226 table->msix_arr[i].entry = i;
227
f3c9407b 228 nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
3a9e161a 229 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 230 if (nvec < 0)
231 return nvec;
e126ba97 232
f3c9407b 233 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 234
235 return 0;
236}
237
238static void mlx5_disable_msix(struct mlx5_core_dev *dev)
239{
240 struct mlx5_eq_table *table = &dev->priv.eq_table;
241
242 pci_disable_msix(dev->pdev);
243 kfree(table->msix_arr);
244}
245
246struct mlx5_reg_host_endianess {
247 u8 he;
248 u8 rsvd[15];
249};
250
87b8de49
EC		 251
252#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
253
254enum {
c7a08ac7
EC		 255 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
256 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 257};
258
c7a08ac7
EC		 259static u16 to_fw_pkey_sz(u32 size)
260{
261 switch (size) {
262 case 128:
263 return 0;
264 case 256:
265 return 1;
266 case 512:
267 return 2;
268 case 1024:
269 return 3;
270 case 2048:
271 return 4;
272 case 4096:
273 return 5;
274 default:
275 pr_warn("invalid pkey table size %d\n", size);
276 return 0;
277 }
278}
279
87b8de49
EC		 280/* selectively copy writable fields clearing any reserved area
281 */
b775516b 282static void copy_rw_fields(void *to, struct mlx5_caps *from)
87b8de49 283{
b775516b 284 __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
87b8de49
EC		 285 u64 v64;
286
b775516b
EC		 287 MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
288 MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
289 MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
290 MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
b775516b 291 MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
de61390c 292 MLX5_SET(cmd_hca_cap, to, log_uar_page_sz, PAGE_SHIFT - 12);
b775516b
EC		 293 v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
294 *flags_off = cpu_to_be64(v64);
87b8de49
EC		 295}
296
c7a08ac7
EC		 297static u16 get_pkey_table_size(int pkey)
298{
299 if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
300 return 0;
87b8de49 301
c7a08ac7
EC		 302 return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
303}
304
b775516b 305static void fw2drv_caps(struct mlx5_caps *caps, void *out)
e126ba97 306{
c7a08ac7 307 struct mlx5_general_caps *gen = &caps->gen;
b775516b
EC		 308
309 gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
310 gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
311 gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
312 gen->log_max_strq = MLX5_GET_PR(cmd_hca_cap, out, log_max_strq_sz);
313 gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srqs);
314 gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
315 gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
316 gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
317 gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
318 gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
319 gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
320 gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
321 gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
322 gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
323 gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
324 gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
325 gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
326 gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
327 gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
328 gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
329 gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
330 gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
331 gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
332 gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
333 gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
c7a08ac7 334 pr_debug("flags = 0x%llx\n", gen->flags);
b775516b
EC		 335 gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
336 gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
337 gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
338 gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
339 gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
340 gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
341 gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
342 gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
343 gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
344 gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
345 gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
c7a08ac7
EC		 346}
347
348static const char *caps_opmod_str(u16 opmod)
349{
350 switch (opmod) {
351 case HCA_CAP_OPMOD_GET_MAX:
352 return "GET_MAX";
353 case HCA_CAP_OPMOD_GET_CUR:
354 return "GET_CUR";
355 default:
356 return "Invalid";
357 }
358}
359
360int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
361 u16 opmod)
362{
b775516b
EC		 363 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
364 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
365 void *out;
e126ba97
EC		 366 int err;
367
b775516b
EC		 368 memset(in, 0, sizeof(in));
369 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 370 if (!out)
e126ba97 371 return -ENOMEM;
b775516b
EC		 372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
373 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
374 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
375 if (err)
376 goto query_ex;
e126ba97 377
b775516b 378 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 379 if (err) {
380 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
e126ba97
EC		 381 goto query_ex;
382 }
c7a08ac7 383 mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
b775516b 384 fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct));
c7a08ac7
EC		 385
386query_ex:
387 kfree(out);
388 return err;
389}
390
b775516b 391static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 392{
b775516b 393 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 394 int err;
395
b775516b 396 memset(out, 0, sizeof(out));
e126ba97 397
b775516b
EC		 398 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
399 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 400 if (err)
c7a08ac7 401 return err;
e126ba97 402
b775516b 403 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 404
405 return err;
406}
407
408static int handle_hca_cap(struct mlx5_core_dev *dev)
409{
b775516b 410 void *set_ctx = NULL;
c7a08ac7
EC		 411 struct mlx5_profile *prof = dev->profile;
412 struct mlx5_caps *cur_caps = NULL;
413 struct mlx5_caps *max_caps = NULL;
414 int err = -ENOMEM;
b775516b 415 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
c7a08ac7 416
b775516b 417 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 418 if (!set_ctx)
e126ba97 419 goto query_ex;
e126ba97 420
c7a08ac7
EC		 421 max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
422 if (!max_caps)
423 goto query_ex;
e126ba97 424
c7a08ac7
EC		 425 cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
426 if (!cur_caps)
427 goto query_ex;
e126ba97 428
c7a08ac7
EC		 429 err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
430 if (err)
e126ba97 431 goto query_ex;
e126ba97 432
c7a08ac7 433 err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 434 if (err)
435 goto query_ex;
436
c7a08ac7
EC		 437 /* we limit the size of the pkey table to 128 entries for now */
438 cur_caps->gen.pkey_table_size = 128;
439
440 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
441 cur_caps->gen.log_max_qp = prof->log_max_qp;
442
443 /* disable checksum */
444 cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
445
b775516b
EC		 446 copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, hca_capability_struct),
447 cur_caps);
448 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 449
e126ba97 450query_ex:
c7a08ac7
EC		 451 kfree(cur_caps);
452 kfree(max_caps);
e126ba97
EC		 453 kfree(set_ctx);
454
455 return err;
456}
457
458static int set_hca_ctrl(struct mlx5_core_dev *dev)
459{
460 struct mlx5_reg_host_endianess he_in;
461 struct mlx5_reg_host_endianess he_out;
462 int err;
463
464 memset(&he_in, 0, sizeof(he_in));
465 he_in.he = MLX5_SET_HOST_ENDIANNESS;
466 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
467 &he_out, sizeof(he_out),
468 MLX5_REG_HOST_ENDIANNESS, 0, 1);
469 return err;
470}
471
cd23b14b
EC		 472static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
473{
474 int err;
475 struct mlx5_enable_hca_mbox_in in;
476 struct mlx5_enable_hca_mbox_out out;
477
478 memset(&in, 0, sizeof(in));
479 memset(&out, 0, sizeof(out));
480 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
481 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
482 if (err)
483 return err;
484
485 if (out.hdr.status)
486 return mlx5_cmd_status_to_err(&out.hdr);
487
488 return 0;
489}
490
491static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
492{
493 int err;
494 struct mlx5_disable_hca_mbox_in in;
495 struct mlx5_disable_hca_mbox_out out;
496
497 memset(&in, 0, sizeof(in));
498 memset(&out, 0, sizeof(out));
499 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
500 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
501 if (err)
502 return err;
503
504 if (out.hdr.status)
505 return mlx5_cmd_status_to_err(&out.hdr);
506
507 return 0;
508}
509
233d05d2
SM		 510int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
511{
512 struct mlx5_eq_table *table = &dev->priv.eq_table;
513 struct mlx5_eq *eq, *n;
514 int err = -ENOENT;
515
516 spin_lock(&table->lock);
517 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
518 if (eq->index == vector) {
519 *eqn = eq->eqn;
520 *irqn = eq->irqn;
521 err = 0;
522 break;
523 }
524 }
525 spin_unlock(&table->lock);
526
527 return err;
528}
529EXPORT_SYMBOL(mlx5_vector2eqn);
530
531static void free_comp_eqs(struct mlx5_core_dev *dev)
532{
533 struct mlx5_eq_table *table = &dev->priv.eq_table;
534 struct mlx5_eq *eq, *n;
535
536 spin_lock(&table->lock);
537 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
538 list_del(&eq->list);
539 spin_unlock(&table->lock);
540 if (mlx5_destroy_unmap_eq(dev, eq))
541 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
542 eq->eqn);
543 kfree(eq);
544 spin_lock(&table->lock);
545 }
546 spin_unlock(&table->lock);
547}
548
549static int alloc_comp_eqs(struct mlx5_core_dev *dev)
550{
551 struct mlx5_eq_table *table = &dev->priv.eq_table;
552 char name[MLX5_MAX_EQ_NAME];
553 struct mlx5_eq *eq;
554 int ncomp_vec;
555 int nent;
556 int err;
557 int i;
558
559 INIT_LIST_HEAD(&table->comp_eqs_list);
560 ncomp_vec = table->num_comp_vectors;
561 nent = MLX5_COMP_EQ_SIZE;
562 for (i = 0; i < ncomp_vec; i++) {
563 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
564 if (!eq) {
565 err = -ENOMEM;
566 goto clean;
567 }
568
569 snprintf(name, MLX5_MAX_EQ_NAME, "mlx5_comp%d", i);
570 err = mlx5_create_map_eq(dev, eq,
571 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
572 name, &dev->priv.uuari.uars[0]);
573 if (err) {
574 kfree(eq);
575 goto clean;
576 }
577 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
578 eq->index = i;
579 spin_lock(&table->lock);
580 list_add_tail(&eq->list, &table->comp_eqs_list);
581 spin_unlock(&table->lock);
582 }
583
584 return 0;
585
586clean:
587 free_comp_eqs(dev);
588 return err;
589}
590
9603b61d 591static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 592{
593 struct mlx5_priv *priv = &dev->priv;
594 int err;
595
596 dev->pdev = pdev;
597 pci_set_drvdata(dev->pdev, dev);
598 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
599 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
600
601 mutex_init(&priv->pgdir_mutex);
602 INIT_LIST_HEAD(&priv->pgdir_list);
603 spin_lock_init(&priv->mkey_lock);
604
605 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
606 if (!priv->dbg_root)
607 return -ENOMEM;
608
609 err = pci_enable_device(pdev);
610 if (err) {
1a91de28 611 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 612 goto err_dbg;
613 }
614
615 err = request_bar(pdev);
616 if (err) {
1a91de28 617 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 618 goto err_disable;
619 }
620
621 pci_set_master(pdev);
622
623 err = set_dma_caps(pdev);
624 if (err) {
625 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
626 goto err_clr_master;
627 }
628
629 dev->iseg_base = pci_resource_start(dev->pdev, 0);
630 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
631 if (!dev->iseg) {
632 err = -ENOMEM;
633 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
634 goto err_clr_master;
635 }
636 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
637 fw_rev_min(dev), fw_rev_sub(dev));
638
639 err = mlx5_cmd_init(dev);
640 if (err) {
641 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
642 goto err_unmap;
643 }
644
645 mlx5_pagealloc_init(dev);
cd23b14b
EC		 646
647 err = mlx5_core_enable_hca(dev);
648 if (err) {
649 dev_err(&pdev->dev, "enable hca failed\n");
650 goto err_pagealloc_cleanup;
651 }
652
653 err = mlx5_satisfy_startup_pages(dev, 1);
654 if (err) {
655 dev_err(&pdev->dev, "failed to allocate boot pages\n");
656 goto err_disable_hca;
657 }
658
e126ba97
EC		 659 err = set_hca_ctrl(dev);
660 if (err) {
661 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 662 goto reclaim_boot_pages;
e126ba97
EC		 663 }
664
665 err = handle_hca_cap(dev);
666 if (err) {
667 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 668 goto reclaim_boot_pages;
e126ba97
EC		 669 }
670
cd23b14b 671 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 672 if (err) {
cd23b14b
EC		 673 dev_err(&pdev->dev, "failed to allocate init pages\n");
674 goto reclaim_boot_pages;
e126ba97
EC		 675 }
676
677 err = mlx5_pagealloc_start(dev);
678 if (err) {
679 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 680 goto reclaim_boot_pages;
e126ba97
EC		 681 }
682
683 err = mlx5_cmd_init_hca(dev);
684 if (err) {
685 dev_err(&pdev->dev, "init hca failed\n");
686 goto err_pagealloc_stop;
687 }
688
689 mlx5_start_health_poll(dev);
690
691 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
692 if (err) {
693 dev_err(&pdev->dev, "query hca failed\n");
694 goto err_stop_poll;
695 }
696
697 err = mlx5_cmd_query_adapter(dev);
698 if (err) {
699 dev_err(&pdev->dev, "query adapter failed\n");
700 goto err_stop_poll;
701 }
702
703 err = mlx5_enable_msix(dev);
704 if (err) {
705 dev_err(&pdev->dev, "enable msix failed\n");
706 goto err_stop_poll;
707 }
708
709 err = mlx5_eq_init(dev);
710 if (err) {
711 dev_err(&pdev->dev, "failed to initialize eq\n");
712 goto disable_msix;
713 }
714
715 err = mlx5_alloc_uuars(dev, &priv->uuari);
716 if (err) {
717 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
718 goto err_eq_cleanup;
719 }
720
721 err = mlx5_start_eqs(dev);
722 if (err) {
723 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
724 goto err_free_uar;
725 }
726
233d05d2
SM		 727 err = alloc_comp_eqs(dev);
728 if (err) {
729 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
730 goto err_stop_eqs;
731 }
732
e126ba97
EC		 733 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
734
735 mlx5_init_cq_table(dev);
736 mlx5_init_qp_table(dev);
737 mlx5_init_srq_table(dev);
3bcdb17a 738 mlx5_init_mr_table(dev);
e126ba97
EC		 739
740 return 0;
741
233d05d2
SM		 742err_stop_eqs:
743 mlx5_stop_eqs(dev);
744
e126ba97
EC		 745err_free_uar:
746 mlx5_free_uuars(dev, &priv->uuari);
747
748err_eq_cleanup:
749 mlx5_eq_cleanup(dev);
750
751disable_msix:
752 mlx5_disable_msix(dev);
753
754err_stop_poll:
755 mlx5_stop_health_poll(dev);
1bde6e30
EC		 756 if (mlx5_cmd_teardown_hca(dev)) {
757 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
758 return err;
759 }
e126ba97
EC		 760
761err_pagealloc_stop:
762 mlx5_pagealloc_stop(dev);
763
cd23b14b 764reclaim_boot_pages:
e126ba97
EC		 765 mlx5_reclaim_startup_pages(dev);
766
cd23b14b
EC		 767err_disable_hca:
768 mlx5_core_disable_hca(dev);
769
e126ba97
EC		 770err_pagealloc_cleanup:
771 mlx5_pagealloc_cleanup(dev);
772 mlx5_cmd_cleanup(dev);
773
774err_unmap:
775 iounmap(dev->iseg);
776
777err_clr_master:
778 pci_clear_master(dev->pdev);
779 release_bar(dev->pdev);
780
781err_disable:
782 pci_disable_device(dev->pdev);
783
784err_dbg:
785 debugfs_remove(priv->dbg_root);
786 return err;
787}
e126ba97 788
9603b61d 789static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 790{
791 struct mlx5_priv *priv = &dev->priv;
792
793 mlx5_cleanup_srq_table(dev);
794 mlx5_cleanup_qp_table(dev);
795 mlx5_cleanup_cq_table(dev);
233d05d2 796 free_comp_eqs(dev);
e126ba97
EC		 797 mlx5_stop_eqs(dev);
798 mlx5_free_uuars(dev, &priv->uuari);
799 mlx5_eq_cleanup(dev);
800 mlx5_disable_msix(dev);
801 mlx5_stop_health_poll(dev);
1bde6e30
EC		 802 if (mlx5_cmd_teardown_hca(dev)) {
803 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
804 return;
805 }
e126ba97
EC		 806 mlx5_pagealloc_stop(dev);
807 mlx5_reclaim_startup_pages(dev);
cd23b14b 808 mlx5_core_disable_hca(dev);
e126ba97
EC		 809 mlx5_pagealloc_cleanup(dev);
810 mlx5_cmd_cleanup(dev);
811 iounmap(dev->iseg);
812 pci_clear_master(dev->pdev);
813 release_bar(dev->pdev);
814 pci_disable_device(dev->pdev);
815 debugfs_remove(priv->dbg_root);
816}
9603b61d
JM		 817
818static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
819{
820 struct mlx5_device_context *dev_ctx;
821 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
822
823 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
824 if (!dev_ctx) {
825 pr_warn("mlx5_add_device: alloc context failed\n");
826 return;
827 }
828
829 dev_ctx->intf = intf;
830 dev_ctx->context = intf->add(dev);
831
832 if (dev_ctx->context) {
833 spin_lock_irq(&priv->ctx_lock);
834 list_add_tail(&dev_ctx->list, &priv->ctx_list);
835 spin_unlock_irq(&priv->ctx_lock);
836 } else {
837 kfree(dev_ctx);
838 }
839}
840
841static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
842{
843 struct mlx5_device_context *dev_ctx;
844 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
845
846 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
847 if (dev_ctx->intf == intf) {
848 spin_lock_irq(&priv->ctx_lock);
849 list_del(&dev_ctx->list);
850 spin_unlock_irq(&priv->ctx_lock);
851
852 intf->remove(dev, dev_ctx->context);
853 kfree(dev_ctx);
854 return;
855 }
856}
857static int mlx5_register_device(struct mlx5_core_dev *dev)
858{
859 struct mlx5_priv *priv = &dev->priv;
860 struct mlx5_interface *intf;
861
862 mutex_lock(&intf_mutex);
863 list_add_tail(&priv->dev_list, &dev_list);
864 list_for_each_entry(intf, &intf_list, list)
865 mlx5_add_device(intf, priv);
866 mutex_unlock(&intf_mutex);
867
868 return 0;
869}
870static void mlx5_unregister_device(struct mlx5_core_dev *dev)
871{
872 struct mlx5_priv *priv = &dev->priv;
873 struct mlx5_interface *intf;
874
875 mutex_lock(&intf_mutex);
876 list_for_each_entry(intf, &intf_list, list)
877 mlx5_remove_device(intf, priv);
878 list_del(&priv->dev_list);
879 mutex_unlock(&intf_mutex);
880}
881
882int mlx5_register_interface(struct mlx5_interface *intf)
883{
884 struct mlx5_priv *priv;
885
886 if (!intf->add || !intf->remove)
887 return -EINVAL;
888
889 mutex_lock(&intf_mutex);
890 list_add_tail(&intf->list, &intf_list);
891 list_for_each_entry(priv, &dev_list, dev_list)
892 mlx5_add_device(intf, priv);
893 mutex_unlock(&intf_mutex);
894
895 return 0;
896}
897EXPORT_SYMBOL(mlx5_register_interface);
898
899void mlx5_unregister_interface(struct mlx5_interface *intf)
900{
901 struct mlx5_priv *priv;
902
903 mutex_lock(&intf_mutex);
904 list_for_each_entry(priv, &dev_list, dev_list)
905 mlx5_remove_device(intf, priv);
906 list_del(&intf->list);
907 mutex_unlock(&intf_mutex);
908}
909EXPORT_SYMBOL(mlx5_unregister_interface);
910
911static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 912 unsigned long param)
9603b61d
JM		 913{
914 struct mlx5_priv *priv = &dev->priv;
915 struct mlx5_device_context *dev_ctx;
916 unsigned long flags;
917
918 spin_lock_irqsave(&priv->ctx_lock, flags);
919
920 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
921 if (dev_ctx->intf->event)
4d2f9bbb 922 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 923
924 spin_unlock_irqrestore(&priv->ctx_lock, flags);
925}
926
927struct mlx5_core_event_handler {
928 void (*event)(struct mlx5_core_dev *dev,
929 enum mlx5_dev_event event,
930 void *data);
931};
932
f66f049f
EC		 933#define MLX5_IB_MOD "mlx5_ib"
934
9603b61d
JM		 935static int init_one(struct pci_dev *pdev,
936 const struct pci_device_id *id)
937{
938 struct mlx5_core_dev *dev;
939 struct mlx5_priv *priv;
940 int err;
941
942 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
943 if (!dev) {
944 dev_err(&pdev->dev, "kzalloc failed\n");
945 return -ENOMEM;
946 }
947 priv = &dev->priv;
948
949 pci_set_drvdata(pdev, dev);
950
951 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
952 pr_warn("selected profile out of range, selecting default (%d)\n",
953 MLX5_DEFAULT_PROF);
954 prof_sel = MLX5_DEFAULT_PROF;
955 }
956 dev->profile = &profile[prof_sel];
957 dev->event = mlx5_core_event;
958
364d1798
EC		 959 INIT_LIST_HEAD(&priv->ctx_list);
960 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 961 err = mlx5_dev_init(dev, pdev);
962 if (err) {
963 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
964 goto out;
965 }
966
9603b61d
JM		 967 err = mlx5_register_device(dev);
968 if (err) {
969 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
970 goto out_init;
971 }
972
f66f049f
EC		 973 err = request_module_nowait(MLX5_IB_MOD);
974 if (err)
975 pr_info("failed request module on %s\n", MLX5_IB_MOD);
976
9603b61d
JM		 977 return 0;
978
979out_init:
980 mlx5_dev_cleanup(dev);
981out:
982 kfree(dev);
983 return err;
984}
985static void remove_one(struct pci_dev *pdev)
986{
987 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
988
989 mlx5_unregister_device(dev);
990 mlx5_dev_cleanup(dev);
991 kfree(dev);
992}
993
994static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 995 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
996 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
997 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
998 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
999 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1000 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1001 { 0, }
1002};
1003
1004MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1005
1006static struct pci_driver mlx5_core_driver = {
1007 .name = DRIVER_NAME,
1008 .id_table = mlx5_core_pci_table,
1009 .probe = init_one,
1010 .remove = remove_one
1011};
e126ba97
EC		 1012
1013static int __init init(void)
1014{
1015 int err;
1016
1017 mlx5_register_debugfs();
1018 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1019 if (!mlx5_core_wq) {
1020 err = -ENOMEM;
1021 goto err_debug;
1022 }
1023 mlx5_health_init();
1024
9603b61d
JM		 1025 err = pci_register_driver(&mlx5_core_driver);
1026 if (err)
1027 goto err_health;
1028
e126ba97
EC		 1029 return 0;
1030
9603b61d
JM		 1031err_health:
1032 mlx5_health_cleanup();
1033 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 1034err_debug:
1035 mlx5_unregister_debugfs();
1036 return err;
1037}
1038
1039static void __exit cleanup(void)
1040{
9603b61d 1041 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1042 mlx5_health_cleanup();
1043 destroy_workqueue(mlx5_core_wq);
1044 mlx5_unregister_debugfs();
1045}
1046
1047module_init(init);
1048module_exit(cleanup);
Linux kernel - Deliverables
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