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net/mlx5_core: Add pci error handlers to mlx5_core driver
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
89d44f0a 48#include <linux/delay.h>
b775516b 49#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 50#include "mlx5_core.h"
51
e126ba97 52MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 53MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 54MODULE_LICENSE("Dual BSD/GPL");
55MODULE_VERSION(DRIVER_VERSION);
56
57int mlx5_core_debug_mask;
58module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
59MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
60
9603b61d
JM		 61#define MLX5_DEFAULT_PROF 2
62static int prof_sel = MLX5_DEFAULT_PROF;
63module_param_named(prof_sel, prof_sel, int, 0444);
64MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
65
9603b61d
JM		 66static LIST_HEAD(intf_list);
67static LIST_HEAD(dev_list);
68static DEFINE_MUTEX(intf_mutex);
69
70struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
73 void *context;
74};
75
76static struct mlx5_profile profile[] = {
77 [0] = {
78 .mask = 0,
79 },
80 [1] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
82 .log_max_qp = 12,
83 },
84 [2] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
87 .log_max_qp = 17,
88 .mr_cache[0] = {
89 .size = 500,
90 .limit = 250
91 },
92 .mr_cache[1] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[2] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[3] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[4] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[5] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[6] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[7] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[8] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[9] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[10] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[11] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[12] = {
137 .size = 64,
138 .limit = 32
139 },
140 .mr_cache[13] = {
141 .size = 32,
142 .limit = 16
143 },
144 .mr_cache[14] = {
145 .size = 16,
146 .limit = 8
147 },
148 .mr_cache[15] = {
149 .size = 8,
150 .limit = 4
151 },
152 },
153};
e126ba97
EC		 154
155static int set_dma_caps(struct pci_dev *pdev)
156{
157 int err;
158
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
160 if (err) {
1a91de28 161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
163 if (err) {
1a91de28 164 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 165 return err;
166 }
167 }
168
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
170 if (err) {
171 dev_warn(&pdev->dev,
1a91de28 172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 if (err) {
175 dev_err(&pdev->dev,
1a91de28 176 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 177 return err;
178 }
179 }
180
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
182 return err;
183}
184
89d44f0a
MD		 185static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
186{
187 struct pci_dev *pdev = dev->pdev;
188 int err = 0;
189
190 mutex_lock(&dev->pci_status_mutex);
191 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
192 err = pci_enable_device(pdev);
193 if (!err)
194 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
195 }
196 mutex_unlock(&dev->pci_status_mutex);
197
198 return err;
199}
200
201static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
202{
203 struct pci_dev *pdev = dev->pdev;
204
205 mutex_lock(&dev->pci_status_mutex);
206 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
207 pci_disable_device(pdev);
208 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
209 }
210 mutex_unlock(&dev->pci_status_mutex);
211}
212
e126ba97
EC		 213static int request_bar(struct pci_dev *pdev)
214{
215 int err = 0;
216
217 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 218 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 219 return -ENODEV;
220 }
221
222 err = pci_request_regions(pdev, DRIVER_NAME);
223 if (err)
224 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225
226 return err;
227}
228
229static void release_bar(struct pci_dev *pdev)
230{
231 pci_release_regions(pdev);
232}
233
234static int mlx5_enable_msix(struct mlx5_core_dev *dev)
235{
db058a18
SM		 236 struct mlx5_priv *priv = &dev->priv;
237 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 238 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 239 int nvec;
e126ba97
EC		 240 int i;
241
938fe83c
SM		 242 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
243 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 244 nvec = min_t(int, nvec, num_eqs);
245 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
246 return -ENOMEM;
247
db058a18
SM		 248 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
249
250 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
251 if (!priv->msix_arr || !priv->irq_info)
252 goto err_free_msix;
e126ba97
EC		 253
254 for (i = 0; i < nvec; i++)
db058a18 255 priv->msix_arr[i].entry = i;
e126ba97 256
db058a18 257 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 258 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 259 if (nvec < 0)
260 return nvec;
e126ba97 261
f3c9407b 262 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 263
264 return 0;
db058a18
SM		 265
266err_free_msix:
267 kfree(priv->irq_info);
268 kfree(priv->msix_arr);
269 return -ENOMEM;
e126ba97
EC		 270}
271
272static void mlx5_disable_msix(struct mlx5_core_dev *dev)
273{
db058a18 274 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 275
276 pci_disable_msix(dev->pdev);
db058a18
SM		 277 kfree(priv->irq_info);
278 kfree(priv->msix_arr);
e126ba97
EC		 279}
280
281struct mlx5_reg_host_endianess {
282 u8 he;
283 u8 rsvd[15];
284};
285
87b8de49
EC		 286
287#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
288
289enum {
c7a08ac7
EC		 290 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
291 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 292};
293
c7a08ac7
EC		 294static u16 to_fw_pkey_sz(u32 size)
295{
296 switch (size) {
297 case 128:
298 return 0;
299 case 256:
300 return 1;
301 case 512:
302 return 2;
303 case 1024:
304 return 3;
305 case 2048:
306 return 4;
307 case 4096:
308 return 5;
309 default:
310 pr_warn("invalid pkey table size %d\n", size);
311 return 0;
312 }
313}
314
938fe83c
SM		 315int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
316 enum mlx5_cap_mode cap_mode)
c7a08ac7 317{
b775516b
EC		 318 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
319 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 320 void *out, *hca_caps;
321 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 322 int err;
323
b775516b
EC		 324 memset(in, 0, sizeof(in));
325 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 326 if (!out)
e126ba97 327 return -ENOMEM;
938fe83c 328
b775516b
EC		 329 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
330 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
331 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
332 if (err)
333 goto query_ex;
e126ba97 334
b775516b 335 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 336 if (err) {
938fe83c
SM		 337 mlx5_core_warn(dev,
338 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
339 cap_type, cap_mode, err);
e126ba97
EC		 340 goto query_ex;
341 }
c7a08ac7 342
938fe83c
SM		 343 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
344
345 switch (cap_mode) {
346 case HCA_CAP_OPMOD_GET_MAX:
347 memcpy(dev->hca_caps_max[cap_type], hca_caps,
348 MLX5_UN_SZ_BYTES(hca_cap_union));
349 break;
350 case HCA_CAP_OPMOD_GET_CUR:
351 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
352 MLX5_UN_SZ_BYTES(hca_cap_union));
353 break;
354 default:
355 mlx5_core_warn(dev,
356 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
357 cap_type, cap_mode);
358 err = -EINVAL;
359 break;
360 }
c7a08ac7
EC		 361query_ex:
362 kfree(out);
363 return err;
364}
365
b775516b 366static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 367{
b775516b 368 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 369 int err;
370
b775516b 371 memset(out, 0, sizeof(out));
e126ba97 372
b775516b
EC		 373 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
374 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 375 if (err)
c7a08ac7 376 return err;
e126ba97 377
b775516b 378 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 379
380 return err;
381}
382
383static int handle_hca_cap(struct mlx5_core_dev *dev)
384{
b775516b 385 void *set_ctx = NULL;
c7a08ac7 386 struct mlx5_profile *prof = dev->profile;
c7a08ac7 387 int err = -ENOMEM;
b775516b 388 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 389 void *set_hca_cap;
c7a08ac7 390
b775516b 391 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 392 if (!set_ctx)
e126ba97 393 goto query_ex;
e126ba97 394
938fe83c 395 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 396 if (err)
e126ba97 397 goto query_ex;
e126ba97 398
938fe83c 399 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 400 if (err)
401 goto query_ex;
402
938fe83c
SM		 403 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
404 capability);
405 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
406 MLX5_ST_SZ_BYTES(cmd_hca_cap));
407
408 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 409 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 410 128);
c7a08ac7 411 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 412 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
413 to_fw_pkey_sz(128));
c7a08ac7
EC		 414
415 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 416 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
417 prof->log_max_qp);
c7a08ac7 418
938fe83c
SM		 419 /* disable cmdif checksum */
420 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 421
fe1e1876
CS		 422 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
423
b775516b 424 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 425
e126ba97 426query_ex:
e126ba97 427 kfree(set_ctx);
e126ba97
EC		 428 return err;
429}
430
431static int set_hca_ctrl(struct mlx5_core_dev *dev)
432{
433 struct mlx5_reg_host_endianess he_in;
434 struct mlx5_reg_host_endianess he_out;
435 int err;
436
437 memset(&he_in, 0, sizeof(he_in));
438 he_in.he = MLX5_SET_HOST_ENDIANNESS;
439 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
440 &he_out, sizeof(he_out),
441 MLX5_REG_HOST_ENDIANNESS, 0, 1);
442 return err;
443}
444
cd23b14b
EC		 445static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
446{
447 int err;
448 struct mlx5_enable_hca_mbox_in in;
449 struct mlx5_enable_hca_mbox_out out;
450
451 memset(&in, 0, sizeof(in));
452 memset(&out, 0, sizeof(out));
453 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
454 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
455 if (err)
456 return err;
457
458 if (out.hdr.status)
459 return mlx5_cmd_status_to_err(&out.hdr);
460
461 return 0;
462}
463
464static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
465{
466 int err;
467 struct mlx5_disable_hca_mbox_in in;
468 struct mlx5_disable_hca_mbox_out out;
469
470 memset(&in, 0, sizeof(in));
471 memset(&out, 0, sizeof(out));
472 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
473 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
474 if (err)
475 return err;
476
477 if (out.hdr.status)
478 return mlx5_cmd_status_to_err(&out.hdr);
479
480 return 0;
481}
482
db058a18
SM		 483static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
484{
485 struct mlx5_priv *priv = &mdev->priv;
486 struct msix_entry *msix = priv->msix_arr;
487 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 488 int numa_node = priv->numa_node;
db058a18
SM		 489 int err;
490
491 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
492 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
493 return -ENOMEM;
494 }
495
dda922c8
DM		 496 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
497 priv->irq_info[i].mask);
db058a18
SM		 498
499 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
500 if (err) {
501 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
502 irq);
503 goto err_clear_mask;
504 }
505
506 return 0;
507
508err_clear_mask:
509 free_cpumask_var(priv->irq_info[i].mask);
510 return err;
511}
512
513static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
514{
515 struct mlx5_priv *priv = &mdev->priv;
516 struct msix_entry *msix = priv->msix_arr;
517 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
518
519 irq_set_affinity_hint(irq, NULL);
520 free_cpumask_var(priv->irq_info[i].mask);
521}
522
523static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
524{
525 int err;
526 int i;
527
528 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
529 err = mlx5_irq_set_affinity_hint(mdev, i);
530 if (err)
531 goto err_out;
532 }
533
534 return 0;
535
536err_out:
537 for (i--; i >= 0; i--)
538 mlx5_irq_clear_affinity_hint(mdev, i);
539
540 return err;
541}
542
543static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
544{
545 int i;
546
547 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
548 mlx5_irq_clear_affinity_hint(mdev, i);
549}
550
233d05d2
SM		 551int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
552{
553 struct mlx5_eq_table *table = &dev->priv.eq_table;
554 struct mlx5_eq *eq, *n;
555 int err = -ENOENT;
556
557 spin_lock(&table->lock);
558 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
559 if (eq->index == vector) {
560 *eqn = eq->eqn;
561 *irqn = eq->irqn;
562 err = 0;
563 break;
564 }
565 }
566 spin_unlock(&table->lock);
567
568 return err;
569}
570EXPORT_SYMBOL(mlx5_vector2eqn);
571
572static void free_comp_eqs(struct mlx5_core_dev *dev)
573{
574 struct mlx5_eq_table *table = &dev->priv.eq_table;
575 struct mlx5_eq *eq, *n;
576
577 spin_lock(&table->lock);
578 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
579 list_del(&eq->list);
580 spin_unlock(&table->lock);
581 if (mlx5_destroy_unmap_eq(dev, eq))
582 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
583 eq->eqn);
584 kfree(eq);
585 spin_lock(&table->lock);
586 }
587 spin_unlock(&table->lock);
588}
589
590static int alloc_comp_eqs(struct mlx5_core_dev *dev)
591{
592 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 593 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 594 struct mlx5_eq *eq;
595 int ncomp_vec;
596 int nent;
597 int err;
598 int i;
599
600 INIT_LIST_HEAD(&table->comp_eqs_list);
601 ncomp_vec = table->num_comp_vectors;
602 nent = MLX5_COMP_EQ_SIZE;
603 for (i = 0; i < ncomp_vec; i++) {
604 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
605 if (!eq) {
606 err = -ENOMEM;
607 goto clean;
608 }
609
db058a18 610 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 611 err = mlx5_create_map_eq(dev, eq,
612 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
613 name, &dev->priv.uuari.uars[0]);
614 if (err) {
615 kfree(eq);
616 goto clean;
617 }
618 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
619 eq->index = i;
620 spin_lock(&table->lock);
621 list_add_tail(&eq->list, &table->comp_eqs_list);
622 spin_unlock(&table->lock);
623 }
624
625 return 0;
626
627clean:
628 free_comp_eqs(dev);
629 return err;
630}
631
f62b8bb8
AV		 632#ifdef CONFIG_MLX5_CORE_EN
633static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
634{
635 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
636 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
637 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
638 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
639 int err;
640 u32 sup_issi;
641
642 memset(query_in, 0, sizeof(query_in));
643 memset(query_out, 0, sizeof(query_out));
644
645 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
646
647 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
648 query_out, sizeof(query_out));
649 if (err) {
650 if (((struct mlx5_outbox_hdr *)query_out)->status ==
651 MLX5_CMD_STAT_BAD_OP_ERR) {
652 pr_debug("Only ISSI 0 is supported\n");
653 return 0;
654 }
655
656 pr_err("failed to query ISSI\n");
657 return err;
658 }
659
660 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
661
662 if (sup_issi & (1 << 1)) {
663 memset(set_in, 0, sizeof(set_in));
664 memset(set_out, 0, sizeof(set_out));
665
666 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
667 MLX5_SET(set_issi_in, set_in, current_issi, 1);
668
669 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
670 set_out, sizeof(set_out));
671 if (err) {
672 pr_err("failed to set ISSI=1\n");
673 return err;
674 }
675
676 dev->issi = 1;
677
678 return 0;
e74a1db0 679 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 680 return 0;
681 }
682
683 return -ENOTSUPP;
684}
685#endif
686
88a85f99
AS		 687static int map_bf_area(struct mlx5_core_dev *dev)
688{
689 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
690 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
691
692 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
693
694 return dev->priv.bf_mapping ? 0 : -ENOMEM;
695}
696
697static void unmap_bf_area(struct mlx5_core_dev *dev)
698{
699 if (dev->priv.bf_mapping)
700 io_mapping_free(dev->priv.bf_mapping);
701}
702
a31208b1
MD		 703static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
704{
705 struct mlx5_device_context *dev_ctx;
706 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
707
708 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
709 if (!dev_ctx)
710 return;
711
712 dev_ctx->intf = intf;
713 dev_ctx->context = intf->add(dev);
714
715 if (dev_ctx->context) {
716 spin_lock_irq(&priv->ctx_lock);
717 list_add_tail(&dev_ctx->list, &priv->ctx_list);
718 spin_unlock_irq(&priv->ctx_lock);
719 } else {
720 kfree(dev_ctx);
721 }
722}
723
724static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
725{
726 struct mlx5_device_context *dev_ctx;
727 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
728
729 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
730 if (dev_ctx->intf == intf) {
731 spin_lock_irq(&priv->ctx_lock);
732 list_del(&dev_ctx->list);
733 spin_unlock_irq(&priv->ctx_lock);
734
735 intf->remove(dev, dev_ctx->context);
736 kfree(dev_ctx);
737 return;
738 }
739}
740
741static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 742{
743 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 744 struct mlx5_interface *intf;
745
746 mutex_lock(&intf_mutex);
747 list_add_tail(&priv->dev_list, &dev_list);
748 list_for_each_entry(intf, &intf_list, list)
749 mlx5_add_device(intf, priv);
750 mutex_unlock(&intf_mutex);
751
752 return 0;
753}
754
755static void mlx5_unregister_device(struct mlx5_core_dev *dev)
756{
757 struct mlx5_priv *priv = &dev->priv;
758 struct mlx5_interface *intf;
759
760 mutex_lock(&intf_mutex);
761 list_for_each_entry(intf, &intf_list, list)
762 mlx5_remove_device(intf, priv);
763 list_del(&priv->dev_list);
764 mutex_unlock(&intf_mutex);
765}
766
767int mlx5_register_interface(struct mlx5_interface *intf)
768{
769 struct mlx5_priv *priv;
770
771 if (!intf->add || !intf->remove)
772 return -EINVAL;
773
774 mutex_lock(&intf_mutex);
775 list_add_tail(&intf->list, &intf_list);
776 list_for_each_entry(priv, &dev_list, dev_list)
777 mlx5_add_device(intf, priv);
778 mutex_unlock(&intf_mutex);
779
780 return 0;
781}
782EXPORT_SYMBOL(mlx5_register_interface);
783
784void mlx5_unregister_interface(struct mlx5_interface *intf)
785{
786 struct mlx5_priv *priv;
787
788 mutex_lock(&intf_mutex);
789 list_for_each_entry(priv, &dev_list, dev_list)
790 mlx5_remove_device(intf, priv);
791 list_del(&intf->list);
792 mutex_unlock(&intf_mutex);
793}
794EXPORT_SYMBOL(mlx5_unregister_interface);
795
796void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
797{
798 struct mlx5_priv *priv = &mdev->priv;
799 struct mlx5_device_context *dev_ctx;
800 unsigned long flags;
801 void *result = NULL;
802
803 spin_lock_irqsave(&priv->ctx_lock, flags);
804
805 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
806 if ((dev_ctx->intf->protocol == protocol) &&
807 dev_ctx->intf->get_dev) {
808 result = dev_ctx->intf->get_dev(dev_ctx->context);
809 break;
810 }
811
812 spin_unlock_irqrestore(&priv->ctx_lock, flags);
813
814 return result;
815}
816EXPORT_SYMBOL(mlx5_get_protocol_dev);
817
818static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
819{
820 struct pci_dev *pdev = dev->pdev;
821 int err = 0;
e126ba97 822
e126ba97
EC		 823 pci_set_drvdata(dev->pdev, dev);
824 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
825 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
826
827 mutex_init(&priv->pgdir_mutex);
828 INIT_LIST_HEAD(&priv->pgdir_list);
829 spin_lock_init(&priv->mkey_lock);
830
311c7c71
SM		 831 mutex_init(&priv->alloc_mutex);
832
833 priv->numa_node = dev_to_node(&dev->pdev->dev);
834
e126ba97
EC		 835 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
836 if (!priv->dbg_root)
837 return -ENOMEM;
838
89d44f0a 839 err = mlx5_pci_enable_device(dev);
e126ba97 840 if (err) {
1a91de28 841 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 842 goto err_dbg;
843 }
844
845 err = request_bar(pdev);
846 if (err) {
1a91de28 847 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 848 goto err_disable;
849 }
850
851 pci_set_master(pdev);
852
853 err = set_dma_caps(pdev);
854 if (err) {
855 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
856 goto err_clr_master;
857 }
858
859 dev->iseg_base = pci_resource_start(dev->pdev, 0);
860 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
861 if (!dev->iseg) {
862 err = -ENOMEM;
863 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
864 goto err_clr_master;
865 }
a31208b1
MD		 866
867 return 0;
868
869err_clr_master:
870 pci_clear_master(dev->pdev);
871 release_bar(dev->pdev);
872err_disable:
89d44f0a 873 mlx5_pci_disable_device(dev);
a31208b1
MD		 874
875err_dbg:
876 debugfs_remove(priv->dbg_root);
877 return err;
878}
879
880static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
881{
882 iounmap(dev->iseg);
883 pci_clear_master(dev->pdev);
884 release_bar(dev->pdev);
89d44f0a 885 mlx5_pci_disable_device(dev);
a31208b1
MD		 886 debugfs_remove(priv->dbg_root);
887}
888
889#define MLX5_IB_MOD "mlx5_ib"
890static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
891{
892 struct pci_dev *pdev = dev->pdev;
893 int err;
894
89d44f0a
MD		 895 mutex_lock(&dev->intf_state_mutex);
896 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
897 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
898 __func__);
899 goto out;
900 }
901
e126ba97
EC		 902 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
903 fw_rev_min(dev), fw_rev_sub(dev));
904
89d44f0a
MD		 905 /* on load removing any previous indication of internal error, device is
906 * up
907 */
908 dev->state = MLX5_DEVICE_STATE_UP;
909
e126ba97
EC		 910 err = mlx5_cmd_init(dev);
911 if (err) {
912 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 913 goto out_err;
e126ba97
EC		 914 }
915
916 mlx5_pagealloc_init(dev);
cd23b14b
EC		 917
918 err = mlx5_core_enable_hca(dev);
919 if (err) {
920 dev_err(&pdev->dev, "enable hca failed\n");
921 goto err_pagealloc_cleanup;
922 }
923
f62b8bb8
AV		 924#ifdef CONFIG_MLX5_CORE_EN
925 err = mlx5_core_set_issi(dev);
926 if (err) {
927 dev_err(&pdev->dev, "failed to set issi\n");
928 goto err_disable_hca;
929 }
930#endif
931
cd23b14b
EC		 932 err = mlx5_satisfy_startup_pages(dev, 1);
933 if (err) {
934 dev_err(&pdev->dev, "failed to allocate boot pages\n");
935 goto err_disable_hca;
936 }
937
e126ba97
EC		 938 err = set_hca_ctrl(dev);
939 if (err) {
940 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 941 goto reclaim_boot_pages;
e126ba97
EC		 942 }
943
944 err = handle_hca_cap(dev);
945 if (err) {
946 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 947 goto reclaim_boot_pages;
e126ba97
EC		 948 }
949
cd23b14b 950 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 951 if (err) {
cd23b14b
EC		 952 dev_err(&pdev->dev, "failed to allocate init pages\n");
953 goto reclaim_boot_pages;
e126ba97
EC		 954 }
955
956 err = mlx5_pagealloc_start(dev);
957 if (err) {
958 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 959 goto reclaim_boot_pages;
e126ba97
EC		 960 }
961
962 err = mlx5_cmd_init_hca(dev);
963 if (err) {
964 dev_err(&pdev->dev, "init hca failed\n");
965 goto err_pagealloc_stop;
966 }
967
968 mlx5_start_health_poll(dev);
969
938fe83c 970 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 971 if (err) {
972 dev_err(&pdev->dev, "query hca failed\n");
973 goto err_stop_poll;
974 }
975
211e6c80 976 err = mlx5_query_board_id(dev);
e126ba97 977 if (err) {
211e6c80 978 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 979 goto err_stop_poll;
980 }
981
982 err = mlx5_enable_msix(dev);
983 if (err) {
984 dev_err(&pdev->dev, "enable msix failed\n");
985 goto err_stop_poll;
986 }
987
988 err = mlx5_eq_init(dev);
989 if (err) {
990 dev_err(&pdev->dev, "failed to initialize eq\n");
991 goto disable_msix;
992 }
993
994 err = mlx5_alloc_uuars(dev, &priv->uuari);
995 if (err) {
996 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
997 goto err_eq_cleanup;
998 }
999
1000 err = mlx5_start_eqs(dev);
1001 if (err) {
1002 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1003 goto err_free_uar;
1004 }
1005
233d05d2
SM		 1006 err = alloc_comp_eqs(dev);
1007 if (err) {
1008 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1009 goto err_stop_eqs;
1010 }
1011
88a85f99
AS		 1012 if (map_bf_area(dev))
1013 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1014
db058a18
SM		 1015 err = mlx5_irq_set_affinity_hints(dev);
1016 if (err) {
1017 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
88a85f99 1018 goto err_unmap_bf_area;
db058a18
SM		 1019 }
1020
e126ba97
EC		 1021 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1022
1023 mlx5_init_cq_table(dev);
1024 mlx5_init_qp_table(dev);
1025 mlx5_init_srq_table(dev);
3bcdb17a 1026 mlx5_init_mr_table(dev);
e126ba97 1027
a31208b1
MD		 1028 err = mlx5_register_device(dev);
1029 if (err) {
1030 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1031 goto err_reg_dev;
1032 }
1033
1034 err = request_module_nowait(MLX5_IB_MOD);
1035 if (err)
1036 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1037
89d44f0a
MD		 1038 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1039out:
1040 mutex_unlock(&dev->intf_state_mutex);
1041
e126ba97
EC		 1042 return 0;
1043
a31208b1
MD		 1044err_reg_dev:
1045 mlx5_cleanup_mr_table(dev);
1046 mlx5_cleanup_srq_table(dev);
1047 mlx5_cleanup_qp_table(dev);
1048 mlx5_cleanup_cq_table(dev);
1049 mlx5_irq_clear_affinity_hints(dev);
1050
88a85f99
AS		 1051err_unmap_bf_area:
1052 unmap_bf_area(dev);
1053
db058a18
SM		 1054 free_comp_eqs(dev);
1055
233d05d2
SM		 1056err_stop_eqs:
1057 mlx5_stop_eqs(dev);
1058
e126ba97
EC		 1059err_free_uar:
1060 mlx5_free_uuars(dev, &priv->uuari);
1061
1062err_eq_cleanup:
1063 mlx5_eq_cleanup(dev);
1064
1065disable_msix:
1066 mlx5_disable_msix(dev);
1067
1068err_stop_poll:
1069 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1070 if (mlx5_cmd_teardown_hca(dev)) {
1071 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1072 goto out_err;
1bde6e30 1073 }
e126ba97
EC		 1074
1075err_pagealloc_stop:
1076 mlx5_pagealloc_stop(dev);
1077
cd23b14b 1078reclaim_boot_pages:
e126ba97
EC		 1079 mlx5_reclaim_startup_pages(dev);
1080
cd23b14b
EC		 1081err_disable_hca:
1082 mlx5_core_disable_hca(dev);
1083
e126ba97
EC		 1084err_pagealloc_cleanup:
1085 mlx5_pagealloc_cleanup(dev);
1086 mlx5_cmd_cleanup(dev);
1087
89d44f0a
MD		 1088out_err:
1089 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1090 mutex_unlock(&dev->intf_state_mutex);
1091
e126ba97
EC		 1092 return err;
1093}
e126ba97 1094
a31208b1 1095static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1096{
89d44f0a 1097 int err = 0;
e126ba97 1098
89d44f0a
MD		 1099 mutex_lock(&dev->intf_state_mutex);
1100 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1101 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1102 __func__);
1103 goto out;
1104 }
a31208b1
MD		 1105 mlx5_unregister_device(dev);
1106 mlx5_cleanup_mr_table(dev);
e126ba97
EC		 1107 mlx5_cleanup_srq_table(dev);
1108 mlx5_cleanup_qp_table(dev);
1109 mlx5_cleanup_cq_table(dev);
db058a18 1110 mlx5_irq_clear_affinity_hints(dev);
88a85f99 1111 unmap_bf_area(dev);
233d05d2 1112 free_comp_eqs(dev);
e126ba97
EC		 1113 mlx5_stop_eqs(dev);
1114 mlx5_free_uuars(dev, &priv->uuari);
1115 mlx5_eq_cleanup(dev);
1116 mlx5_disable_msix(dev);
1117 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1118 err = mlx5_cmd_teardown_hca(dev);
1119 if (err) {
1bde6e30 1120 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1121 goto out;
1bde6e30 1122 }
e126ba97
EC		 1123 mlx5_pagealloc_stop(dev);
1124 mlx5_reclaim_startup_pages(dev);
cd23b14b 1125 mlx5_core_disable_hca(dev);
e126ba97
EC		 1126 mlx5_pagealloc_cleanup(dev);
1127 mlx5_cmd_cleanup(dev);
9603b61d 1128
ac6ea6e8 1129out:
89d44f0a
MD		 1130 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1131 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1132 return err;
9603b61d 1133}
64613d94 1134
89d44f0a 1135void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
ac6ea6e8 1136 unsigned long param)
9603b61d
JM		 1137{
1138 struct mlx5_priv *priv = &dev->priv;
1139 struct mlx5_device_context *dev_ctx;
1140 unsigned long flags;
1141
1142 spin_lock_irqsave(&priv->ctx_lock, flags);
1143
1144 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1145 if (dev_ctx->intf->event)
4d2f9bbb 1146 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1147
1148 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1149}
1150
1151struct mlx5_core_event_handler {
1152 void (*event)(struct mlx5_core_dev *dev,
1153 enum mlx5_dev_event event,
1154 void *data);
1155};
1156
f66f049f 1157
9603b61d
JM		 1158static int init_one(struct pci_dev *pdev,
1159 const struct pci_device_id *id)
1160{
1161 struct mlx5_core_dev *dev;
1162 struct mlx5_priv *priv;
1163 int err;
1164
1165 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1166 if (!dev) {
1167 dev_err(&pdev->dev, "kzalloc failed\n");
1168 return -ENOMEM;
1169 }
1170 priv = &dev->priv;
1171
1172 pci_set_drvdata(pdev, dev);
1173
1174 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1175 pr_warn("selected profile out of range, selecting default (%d)\n",
1176 MLX5_DEFAULT_PROF);
1177 prof_sel = MLX5_DEFAULT_PROF;
1178 }
1179 dev->profile = &profile[prof_sel];
a31208b1 1180 dev->pdev = pdev;
9603b61d
JM		 1181 dev->event = mlx5_core_event;
1182
364d1798
EC		 1183 INIT_LIST_HEAD(&priv->ctx_list);
1184 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1185 mutex_init(&dev->pci_status_mutex);
1186 mutex_init(&dev->intf_state_mutex);
a31208b1 1187 err = mlx5_pci_init(dev, priv);
9603b61d 1188 if (err) {
a31208b1
MD		 1189 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1190 goto clean_dev;
9603b61d
JM		 1191 }
1192
ac6ea6e8
EC		 1193 err = mlx5_health_init(dev);
1194 if (err) {
1195 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1196 goto close_pci;
1197 }
1198
a31208b1 1199 err = mlx5_load_one(dev, priv);
9603b61d 1200 if (err) {
a31208b1 1201 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1202 goto clean_health;
9603b61d
JM		 1203 }
1204
1205 return 0;
1206
ac6ea6e8
EC		 1207clean_health:
1208 mlx5_health_cleanup(dev);
a31208b1
MD		 1209close_pci:
1210 mlx5_pci_close(dev, priv);
1211clean_dev:
1212 pci_set_drvdata(pdev, NULL);
9603b61d 1213 kfree(dev);
a31208b1 1214
9603b61d
JM		 1215 return err;
1216}
a31208b1 1217
9603b61d
JM		 1218static void remove_one(struct pci_dev *pdev)
1219{
1220 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
a31208b1 1221 struct mlx5_priv *priv = &dev->priv;
9603b61d 1222
a31208b1
MD		 1223 if (mlx5_unload_one(dev, priv)) {
1224 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1225 mlx5_health_cleanup(dev);
a31208b1
MD		 1226 return;
1227 }
ac6ea6e8 1228 mlx5_health_cleanup(dev);
a31208b1
MD		 1229 mlx5_pci_close(dev, priv);
1230 pci_set_drvdata(pdev, NULL);
9603b61d
JM		 1231 kfree(dev);
1232}
1233
89d44f0a
MD		 1234static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1235 pci_channel_state_t state)
1236{
1237 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1238 struct mlx5_priv *priv = &dev->priv;
1239
1240 dev_info(&pdev->dev, "%s was called\n", __func__);
1241 mlx5_enter_error_state(dev);
1242 mlx5_unload_one(dev, priv);
1243 mlx5_pci_disable_device(dev);
1244 return state == pci_channel_io_perm_failure ?
1245 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1246}
1247
1248static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1249{
1250 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1251 int err = 0;
1252
1253 dev_info(&pdev->dev, "%s was called\n", __func__);
1254
1255 err = mlx5_pci_enable_device(dev);
1256 if (err) {
1257 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1258 , __func__, err);
1259 return PCI_ERS_RESULT_DISCONNECT;
1260 }
1261 pci_set_master(pdev);
1262 pci_set_power_state(pdev, PCI_D0);
1263 pci_restore_state(pdev);
1264
1265 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1266}
1267
1268void mlx5_disable_device(struct mlx5_core_dev *dev)
1269{
1270 mlx5_pci_err_detected(dev->pdev, 0);
1271}
1272
1273/* wait for the device to show vital signs. For now we check
1274 * that we can read the device ID and that the health buffer
1275 * shows a non zero value which is different than 0xffffffff
1276 */
1277static void wait_vital(struct pci_dev *pdev)
1278{
1279 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1280 struct mlx5_core_health *health = &dev->priv.health;
1281 const int niter = 100;
1282 u32 count;
1283 u16 did;
1284 int i;
1285
1286 /* Wait for firmware to be ready after reset */
1287 msleep(1000);
1288 for (i = 0; i < niter; i++) {
1289 if (pci_read_config_word(pdev, 2, &did)) {
1290 dev_warn(&pdev->dev, "failed reading config word\n");
1291 break;
1292 }
1293 if (did == pdev->device) {
1294 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1295 break;
1296 }
1297 msleep(50);
1298 }
1299 if (i == niter)
1300 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1301
1302 for (i = 0; i < niter; i++) {
1303 count = ioread32be(health->health_counter);
1304 if (count && count != 0xffffffff) {
1305 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1306 break;
1307 }
1308 msleep(50);
1309 }
1310
1311 if (i == niter)
1312 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1313}
1314
1315static void mlx5_pci_resume(struct pci_dev *pdev)
1316{
1317 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1318 struct mlx5_priv *priv = &dev->priv;
1319 int err;
1320
1321 dev_info(&pdev->dev, "%s was called\n", __func__);
1322
1323 pci_save_state(pdev);
1324 wait_vital(pdev);
1325
1326 err = mlx5_load_one(dev, priv);
1327 if (err)
1328 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1329 , __func__, err);
1330 else
1331 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1332}
1333
1334static const struct pci_error_handlers mlx5_err_handler = {
1335 .error_detected = mlx5_pci_err_detected,
1336 .slot_reset = mlx5_pci_slot_reset,
1337 .resume = mlx5_pci_resume
1338};
1339
9603b61d 1340static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1341 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1342 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1343 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1344 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1345 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1346 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1347 { 0, }
1348};
1349
1350MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1351
1352static struct pci_driver mlx5_core_driver = {
1353 .name = DRIVER_NAME,
1354 .id_table = mlx5_core_pci_table,
1355 .probe = init_one,
89d44f0a
MD		 1356 .remove = remove_one,
1357 .err_handler = &mlx5_err_handler
9603b61d 1358};
e126ba97
EC		 1359
1360static int __init init(void)
1361{
1362 int err;
1363
1364 mlx5_register_debugfs();
e126ba97 1365
9603b61d
JM		 1366 err = pci_register_driver(&mlx5_core_driver);
1367 if (err)
ac6ea6e8 1368 goto err_debug;
9603b61d 1369
f62b8bb8
AV		 1370#ifdef CONFIG_MLX5_CORE_EN
1371 mlx5e_init();
1372#endif
1373
e126ba97
EC		 1374 return 0;
1375
e126ba97
EC		 1376err_debug:
1377 mlx5_unregister_debugfs();
1378 return err;
1379}
1380
1381static void __exit cleanup(void)
1382{
f62b8bb8
AV		 1383#ifdef CONFIG_MLX5_CORE_EN
1384 mlx5e_cleanup();
1385#endif
9603b61d 1386 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1387 mlx5_unregister_debugfs();
1388}
1389
1390module_init(init);
1391module_exit(cleanup);
Linux kernel - Deliverables
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