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Merge tag 'batman-adv-fix-for-davem' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
b775516b 48#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 49#include "mlx5_core.h"
50
e126ba97 51MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 52MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 53MODULE_LICENSE("Dual BSD/GPL");
54MODULE_VERSION(DRIVER_VERSION);
55
56int mlx5_core_debug_mask;
57module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
58MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59
9603b61d
JM		 60#define MLX5_DEFAULT_PROF 2
61static int prof_sel = MLX5_DEFAULT_PROF;
62module_param_named(prof_sel, prof_sel, int, 0444);
63MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64
e126ba97 65struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 66static LIST_HEAD(intf_list);
67static LIST_HEAD(dev_list);
68static DEFINE_MUTEX(intf_mutex);
69
70struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
73 void *context;
74};
75
76static struct mlx5_profile profile[] = {
77 [0] = {
78 .mask = 0,
79 },
80 [1] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
82 .log_max_qp = 12,
83 },
84 [2] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
87 .log_max_qp = 17,
88 .mr_cache[0] = {
89 .size = 500,
90 .limit = 250
91 },
92 .mr_cache[1] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[2] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[3] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[4] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[5] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[6] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[7] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[8] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[9] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[10] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[11] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[12] = {
137 .size = 64,
138 .limit = 32
139 },
140 .mr_cache[13] = {
141 .size = 32,
142 .limit = 16
143 },
144 .mr_cache[14] = {
145 .size = 16,
146 .limit = 8
147 },
148 .mr_cache[15] = {
149 .size = 8,
150 .limit = 4
151 },
152 },
153};
e126ba97
EC		 154
155static int set_dma_caps(struct pci_dev *pdev)
156{
157 int err;
158
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
160 if (err) {
1a91de28 161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
163 if (err) {
1a91de28 164 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 165 return err;
166 }
167 }
168
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
170 if (err) {
171 dev_warn(&pdev->dev,
1a91de28 172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 if (err) {
175 dev_err(&pdev->dev,
1a91de28 176 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 177 return err;
178 }
179 }
180
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
182 return err;
183}
184
185static int request_bar(struct pci_dev *pdev)
186{
187 int err = 0;
188
189 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 190 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 191 return -ENODEV;
192 }
193
194 err = pci_request_regions(pdev, DRIVER_NAME);
195 if (err)
196 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
197
198 return err;
199}
200
201static void release_bar(struct pci_dev *pdev)
202{
203 pci_release_regions(pdev);
204}
205
206static int mlx5_enable_msix(struct mlx5_core_dev *dev)
207{
db058a18
SM		 208 struct mlx5_priv *priv = &dev->priv;
209 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 210 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 211 int nvec;
e126ba97
EC		 212 int i;
213
938fe83c
SM		 214 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
215 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 216 nvec = min_t(int, nvec, num_eqs);
217 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
218 return -ENOMEM;
219
db058a18
SM		 220 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
221
222 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
223 if (!priv->msix_arr || !priv->irq_info)
224 goto err_free_msix;
e126ba97
EC		 225
226 for (i = 0; i < nvec; i++)
db058a18 227 priv->msix_arr[i].entry = i;
e126ba97 228
db058a18 229 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 230 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 231 if (nvec < 0)
232 return nvec;
e126ba97 233
f3c9407b 234 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 235
236 return 0;
db058a18
SM		 237
238err_free_msix:
239 kfree(priv->irq_info);
240 kfree(priv->msix_arr);
241 return -ENOMEM;
e126ba97
EC		 242}
243
244static void mlx5_disable_msix(struct mlx5_core_dev *dev)
245{
db058a18 246 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 247
248 pci_disable_msix(dev->pdev);
db058a18
SM		 249 kfree(priv->irq_info);
250 kfree(priv->msix_arr);
e126ba97
EC		 251}
252
253struct mlx5_reg_host_endianess {
254 u8 he;
255 u8 rsvd[15];
256};
257
87b8de49
EC		 258
259#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
260
261enum {
c7a08ac7
EC		 262 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
263 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 264};
265
c7a08ac7
EC		 266static u16 to_fw_pkey_sz(u32 size)
267{
268 switch (size) {
269 case 128:
270 return 0;
271 case 256:
272 return 1;
273 case 512:
274 return 2;
275 case 1024:
276 return 3;
277 case 2048:
278 return 4;
279 case 4096:
280 return 5;
281 default:
282 pr_warn("invalid pkey table size %d\n", size);
283 return 0;
284 }
285}
286
938fe83c
SM		 287int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
288 enum mlx5_cap_mode cap_mode)
c7a08ac7 289{
b775516b
EC		 290 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
291 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 292 void *out, *hca_caps;
293 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 294 int err;
295
b775516b
EC		 296 memset(in, 0, sizeof(in));
297 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 298 if (!out)
e126ba97 299 return -ENOMEM;
938fe83c 300
b775516b
EC		 301 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
302 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
303 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
304 if (err)
305 goto query_ex;
e126ba97 306
b775516b 307 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 308 if (err) {
938fe83c
SM		 309 mlx5_core_warn(dev,
310 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
311 cap_type, cap_mode, err);
e126ba97
EC		 312 goto query_ex;
313 }
c7a08ac7 314
938fe83c
SM		 315 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
316
317 switch (cap_mode) {
318 case HCA_CAP_OPMOD_GET_MAX:
319 memcpy(dev->hca_caps_max[cap_type], hca_caps,
320 MLX5_UN_SZ_BYTES(hca_cap_union));
321 break;
322 case HCA_CAP_OPMOD_GET_CUR:
323 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
324 MLX5_UN_SZ_BYTES(hca_cap_union));
325 break;
326 default:
327 mlx5_core_warn(dev,
328 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
329 cap_type, cap_mode);
330 err = -EINVAL;
331 break;
332 }
c7a08ac7
EC		 333query_ex:
334 kfree(out);
335 return err;
336}
337
b775516b 338static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 339{
b775516b 340 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 341 int err;
342
b775516b 343 memset(out, 0, sizeof(out));
e126ba97 344
b775516b
EC		 345 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
346 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 347 if (err)
c7a08ac7 348 return err;
e126ba97 349
b775516b 350 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 351
352 return err;
353}
354
355static int handle_hca_cap(struct mlx5_core_dev *dev)
356{
b775516b 357 void *set_ctx = NULL;
c7a08ac7 358 struct mlx5_profile *prof = dev->profile;
c7a08ac7 359 int err = -ENOMEM;
b775516b 360 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 361 void *set_hca_cap;
c7a08ac7 362
b775516b 363 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 364 if (!set_ctx)
e126ba97 365 goto query_ex;
e126ba97 366
938fe83c 367 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 368 if (err)
e126ba97 369 goto query_ex;
e126ba97 370
938fe83c 371 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 372 if (err)
373 goto query_ex;
374
938fe83c
SM		 375 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
376 capability);
377 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
378 MLX5_ST_SZ_BYTES(cmd_hca_cap));
379
380 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 381 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 382 128);
c7a08ac7 383 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 384 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
385 to_fw_pkey_sz(128));
c7a08ac7
EC		 386
387 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 388 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
389 prof->log_max_qp);
c7a08ac7 390
938fe83c
SM		 391 /* disable cmdif checksum */
392 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 393
b775516b 394 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 395
e126ba97 396query_ex:
e126ba97 397 kfree(set_ctx);
e126ba97
EC		 398 return err;
399}
400
401static int set_hca_ctrl(struct mlx5_core_dev *dev)
402{
403 struct mlx5_reg_host_endianess he_in;
404 struct mlx5_reg_host_endianess he_out;
405 int err;
406
407 memset(&he_in, 0, sizeof(he_in));
408 he_in.he = MLX5_SET_HOST_ENDIANNESS;
409 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
410 &he_out, sizeof(he_out),
411 MLX5_REG_HOST_ENDIANNESS, 0, 1);
412 return err;
413}
414
cd23b14b
EC		 415static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
416{
417 int err;
418 struct mlx5_enable_hca_mbox_in in;
419 struct mlx5_enable_hca_mbox_out out;
420
421 memset(&in, 0, sizeof(in));
422 memset(&out, 0, sizeof(out));
423 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
424 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
425 if (err)
426 return err;
427
428 if (out.hdr.status)
429 return mlx5_cmd_status_to_err(&out.hdr);
430
431 return 0;
432}
433
434static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
435{
436 int err;
437 struct mlx5_disable_hca_mbox_in in;
438 struct mlx5_disable_hca_mbox_out out;
439
440 memset(&in, 0, sizeof(in));
441 memset(&out, 0, sizeof(out));
442 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
443 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
444 if (err)
445 return err;
446
447 if (out.hdr.status)
448 return mlx5_cmd_status_to_err(&out.hdr);
449
450 return 0;
451}
452
db058a18
SM		 453static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
454{
455 struct mlx5_priv *priv = &mdev->priv;
456 struct msix_entry *msix = priv->msix_arr;
457 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
458 int numa_node = dev_to_node(&mdev->pdev->dev);
459 int err;
460
461 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
462 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
463 return -ENOMEM;
464 }
465
dda922c8
DM		 466 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
467 priv->irq_info[i].mask);
db058a18
SM		 468
469 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
470 if (err) {
471 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
472 irq);
473 goto err_clear_mask;
474 }
475
476 return 0;
477
478err_clear_mask:
479 free_cpumask_var(priv->irq_info[i].mask);
480 return err;
481}
482
483static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
484{
485 struct mlx5_priv *priv = &mdev->priv;
486 struct msix_entry *msix = priv->msix_arr;
487 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
488
489 irq_set_affinity_hint(irq, NULL);
490 free_cpumask_var(priv->irq_info[i].mask);
491}
492
493static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
494{
495 int err;
496 int i;
497
498 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
499 err = mlx5_irq_set_affinity_hint(mdev, i);
500 if (err)
501 goto err_out;
502 }
503
504 return 0;
505
506err_out:
507 for (i--; i >= 0; i--)
508 mlx5_irq_clear_affinity_hint(mdev, i);
509
510 return err;
511}
512
513static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
514{
515 int i;
516
517 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
518 mlx5_irq_clear_affinity_hint(mdev, i);
519}
520
233d05d2
SM		 521int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
522{
523 struct mlx5_eq_table *table = &dev->priv.eq_table;
524 struct mlx5_eq *eq, *n;
525 int err = -ENOENT;
526
527 spin_lock(&table->lock);
528 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
529 if (eq->index == vector) {
530 *eqn = eq->eqn;
531 *irqn = eq->irqn;
532 err = 0;
533 break;
534 }
535 }
536 spin_unlock(&table->lock);
537
538 return err;
539}
540EXPORT_SYMBOL(mlx5_vector2eqn);
541
542static void free_comp_eqs(struct mlx5_core_dev *dev)
543{
544 struct mlx5_eq_table *table = &dev->priv.eq_table;
545 struct mlx5_eq *eq, *n;
546
547 spin_lock(&table->lock);
548 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
549 list_del(&eq->list);
550 spin_unlock(&table->lock);
551 if (mlx5_destroy_unmap_eq(dev, eq))
552 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
553 eq->eqn);
554 kfree(eq);
555 spin_lock(&table->lock);
556 }
557 spin_unlock(&table->lock);
558}
559
560static int alloc_comp_eqs(struct mlx5_core_dev *dev)
561{
562 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 563 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 564 struct mlx5_eq *eq;
565 int ncomp_vec;
566 int nent;
567 int err;
568 int i;
569
570 INIT_LIST_HEAD(&table->comp_eqs_list);
571 ncomp_vec = table->num_comp_vectors;
572 nent = MLX5_COMP_EQ_SIZE;
573 for (i = 0; i < ncomp_vec; i++) {
574 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
575 if (!eq) {
576 err = -ENOMEM;
577 goto clean;
578 }
579
db058a18 580 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 581 err = mlx5_create_map_eq(dev, eq,
582 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
583 name, &dev->priv.uuari.uars[0]);
584 if (err) {
585 kfree(eq);
586 goto clean;
587 }
588 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
589 eq->index = i;
590 spin_lock(&table->lock);
591 list_add_tail(&eq->list, &table->comp_eqs_list);
592 spin_unlock(&table->lock);
593 }
594
595 return 0;
596
597clean:
598 free_comp_eqs(dev);
599 return err;
600}
601
f62b8bb8
AV		 602#ifdef CONFIG_MLX5_CORE_EN
603static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
604{
605 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
606 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
607 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
608 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
609 int err;
610 u32 sup_issi;
611
612 memset(query_in, 0, sizeof(query_in));
613 memset(query_out, 0, sizeof(query_out));
614
615 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
616
617 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
618 query_out, sizeof(query_out));
619 if (err) {
620 if (((struct mlx5_outbox_hdr *)query_out)->status ==
621 MLX5_CMD_STAT_BAD_OP_ERR) {
622 pr_debug("Only ISSI 0 is supported\n");
623 return 0;
624 }
625
626 pr_err("failed to query ISSI\n");
627 return err;
628 }
629
630 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
631
632 if (sup_issi & (1 << 1)) {
633 memset(set_in, 0, sizeof(set_in));
634 memset(set_out, 0, sizeof(set_out));
635
636 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
637 MLX5_SET(set_issi_in, set_in, current_issi, 1);
638
639 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
640 set_out, sizeof(set_out));
641 if (err) {
642 pr_err("failed to set ISSI=1\n");
643 return err;
644 }
645
646 dev->issi = 1;
647
648 return 0;
e74a1db0 649 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 650 return 0;
651 }
652
653 return -ENOTSUPP;
654}
655#endif
656
9603b61d 657static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 658{
659 struct mlx5_priv *priv = &dev->priv;
660 int err;
661
662 dev->pdev = pdev;
663 pci_set_drvdata(dev->pdev, dev);
664 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
665 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
666
667 mutex_init(&priv->pgdir_mutex);
668 INIT_LIST_HEAD(&priv->pgdir_list);
669 spin_lock_init(&priv->mkey_lock);
670
671 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
672 if (!priv->dbg_root)
673 return -ENOMEM;
674
675 err = pci_enable_device(pdev);
676 if (err) {
1a91de28 677 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 678 goto err_dbg;
679 }
680
681 err = request_bar(pdev);
682 if (err) {
1a91de28 683 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 684 goto err_disable;
685 }
686
687 pci_set_master(pdev);
688
689 err = set_dma_caps(pdev);
690 if (err) {
691 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
692 goto err_clr_master;
693 }
694
695 dev->iseg_base = pci_resource_start(dev->pdev, 0);
696 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
697 if (!dev->iseg) {
698 err = -ENOMEM;
699 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
700 goto err_clr_master;
701 }
702 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
703 fw_rev_min(dev), fw_rev_sub(dev));
704
705 err = mlx5_cmd_init(dev);
706 if (err) {
707 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
708 goto err_unmap;
709 }
710
711 mlx5_pagealloc_init(dev);
cd23b14b
EC		 712
713 err = mlx5_core_enable_hca(dev);
714 if (err) {
715 dev_err(&pdev->dev, "enable hca failed\n");
716 goto err_pagealloc_cleanup;
717 }
718
f62b8bb8
AV		 719#ifdef CONFIG_MLX5_CORE_EN
720 err = mlx5_core_set_issi(dev);
721 if (err) {
722 dev_err(&pdev->dev, "failed to set issi\n");
723 goto err_disable_hca;
724 }
725#endif
726
cd23b14b
EC		 727 err = mlx5_satisfy_startup_pages(dev, 1);
728 if (err) {
729 dev_err(&pdev->dev, "failed to allocate boot pages\n");
730 goto err_disable_hca;
731 }
732
e126ba97
EC		 733 err = set_hca_ctrl(dev);
734 if (err) {
735 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 736 goto reclaim_boot_pages;
e126ba97
EC		 737 }
738
739 err = handle_hca_cap(dev);
740 if (err) {
741 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 742 goto reclaim_boot_pages;
e126ba97
EC		 743 }
744
cd23b14b 745 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 746 if (err) {
cd23b14b
EC		 747 dev_err(&pdev->dev, "failed to allocate init pages\n");
748 goto reclaim_boot_pages;
e126ba97
EC		 749 }
750
751 err = mlx5_pagealloc_start(dev);
752 if (err) {
753 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 754 goto reclaim_boot_pages;
e126ba97
EC		 755 }
756
757 err = mlx5_cmd_init_hca(dev);
758 if (err) {
759 dev_err(&pdev->dev, "init hca failed\n");
760 goto err_pagealloc_stop;
761 }
762
763 mlx5_start_health_poll(dev);
764
938fe83c 765 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 766 if (err) {
767 dev_err(&pdev->dev, "query hca failed\n");
768 goto err_stop_poll;
769 }
770
211e6c80 771 err = mlx5_query_board_id(dev);
e126ba97 772 if (err) {
211e6c80 773 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 774 goto err_stop_poll;
775 }
776
777 err = mlx5_enable_msix(dev);
778 if (err) {
779 dev_err(&pdev->dev, "enable msix failed\n");
780 goto err_stop_poll;
781 }
782
783 err = mlx5_eq_init(dev);
784 if (err) {
785 dev_err(&pdev->dev, "failed to initialize eq\n");
786 goto disable_msix;
787 }
788
789 err = mlx5_alloc_uuars(dev, &priv->uuari);
790 if (err) {
791 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
792 goto err_eq_cleanup;
793 }
794
795 err = mlx5_start_eqs(dev);
796 if (err) {
797 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
798 goto err_free_uar;
799 }
800
233d05d2
SM		 801 err = alloc_comp_eqs(dev);
802 if (err) {
803 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
804 goto err_stop_eqs;
805 }
806
db058a18
SM		 807 err = mlx5_irq_set_affinity_hints(dev);
808 if (err) {
809 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
810 goto err_free_comp_eqs;
811 }
812
e126ba97
EC		 813 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
814
815 mlx5_init_cq_table(dev);
816 mlx5_init_qp_table(dev);
817 mlx5_init_srq_table(dev);
3bcdb17a 818 mlx5_init_mr_table(dev);
e126ba97
EC		 819
820 return 0;
821
db058a18
SM		 822err_free_comp_eqs:
823 free_comp_eqs(dev);
824
233d05d2
SM		 825err_stop_eqs:
826 mlx5_stop_eqs(dev);
827
e126ba97
EC		 828err_free_uar:
829 mlx5_free_uuars(dev, &priv->uuari);
830
831err_eq_cleanup:
832 mlx5_eq_cleanup(dev);
833
834disable_msix:
835 mlx5_disable_msix(dev);
836
837err_stop_poll:
838 mlx5_stop_health_poll(dev);
1bde6e30
EC		 839 if (mlx5_cmd_teardown_hca(dev)) {
840 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
841 return err;
842 }
e126ba97
EC		 843
844err_pagealloc_stop:
845 mlx5_pagealloc_stop(dev);
846
cd23b14b 847reclaim_boot_pages:
e126ba97
EC		 848 mlx5_reclaim_startup_pages(dev);
849
cd23b14b
EC		 850err_disable_hca:
851 mlx5_core_disable_hca(dev);
852
e126ba97
EC		 853err_pagealloc_cleanup:
854 mlx5_pagealloc_cleanup(dev);
855 mlx5_cmd_cleanup(dev);
856
857err_unmap:
858 iounmap(dev->iseg);
859
860err_clr_master:
861 pci_clear_master(dev->pdev);
862 release_bar(dev->pdev);
863
864err_disable:
865 pci_disable_device(dev->pdev);
866
867err_dbg:
868 debugfs_remove(priv->dbg_root);
869 return err;
870}
e126ba97 871
9603b61d 872static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 873{
874 struct mlx5_priv *priv = &dev->priv;
875
876 mlx5_cleanup_srq_table(dev);
877 mlx5_cleanup_qp_table(dev);
878 mlx5_cleanup_cq_table(dev);
db058a18 879 mlx5_irq_clear_affinity_hints(dev);
233d05d2 880 free_comp_eqs(dev);
e126ba97
EC		 881 mlx5_stop_eqs(dev);
882 mlx5_free_uuars(dev, &priv->uuari);
883 mlx5_eq_cleanup(dev);
884 mlx5_disable_msix(dev);
885 mlx5_stop_health_poll(dev);
1bde6e30
EC		 886 if (mlx5_cmd_teardown_hca(dev)) {
887 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
888 return;
889 }
e126ba97
EC		 890 mlx5_pagealloc_stop(dev);
891 mlx5_reclaim_startup_pages(dev);
cd23b14b 892 mlx5_core_disable_hca(dev);
e126ba97
EC		 893 mlx5_pagealloc_cleanup(dev);
894 mlx5_cmd_cleanup(dev);
895 iounmap(dev->iseg);
896 pci_clear_master(dev->pdev);
897 release_bar(dev->pdev);
898 pci_disable_device(dev->pdev);
899 debugfs_remove(priv->dbg_root);
900}
9603b61d
JM		 901
902static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
903{
904 struct mlx5_device_context *dev_ctx;
905 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
906
907 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
908 if (!dev_ctx) {
909 pr_warn("mlx5_add_device: alloc context failed\n");
910 return;
911 }
912
913 dev_ctx->intf = intf;
914 dev_ctx->context = intf->add(dev);
915
916 if (dev_ctx->context) {
917 spin_lock_irq(&priv->ctx_lock);
918 list_add_tail(&dev_ctx->list, &priv->ctx_list);
919 spin_unlock_irq(&priv->ctx_lock);
920 } else {
921 kfree(dev_ctx);
922 }
923}
924
925static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
926{
927 struct mlx5_device_context *dev_ctx;
928 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
929
930 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
931 if (dev_ctx->intf == intf) {
932 spin_lock_irq(&priv->ctx_lock);
933 list_del(&dev_ctx->list);
934 spin_unlock_irq(&priv->ctx_lock);
935
936 intf->remove(dev, dev_ctx->context);
937 kfree(dev_ctx);
938 return;
939 }
940}
941static int mlx5_register_device(struct mlx5_core_dev *dev)
942{
943 struct mlx5_priv *priv = &dev->priv;
944 struct mlx5_interface *intf;
945
946 mutex_lock(&intf_mutex);
947 list_add_tail(&priv->dev_list, &dev_list);
948 list_for_each_entry(intf, &intf_list, list)
949 mlx5_add_device(intf, priv);
950 mutex_unlock(&intf_mutex);
951
952 return 0;
953}
954static void mlx5_unregister_device(struct mlx5_core_dev *dev)
955{
956 struct mlx5_priv *priv = &dev->priv;
957 struct mlx5_interface *intf;
958
959 mutex_lock(&intf_mutex);
960 list_for_each_entry(intf, &intf_list, list)
961 mlx5_remove_device(intf, priv);
962 list_del(&priv->dev_list);
963 mutex_unlock(&intf_mutex);
964}
965
966int mlx5_register_interface(struct mlx5_interface *intf)
967{
968 struct mlx5_priv *priv;
969
970 if (!intf->add || !intf->remove)
971 return -EINVAL;
972
973 mutex_lock(&intf_mutex);
974 list_add_tail(&intf->list, &intf_list);
975 list_for_each_entry(priv, &dev_list, dev_list)
976 mlx5_add_device(intf, priv);
977 mutex_unlock(&intf_mutex);
978
979 return 0;
980}
981EXPORT_SYMBOL(mlx5_register_interface);
982
983void mlx5_unregister_interface(struct mlx5_interface *intf)
984{
985 struct mlx5_priv *priv;
986
987 mutex_lock(&intf_mutex);
988 list_for_each_entry(priv, &dev_list, dev_list)
989 mlx5_remove_device(intf, priv);
990 list_del(&intf->list);
991 mutex_unlock(&intf_mutex);
992}
993EXPORT_SYMBOL(mlx5_unregister_interface);
994
64613d94
SM		 995void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
996{
997 struct mlx5_priv *priv = &mdev->priv;
998 struct mlx5_device_context *dev_ctx;
999 unsigned long flags;
1000 void *result = NULL;
1001
1002 spin_lock_irqsave(&priv->ctx_lock, flags);
1003
1004 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
1005 if ((dev_ctx->intf->protocol == protocol) &&
1006 dev_ctx->intf->get_dev) {
1007 result = dev_ctx->intf->get_dev(dev_ctx->context);
1008 break;
1009 }
1010
1011 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1012
1013 return result;
1014}
1015EXPORT_SYMBOL(mlx5_get_protocol_dev);
1016
9603b61d 1017static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 1018 unsigned long param)
9603b61d
JM		 1019{
1020 struct mlx5_priv *priv = &dev->priv;
1021 struct mlx5_device_context *dev_ctx;
1022 unsigned long flags;
1023
1024 spin_lock_irqsave(&priv->ctx_lock, flags);
1025
1026 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1027 if (dev_ctx->intf->event)
4d2f9bbb 1028 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1029
1030 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1031}
1032
1033struct mlx5_core_event_handler {
1034 void (*event)(struct mlx5_core_dev *dev,
1035 enum mlx5_dev_event event,
1036 void *data);
1037};
1038
f66f049f
EC		 1039#define MLX5_IB_MOD "mlx5_ib"
1040
9603b61d
JM		 1041static int init_one(struct pci_dev *pdev,
1042 const struct pci_device_id *id)
1043{
1044 struct mlx5_core_dev *dev;
1045 struct mlx5_priv *priv;
1046 int err;
1047
1048 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1049 if (!dev) {
1050 dev_err(&pdev->dev, "kzalloc failed\n");
1051 return -ENOMEM;
1052 }
1053 priv = &dev->priv;
1054
1055 pci_set_drvdata(pdev, dev);
1056
1057 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1058 pr_warn("selected profile out of range, selecting default (%d)\n",
1059 MLX5_DEFAULT_PROF);
1060 prof_sel = MLX5_DEFAULT_PROF;
1061 }
1062 dev->profile = &profile[prof_sel];
1063 dev->event = mlx5_core_event;
1064
364d1798
EC		 1065 INIT_LIST_HEAD(&priv->ctx_list);
1066 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 1067 err = mlx5_dev_init(dev, pdev);
1068 if (err) {
1069 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1070 goto out;
1071 }
1072
9603b61d
JM		 1073 err = mlx5_register_device(dev);
1074 if (err) {
1075 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1076 goto out_init;
1077 }
1078
f66f049f
EC		 1079 err = request_module_nowait(MLX5_IB_MOD);
1080 if (err)
1081 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1082
9603b61d
JM		 1083 return 0;
1084
1085out_init:
1086 mlx5_dev_cleanup(dev);
1087out:
1088 kfree(dev);
1089 return err;
1090}
1091static void remove_one(struct pci_dev *pdev)
1092{
1093 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1094
1095 mlx5_unregister_device(dev);
1096 mlx5_dev_cleanup(dev);
1097 kfree(dev);
1098}
1099
1100static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1101 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1102 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1103 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1104 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1105 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1106 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1107 { 0, }
1108};
1109
1110MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1111
1112static struct pci_driver mlx5_core_driver = {
1113 .name = DRIVER_NAME,
1114 .id_table = mlx5_core_pci_table,
1115 .probe = init_one,
1116 .remove = remove_one
1117};
e126ba97
EC		 1118
1119static int __init init(void)
1120{
1121 int err;
1122
1123 mlx5_register_debugfs();
1124 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1125 if (!mlx5_core_wq) {
1126 err = -ENOMEM;
1127 goto err_debug;
1128 }
1129 mlx5_health_init();
1130
9603b61d
JM		 1131 err = pci_register_driver(&mlx5_core_driver);
1132 if (err)
1133 goto err_health;
1134
f62b8bb8
AV		 1135#ifdef CONFIG_MLX5_CORE_EN
1136 mlx5e_init();
1137#endif
1138
e126ba97
EC		 1139 return 0;
1140
9603b61d
JM		 1141err_health:
1142 mlx5_health_cleanup();
1143 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 1144err_debug:
1145 mlx5_unregister_debugfs();
1146 return err;
1147}
1148
1149static void __exit cleanup(void)
1150{
f62b8bb8
AV		 1151#ifdef CONFIG_MLX5_CORE_EN
1152 mlx5e_cleanup();
1153#endif
9603b61d 1154 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1155 mlx5_health_cleanup();
1156 destroy_workqueue(mlx5_core_wq);
1157 mlx5_unregister_debugfs();
1158}
1159
1160module_init(init);
1161module_exit(cleanup);
Linux kernel - Deliverables
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