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e126ba97 EC |
1 | /* |
2 | * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <asm-generic/kmap_types.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
41 | #include <linux/mlx5/driver.h> | |
42 | #include <linux/mlx5/cq.h> | |
43 | #include <linux/mlx5/qp.h> | |
44 | #include <linux/mlx5/srq.h> | |
45 | #include <linux/debugfs.h> | |
46 | #include "mlx5_core.h" | |
47 | ||
48 | #define DRIVER_NAME "mlx5_core" | |
49 | #define DRIVER_VERSION "1.0" | |
50 | #define DRIVER_RELDATE "June 2013" | |
51 | ||
52 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); | |
53 | MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library"); | |
54 | MODULE_LICENSE("Dual BSD/GPL"); | |
55 | MODULE_VERSION(DRIVER_VERSION); | |
56 | ||
57 | int mlx5_core_debug_mask; | |
58 | module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644); | |
59 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); | |
60 | ||
61 | struct workqueue_struct *mlx5_core_wq; | |
62 | ||
63 | static int set_dma_caps(struct pci_dev *pdev) | |
64 | { | |
65 | int err; | |
66 | ||
67 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
68 | if (err) { | |
69 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); | |
70 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
71 | if (err) { | |
72 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); | |
73 | return err; | |
74 | } | |
75 | } | |
76 | ||
77 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
78 | if (err) { | |
79 | dev_warn(&pdev->dev, | |
80 | "Warning: couldn't set 64-bit consistent PCI DMA mask.\n"); | |
81 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
82 | if (err) { | |
83 | dev_err(&pdev->dev, | |
84 | "Can't set consistent PCI DMA mask, aborting.\n"); | |
85 | return err; | |
86 | } | |
87 | } | |
88 | ||
89 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
90 | return err; | |
91 | } | |
92 | ||
93 | static int request_bar(struct pci_dev *pdev) | |
94 | { | |
95 | int err = 0; | |
96 | ||
97 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
98 | dev_err(&pdev->dev, "Missing registers BAR, aborting.\n"); | |
99 | return -ENODEV; | |
100 | } | |
101 | ||
102 | err = pci_request_regions(pdev, DRIVER_NAME); | |
103 | if (err) | |
104 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
105 | ||
106 | return err; | |
107 | } | |
108 | ||
109 | static void release_bar(struct pci_dev *pdev) | |
110 | { | |
111 | pci_release_regions(pdev); | |
112 | } | |
113 | ||
114 | static int mlx5_enable_msix(struct mlx5_core_dev *dev) | |
115 | { | |
116 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
117 | int num_eqs = 1 << dev->caps.log_max_eq; | |
118 | int nvec; | |
119 | int err; | |
120 | int i; | |
121 | ||
122 | nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE; | |
123 | nvec = min_t(int, nvec, num_eqs); | |
124 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
125 | return -ENOMEM; | |
126 | ||
127 | table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL); | |
128 | if (!table->msix_arr) | |
129 | return -ENOMEM; | |
130 | ||
131 | for (i = 0; i < nvec; i++) | |
132 | table->msix_arr[i].entry = i; | |
133 | ||
134 | retry: | |
135 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; | |
136 | err = pci_enable_msix(dev->pdev, table->msix_arr, nvec); | |
137 | if (err <= 0) { | |
138 | return err; | |
139 | } else if (err > 2) { | |
140 | nvec = err; | |
141 | goto retry; | |
142 | } | |
143 | ||
144 | mlx5_core_dbg(dev, "received %d MSI vectors out of %d requested\n", err, nvec); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static void mlx5_disable_msix(struct mlx5_core_dev *dev) | |
150 | { | |
151 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
152 | ||
153 | pci_disable_msix(dev->pdev); | |
154 | kfree(table->msix_arr); | |
155 | } | |
156 | ||
157 | struct mlx5_reg_host_endianess { | |
158 | u8 he; | |
159 | u8 rsvd[15]; | |
160 | }; | |
161 | ||
87b8de49 EC |
162 | |
163 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) | |
164 | ||
165 | enum { | |
166 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | | |
167 | CAP_MASK(MLX5_CAP_OFF_DCT, 1), | |
168 | }; | |
169 | ||
170 | /* selectively copy writable fields clearing any reserved area | |
171 | */ | |
172 | static void copy_rw_fields(struct mlx5_hca_cap *to, struct mlx5_hca_cap *from) | |
173 | { | |
174 | u64 v64; | |
175 | ||
176 | to->log_max_qp = from->log_max_qp & 0x1f; | |
177 | to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f; | |
178 | to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f; | |
179 | to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f; | |
180 | to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f; | |
181 | to->log_max_atomic_size_qp = from->log_max_atomic_size_qp; | |
182 | to->log_max_atomic_size_dc = from->log_max_atomic_size_dc; | |
183 | v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK; | |
184 | to->flags = cpu_to_be64(v64); | |
185 | } | |
186 | ||
187 | enum { | |
188 | HCA_CAP_OPMOD_GET_MAX = 0, | |
189 | HCA_CAP_OPMOD_GET_CUR = 1, | |
190 | }; | |
191 | ||
e126ba97 EC |
192 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
193 | { | |
194 | struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL; | |
195 | struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL; | |
196 | struct mlx5_cmd_query_hca_cap_mbox_in query_ctx; | |
197 | struct mlx5_cmd_set_hca_cap_mbox_out set_out; | |
e126ba97 | 198 | u64 flags; |
e126ba97 EC |
199 | int err; |
200 | ||
201 | memset(&query_ctx, 0, sizeof(query_ctx)); | |
202 | query_out = kzalloc(sizeof(*query_out), GFP_KERNEL); | |
203 | if (!query_out) | |
204 | return -ENOMEM; | |
205 | ||
206 | set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL); | |
207 | if (!set_ctx) { | |
208 | err = -ENOMEM; | |
209 | goto query_ex; | |
210 | } | |
211 | ||
212 | query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP); | |
87b8de49 | 213 | query_ctx.hdr.opmod = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR); |
e126ba97 EC |
214 | err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx), |
215 | query_out, sizeof(*query_out)); | |
216 | if (err) | |
217 | goto query_ex; | |
218 | ||
219 | err = mlx5_cmd_status_to_err(&query_out->hdr); | |
220 | if (err) { | |
221 | mlx5_core_warn(dev, "query hca cap failed, %d\n", err); | |
222 | goto query_ex; | |
223 | } | |
224 | ||
87b8de49 | 225 | copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap); |
e126ba97 | 226 | |
e126ba97 EC |
227 | if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE) |
228 | set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp; | |
229 | ||
c1868b82 EC |
230 | flags = be64_to_cpu(query_out->hca_cap.flags); |
231 | /* disable checksum */ | |
232 | flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM; | |
233 | ||
234 | set_ctx->hca_cap.flags = cpu_to_be64(flags); | |
e126ba97 | 235 | memset(&set_out, 0, sizeof(set_out)); |
288dde9f | 236 | set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12); |
e126ba97 EC |
237 | set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP); |
238 | err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx), | |
239 | &set_out, sizeof(set_out)); | |
240 | if (err) { | |
241 | mlx5_core_warn(dev, "set hca cap failed, %d\n", err); | |
242 | goto query_ex; | |
243 | } | |
244 | ||
245 | err = mlx5_cmd_status_to_err(&set_out.hdr); | |
246 | if (err) | |
247 | goto query_ex; | |
248 | ||
e126ba97 EC |
249 | query_ex: |
250 | kfree(query_out); | |
251 | kfree(set_ctx); | |
252 | ||
253 | return err; | |
254 | } | |
255 | ||
256 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
257 | { | |
258 | struct mlx5_reg_host_endianess he_in; | |
259 | struct mlx5_reg_host_endianess he_out; | |
260 | int err; | |
261 | ||
262 | memset(&he_in, 0, sizeof(he_in)); | |
263 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
264 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
265 | &he_out, sizeof(he_out), | |
266 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
267 | return err; | |
268 | } | |
269 | ||
cd23b14b EC |
270 | static int mlx5_core_enable_hca(struct mlx5_core_dev *dev) |
271 | { | |
272 | int err; | |
273 | struct mlx5_enable_hca_mbox_in in; | |
274 | struct mlx5_enable_hca_mbox_out out; | |
275 | ||
276 | memset(&in, 0, sizeof(in)); | |
277 | memset(&out, 0, sizeof(out)); | |
278 | in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA); | |
279 | err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); | |
280 | if (err) | |
281 | return err; | |
282 | ||
283 | if (out.hdr.status) | |
284 | return mlx5_cmd_status_to_err(&out.hdr); | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
289 | static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) | |
290 | { | |
291 | int err; | |
292 | struct mlx5_disable_hca_mbox_in in; | |
293 | struct mlx5_disable_hca_mbox_out out; | |
294 | ||
295 | memset(&in, 0, sizeof(in)); | |
296 | memset(&out, 0, sizeof(out)); | |
297 | in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA); | |
298 | err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); | |
299 | if (err) | |
300 | return err; | |
301 | ||
302 | if (out.hdr.status) | |
303 | return mlx5_cmd_status_to_err(&out.hdr); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
e126ba97 EC |
308 | int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev) |
309 | { | |
310 | struct mlx5_priv *priv = &dev->priv; | |
311 | int err; | |
312 | ||
313 | dev->pdev = pdev; | |
314 | pci_set_drvdata(dev->pdev, dev); | |
315 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
316 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
317 | ||
318 | mutex_init(&priv->pgdir_mutex); | |
319 | INIT_LIST_HEAD(&priv->pgdir_list); | |
320 | spin_lock_init(&priv->mkey_lock); | |
321 | ||
322 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); | |
323 | if (!priv->dbg_root) | |
324 | return -ENOMEM; | |
325 | ||
326 | err = pci_enable_device(pdev); | |
327 | if (err) { | |
328 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n"); | |
329 | goto err_dbg; | |
330 | } | |
331 | ||
332 | err = request_bar(pdev); | |
333 | if (err) { | |
334 | dev_err(&pdev->dev, "error requesting BARs, aborting.\n"); | |
335 | goto err_disable; | |
336 | } | |
337 | ||
338 | pci_set_master(pdev); | |
339 | ||
340 | err = set_dma_caps(pdev); | |
341 | if (err) { | |
342 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
343 | goto err_clr_master; | |
344 | } | |
345 | ||
346 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
347 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
348 | if (!dev->iseg) { | |
349 | err = -ENOMEM; | |
350 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
351 | goto err_clr_master; | |
352 | } | |
353 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), | |
354 | fw_rev_min(dev), fw_rev_sub(dev)); | |
355 | ||
356 | err = mlx5_cmd_init(dev); | |
357 | if (err) { | |
358 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
359 | goto err_unmap; | |
360 | } | |
361 | ||
362 | mlx5_pagealloc_init(dev); | |
cd23b14b EC |
363 | |
364 | err = mlx5_core_enable_hca(dev); | |
365 | if (err) { | |
366 | dev_err(&pdev->dev, "enable hca failed\n"); | |
367 | goto err_pagealloc_cleanup; | |
368 | } | |
369 | ||
370 | err = mlx5_satisfy_startup_pages(dev, 1); | |
371 | if (err) { | |
372 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
373 | goto err_disable_hca; | |
374 | } | |
375 | ||
e126ba97 EC |
376 | err = set_hca_ctrl(dev); |
377 | if (err) { | |
378 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 379 | goto reclaim_boot_pages; |
e126ba97 EC |
380 | } |
381 | ||
382 | err = handle_hca_cap(dev); | |
383 | if (err) { | |
384 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 385 | goto reclaim_boot_pages; |
e126ba97 EC |
386 | } |
387 | ||
cd23b14b | 388 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 389 | if (err) { |
cd23b14b EC |
390 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
391 | goto reclaim_boot_pages; | |
e126ba97 EC |
392 | } |
393 | ||
394 | err = mlx5_pagealloc_start(dev); | |
395 | if (err) { | |
396 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 397 | goto reclaim_boot_pages; |
e126ba97 EC |
398 | } |
399 | ||
400 | err = mlx5_cmd_init_hca(dev); | |
401 | if (err) { | |
402 | dev_err(&pdev->dev, "init hca failed\n"); | |
403 | goto err_pagealloc_stop; | |
404 | } | |
405 | ||
406 | mlx5_start_health_poll(dev); | |
407 | ||
408 | err = mlx5_cmd_query_hca_cap(dev, &dev->caps); | |
409 | if (err) { | |
410 | dev_err(&pdev->dev, "query hca failed\n"); | |
411 | goto err_stop_poll; | |
412 | } | |
413 | ||
414 | err = mlx5_cmd_query_adapter(dev); | |
415 | if (err) { | |
416 | dev_err(&pdev->dev, "query adapter failed\n"); | |
417 | goto err_stop_poll; | |
418 | } | |
419 | ||
420 | err = mlx5_enable_msix(dev); | |
421 | if (err) { | |
422 | dev_err(&pdev->dev, "enable msix failed\n"); | |
423 | goto err_stop_poll; | |
424 | } | |
425 | ||
426 | err = mlx5_eq_init(dev); | |
427 | if (err) { | |
428 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
429 | goto disable_msix; | |
430 | } | |
431 | ||
432 | err = mlx5_alloc_uuars(dev, &priv->uuari); | |
433 | if (err) { | |
434 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); | |
435 | goto err_eq_cleanup; | |
436 | } | |
437 | ||
438 | err = mlx5_start_eqs(dev); | |
439 | if (err) { | |
440 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
441 | goto err_free_uar; | |
442 | } | |
443 | ||
444 | MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); | |
445 | ||
446 | mlx5_init_cq_table(dev); | |
447 | mlx5_init_qp_table(dev); | |
448 | mlx5_init_srq_table(dev); | |
449 | ||
450 | return 0; | |
451 | ||
452 | err_free_uar: | |
453 | mlx5_free_uuars(dev, &priv->uuari); | |
454 | ||
455 | err_eq_cleanup: | |
456 | mlx5_eq_cleanup(dev); | |
457 | ||
458 | disable_msix: | |
459 | mlx5_disable_msix(dev); | |
460 | ||
461 | err_stop_poll: | |
462 | mlx5_stop_health_poll(dev); | |
463 | mlx5_cmd_teardown_hca(dev); | |
464 | ||
465 | err_pagealloc_stop: | |
466 | mlx5_pagealloc_stop(dev); | |
467 | ||
cd23b14b | 468 | reclaim_boot_pages: |
e126ba97 EC |
469 | mlx5_reclaim_startup_pages(dev); |
470 | ||
cd23b14b EC |
471 | err_disable_hca: |
472 | mlx5_core_disable_hca(dev); | |
473 | ||
e126ba97 EC |
474 | err_pagealloc_cleanup: |
475 | mlx5_pagealloc_cleanup(dev); | |
476 | mlx5_cmd_cleanup(dev); | |
477 | ||
478 | err_unmap: | |
479 | iounmap(dev->iseg); | |
480 | ||
481 | err_clr_master: | |
482 | pci_clear_master(dev->pdev); | |
483 | release_bar(dev->pdev); | |
484 | ||
485 | err_disable: | |
486 | pci_disable_device(dev->pdev); | |
487 | ||
488 | err_dbg: | |
489 | debugfs_remove(priv->dbg_root); | |
490 | return err; | |
491 | } | |
492 | EXPORT_SYMBOL(mlx5_dev_init); | |
493 | ||
494 | void mlx5_dev_cleanup(struct mlx5_core_dev *dev) | |
495 | { | |
496 | struct mlx5_priv *priv = &dev->priv; | |
497 | ||
498 | mlx5_cleanup_srq_table(dev); | |
499 | mlx5_cleanup_qp_table(dev); | |
500 | mlx5_cleanup_cq_table(dev); | |
501 | mlx5_stop_eqs(dev); | |
502 | mlx5_free_uuars(dev, &priv->uuari); | |
503 | mlx5_eq_cleanup(dev); | |
504 | mlx5_disable_msix(dev); | |
505 | mlx5_stop_health_poll(dev); | |
506 | mlx5_cmd_teardown_hca(dev); | |
507 | mlx5_pagealloc_stop(dev); | |
508 | mlx5_reclaim_startup_pages(dev); | |
cd23b14b | 509 | mlx5_core_disable_hca(dev); |
e126ba97 EC |
510 | mlx5_pagealloc_cleanup(dev); |
511 | mlx5_cmd_cleanup(dev); | |
512 | iounmap(dev->iseg); | |
513 | pci_clear_master(dev->pdev); | |
514 | release_bar(dev->pdev); | |
515 | pci_disable_device(dev->pdev); | |
516 | debugfs_remove(priv->dbg_root); | |
517 | } | |
518 | EXPORT_SYMBOL(mlx5_dev_cleanup); | |
519 | ||
520 | static int __init init(void) | |
521 | { | |
522 | int err; | |
523 | ||
524 | mlx5_register_debugfs(); | |
525 | mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq"); | |
526 | if (!mlx5_core_wq) { | |
527 | err = -ENOMEM; | |
528 | goto err_debug; | |
529 | } | |
530 | mlx5_health_init(); | |
531 | ||
532 | return 0; | |
533 | ||
534 | mlx5_health_cleanup(); | |
535 | err_debug: | |
536 | mlx5_unregister_debugfs(); | |
537 | return err; | |
538 | } | |
539 | ||
540 | static void __exit cleanup(void) | |
541 | { | |
542 | mlx5_health_cleanup(); | |
543 | destroy_workqueue(mlx5_core_wq); | |
544 | mlx5_unregister_debugfs(); | |
545 | } | |
546 | ||
547 | module_init(init); | |
548 | module_exit(cleanup); |