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net/mlx5_core: HW data structs/types definitions cleanup
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
b775516b 48#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 49#include "mlx5_core.h"
50
51#define DRIVER_NAME "mlx5_core"
4ae6c18c
AS		 52#define DRIVER_VERSION "3.0"
53#define DRIVER_RELDATE "January 2015"
e126ba97
EC		 54
55MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 56MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 57MODULE_LICENSE("Dual BSD/GPL");
58MODULE_VERSION(DRIVER_VERSION);
59
60int mlx5_core_debug_mask;
61module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
62MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
63
9603b61d
JM		 64#define MLX5_DEFAULT_PROF 2
65static int prof_sel = MLX5_DEFAULT_PROF;
66module_param_named(prof_sel, prof_sel, int, 0444);
67MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
68
e126ba97 69struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 70static LIST_HEAD(intf_list);
71static LIST_HEAD(dev_list);
72static DEFINE_MUTEX(intf_mutex);
73
74struct mlx5_device_context {
75 struct list_head list;
76 struct mlx5_interface *intf;
77 void *context;
78};
79
80static struct mlx5_profile profile[] = {
81 [0] = {
82 .mask = 0,
83 },
84 [1] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE,
86 .log_max_qp = 12,
87 },
88 [2] = {
89 .mask = MLX5_PROF_MASK_QP_SIZE |
90 MLX5_PROF_MASK_MR_CACHE,
91 .log_max_qp = 17,
92 .mr_cache[0] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[1] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[2] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[3] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[4] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[5] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[6] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[7] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[8] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[9] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[10] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[11] = {
137 .size = 500,
138 .limit = 250
139 },
140 .mr_cache[12] = {
141 .size = 64,
142 .limit = 32
143 },
144 .mr_cache[13] = {
145 .size = 32,
146 .limit = 16
147 },
148 .mr_cache[14] = {
149 .size = 16,
150 .limit = 8
151 },
152 .mr_cache[15] = {
153 .size = 8,
154 .limit = 4
155 },
156 },
157};
e126ba97
EC		 158
159static int set_dma_caps(struct pci_dev *pdev)
160{
161 int err;
162
163 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
164 if (err) {
1a91de28 165 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 166 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
167 if (err) {
1a91de28 168 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 169 return err;
170 }
171 }
172
173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
174 if (err) {
175 dev_warn(&pdev->dev,
1a91de28 176 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
178 if (err) {
179 dev_err(&pdev->dev,
1a91de28 180 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 181 return err;
182 }
183 }
184
185 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
186 return err;
187}
188
189static int request_bar(struct pci_dev *pdev)
190{
191 int err = 0;
192
193 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 194 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 195 return -ENODEV;
196 }
197
198 err = pci_request_regions(pdev, DRIVER_NAME);
199 if (err)
200 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
201
202 return err;
203}
204
205static void release_bar(struct pci_dev *pdev)
206{
207 pci_release_regions(pdev);
208}
209
210static int mlx5_enable_msix(struct mlx5_core_dev *dev)
211{
db058a18
SM		 212 struct mlx5_priv *priv = &dev->priv;
213 struct mlx5_eq_table *table = &priv->eq_table;
c7a08ac7 214 int num_eqs = 1 << dev->caps.gen.log_max_eq;
e126ba97 215 int nvec;
e126ba97
EC		 216 int i;
217
c7a08ac7 218 nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 219 nvec = min_t(int, nvec, num_eqs);
220 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
221 return -ENOMEM;
222
db058a18
SM		 223 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
224
225 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
226 if (!priv->msix_arr || !priv->irq_info)
227 goto err_free_msix;
e126ba97
EC		 228
229 for (i = 0; i < nvec; i++)
db058a18 230 priv->msix_arr[i].entry = i;
e126ba97 231
db058a18 232 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 233 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 234 if (nvec < 0)
235 return nvec;
e126ba97 236
f3c9407b 237 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 238
239 return 0;
db058a18
SM		 240
241err_free_msix:
242 kfree(priv->irq_info);
243 kfree(priv->msix_arr);
244 return -ENOMEM;
e126ba97
EC		 245}
246
247static void mlx5_disable_msix(struct mlx5_core_dev *dev)
248{
db058a18 249 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 250
251 pci_disable_msix(dev->pdev);
db058a18
SM		 252 kfree(priv->irq_info);
253 kfree(priv->msix_arr);
e126ba97
EC		 254}
255
256struct mlx5_reg_host_endianess {
257 u8 he;
258 u8 rsvd[15];
259};
260
87b8de49
EC		 261
262#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
263
264enum {
c7a08ac7
EC		 265 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
266 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 267};
268
c7a08ac7
EC		 269static u16 to_fw_pkey_sz(u32 size)
270{
271 switch (size) {
272 case 128:
273 return 0;
274 case 256:
275 return 1;
276 case 512:
277 return 2;
278 case 1024:
279 return 3;
280 case 2048:
281 return 4;
282 case 4096:
283 return 5;
284 default:
285 pr_warn("invalid pkey table size %d\n", size);
286 return 0;
287 }
288}
289
87b8de49
EC		 290/* selectively copy writable fields clearing any reserved area
291 */
b775516b 292static void copy_rw_fields(void *to, struct mlx5_caps *from)
87b8de49 293{
b775516b 294 __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
87b8de49
EC		 295 u64 v64;
296
b775516b
EC		 297 MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
298 MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
299 MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
300 MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
b775516b 301 MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
de61390c 302 MLX5_SET(cmd_hca_cap, to, log_uar_page_sz, PAGE_SHIFT - 12);
b775516b
EC		 303 v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
304 *flags_off = cpu_to_be64(v64);
87b8de49
EC		 305}
306
c7a08ac7
EC		 307static u16 get_pkey_table_size(int pkey)
308{
309 if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
310 return 0;
87b8de49 311
c7a08ac7
EC		 312 return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
313}
314
b775516b 315static void fw2drv_caps(struct mlx5_caps *caps, void *out)
e126ba97 316{
c7a08ac7 317 struct mlx5_general_caps *gen = &caps->gen;
b775516b
EC		 318
319 gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
320 gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
321 gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
e281682b 322 gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srq);
b775516b
EC		 323 gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
324 gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
325 gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
326 gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
327 gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
328 gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
329 gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
330 gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
331 gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
332 gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
333 gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
334 gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
335 gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
336 gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
337 gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
338 gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
339 gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
340 gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
341 gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
342 gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
c7a08ac7 343 pr_debug("flags = 0x%llx\n", gen->flags);
b775516b
EC		 344 gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
345 gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
346 gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
347 gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
348 gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
349 gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
350 gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
351 gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
352 gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
353 gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
354 gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
c7a08ac7
EC		 355}
356
357static const char *caps_opmod_str(u16 opmod)
358{
359 switch (opmod) {
360 case HCA_CAP_OPMOD_GET_MAX:
361 return "GET_MAX";
362 case HCA_CAP_OPMOD_GET_CUR:
363 return "GET_CUR";
364 default:
365 return "Invalid";
366 }
367}
368
369int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
370 u16 opmod)
371{
b775516b
EC		 372 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
373 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
374 void *out;
e126ba97
EC		 375 int err;
376
b775516b
EC		 377 memset(in, 0, sizeof(in));
378 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 379 if (!out)
e126ba97 380 return -ENOMEM;
b775516b
EC		 381 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
382 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
383 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
384 if (err)
385 goto query_ex;
e126ba97 386
b775516b 387 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 388 if (err) {
389 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
e126ba97
EC		 390 goto query_ex;
391 }
c7a08ac7 392 mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
e281682b 393 fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability));
c7a08ac7
EC		 394
395query_ex:
396 kfree(out);
397 return err;
398}
399
b775516b 400static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 401{
b775516b 402 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 403 int err;
404
b775516b 405 memset(out, 0, sizeof(out));
e126ba97 406
b775516b
EC		 407 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
408 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 409 if (err)
c7a08ac7 410 return err;
e126ba97 411
b775516b 412 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 413
414 return err;
415}
416
417static int handle_hca_cap(struct mlx5_core_dev *dev)
418{
b775516b 419 void *set_ctx = NULL;
c7a08ac7
EC		 420 struct mlx5_profile *prof = dev->profile;
421 struct mlx5_caps *cur_caps = NULL;
422 struct mlx5_caps *max_caps = NULL;
423 int err = -ENOMEM;
b775516b 424 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
c7a08ac7 425
b775516b 426 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 427 if (!set_ctx)
e126ba97 428 goto query_ex;
e126ba97 429
c7a08ac7
EC		 430 max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
431 if (!max_caps)
432 goto query_ex;
e126ba97 433
c7a08ac7
EC		 434 cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
435 if (!cur_caps)
436 goto query_ex;
e126ba97 437
c7a08ac7
EC		 438 err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
439 if (err)
e126ba97 440 goto query_ex;
e126ba97 441
c7a08ac7 442 err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 443 if (err)
444 goto query_ex;
445
c7a08ac7
EC		 446 /* we limit the size of the pkey table to 128 entries for now */
447 cur_caps->gen.pkey_table_size = 128;
448
449 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
450 cur_caps->gen.log_max_qp = prof->log_max_qp;
451
452 /* disable checksum */
453 cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
454
e281682b 455 copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability),
b775516b
EC		 456 cur_caps);
457 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 458
e126ba97 459query_ex:
c7a08ac7
EC		 460 kfree(cur_caps);
461 kfree(max_caps);
e126ba97
EC		 462 kfree(set_ctx);
463
464 return err;
465}
466
467static int set_hca_ctrl(struct mlx5_core_dev *dev)
468{
469 struct mlx5_reg_host_endianess he_in;
470 struct mlx5_reg_host_endianess he_out;
471 int err;
472
473 memset(&he_in, 0, sizeof(he_in));
474 he_in.he = MLX5_SET_HOST_ENDIANNESS;
475 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
476 &he_out, sizeof(he_out),
477 MLX5_REG_HOST_ENDIANNESS, 0, 1);
478 return err;
479}
480
cd23b14b
EC		 481static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
482{
483 int err;
484 struct mlx5_enable_hca_mbox_in in;
485 struct mlx5_enable_hca_mbox_out out;
486
487 memset(&in, 0, sizeof(in));
488 memset(&out, 0, sizeof(out));
489 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
490 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
491 if (err)
492 return err;
493
494 if (out.hdr.status)
495 return mlx5_cmd_status_to_err(&out.hdr);
496
497 return 0;
498}
499
500static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
501{
502 int err;
503 struct mlx5_disable_hca_mbox_in in;
504 struct mlx5_disable_hca_mbox_out out;
505
506 memset(&in, 0, sizeof(in));
507 memset(&out, 0, sizeof(out));
508 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
509 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
510 if (err)
511 return err;
512
513 if (out.hdr.status)
514 return mlx5_cmd_status_to_err(&out.hdr);
515
516 return 0;
517}
518
db058a18
SM		 519static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
520{
521 struct mlx5_priv *priv = &mdev->priv;
522 struct msix_entry *msix = priv->msix_arr;
523 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
524 int numa_node = dev_to_node(&mdev->pdev->dev);
525 int err;
526
527 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
528 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
529 return -ENOMEM;
530 }
531
532 err = cpumask_set_cpu_local_first(i, numa_node, priv->irq_info[i].mask);
533 if (err) {
534 mlx5_core_warn(mdev, "cpumask_set_cpu_local_first failed");
535 goto err_clear_mask;
536 }
537
538 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
539 if (err) {
540 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
541 irq);
542 goto err_clear_mask;
543 }
544
545 return 0;
546
547err_clear_mask:
548 free_cpumask_var(priv->irq_info[i].mask);
549 return err;
550}
551
552static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
553{
554 struct mlx5_priv *priv = &mdev->priv;
555 struct msix_entry *msix = priv->msix_arr;
556 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
557
558 irq_set_affinity_hint(irq, NULL);
559 free_cpumask_var(priv->irq_info[i].mask);
560}
561
562static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
563{
564 int err;
565 int i;
566
567 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
568 err = mlx5_irq_set_affinity_hint(mdev, i);
569 if (err)
570 goto err_out;
571 }
572
573 return 0;
574
575err_out:
576 for (i--; i >= 0; i--)
577 mlx5_irq_clear_affinity_hint(mdev, i);
578
579 return err;
580}
581
582static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
583{
584 int i;
585
586 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
587 mlx5_irq_clear_affinity_hint(mdev, i);
588}
589
233d05d2
SM		 590int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
591{
592 struct mlx5_eq_table *table = &dev->priv.eq_table;
593 struct mlx5_eq *eq, *n;
594 int err = -ENOENT;
595
596 spin_lock(&table->lock);
597 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
598 if (eq->index == vector) {
599 *eqn = eq->eqn;
600 *irqn = eq->irqn;
601 err = 0;
602 break;
603 }
604 }
605 spin_unlock(&table->lock);
606
607 return err;
608}
609EXPORT_SYMBOL(mlx5_vector2eqn);
610
611static void free_comp_eqs(struct mlx5_core_dev *dev)
612{
613 struct mlx5_eq_table *table = &dev->priv.eq_table;
614 struct mlx5_eq *eq, *n;
615
616 spin_lock(&table->lock);
617 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
618 list_del(&eq->list);
619 spin_unlock(&table->lock);
620 if (mlx5_destroy_unmap_eq(dev, eq))
621 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
622 eq->eqn);
623 kfree(eq);
624 spin_lock(&table->lock);
625 }
626 spin_unlock(&table->lock);
627}
628
629static int alloc_comp_eqs(struct mlx5_core_dev *dev)
630{
631 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 632 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 633 struct mlx5_eq *eq;
634 int ncomp_vec;
635 int nent;
636 int err;
637 int i;
638
639 INIT_LIST_HEAD(&table->comp_eqs_list);
640 ncomp_vec = table->num_comp_vectors;
641 nent = MLX5_COMP_EQ_SIZE;
642 for (i = 0; i < ncomp_vec; i++) {
643 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
644 if (!eq) {
645 err = -ENOMEM;
646 goto clean;
647 }
648
db058a18 649 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 650 err = mlx5_create_map_eq(dev, eq,
651 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
652 name, &dev->priv.uuari.uars[0]);
653 if (err) {
654 kfree(eq);
655 goto clean;
656 }
657 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
658 eq->index = i;
659 spin_lock(&table->lock);
660 list_add_tail(&eq->list, &table->comp_eqs_list);
661 spin_unlock(&table->lock);
662 }
663
664 return 0;
665
666clean:
667 free_comp_eqs(dev);
668 return err;
669}
670
9603b61d 671static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 672{
673 struct mlx5_priv *priv = &dev->priv;
674 int err;
675
676 dev->pdev = pdev;
677 pci_set_drvdata(dev->pdev, dev);
678 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
679 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
680
681 mutex_init(&priv->pgdir_mutex);
682 INIT_LIST_HEAD(&priv->pgdir_list);
683 spin_lock_init(&priv->mkey_lock);
684
685 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
686 if (!priv->dbg_root)
687 return -ENOMEM;
688
689 err = pci_enable_device(pdev);
690 if (err) {
1a91de28 691 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 692 goto err_dbg;
693 }
694
695 err = request_bar(pdev);
696 if (err) {
1a91de28 697 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 698 goto err_disable;
699 }
700
701 pci_set_master(pdev);
702
703 err = set_dma_caps(pdev);
704 if (err) {
705 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
706 goto err_clr_master;
707 }
708
709 dev->iseg_base = pci_resource_start(dev->pdev, 0);
710 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
711 if (!dev->iseg) {
712 err = -ENOMEM;
713 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
714 goto err_clr_master;
715 }
716 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
717 fw_rev_min(dev), fw_rev_sub(dev));
718
719 err = mlx5_cmd_init(dev);
720 if (err) {
721 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
722 goto err_unmap;
723 }
724
725 mlx5_pagealloc_init(dev);
cd23b14b
EC		 726
727 err = mlx5_core_enable_hca(dev);
728 if (err) {
729 dev_err(&pdev->dev, "enable hca failed\n");
730 goto err_pagealloc_cleanup;
731 }
732
733 err = mlx5_satisfy_startup_pages(dev, 1);
734 if (err) {
735 dev_err(&pdev->dev, "failed to allocate boot pages\n");
736 goto err_disable_hca;
737 }
738
e126ba97
EC		 739 err = set_hca_ctrl(dev);
740 if (err) {
741 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 742 goto reclaim_boot_pages;
e126ba97
EC		 743 }
744
745 err = handle_hca_cap(dev);
746 if (err) {
747 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 748 goto reclaim_boot_pages;
e126ba97
EC		 749 }
750
cd23b14b 751 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 752 if (err) {
cd23b14b
EC		 753 dev_err(&pdev->dev, "failed to allocate init pages\n");
754 goto reclaim_boot_pages;
e126ba97
EC		 755 }
756
757 err = mlx5_pagealloc_start(dev);
758 if (err) {
759 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 760 goto reclaim_boot_pages;
e126ba97
EC		 761 }
762
763 err = mlx5_cmd_init_hca(dev);
764 if (err) {
765 dev_err(&pdev->dev, "init hca failed\n");
766 goto err_pagealloc_stop;
767 }
768
769 mlx5_start_health_poll(dev);
770
771 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
772 if (err) {
773 dev_err(&pdev->dev, "query hca failed\n");
774 goto err_stop_poll;
775 }
776
777 err = mlx5_cmd_query_adapter(dev);
778 if (err) {
779 dev_err(&pdev->dev, "query adapter failed\n");
780 goto err_stop_poll;
781 }
782
783 err = mlx5_enable_msix(dev);
784 if (err) {
785 dev_err(&pdev->dev, "enable msix failed\n");
786 goto err_stop_poll;
787 }
788
789 err = mlx5_eq_init(dev);
790 if (err) {
791 dev_err(&pdev->dev, "failed to initialize eq\n");
792 goto disable_msix;
793 }
794
795 err = mlx5_alloc_uuars(dev, &priv->uuari);
796 if (err) {
797 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
798 goto err_eq_cleanup;
799 }
800
801 err = mlx5_start_eqs(dev);
802 if (err) {
803 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
804 goto err_free_uar;
805 }
806
233d05d2
SM		 807 err = alloc_comp_eqs(dev);
808 if (err) {
809 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
810 goto err_stop_eqs;
811 }
812
db058a18
SM		 813 err = mlx5_irq_set_affinity_hints(dev);
814 if (err) {
815 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
816 goto err_free_comp_eqs;
817 }
818
e126ba97
EC		 819 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
820
821 mlx5_init_cq_table(dev);
822 mlx5_init_qp_table(dev);
823 mlx5_init_srq_table(dev);
3bcdb17a 824 mlx5_init_mr_table(dev);
e126ba97
EC		 825
826 return 0;
827
db058a18
SM		 828err_free_comp_eqs:
829 free_comp_eqs(dev);
830
233d05d2
SM		 831err_stop_eqs:
832 mlx5_stop_eqs(dev);
833
e126ba97
EC		 834err_free_uar:
835 mlx5_free_uuars(dev, &priv->uuari);
836
837err_eq_cleanup:
838 mlx5_eq_cleanup(dev);
839
840disable_msix:
841 mlx5_disable_msix(dev);
842
843err_stop_poll:
844 mlx5_stop_health_poll(dev);
1bde6e30
EC		 845 if (mlx5_cmd_teardown_hca(dev)) {
846 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
847 return err;
848 }
e126ba97
EC		 849
850err_pagealloc_stop:
851 mlx5_pagealloc_stop(dev);
852
cd23b14b 853reclaim_boot_pages:
e126ba97
EC		 854 mlx5_reclaim_startup_pages(dev);
855
cd23b14b
EC		 856err_disable_hca:
857 mlx5_core_disable_hca(dev);
858
e126ba97
EC		 859err_pagealloc_cleanup:
860 mlx5_pagealloc_cleanup(dev);
861 mlx5_cmd_cleanup(dev);
862
863err_unmap:
864 iounmap(dev->iseg);
865
866err_clr_master:
867 pci_clear_master(dev->pdev);
868 release_bar(dev->pdev);
869
870err_disable:
871 pci_disable_device(dev->pdev);
872
873err_dbg:
874 debugfs_remove(priv->dbg_root);
875 return err;
876}
e126ba97 877
9603b61d 878static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 879{
880 struct mlx5_priv *priv = &dev->priv;
881
882 mlx5_cleanup_srq_table(dev);
883 mlx5_cleanup_qp_table(dev);
884 mlx5_cleanup_cq_table(dev);
db058a18 885 mlx5_irq_clear_affinity_hints(dev);
233d05d2 886 free_comp_eqs(dev);
e126ba97
EC		 887 mlx5_stop_eqs(dev);
888 mlx5_free_uuars(dev, &priv->uuari);
889 mlx5_eq_cleanup(dev);
890 mlx5_disable_msix(dev);
891 mlx5_stop_health_poll(dev);
1bde6e30
EC		 892 if (mlx5_cmd_teardown_hca(dev)) {
893 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
894 return;
895 }
e126ba97
EC		 896 mlx5_pagealloc_stop(dev);
897 mlx5_reclaim_startup_pages(dev);
cd23b14b 898 mlx5_core_disable_hca(dev);
e126ba97
EC		 899 mlx5_pagealloc_cleanup(dev);
900 mlx5_cmd_cleanup(dev);
901 iounmap(dev->iseg);
902 pci_clear_master(dev->pdev);
903 release_bar(dev->pdev);
904 pci_disable_device(dev->pdev);
905 debugfs_remove(priv->dbg_root);
906}
9603b61d
JM		 907
908static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
909{
910 struct mlx5_device_context *dev_ctx;
911 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
912
913 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
914 if (!dev_ctx) {
915 pr_warn("mlx5_add_device: alloc context failed\n");
916 return;
917 }
918
919 dev_ctx->intf = intf;
920 dev_ctx->context = intf->add(dev);
921
922 if (dev_ctx->context) {
923 spin_lock_irq(&priv->ctx_lock);
924 list_add_tail(&dev_ctx->list, &priv->ctx_list);
925 spin_unlock_irq(&priv->ctx_lock);
926 } else {
927 kfree(dev_ctx);
928 }
929}
930
931static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
932{
933 struct mlx5_device_context *dev_ctx;
934 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
935
936 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
937 if (dev_ctx->intf == intf) {
938 spin_lock_irq(&priv->ctx_lock);
939 list_del(&dev_ctx->list);
940 spin_unlock_irq(&priv->ctx_lock);
941
942 intf->remove(dev, dev_ctx->context);
943 kfree(dev_ctx);
944 return;
945 }
946}
947static int mlx5_register_device(struct mlx5_core_dev *dev)
948{
949 struct mlx5_priv *priv = &dev->priv;
950 struct mlx5_interface *intf;
951
952 mutex_lock(&intf_mutex);
953 list_add_tail(&priv->dev_list, &dev_list);
954 list_for_each_entry(intf, &intf_list, list)
955 mlx5_add_device(intf, priv);
956 mutex_unlock(&intf_mutex);
957
958 return 0;
959}
960static void mlx5_unregister_device(struct mlx5_core_dev *dev)
961{
962 struct mlx5_priv *priv = &dev->priv;
963 struct mlx5_interface *intf;
964
965 mutex_lock(&intf_mutex);
966 list_for_each_entry(intf, &intf_list, list)
967 mlx5_remove_device(intf, priv);
968 list_del(&priv->dev_list);
969 mutex_unlock(&intf_mutex);
970}
971
972int mlx5_register_interface(struct mlx5_interface *intf)
973{
974 struct mlx5_priv *priv;
975
976 if (!intf->add || !intf->remove)
977 return -EINVAL;
978
979 mutex_lock(&intf_mutex);
980 list_add_tail(&intf->list, &intf_list);
981 list_for_each_entry(priv, &dev_list, dev_list)
982 mlx5_add_device(intf, priv);
983 mutex_unlock(&intf_mutex);
984
985 return 0;
986}
987EXPORT_SYMBOL(mlx5_register_interface);
988
989void mlx5_unregister_interface(struct mlx5_interface *intf)
990{
991 struct mlx5_priv *priv;
992
993 mutex_lock(&intf_mutex);
994 list_for_each_entry(priv, &dev_list, dev_list)
995 mlx5_remove_device(intf, priv);
996 list_del(&intf->list);
997 mutex_unlock(&intf_mutex);
998}
999EXPORT_SYMBOL(mlx5_unregister_interface);
1000
64613d94
SM		 1001void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
1002{
1003 struct mlx5_priv *priv = &mdev->priv;
1004 struct mlx5_device_context *dev_ctx;
1005 unsigned long flags;
1006 void *result = NULL;
1007
1008 spin_lock_irqsave(&priv->ctx_lock, flags);
1009
1010 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
1011 if ((dev_ctx->intf->protocol == protocol) &&
1012 dev_ctx->intf->get_dev) {
1013 result = dev_ctx->intf->get_dev(dev_ctx->context);
1014 break;
1015 }
1016
1017 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1018
1019 return result;
1020}
1021EXPORT_SYMBOL(mlx5_get_protocol_dev);
1022
9603b61d 1023static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 1024 unsigned long param)
9603b61d
JM		 1025{
1026 struct mlx5_priv *priv = &dev->priv;
1027 struct mlx5_device_context *dev_ctx;
1028 unsigned long flags;
1029
1030 spin_lock_irqsave(&priv->ctx_lock, flags);
1031
1032 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1033 if (dev_ctx->intf->event)
4d2f9bbb 1034 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1035
1036 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1037}
1038
1039struct mlx5_core_event_handler {
1040 void (*event)(struct mlx5_core_dev *dev,
1041 enum mlx5_dev_event event,
1042 void *data);
1043};
1044
f66f049f
EC		 1045#define MLX5_IB_MOD "mlx5_ib"
1046
9603b61d
JM		 1047static int init_one(struct pci_dev *pdev,
1048 const struct pci_device_id *id)
1049{
1050 struct mlx5_core_dev *dev;
1051 struct mlx5_priv *priv;
1052 int err;
1053
1054 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1055 if (!dev) {
1056 dev_err(&pdev->dev, "kzalloc failed\n");
1057 return -ENOMEM;
1058 }
1059 priv = &dev->priv;
1060
1061 pci_set_drvdata(pdev, dev);
1062
1063 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1064 pr_warn("selected profile out of range, selecting default (%d)\n",
1065 MLX5_DEFAULT_PROF);
1066 prof_sel = MLX5_DEFAULT_PROF;
1067 }
1068 dev->profile = &profile[prof_sel];
1069 dev->event = mlx5_core_event;
1070
364d1798
EC		 1071 INIT_LIST_HEAD(&priv->ctx_list);
1072 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 1073 err = mlx5_dev_init(dev, pdev);
1074 if (err) {
1075 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1076 goto out;
1077 }
1078
9603b61d
JM		 1079 err = mlx5_register_device(dev);
1080 if (err) {
1081 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1082 goto out_init;
1083 }
1084
f66f049f
EC		 1085 err = request_module_nowait(MLX5_IB_MOD);
1086 if (err)
1087 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1088
9603b61d
JM		 1089 return 0;
1090
1091out_init:
1092 mlx5_dev_cleanup(dev);
1093out:
1094 kfree(dev);
1095 return err;
1096}
1097static void remove_one(struct pci_dev *pdev)
1098{
1099 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1100
1101 mlx5_unregister_device(dev);
1102 mlx5_dev_cleanup(dev);
1103 kfree(dev);
1104}
1105
1106static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1107 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1108 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1109 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1110 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1111 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1112 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1113 { 0, }
1114};
1115
1116MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1117
1118static struct pci_driver mlx5_core_driver = {
1119 .name = DRIVER_NAME,
1120 .id_table = mlx5_core_pci_table,
1121 .probe = init_one,
1122 .remove = remove_one
1123};
e126ba97
EC		 1124
1125static int __init init(void)
1126{
1127 int err;
1128
1129 mlx5_register_debugfs();
1130 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1131 if (!mlx5_core_wq) {
1132 err = -ENOMEM;
1133 goto err_debug;
1134 }
1135 mlx5_health_init();
1136
9603b61d
JM		 1137 err = pci_register_driver(&mlx5_core_driver);
1138 if (err)
1139 goto err_health;
1140
e126ba97
EC		 1141 return 0;
1142
9603b61d
JM		 1143err_health:
1144 mlx5_health_cleanup();
1145 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 1146err_debug:
1147 mlx5_unregister_debugfs();
1148 return err;
1149}
1150
1151static void __exit cleanup(void)
1152{
9603b61d 1153 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1154 mlx5_health_cleanup();
1155 destroy_workqueue(mlx5_core_wq);
1156 mlx5_unregister_debugfs();
1157}
1158
1159module_init(init);
1160module_exit(cleanup);
Linux kernel - Deliverables
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