projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5_core: Fix internal error detection conditions
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
b775516b 48#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 49#include "mlx5_core.h"
50
e126ba97 51MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 52MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 53MODULE_LICENSE("Dual BSD/GPL");
54MODULE_VERSION(DRIVER_VERSION);
55
56int mlx5_core_debug_mask;
57module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
58MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59
9603b61d
JM		 60#define MLX5_DEFAULT_PROF 2
61static int prof_sel = MLX5_DEFAULT_PROF;
62module_param_named(prof_sel, prof_sel, int, 0444);
63MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64
9603b61d
JM		 65static LIST_HEAD(intf_list);
66static LIST_HEAD(dev_list);
67static DEFINE_MUTEX(intf_mutex);
68
69struct mlx5_device_context {
70 struct list_head list;
71 struct mlx5_interface *intf;
72 void *context;
73};
74
75static struct mlx5_profile profile[] = {
76 [0] = {
77 .mask = 0,
78 },
79 [1] = {
80 .mask = MLX5_PROF_MASK_QP_SIZE,
81 .log_max_qp = 12,
82 },
83 [2] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE |
85 MLX5_PROF_MASK_MR_CACHE,
86 .log_max_qp = 17,
87 .mr_cache[0] = {
88 .size = 500,
89 .limit = 250
90 },
91 .mr_cache[1] = {
92 .size = 500,
93 .limit = 250
94 },
95 .mr_cache[2] = {
96 .size = 500,
97 .limit = 250
98 },
99 .mr_cache[3] = {
100 .size = 500,
101 .limit = 250
102 },
103 .mr_cache[4] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[5] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[6] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[7] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[8] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[9] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[10] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[11] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[12] = {
136 .size = 64,
137 .limit = 32
138 },
139 .mr_cache[13] = {
140 .size = 32,
141 .limit = 16
142 },
143 .mr_cache[14] = {
144 .size = 16,
145 .limit = 8
146 },
147 .mr_cache[15] = {
148 .size = 8,
149 .limit = 4
150 },
151 },
152};
e126ba97
EC		 153
154static int set_dma_caps(struct pci_dev *pdev)
155{
156 int err;
157
158 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
159 if (err) {
1a91de28 160 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 161 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
162 if (err) {
1a91de28 163 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 164 return err;
165 }
166 }
167
168 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
169 if (err) {
170 dev_warn(&pdev->dev,
1a91de28 171 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 172 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
173 if (err) {
174 dev_err(&pdev->dev,
1a91de28 175 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 176 return err;
177 }
178 }
179
180 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
181 return err;
182}
183
184static int request_bar(struct pci_dev *pdev)
185{
186 int err = 0;
187
188 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 189 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 190 return -ENODEV;
191 }
192
193 err = pci_request_regions(pdev, DRIVER_NAME);
194 if (err)
195 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
196
197 return err;
198}
199
200static void release_bar(struct pci_dev *pdev)
201{
202 pci_release_regions(pdev);
203}
204
205static int mlx5_enable_msix(struct mlx5_core_dev *dev)
206{
db058a18
SM		 207 struct mlx5_priv *priv = &dev->priv;
208 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 209 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 210 int nvec;
e126ba97
EC		 211 int i;
212
938fe83c
SM		 213 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
214 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 215 nvec = min_t(int, nvec, num_eqs);
216 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
217 return -ENOMEM;
218
db058a18
SM		 219 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
220
221 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
222 if (!priv->msix_arr || !priv->irq_info)
223 goto err_free_msix;
e126ba97
EC		 224
225 for (i = 0; i < nvec; i++)
db058a18 226 priv->msix_arr[i].entry = i;
e126ba97 227
db058a18 228 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 229 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 230 if (nvec < 0)
231 return nvec;
e126ba97 232
f3c9407b 233 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 234
235 return 0;
db058a18
SM		 236
237err_free_msix:
238 kfree(priv->irq_info);
239 kfree(priv->msix_arr);
240 return -ENOMEM;
e126ba97
EC		 241}
242
243static void mlx5_disable_msix(struct mlx5_core_dev *dev)
244{
db058a18 245 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 246
247 pci_disable_msix(dev->pdev);
db058a18
SM		 248 kfree(priv->irq_info);
249 kfree(priv->msix_arr);
e126ba97
EC		 250}
251
252struct mlx5_reg_host_endianess {
253 u8 he;
254 u8 rsvd[15];
255};
256
87b8de49
EC		 257
258#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
259
260enum {
c7a08ac7
EC		 261 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
262 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 263};
264
c7a08ac7
EC		 265static u16 to_fw_pkey_sz(u32 size)
266{
267 switch (size) {
268 case 128:
269 return 0;
270 case 256:
271 return 1;
272 case 512:
273 return 2;
274 case 1024:
275 return 3;
276 case 2048:
277 return 4;
278 case 4096:
279 return 5;
280 default:
281 pr_warn("invalid pkey table size %d\n", size);
282 return 0;
283 }
284}
285
938fe83c
SM		 286int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
287 enum mlx5_cap_mode cap_mode)
c7a08ac7 288{
b775516b
EC		 289 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
290 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 291 void *out, *hca_caps;
292 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 293 int err;
294
b775516b
EC		 295 memset(in, 0, sizeof(in));
296 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 297 if (!out)
e126ba97 298 return -ENOMEM;
938fe83c 299
b775516b
EC		 300 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
301 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
302 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
303 if (err)
304 goto query_ex;
e126ba97 305
b775516b 306 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 307 if (err) {
938fe83c
SM		 308 mlx5_core_warn(dev,
309 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
310 cap_type, cap_mode, err);
e126ba97
EC		 311 goto query_ex;
312 }
c7a08ac7 313
938fe83c
SM		 314 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
315
316 switch (cap_mode) {
317 case HCA_CAP_OPMOD_GET_MAX:
318 memcpy(dev->hca_caps_max[cap_type], hca_caps,
319 MLX5_UN_SZ_BYTES(hca_cap_union));
320 break;
321 case HCA_CAP_OPMOD_GET_CUR:
322 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
323 MLX5_UN_SZ_BYTES(hca_cap_union));
324 break;
325 default:
326 mlx5_core_warn(dev,
327 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
328 cap_type, cap_mode);
329 err = -EINVAL;
330 break;
331 }
c7a08ac7
EC		 332query_ex:
333 kfree(out);
334 return err;
335}
336
b775516b 337static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 338{
b775516b 339 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 340 int err;
341
b775516b 342 memset(out, 0, sizeof(out));
e126ba97 343
b775516b
EC		 344 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
345 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 346 if (err)
c7a08ac7 347 return err;
e126ba97 348
b775516b 349 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 350
351 return err;
352}
353
354static int handle_hca_cap(struct mlx5_core_dev *dev)
355{
b775516b 356 void *set_ctx = NULL;
c7a08ac7 357 struct mlx5_profile *prof = dev->profile;
c7a08ac7 358 int err = -ENOMEM;
b775516b 359 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 360 void *set_hca_cap;
c7a08ac7 361
b775516b 362 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 363 if (!set_ctx)
e126ba97 364 goto query_ex;
e126ba97 365
938fe83c 366 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 367 if (err)
e126ba97 368 goto query_ex;
e126ba97 369
938fe83c 370 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 371 if (err)
372 goto query_ex;
373
938fe83c
SM		 374 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
375 capability);
376 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
377 MLX5_ST_SZ_BYTES(cmd_hca_cap));
378
379 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 380 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 381 128);
c7a08ac7 382 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 383 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
384 to_fw_pkey_sz(128));
c7a08ac7
EC		 385
386 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 387 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
388 prof->log_max_qp);
c7a08ac7 389
938fe83c
SM		 390 /* disable cmdif checksum */
391 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 392
fe1e1876
CS		 393 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
394
b775516b 395 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 396
e126ba97 397query_ex:
e126ba97 398 kfree(set_ctx);
e126ba97
EC		 399 return err;
400}
401
402static int set_hca_ctrl(struct mlx5_core_dev *dev)
403{
404 struct mlx5_reg_host_endianess he_in;
405 struct mlx5_reg_host_endianess he_out;
406 int err;
407
408 memset(&he_in, 0, sizeof(he_in));
409 he_in.he = MLX5_SET_HOST_ENDIANNESS;
410 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
411 &he_out, sizeof(he_out),
412 MLX5_REG_HOST_ENDIANNESS, 0, 1);
413 return err;
414}
415
cd23b14b
EC		 416static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
417{
418 int err;
419 struct mlx5_enable_hca_mbox_in in;
420 struct mlx5_enable_hca_mbox_out out;
421
422 memset(&in, 0, sizeof(in));
423 memset(&out, 0, sizeof(out));
424 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
425 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
426 if (err)
427 return err;
428
429 if (out.hdr.status)
430 return mlx5_cmd_status_to_err(&out.hdr);
431
432 return 0;
433}
434
435static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
436{
437 int err;
438 struct mlx5_disable_hca_mbox_in in;
439 struct mlx5_disable_hca_mbox_out out;
440
441 memset(&in, 0, sizeof(in));
442 memset(&out, 0, sizeof(out));
443 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
444 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
445 if (err)
446 return err;
447
448 if (out.hdr.status)
449 return mlx5_cmd_status_to_err(&out.hdr);
450
451 return 0;
452}
453
db058a18
SM		 454static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
455{
456 struct mlx5_priv *priv = &mdev->priv;
457 struct msix_entry *msix = priv->msix_arr;
458 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 459 int numa_node = priv->numa_node;
db058a18
SM		 460 int err;
461
462 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
463 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
464 return -ENOMEM;
465 }
466
dda922c8
DM		 467 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
468 priv->irq_info[i].mask);
db058a18
SM		 469
470 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
471 if (err) {
472 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
473 irq);
474 goto err_clear_mask;
475 }
476
477 return 0;
478
479err_clear_mask:
480 free_cpumask_var(priv->irq_info[i].mask);
481 return err;
482}
483
484static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
485{
486 struct mlx5_priv *priv = &mdev->priv;
487 struct msix_entry *msix = priv->msix_arr;
488 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
489
490 irq_set_affinity_hint(irq, NULL);
491 free_cpumask_var(priv->irq_info[i].mask);
492}
493
494static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
495{
496 int err;
497 int i;
498
499 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
500 err = mlx5_irq_set_affinity_hint(mdev, i);
501 if (err)
502 goto err_out;
503 }
504
505 return 0;
506
507err_out:
508 for (i--; i >= 0; i--)
509 mlx5_irq_clear_affinity_hint(mdev, i);
510
511 return err;
512}
513
514static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
515{
516 int i;
517
518 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
519 mlx5_irq_clear_affinity_hint(mdev, i);
520}
521
233d05d2
SM		 522int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
523{
524 struct mlx5_eq_table *table = &dev->priv.eq_table;
525 struct mlx5_eq *eq, *n;
526 int err = -ENOENT;
527
528 spin_lock(&table->lock);
529 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
530 if (eq->index == vector) {
531 *eqn = eq->eqn;
532 *irqn = eq->irqn;
533 err = 0;
534 break;
535 }
536 }
537 spin_unlock(&table->lock);
538
539 return err;
540}
541EXPORT_SYMBOL(mlx5_vector2eqn);
542
543static void free_comp_eqs(struct mlx5_core_dev *dev)
544{
545 struct mlx5_eq_table *table = &dev->priv.eq_table;
546 struct mlx5_eq *eq, *n;
547
548 spin_lock(&table->lock);
549 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
550 list_del(&eq->list);
551 spin_unlock(&table->lock);
552 if (mlx5_destroy_unmap_eq(dev, eq))
553 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
554 eq->eqn);
555 kfree(eq);
556 spin_lock(&table->lock);
557 }
558 spin_unlock(&table->lock);
559}
560
561static int alloc_comp_eqs(struct mlx5_core_dev *dev)
562{
563 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 564 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 565 struct mlx5_eq *eq;
566 int ncomp_vec;
567 int nent;
568 int err;
569 int i;
570
571 INIT_LIST_HEAD(&table->comp_eqs_list);
572 ncomp_vec = table->num_comp_vectors;
573 nent = MLX5_COMP_EQ_SIZE;
574 for (i = 0; i < ncomp_vec; i++) {
575 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
576 if (!eq) {
577 err = -ENOMEM;
578 goto clean;
579 }
580
db058a18 581 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 582 err = mlx5_create_map_eq(dev, eq,
583 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
584 name, &dev->priv.uuari.uars[0]);
585 if (err) {
586 kfree(eq);
587 goto clean;
588 }
589 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
590 eq->index = i;
591 spin_lock(&table->lock);
592 list_add_tail(&eq->list, &table->comp_eqs_list);
593 spin_unlock(&table->lock);
594 }
595
596 return 0;
597
598clean:
599 free_comp_eqs(dev);
600 return err;
601}
602
f62b8bb8
AV		 603#ifdef CONFIG_MLX5_CORE_EN
604static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
605{
606 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
607 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
608 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
609 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
610 int err;
611 u32 sup_issi;
612
613 memset(query_in, 0, sizeof(query_in));
614 memset(query_out, 0, sizeof(query_out));
615
616 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
617
618 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
619 query_out, sizeof(query_out));
620 if (err) {
621 if (((struct mlx5_outbox_hdr *)query_out)->status ==
622 MLX5_CMD_STAT_BAD_OP_ERR) {
623 pr_debug("Only ISSI 0 is supported\n");
624 return 0;
625 }
626
627 pr_err("failed to query ISSI\n");
628 return err;
629 }
630
631 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
632
633 if (sup_issi & (1 << 1)) {
634 memset(set_in, 0, sizeof(set_in));
635 memset(set_out, 0, sizeof(set_out));
636
637 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
638 MLX5_SET(set_issi_in, set_in, current_issi, 1);
639
640 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
641 set_out, sizeof(set_out));
642 if (err) {
643 pr_err("failed to set ISSI=1\n");
644 return err;
645 }
646
647 dev->issi = 1;
648
649 return 0;
e74a1db0 650 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 651 return 0;
652 }
653
654 return -ENOTSUPP;
655}
656#endif
657
88a85f99
AS		 658static int map_bf_area(struct mlx5_core_dev *dev)
659{
660 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
661 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
662
663 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
664
665 return dev->priv.bf_mapping ? 0 : -ENOMEM;
666}
667
668static void unmap_bf_area(struct mlx5_core_dev *dev)
669{
670 if (dev->priv.bf_mapping)
671 io_mapping_free(dev->priv.bf_mapping);
672}
673
a31208b1
MD		 674static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
675{
676 struct mlx5_device_context *dev_ctx;
677 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
678
679 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
680 if (!dev_ctx)
681 return;
682
683 dev_ctx->intf = intf;
684 dev_ctx->context = intf->add(dev);
685
686 if (dev_ctx->context) {
687 spin_lock_irq(&priv->ctx_lock);
688 list_add_tail(&dev_ctx->list, &priv->ctx_list);
689 spin_unlock_irq(&priv->ctx_lock);
690 } else {
691 kfree(dev_ctx);
692 }
693}
694
695static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
696{
697 struct mlx5_device_context *dev_ctx;
698 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
699
700 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
701 if (dev_ctx->intf == intf) {
702 spin_lock_irq(&priv->ctx_lock);
703 list_del(&dev_ctx->list);
704 spin_unlock_irq(&priv->ctx_lock);
705
706 intf->remove(dev, dev_ctx->context);
707 kfree(dev_ctx);
708 return;
709 }
710}
711
712static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 713{
714 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 715 struct mlx5_interface *intf;
716
717 mutex_lock(&intf_mutex);
718 list_add_tail(&priv->dev_list, &dev_list);
719 list_for_each_entry(intf, &intf_list, list)
720 mlx5_add_device(intf, priv);
721 mutex_unlock(&intf_mutex);
722
723 return 0;
724}
725
726static void mlx5_unregister_device(struct mlx5_core_dev *dev)
727{
728 struct mlx5_priv *priv = &dev->priv;
729 struct mlx5_interface *intf;
730
731 mutex_lock(&intf_mutex);
732 list_for_each_entry(intf, &intf_list, list)
733 mlx5_remove_device(intf, priv);
734 list_del(&priv->dev_list);
735 mutex_unlock(&intf_mutex);
736}
737
738int mlx5_register_interface(struct mlx5_interface *intf)
739{
740 struct mlx5_priv *priv;
741
742 if (!intf->add || !intf->remove)
743 return -EINVAL;
744
745 mutex_lock(&intf_mutex);
746 list_add_tail(&intf->list, &intf_list);
747 list_for_each_entry(priv, &dev_list, dev_list)
748 mlx5_add_device(intf, priv);
749 mutex_unlock(&intf_mutex);
750
751 return 0;
752}
753EXPORT_SYMBOL(mlx5_register_interface);
754
755void mlx5_unregister_interface(struct mlx5_interface *intf)
756{
757 struct mlx5_priv *priv;
758
759 mutex_lock(&intf_mutex);
760 list_for_each_entry(priv, &dev_list, dev_list)
761 mlx5_remove_device(intf, priv);
762 list_del(&intf->list);
763 mutex_unlock(&intf_mutex);
764}
765EXPORT_SYMBOL(mlx5_unregister_interface);
766
767void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
768{
769 struct mlx5_priv *priv = &mdev->priv;
770 struct mlx5_device_context *dev_ctx;
771 unsigned long flags;
772 void *result = NULL;
773
774 spin_lock_irqsave(&priv->ctx_lock, flags);
775
776 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
777 if ((dev_ctx->intf->protocol == protocol) &&
778 dev_ctx->intf->get_dev) {
779 result = dev_ctx->intf->get_dev(dev_ctx->context);
780 break;
781 }
782
783 spin_unlock_irqrestore(&priv->ctx_lock, flags);
784
785 return result;
786}
787EXPORT_SYMBOL(mlx5_get_protocol_dev);
788
789static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
790{
791 struct pci_dev *pdev = dev->pdev;
792 int err = 0;
e126ba97 793
e126ba97
EC		 794 pci_set_drvdata(dev->pdev, dev);
795 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
796 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
797
798 mutex_init(&priv->pgdir_mutex);
799 INIT_LIST_HEAD(&priv->pgdir_list);
800 spin_lock_init(&priv->mkey_lock);
801
311c7c71
SM		 802 mutex_init(&priv->alloc_mutex);
803
804 priv->numa_node = dev_to_node(&dev->pdev->dev);
805
e126ba97
EC		 806 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
807 if (!priv->dbg_root)
808 return -ENOMEM;
809
810 err = pci_enable_device(pdev);
811 if (err) {
1a91de28 812 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 813 goto err_dbg;
814 }
815
816 err = request_bar(pdev);
817 if (err) {
1a91de28 818 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 819 goto err_disable;
820 }
821
822 pci_set_master(pdev);
823
824 err = set_dma_caps(pdev);
825 if (err) {
826 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
827 goto err_clr_master;
828 }
829
830 dev->iseg_base = pci_resource_start(dev->pdev, 0);
831 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
832 if (!dev->iseg) {
833 err = -ENOMEM;
834 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
835 goto err_clr_master;
836 }
a31208b1
MD		 837
838 return 0;
839
840err_clr_master:
841 pci_clear_master(dev->pdev);
842 release_bar(dev->pdev);
843err_disable:
844 pci_disable_device(dev->pdev);
845
846err_dbg:
847 debugfs_remove(priv->dbg_root);
848 return err;
849}
850
851static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
852{
853 iounmap(dev->iseg);
854 pci_clear_master(dev->pdev);
855 release_bar(dev->pdev);
856 pci_disable_device(dev->pdev);
857 debugfs_remove(priv->dbg_root);
858}
859
860#define MLX5_IB_MOD "mlx5_ib"
861static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
862{
863 struct pci_dev *pdev = dev->pdev;
864 int err;
865
e126ba97
EC		 866 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
867 fw_rev_min(dev), fw_rev_sub(dev));
868
869 err = mlx5_cmd_init(dev);
870 if (err) {
871 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
a31208b1 872 return err;
e126ba97
EC		 873 }
874
875 mlx5_pagealloc_init(dev);
cd23b14b
EC		 876
877 err = mlx5_core_enable_hca(dev);
878 if (err) {
879 dev_err(&pdev->dev, "enable hca failed\n");
880 goto err_pagealloc_cleanup;
881 }
882
f62b8bb8
AV		 883#ifdef CONFIG_MLX5_CORE_EN
884 err = mlx5_core_set_issi(dev);
885 if (err) {
886 dev_err(&pdev->dev, "failed to set issi\n");
887 goto err_disable_hca;
888 }
889#endif
890
cd23b14b
EC		 891 err = mlx5_satisfy_startup_pages(dev, 1);
892 if (err) {
893 dev_err(&pdev->dev, "failed to allocate boot pages\n");
894 goto err_disable_hca;
895 }
896
e126ba97
EC		 897 err = set_hca_ctrl(dev);
898 if (err) {
899 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 900 goto reclaim_boot_pages;
e126ba97
EC		 901 }
902
903 err = handle_hca_cap(dev);
904 if (err) {
905 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 906 goto reclaim_boot_pages;
e126ba97
EC		 907 }
908
cd23b14b 909 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 910 if (err) {
cd23b14b
EC		 911 dev_err(&pdev->dev, "failed to allocate init pages\n");
912 goto reclaim_boot_pages;
e126ba97
EC		 913 }
914
915 err = mlx5_pagealloc_start(dev);
916 if (err) {
917 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 918 goto reclaim_boot_pages;
e126ba97
EC		 919 }
920
921 err = mlx5_cmd_init_hca(dev);
922 if (err) {
923 dev_err(&pdev->dev, "init hca failed\n");
924 goto err_pagealloc_stop;
925 }
926
927 mlx5_start_health_poll(dev);
928
938fe83c 929 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 930 if (err) {
931 dev_err(&pdev->dev, "query hca failed\n");
932 goto err_stop_poll;
933 }
934
211e6c80 935 err = mlx5_query_board_id(dev);
e126ba97 936 if (err) {
211e6c80 937 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 938 goto err_stop_poll;
939 }
940
941 err = mlx5_enable_msix(dev);
942 if (err) {
943 dev_err(&pdev->dev, "enable msix failed\n");
944 goto err_stop_poll;
945 }
946
947 err = mlx5_eq_init(dev);
948 if (err) {
949 dev_err(&pdev->dev, "failed to initialize eq\n");
950 goto disable_msix;
951 }
952
953 err = mlx5_alloc_uuars(dev, &priv->uuari);
954 if (err) {
955 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
956 goto err_eq_cleanup;
957 }
958
959 err = mlx5_start_eqs(dev);
960 if (err) {
961 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
962 goto err_free_uar;
963 }
964
233d05d2
SM		 965 err = alloc_comp_eqs(dev);
966 if (err) {
967 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
968 goto err_stop_eqs;
969 }
970
88a85f99
AS		 971 if (map_bf_area(dev))
972 dev_err(&pdev->dev, "Failed to map blue flame area\n");
973
db058a18
SM		 974 err = mlx5_irq_set_affinity_hints(dev);
975 if (err) {
976 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
88a85f99 977 goto err_unmap_bf_area;
db058a18
SM		 978 }
979
e126ba97
EC		 980 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
981
982 mlx5_init_cq_table(dev);
983 mlx5_init_qp_table(dev);
984 mlx5_init_srq_table(dev);
3bcdb17a 985 mlx5_init_mr_table(dev);
e126ba97 986
a31208b1
MD		 987 err = mlx5_register_device(dev);
988 if (err) {
989 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
990 goto err_reg_dev;
991 }
992
993 err = request_module_nowait(MLX5_IB_MOD);
994 if (err)
995 pr_info("failed request module on %s\n", MLX5_IB_MOD);
996
e126ba97
EC		 997 return 0;
998
a31208b1
MD		 999err_reg_dev:
1000 mlx5_cleanup_mr_table(dev);
1001 mlx5_cleanup_srq_table(dev);
1002 mlx5_cleanup_qp_table(dev);
1003 mlx5_cleanup_cq_table(dev);
1004 mlx5_irq_clear_affinity_hints(dev);
1005
88a85f99
AS		 1006err_unmap_bf_area:
1007 unmap_bf_area(dev);
1008
db058a18
SM		 1009 free_comp_eqs(dev);
1010
233d05d2
SM		 1011err_stop_eqs:
1012 mlx5_stop_eqs(dev);
1013
e126ba97
EC		 1014err_free_uar:
1015 mlx5_free_uuars(dev, &priv->uuari);
1016
1017err_eq_cleanup:
1018 mlx5_eq_cleanup(dev);
1019
1020disable_msix:
1021 mlx5_disable_msix(dev);
1022
1023err_stop_poll:
1024 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1025 if (mlx5_cmd_teardown_hca(dev)) {
1026 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1027 return err;
1028 }
e126ba97
EC		 1029
1030err_pagealloc_stop:
1031 mlx5_pagealloc_stop(dev);
1032
cd23b14b 1033reclaim_boot_pages:
e126ba97
EC		 1034 mlx5_reclaim_startup_pages(dev);
1035
cd23b14b
EC		 1036err_disable_hca:
1037 mlx5_core_disable_hca(dev);
1038
e126ba97
EC		 1039err_pagealloc_cleanup:
1040 mlx5_pagealloc_cleanup(dev);
1041 mlx5_cmd_cleanup(dev);
1042
e126ba97
EC		 1043 return err;
1044}
e126ba97 1045
a31208b1 1046static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1047{
ac6ea6e8 1048 int err;
e126ba97 1049
a31208b1
MD		 1050 mlx5_unregister_device(dev);
1051 mlx5_cleanup_mr_table(dev);
e126ba97
EC		 1052 mlx5_cleanup_srq_table(dev);
1053 mlx5_cleanup_qp_table(dev);
1054 mlx5_cleanup_cq_table(dev);
db058a18 1055 mlx5_irq_clear_affinity_hints(dev);
88a85f99 1056 unmap_bf_area(dev);
233d05d2 1057 free_comp_eqs(dev);
e126ba97
EC		 1058 mlx5_stop_eqs(dev);
1059 mlx5_free_uuars(dev, &priv->uuari);
1060 mlx5_eq_cleanup(dev);
1061 mlx5_disable_msix(dev);
1062 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1063 err = mlx5_cmd_teardown_hca(dev);
1064 if (err) {
1bde6e30 1065 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1066 goto out;
1bde6e30 1067 }
e126ba97
EC		 1068 mlx5_pagealloc_stop(dev);
1069 mlx5_reclaim_startup_pages(dev);
cd23b14b 1070 mlx5_core_disable_hca(dev);
e126ba97
EC		 1071 mlx5_pagealloc_cleanup(dev);
1072 mlx5_cmd_cleanup(dev);
9603b61d 1073
ac6ea6e8
EC		 1074out:
1075 return err;
9603b61d 1076}
64613d94 1077
9603b61d 1078static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
ac6ea6e8 1079 unsigned long param)
9603b61d
JM		 1080{
1081 struct mlx5_priv *priv = &dev->priv;
1082 struct mlx5_device_context *dev_ctx;
1083 unsigned long flags;
1084
1085 spin_lock_irqsave(&priv->ctx_lock, flags);
1086
1087 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1088 if (dev_ctx->intf->event)
4d2f9bbb 1089 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1090
1091 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1092}
1093
1094struct mlx5_core_event_handler {
1095 void (*event)(struct mlx5_core_dev *dev,
1096 enum mlx5_dev_event event,
1097 void *data);
1098};
1099
f66f049f 1100
9603b61d
JM		 1101static int init_one(struct pci_dev *pdev,
1102 const struct pci_device_id *id)
1103{
1104 struct mlx5_core_dev *dev;
1105 struct mlx5_priv *priv;
1106 int err;
1107
1108 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1109 if (!dev) {
1110 dev_err(&pdev->dev, "kzalloc failed\n");
1111 return -ENOMEM;
1112 }
1113 priv = &dev->priv;
1114
1115 pci_set_drvdata(pdev, dev);
1116
1117 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1118 pr_warn("selected profile out of range, selecting default (%d)\n",
1119 MLX5_DEFAULT_PROF);
1120 prof_sel = MLX5_DEFAULT_PROF;
1121 }
1122 dev->profile = &profile[prof_sel];
a31208b1 1123 dev->pdev = pdev;
9603b61d
JM		 1124 dev->event = mlx5_core_event;
1125
364d1798
EC		 1126 INIT_LIST_HEAD(&priv->ctx_list);
1127 spin_lock_init(&priv->ctx_lock);
a31208b1 1128 err = mlx5_pci_init(dev, priv);
9603b61d 1129 if (err) {
a31208b1
MD		 1130 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1131 goto clean_dev;
9603b61d
JM		 1132 }
1133
ac6ea6e8
EC		 1134 err = mlx5_health_init(dev);
1135 if (err) {
1136 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1137 goto close_pci;
1138 }
1139
a31208b1 1140 err = mlx5_load_one(dev, priv);
9603b61d 1141 if (err) {
a31208b1 1142 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1143 goto clean_health;
9603b61d
JM		 1144 }
1145
1146 return 0;
1147
ac6ea6e8
EC		 1148clean_health:
1149 mlx5_health_cleanup(dev);
a31208b1
MD		 1150close_pci:
1151 mlx5_pci_close(dev, priv);
1152clean_dev:
1153 pci_set_drvdata(pdev, NULL);
9603b61d 1154 kfree(dev);
a31208b1 1155
9603b61d
JM		 1156 return err;
1157}
a31208b1 1158
9603b61d
JM		 1159static void remove_one(struct pci_dev *pdev)
1160{
1161 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
a31208b1 1162 struct mlx5_priv *priv = &dev->priv;
9603b61d 1163
a31208b1
MD		 1164 if (mlx5_unload_one(dev, priv)) {
1165 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1166 mlx5_health_cleanup(dev);
a31208b1
MD		 1167 return;
1168 }
ac6ea6e8 1169 mlx5_health_cleanup(dev);
a31208b1
MD		 1170 mlx5_pci_close(dev, priv);
1171 pci_set_drvdata(pdev, NULL);
9603b61d
JM		 1172 kfree(dev);
1173}
1174
1175static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1176 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1177 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1178 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1179 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1180 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1181 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1182 { 0, }
1183};
1184
1185MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1186
1187static struct pci_driver mlx5_core_driver = {
1188 .name = DRIVER_NAME,
1189 .id_table = mlx5_core_pci_table,
1190 .probe = init_one,
1191 .remove = remove_one
1192};
e126ba97
EC		 1193
1194static int __init init(void)
1195{
1196 int err;
1197
1198 mlx5_register_debugfs();
e126ba97 1199
9603b61d
JM		 1200 err = pci_register_driver(&mlx5_core_driver);
1201 if (err)
ac6ea6e8 1202 goto err_debug;
9603b61d 1203
f62b8bb8
AV		 1204#ifdef CONFIG_MLX5_CORE_EN
1205 mlx5e_init();
1206#endif
1207
e126ba97
EC		 1208 return 0;
1209
e126ba97
EC		 1210err_debug:
1211 mlx5_unregister_debugfs();
1212 return err;
1213}
1214
1215static void __exit cleanup(void)
1216{
f62b8bb8
AV		 1217#ifdef CONFIG_MLX5_CORE_EN
1218 mlx5e_cleanup();
1219#endif
9603b61d 1220 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1221 mlx5_unregister_debugfs();
1222}
1223
1224module_init(init);
1225module_exit(cleanup);
Linux kernel - Deliverables
This page took 0.224534 seconds and 5 git commands to generate.