[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / qp.c

/*
 * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */


#include <linux/gfp.h>
#include <linux/export.h>
#include <linux/mlx5/cmd.h>
#include <linux/mlx5/qp.h>
#include <linux/mlx5/driver.h>

#include "mlx5_core.h"

void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type)
{
	struct mlx5_qp_table *table = &dev->priv.qp_table;
	struct mlx5_core_qp *qp;

	spin_lock(&table->lock);

	qp = radix_tree_lookup(&table->tree, qpn);
	if (qp)
		atomic_inc(&qp->refcount);

	spin_unlock(&table->lock);

	if (!qp) {
		mlx5_core_warn(dev, "Async event for bogus QP 0x%x\n", qpn);
		return;
	}

	qp->event(qp, event_type);

	if (atomic_dec_and_test(&qp->refcount))
		complete(&qp->free);
}

int mlx5_core_create_qp(struct mlx5_core_dev *dev,
			struct mlx5_core_qp *qp,
			struct mlx5_create_qp_mbox_in *in,
			int inlen)
{
	struct mlx5_qp_table *table = &dev->priv.qp_table;
	struct mlx5_create_qp_mbox_out out;
	struct mlx5_destroy_qp_mbox_in din;
	struct mlx5_destroy_qp_mbox_out dout;
	int err;

	memset(&dout, 0, sizeof(dout));
	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_QP);

	err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
	if (err) {
		mlx5_core_warn(dev, "ret %d", err);
		return err;
	}

	if (out.hdr.status) {
		pr_warn("current num of QPs 0x%x\n", atomic_read(&dev->num_qps));
		return mlx5_cmd_status_to_err(&out.hdr);
	}

	qp->qpn = be32_to_cpu(out.qpn) & 0xffffff;
	mlx5_core_dbg(dev, "qpn = 0x%x\n", qp->qpn);

	spin_lock_irq(&table->lock);
	err = radix_tree_insert(&table->tree, qp->qpn, qp);
	spin_unlock_irq(&table->lock);
	if (err) {
		mlx5_core_warn(dev, "err %d", err);
		goto err_cmd;
	}

	err = mlx5_debug_qp_add(dev, qp);
	if (err)
		mlx5_core_dbg(dev, "failed adding QP 0x%x to debug file system\n",
			      qp->qpn);

	qp->pid = current->pid;
	atomic_set(&qp->refcount, 1);
	atomic_inc(&dev->num_qps);
	init_completion(&qp->free);

	return 0;

err_cmd:
	memset(&din, 0, sizeof(din));
	memset(&dout, 0, sizeof(dout));
	din.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
	din.qpn = cpu_to_be32(qp->qpn);
	mlx5_cmd_exec(dev, &din, sizeof(din), &out, sizeof(dout));

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_create_qp);

int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
			 struct mlx5_core_qp *qp)
{
	struct mlx5_destroy_qp_mbox_in in;
	struct mlx5_destroy_qp_mbox_out out;
	struct mlx5_qp_table *table = &dev->priv.qp_table;
	unsigned long flags;
	int err;

	mlx5_debug_qp_remove(dev, qp);

	spin_lock_irqsave(&table->lock, flags);
	radix_tree_delete(&table->tree, qp->qpn);
	spin_unlock_irqrestore(&table->lock, flags);

	if (atomic_dec_and_test(&qp->refcount))
		complete(&qp->free);
	wait_for_completion(&qp->free);

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
	in.qpn = cpu_to_be32(qp->qpn);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		return mlx5_cmd_status_to_err(&out.hdr);

	atomic_dec(&dev->num_qps);
	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_core_destroy_qp);

int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
			enum mlx5_qp_state new_state,
			struct mlx5_modify_qp_mbox_in *in, int sqd_event,
			struct mlx5_core_qp *qp)
{
	static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
		[MLX5_QP_STATE_RST] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_RST2INIT_QP,
		},
		[MLX5_QP_STATE_INIT]  = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_INIT2INIT_QP,
			[MLX5_QP_STATE_RTR]	= MLX5_CMD_OP_INIT2RTR_QP,
		},
		[MLX5_QP_STATE_RTR]   = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTR2RTS_QP,
		},
		[MLX5_QP_STATE_RTS]   = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTS2RTS_QP,
			[MLX5_QP_STATE_SQD]	= MLX5_CMD_OP_RTS2SQD_QP,
		},
		[MLX5_QP_STATE_SQD] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_SQD2RTS_QP,
			[MLX5_QP_STATE_SQD]	= MLX5_CMD_OP_SQD2SQD_QP,
		},
		[MLX5_QP_STATE_SQER] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_SQERR2RTS_QP,
		},
		[MLX5_QP_STATE_ERR] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
		}
	};

	struct mlx5_modify_qp_mbox_out out;
	int err = 0;
	u16 op;

	if (cur_state >= MLX5_QP_NUM_STATE || new_state >= MLX5_QP_NUM_STATE ||
	    !optab[cur_state][new_state])
		return -EINVAL;

	memset(&out, 0, sizeof(out));
	op = optab[cur_state][new_state];
	in->hdr.opcode = cpu_to_be16(op);
	in->qpn = cpu_to_be32(qp->qpn);
	err = mlx5_cmd_exec(dev, in, sizeof(*in), &out, sizeof(out));
	if (err)
		return err;

	return mlx5_cmd_status_to_err(&out.hdr);
}
EXPORT_SYMBOL_GPL(mlx5_core_qp_modify);

void mlx5_init_qp_table(struct mlx5_core_dev *dev)
{
	struct mlx5_qp_table *table = &dev->priv.qp_table;

	spin_lock_init(&table->lock);
	INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
	mlx5_qp_debugfs_init(dev);
}

void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev)
{
	mlx5_qp_debugfs_cleanup(dev);
}

int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
		       struct mlx5_query_qp_mbox_out *out, int outlen)
{
	struct mlx5_query_qp_mbox_in in;
	int err;

	memset(&in, 0, sizeof(in));
	memset(out, 0, outlen);
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_QP);
	in.qpn = cpu_to_be32(qp->qpn);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
	if (err)
		return err;

	if (out->hdr.status)
		return mlx5_cmd_status_to_err(&out->hdr);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_qp_query);

int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn)
{
	struct mlx5_alloc_xrcd_mbox_in in;
	struct mlx5_alloc_xrcd_mbox_out out;
	int err;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_XRCD);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		err = mlx5_cmd_status_to_err(&out.hdr);
	else
		*xrcdn = be32_to_cpu(out.xrcdn);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_xrcd_alloc);

int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn)
{
	struct mlx5_dealloc_xrcd_mbox_in in;
	struct mlx5_dealloc_xrcd_mbox_out out;
	int err;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_XRCD);
	in.xrcdn = cpu_to_be32(xrcdn);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		err = mlx5_cmd_status_to_err(&out.hdr);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_xrcd_dealloc);
Commit	Line	Data
e126ba97 EC	1	/*
	2	* Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33
	34	#include <linux/gfp.h>
	35	#include <linux/export.h>
	36	#include <linux/mlx5/cmd.h>
	37	#include <linux/mlx5/qp.h>
	38	#include <linux/mlx5/driver.h>
	39
	40	#include "mlx5_core.h"
	41
	42	void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type)
	43	{
	44	struct mlx5_qp_table *table = &dev->priv.qp_table;
	45	struct mlx5_core_qp *qp;
	46
	47	spin_lock(&table->lock);
	48
	49	qp = radix_tree_lookup(&table->tree, qpn);
	50	if (qp)
	51	atomic_inc(&qp->refcount);
	52
	53	spin_unlock(&table->lock);
	54
	55	if (!qp) {
	56	mlx5_core_warn(dev, "Async event for bogus QP 0x%x\n", qpn);
	57	return;
	58	}
	59
	60	qp->event(qp, event_type);
	61
	62	if (atomic_dec_and_test(&qp->refcount))
	63	complete(&qp->free);
	64	}
65
66	int mlx5_core_create_qp(struct mlx5_core_dev *dev,
67	struct mlx5_core_qp *qp,
68	struct mlx5_create_qp_mbox_in *in,
69	int inlen)
70	{
71	struct mlx5_qp_table *table = &dev->priv.qp_table;
72	struct mlx5_create_qp_mbox_out out;
73	struct mlx5_destroy_qp_mbox_in din;
74	struct mlx5_destroy_qp_mbox_out dout;
75	int err;
76
77	memset(&dout, 0, sizeof(dout));
78	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_QP);
79
80	err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
81	if (err) {
82	mlx5_core_warn(dev, "ret %d", err);
83	return err;
84	}
85
86	if (out.hdr.status) {
87	pr_warn("current num of QPs 0x%x\n", atomic_read(&dev->num_qps));
88	return mlx5_cmd_status_to_err(&out.hdr);
89	}
90
91	qp->qpn = be32_to_cpu(out.qpn) & 0xffffff;
92	mlx5_core_dbg(dev, "qpn = 0x%x\n", qp->qpn);
93
94	spin_lock_irq(&table->lock);
95	err = radix_tree_insert(&table->tree, qp->qpn, qp);
96	spin_unlock_irq(&table->lock);
97	if (err) {
98	mlx5_core_warn(dev, "err %d", err);
99	goto err_cmd;
100	}
101
102	err = mlx5_debug_qp_add(dev, qp);
103	if (err)
104	mlx5_core_dbg(dev, "failed adding QP 0x%x to debug file system\n",
105	qp->qpn);
106
107	qp->pid = current->pid;
108	atomic_set(&qp->refcount, 1);
109	atomic_inc(&dev->num_qps);
110	init_completion(&qp->free);
111
112	return 0;
113
114	err_cmd:
115	memset(&din, 0, sizeof(din));
116	memset(&dout, 0, sizeof(dout));
117	din.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
118	din.qpn = cpu_to_be32(qp->qpn);
119	mlx5_cmd_exec(dev, &din, sizeof(din), &out, sizeof(dout));
120
121	return err;
122	}
123	EXPORT_SYMBOL_GPL(mlx5_core_create_qp);
124
125	int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
126	struct mlx5_core_qp *qp)
127	{
128	struct mlx5_destroy_qp_mbox_in in;
129	struct mlx5_destroy_qp_mbox_out out;
130	struct mlx5_qp_table *table = &dev->priv.qp_table;
131	unsigned long flags;
132	int err;
133
134	mlx5_debug_qp_remove(dev, qp);
135
136	spin_lock_irqsave(&table->lock, flags);
137	radix_tree_delete(&table->tree, qp->qpn);
138	spin_unlock_irqrestore(&table->lock, flags);
139
140	if (atomic_dec_and_test(&qp->refcount))
141	complete(&qp->free);
142	wait_for_completion(&qp->free);
143
144	memset(&in, 0, sizeof(in));
145	memset(&out, 0, sizeof(out));
146	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
147	in.qpn = cpu_to_be32(qp->qpn);
148	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
149	if (err)
150	return err;
151
152	if (out.hdr.status)
153	return mlx5_cmd_status_to_err(&out.hdr);
154
155	atomic_dec(&dev->num_qps);
156	return 0;
157	}
158	EXPORT_SYMBOL_GPL(mlx5_core_destroy_qp);
159
160	int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
161	enum mlx5_qp_state new_state,
162	struct mlx5_modify_qp_mbox_in *in, int sqd_event,
163	struct mlx5_core_qp *qp)
164	{
165	static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
166	[MLX5_QP_STATE_RST] = {
167	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
168	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
169	[MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
170	},
171	[MLX5_QP_STATE_INIT] = {
172	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
173	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
174	[MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
175	[MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
176	},
177	[MLX5_QP_STATE_RTR] = {
178	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
179	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
180	[MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
181	},
182	[MLX5_QP_STATE_RTS] = {
183	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
184	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
185	[MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
186	[MLX5_QP_STATE_SQD] = MLX5_CMD_OP_RTS2SQD_QP,
187	},
188	[MLX5_QP_STATE_SQD] = {
189	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
190	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
191	[MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD2RTS_QP,
192	[MLX5_QP_STATE_SQD] = MLX5_CMD_OP_SQD2SQD_QP,
193	},
194	[MLX5_QP_STATE_SQER] = {
195	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
196	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
197	[MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
198	},
199	[MLX5_QP_STATE_ERR] = {
200	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
201	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
202	}
203	};
204
205	struct mlx5_modify_qp_mbox_out out;
206	int err = 0;
207	u16 op;
208
209	if (cur_state >= MLX5_QP_NUM_STATE \|\| new_state >= MLX5_QP_NUM_STATE \|\|
210	!optab[cur_state][new_state])
211	return -EINVAL;
212
213	memset(&out, 0, sizeof(out));
214	op = optab[cur_state][new_state];
215	in->hdr.opcode = cpu_to_be16(op);
216	in->qpn = cpu_to_be32(qp->qpn);
217	err = mlx5_cmd_exec(dev, in, sizeof(*in), &out, sizeof(out));
218	if (err)
219	return err;
220
221	return mlx5_cmd_status_to_err(&out.hdr);
222	}
223	EXPORT_SYMBOL_GPL(mlx5_core_qp_modify);
224
225	void mlx5_init_qp_table(struct mlx5_core_dev *dev)
226	{
227	struct mlx5_qp_table *table = &dev->priv.qp_table;
228
229	spin_lock_init(&table->lock);
230	INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
231	mlx5_qp_debugfs_init(dev);
232	}
233
234	void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev)
235	{
236	mlx5_qp_debugfs_cleanup(dev);
237	}
238
239	int mlx5_core_qp_query(struct mlx5_core_dev dev, struct mlx5_core_qp qp,
240	struct mlx5_query_qp_mbox_out *out, int outlen)
241	{
242	struct mlx5_query_qp_mbox_in in;
243	int err;
244
245	memset(&in, 0, sizeof(in));
246	memset(out, 0, outlen);
247	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_QP);
248	in.qpn = cpu_to_be32(qp->qpn);
249	err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
250	if (err)
251	return err;
252
253	if (out->hdr.status)
254	return mlx5_cmd_status_to_err(&out->hdr);
255
256	return err;
257	}
258	EXPORT_SYMBOL_GPL(mlx5_core_qp_query);
259
260	int mlx5_core_xrcd_alloc(struct mlx5_core_dev dev, u32 xrcdn)
261	{
262	struct mlx5_alloc_xrcd_mbox_in in;
263	struct mlx5_alloc_xrcd_mbox_out out;
264	int err;
265
266	memset(&in, 0, sizeof(in));
267	memset(&out, 0, sizeof(out));
268	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_XRCD);
269	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
270	if (err)
271	return err;
272
273	if (out.hdr.status)
274	err = mlx5_cmd_status_to_err(&out.hdr);
275	else
276	*xrcdn = be32_to_cpu(out.xrcdn);
277
278	return err;
279	}
280	EXPORT_SYMBOL_GPL(mlx5_core_xrcd_alloc);
281
282	int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn)
283	{
284	struct mlx5_dealloc_xrcd_mbox_in in;
285	struct mlx5_dealloc_xrcd_mbox_out out;
286	int err;
287
288	memset(&in, 0, sizeof(in));
289	memset(&out, 0, sizeof(out));
290	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_XRCD);
291	in.xrcdn = cpu_to_be32(xrcdn);
292	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
293	if (err)
294	return err;
295
296	if (out.hdr.status)
297	err = mlx5_cmd_status_to_err(&out.hdr);
298
299	return err;
300	}
301	EXPORT_SYMBOL_GPL(mlx5_core_xrcd_dealloc);