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mlxsw: reg: Uppercase letters in register IDs
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlxsw / reg.h
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4ec14b76
IS		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_REG_H
38#define _MLXSW_REG_H
39
40#include <linux/string.h>
41#include <linux/bitops.h>
42#include <linux/if_vlan.h>
43
44#include "item.h"
45#include "port.h"
46
47struct mlxsw_reg_info {
48 u16 id;
49 u16 len; /* In u8 */
50};
51
52#define MLXSW_REG(type) (&mlxsw_reg_##type)
53#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
54#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
55
56/* SGCR - Switch General Configuration Register
57 * --------------------------------------------
58 * This register is used for configuration of the switch capabilities.
59 */
60#define MLXSW_REG_SGCR_ID 0x2000
61#define MLXSW_REG_SGCR_LEN 0x10
62
63static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
64 .id = MLXSW_REG_SGCR_ID,
65 .len = MLXSW_REG_SGCR_LEN,
66};
67
68/* reg_sgcr_llb
69 * Link Local Broadcast (Default=0)
70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
71 * packets and ignore the IGMP snooping entries.
72 * Access: RW
73 */
74MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
75
76static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
77{
78 MLXSW_REG_ZERO(sgcr, payload);
79 mlxsw_reg_sgcr_llb_set(payload, !!llb);
80}
81
82/* SPAD - Switch Physical Address Register
83 * ---------------------------------------
84 * The SPAD register configures the switch physical MAC address.
85 */
86#define MLXSW_REG_SPAD_ID 0x2002
87#define MLXSW_REG_SPAD_LEN 0x10
88
89static const struct mlxsw_reg_info mlxsw_reg_spad = {
90 .id = MLXSW_REG_SPAD_ID,
91 .len = MLXSW_REG_SPAD_LEN,
92};
93
94/* reg_spad_base_mac
95 * Base MAC address for the switch partitions.
96 * Per switch partition MAC address is equal to:
97 * base_mac + swid
98 * Access: RW
99 */
100MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
101
e61011b5
IS		 102/* SSPR - Switch System Port Record Register
103 * -----------------------------------------
104 * Configures the system port to local port mapping.
105 */
106#define MLXSW_REG_SSPR_ID 0x2008
107#define MLXSW_REG_SSPR_LEN 0x8
108
109static const struct mlxsw_reg_info mlxsw_reg_sspr = {
110 .id = MLXSW_REG_SSPR_ID,
111 .len = MLXSW_REG_SSPR_LEN,
112};
113
114/* reg_sspr_m
115 * Master - if set, then the record describes the master system port.
116 * This is needed in case a local port is mapped into several system ports
117 * (for multipathing). That number will be reported as the source system
118 * port when packets are forwarded to the CPU. Only one master port is allowed
119 * per local port.
120 *
121 * Note: Must be set for Spectrum.
122 * Access: RW
123 */
124MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
125
126/* reg_sspr_local_port
127 * Local port number.
128 *
129 * Access: RW
130 */
131MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
132
133/* reg_sspr_sub_port
134 * Virtual port within the physical port.
135 * Should be set to 0 when virtual ports are not enabled on the port.
136 *
137 * Access: RW
138 */
139MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
140
141/* reg_sspr_system_port
142 * Unique identifier within the stacking domain that represents all the ports
143 * that are available in the system (external ports).
144 *
145 * Currently, only single-ASIC configurations are supported, so we default to
146 * 1:1 mapping between system ports and local ports.
147 * Access: Index
148 */
149MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
150
151static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
152{
153 MLXSW_REG_ZERO(sspr, payload);
154 mlxsw_reg_sspr_m_set(payload, 1);
155 mlxsw_reg_sspr_local_port_set(payload, local_port);
156 mlxsw_reg_sspr_sub_port_set(payload, 0);
157 mlxsw_reg_sspr_system_port_set(payload, local_port);
158}
159
4ec14b76
IS		 160/* SPMS - Switch Port MSTP/RSTP State Register
161 * -------------------------------------------
162 * Configures the spanning tree state of a physical port.
163 */
3f0effd1 164#define MLXSW_REG_SPMS_ID 0x200D
4ec14b76
IS		 165#define MLXSW_REG_SPMS_LEN 0x404
166
167static const struct mlxsw_reg_info mlxsw_reg_spms = {
168 .id = MLXSW_REG_SPMS_ID,
169 .len = MLXSW_REG_SPMS_LEN,
170};
171
172/* reg_spms_local_port
173 * Local port number.
174 * Access: Index
175 */
176MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
177
178enum mlxsw_reg_spms_state {
179 MLXSW_REG_SPMS_STATE_NO_CHANGE,
180 MLXSW_REG_SPMS_STATE_DISCARDING,
181 MLXSW_REG_SPMS_STATE_LEARNING,
182 MLXSW_REG_SPMS_STATE_FORWARDING,
183};
184
185/* reg_spms_state
186 * Spanning tree state of each VLAN ID (VID) of the local port.
187 * 0 - Do not change spanning tree state (used only when writing).
188 * 1 - Discarding. No learning or forwarding to/from this port (default).
189 * 2 - Learning. Port is learning, but not forwarding.
190 * 3 - Forwarding. Port is learning and forwarding.
191 * Access: RW
192 */
193MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
194
195static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port, u16 vid,
196 enum mlxsw_reg_spms_state state)
197{
198 MLXSW_REG_ZERO(spms, payload);
199 mlxsw_reg_spms_local_port_set(payload, local_port);
200 mlxsw_reg_spms_state_set(payload, vid, state);
201}
202
203/* SFGC - Switch Flooding Group Configuration
204 * ------------------------------------------
205 * The following register controls the association of flooding tables and MIDs
206 * to packet types used for flooding.
207 */
208#define MLXSW_REG_SFGC_ID 0x2011
209#define MLXSW_REG_SFGC_LEN 0x10
210
211static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
212 .id = MLXSW_REG_SFGC_ID,
213 .len = MLXSW_REG_SFGC_LEN,
214};
215
216enum mlxsw_reg_sfgc_type {
217 MLXSW_REG_SFGC_TYPE_BROADCAST = 0,
218 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST = 1,
219 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4 = 2,
220 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6 = 3,
221 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP = 5,
222 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL = 6,
223 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST = 7,
224};
225
226/* reg_sfgc_type
227 * The traffic type to reach the flooding table.
228 * Access: Index
229 */
230MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
231
232enum mlxsw_reg_sfgc_bridge_type {
233 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
234 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
235};
236
237/* reg_sfgc_bridge_type
238 * Access: Index
239 *
240 * Note: SwitchX-2 only supports 802.1Q mode.
241 */
242MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
243
244enum mlxsw_flood_table_type {
245 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
246 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
247 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
248 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
249 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
250};
251
252/* reg_sfgc_table_type
253 * See mlxsw_flood_table_type
254 * Access: RW
255 *
256 * Note: FID offset and FID types are not supported in SwitchX-2.
257 */
258MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
259
260/* reg_sfgc_flood_table
261 * Flooding table index to associate with the specific type on the specific
262 * switch partition.
263 * Access: RW
264 */
265MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
266
267/* reg_sfgc_mid
268 * The multicast ID for the swid. Not supported for Spectrum
269 * Access: RW
270 */
271MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
272
273/* reg_sfgc_counter_set_type
274 * Counter Set Type for flow counters.
275 * Access: RW
276 */
277MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
278
279/* reg_sfgc_counter_index
280 * Counter Index for flow counters.
281 * Access: RW
282 */
283MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
284
285static inline void
286mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
287 enum mlxsw_reg_sfgc_bridge_type bridge_type,
288 enum mlxsw_flood_table_type table_type,
289 unsigned int flood_table)
290{
291 MLXSW_REG_ZERO(sfgc, payload);
292 mlxsw_reg_sfgc_type_set(payload, type);
293 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
294 mlxsw_reg_sfgc_table_type_set(payload, table_type);
295 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
296 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
297}
298
299/* SFTR - Switch Flooding Table Register
300 * -------------------------------------
301 * The switch flooding table is used for flooding packet replication. The table
302 * defines a bit mask of ports for packet replication.
303 */
304#define MLXSW_REG_SFTR_ID 0x2012
305#define MLXSW_REG_SFTR_LEN 0x420
306
307static const struct mlxsw_reg_info mlxsw_reg_sftr = {
308 .id = MLXSW_REG_SFTR_ID,
309 .len = MLXSW_REG_SFTR_LEN,
310};
311
312/* reg_sftr_swid
313 * Switch partition ID with which to associate the port.
314 * Access: Index
315 */
316MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
317
318/* reg_sftr_flood_table
319 * Flooding table index to associate with the specific type on the specific
320 * switch partition.
321 * Access: Index
322 */
323MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
324
325/* reg_sftr_index
326 * Index. Used as an index into the Flooding Table in case the table is
327 * configured to use VID / FID or FID Offset.
328 * Access: Index
329 */
330MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
331
332/* reg_sftr_table_type
333 * See mlxsw_flood_table_type
334 * Access: RW
335 */
336MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
337
338/* reg_sftr_range
339 * Range of entries to update
340 * Access: Index
341 */
342MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
343
344/* reg_sftr_port
345 * Local port membership (1 bit per port).
346 * Access: RW
347 */
348MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
349
350/* reg_sftr_cpu_port_mask
351 * CPU port mask (1 bit per port).
352 * Access: W
353 */
354MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
355
356static inline void mlxsw_reg_sftr_pack(char *payload,
357 unsigned int flood_table,
358 unsigned int index,
359 enum mlxsw_flood_table_type table_type,
360 unsigned int range)
361{
362 MLXSW_REG_ZERO(sftr, payload);
363 mlxsw_reg_sftr_swid_set(payload, 0);
364 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
365 mlxsw_reg_sftr_index_set(payload, index);
366 mlxsw_reg_sftr_table_type_set(payload, table_type);
367 mlxsw_reg_sftr_range_set(payload, range);
368 mlxsw_reg_sftr_port_set(payload, MLXSW_PORT_CPU_PORT, 1);
369 mlxsw_reg_sftr_port_mask_set(payload, MLXSW_PORT_CPU_PORT, 1);
370}
371
372/* SPMLR - Switch Port MAC Learning Register
373 * -----------------------------------------
374 * Controls the Switch MAC learning policy per port.
375 */
376#define MLXSW_REG_SPMLR_ID 0x2018
377#define MLXSW_REG_SPMLR_LEN 0x8
378
379static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
380 .id = MLXSW_REG_SPMLR_ID,
381 .len = MLXSW_REG_SPMLR_LEN,
382};
383
384/* reg_spmlr_local_port
385 * Local port number.
386 * Access: Index
387 */
388MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
389
390/* reg_spmlr_sub_port
391 * Virtual port within the physical port.
392 * Should be set to 0 when virtual ports are not enabled on the port.
393 * Access: Index
394 */
395MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
396
397enum mlxsw_reg_spmlr_learn_mode {
398 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
399 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
400 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
401};
402
403/* reg_spmlr_learn_mode
404 * Learning mode on the port.
405 * 0 - Learning disabled.
406 * 2 - Learning enabled.
407 * 3 - Security mode.
408 *
409 * In security mode the switch does not learn MACs on the port, but uses the
410 * SMAC to see if it exists on another ingress port. If so, the packet is
411 * classified as a bad packet and is discarded unless the software registers
412 * to receive port security error packets usign HPKT.
413 */
414MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
415
416static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
417 enum mlxsw_reg_spmlr_learn_mode mode)
418{
419 MLXSW_REG_ZERO(spmlr, payload);
420 mlxsw_reg_spmlr_local_port_set(payload, local_port);
421 mlxsw_reg_spmlr_sub_port_set(payload, 0);
422 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
423}
424
425/* PMLP - Ports Module to Local Port Register
426 * ------------------------------------------
427 * Configures the assignment of modules to local ports.
428 */
429#define MLXSW_REG_PMLP_ID 0x5002
430#define MLXSW_REG_PMLP_LEN 0x40
431
432static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
433 .id = MLXSW_REG_PMLP_ID,
434 .len = MLXSW_REG_PMLP_LEN,
435};
436
437/* reg_pmlp_rxtx
438 * 0 - Tx value is used for both Tx and Rx.
439 * 1 - Rx value is taken from a separte field.
440 * Access: RW
441 */
442MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
443
444/* reg_pmlp_local_port
445 * Local port number.
446 * Access: Index
447 */
448MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
449
450/* reg_pmlp_width
451 * 0 - Unmap local port.
452 * 1 - Lane 0 is used.
453 * 2 - Lanes 0 and 1 are used.
454 * 4 - Lanes 0, 1, 2 and 3 are used.
455 * Access: RW
456 */
457MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
458
459/* reg_pmlp_module
460 * Module number.
461 * Access: RW
462 */
463MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false);
464
465/* reg_pmlp_tx_lane
466 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
467 * Access: RW
468 */
469MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false);
470
471/* reg_pmlp_rx_lane
472 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
473 * equal to Tx lane.
474 * Access: RW
475 */
476MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false);
477
478static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
479{
480 MLXSW_REG_ZERO(pmlp, payload);
481 mlxsw_reg_pmlp_local_port_set(payload, local_port);
482}
483
484/* PMTU - Port MTU Register
485 * ------------------------
486 * Configures and reports the port MTU.
487 */
488#define MLXSW_REG_PMTU_ID 0x5003
489#define MLXSW_REG_PMTU_LEN 0x10
490
491static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
492 .id = MLXSW_REG_PMTU_ID,
493 .len = MLXSW_REG_PMTU_LEN,
494};
495
496/* reg_pmtu_local_port
497 * Local port number.
498 * Access: Index
499 */
500MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
501
502/* reg_pmtu_max_mtu
503 * Maximum MTU.
504 * When port type (e.g. Ethernet) is configured, the relevant MTU is
505 * reported, otherwise the minimum between the max_mtu of the different
506 * types is reported.
507 * Access: RO
508 */
509MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
510
511/* reg_pmtu_admin_mtu
512 * MTU value to set port to. Must be smaller or equal to max_mtu.
513 * Note: If port type is Infiniband, then port must be disabled, when its
514 * MTU is set.
515 * Access: RW
516 */
517MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
518
519/* reg_pmtu_oper_mtu
520 * The actual MTU configured on the port. Packets exceeding this size
521 * will be dropped.
522 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
523 * oper_mtu might be smaller than admin_mtu.
524 * Access: RO
525 */
526MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
527
528static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
529 u16 new_mtu)
530{
531 MLXSW_REG_ZERO(pmtu, payload);
532 mlxsw_reg_pmtu_local_port_set(payload, local_port);
533 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
534 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
535 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
536}
537
538/* PTYS - Port Type and Speed Register
539 * -----------------------------------
540 * Configures and reports the port speed type.
541 *
542 * Note: When set while the link is up, the changes will not take effect
543 * until the port transitions from down to up state.
544 */
545#define MLXSW_REG_PTYS_ID 0x5004
546#define MLXSW_REG_PTYS_LEN 0x40
547
548static const struct mlxsw_reg_info mlxsw_reg_ptys = {
549 .id = MLXSW_REG_PTYS_ID,
550 .len = MLXSW_REG_PTYS_LEN,
551};
552
553/* reg_ptys_local_port
554 * Local port number.
555 * Access: Index
556 */
557MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
558
559#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
560
561/* reg_ptys_proto_mask
562 * Protocol mask. Indicates which protocol is used.
563 * 0 - Infiniband.
564 * 1 - Fibre Channel.
565 * 2 - Ethernet.
566 * Access: Index
567 */
568MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
569
570#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
571#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
572#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
573#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
574#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
575#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
576#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
577#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
578#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
579#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
580#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
581#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
582#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
583#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
584#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
585#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
586#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
587#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
588#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
589#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
590#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
591#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
592#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
593#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
594#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
595#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
596#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
597
598/* reg_ptys_eth_proto_cap
599 * Ethernet port supported speeds and protocols.
600 * Access: RO
601 */
602MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
603
604/* reg_ptys_eth_proto_admin
605 * Speed and protocol to set port to.
606 * Access: RW
607 */
608MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
609
610/* reg_ptys_eth_proto_oper
611 * The current speed and protocol configured for the port.
612 * Access: RO
613 */
614MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
615
616static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
617 u32 proto_admin)
618{
619 MLXSW_REG_ZERO(ptys, payload);
620 mlxsw_reg_ptys_local_port_set(payload, local_port);
621 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
622 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
623}
624
625static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
626 u32 *p_eth_proto_adm,
627 u32 *p_eth_proto_oper)
628{
629 if (p_eth_proto_cap)
630 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
631 if (p_eth_proto_adm)
632 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
633 if (p_eth_proto_oper)
634 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
635}
636
637/* PPAD - Port Physical Address Register
638 * -------------------------------------
639 * The PPAD register configures the per port physical MAC address.
640 */
641#define MLXSW_REG_PPAD_ID 0x5005
642#define MLXSW_REG_PPAD_LEN 0x10
643
644static const struct mlxsw_reg_info mlxsw_reg_ppad = {
645 .id = MLXSW_REG_PPAD_ID,
646 .len = MLXSW_REG_PPAD_LEN,
647};
648
649/* reg_ppad_single_base_mac
650 * 0: base_mac, local port should be 0 and mac[7:0] is
651 * reserved. HW will set incremental
652 * 1: single_mac - mac of the local_port
653 * Access: RW
654 */
655MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
656
657/* reg_ppad_local_port
658 * port number, if single_base_mac = 0 then local_port is reserved
659 * Access: RW
660 */
661MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
662
663/* reg_ppad_mac
664 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
665 * If single_base_mac = 1 - the per port MAC address
666 * Access: RW
667 */
668MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
669
670static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
671 u8 local_port)
672{
673 MLXSW_REG_ZERO(ppad, payload);
674 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
675 mlxsw_reg_ppad_local_port_set(payload, local_port);
676}
677
678/* PAOS - Ports Administrative and Operational Status Register
679 * -----------------------------------------------------------
680 * Configures and retrieves per port administrative and operational status.
681 */
682#define MLXSW_REG_PAOS_ID 0x5006
683#define MLXSW_REG_PAOS_LEN 0x10
684
685static const struct mlxsw_reg_info mlxsw_reg_paos = {
686 .id = MLXSW_REG_PAOS_ID,
687 .len = MLXSW_REG_PAOS_LEN,
688};
689
690/* reg_paos_swid
691 * Switch partition ID with which to associate the port.
692 * Note: while external ports uses unique local port numbers (and thus swid is
693 * redundant), router ports use the same local port number where swid is the
694 * only indication for the relevant port.
695 * Access: Index
696 */
697MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
698
699/* reg_paos_local_port
700 * Local port number.
701 * Access: Index
702 */
703MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
704
705/* reg_paos_admin_status
706 * Port administrative state (the desired state of the port):
707 * 1 - Up.
708 * 2 - Down.
709 * 3 - Up once. This means that in case of link failure, the port won't go
710 * into polling mode, but will wait to be re-enabled by software.
711 * 4 - Disabled by system. Can only be set by hardware.
712 * Access: RW
713 */
714MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
715
716/* reg_paos_oper_status
717 * Port operational state (the current state):
718 * 1 - Up.
719 * 2 - Down.
720 * 3 - Down by port failure. This means that the device will not let the
721 * port up again until explicitly specified by software.
722 * Access: RO
723 */
724MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
725
726/* reg_paos_ase
727 * Admin state update enabled.
728 * Access: WO
729 */
730MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
731
732/* reg_paos_ee
733 * Event update enable. If this bit is set, event generation will be
734 * updated based on the e field.
735 * Access: WO
736 */
737MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
738
739/* reg_paos_e
740 * Event generation on operational state change:
741 * 0 - Do not generate event.
742 * 1 - Generate Event.
743 * 2 - Generate Single Event.
744 * Access: RW
745 */
746MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
747
748static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
749 enum mlxsw_port_admin_status status)
750{
751 MLXSW_REG_ZERO(paos, payload);
752 mlxsw_reg_paos_swid_set(payload, 0);
753 mlxsw_reg_paos_local_port_set(payload, local_port);
754 mlxsw_reg_paos_admin_status_set(payload, status);
755 mlxsw_reg_paos_oper_status_set(payload, 0);
756 mlxsw_reg_paos_ase_set(payload, 1);
757 mlxsw_reg_paos_ee_set(payload, 1);
758 mlxsw_reg_paos_e_set(payload, 1);
759}
760
761/* PPCNT - Ports Performance Counters Register
762 * -------------------------------------------
763 * The PPCNT register retrieves per port performance counters.
764 */
765#define MLXSW_REG_PPCNT_ID 0x5008
766#define MLXSW_REG_PPCNT_LEN 0x100
767
768static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
769 .id = MLXSW_REG_PPCNT_ID,
770 .len = MLXSW_REG_PPCNT_LEN,
771};
772
773/* reg_ppcnt_swid
774 * For HCA: must be always 0.
775 * Switch partition ID to associate port with.
776 * Switch partitions are numbered from 0 to 7 inclusively.
777 * Switch partition 254 indicates stacking ports.
778 * Switch partition 255 indicates all switch partitions.
779 * Only valid on Set() operation with local_port=255.
780 * Access: Index
781 */
782MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
783
784/* reg_ppcnt_local_port
785 * Local port number.
786 * 255 indicates all ports on the device, and is only allowed
787 * for Set() operation.
788 * Access: Index
789 */
790MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
791
792/* reg_ppcnt_pnat
793 * Port number access type:
794 * 0 - Local port number
795 * 1 - IB port number
796 * Access: Index
797 */
798MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
799
800/* reg_ppcnt_grp
801 * Performance counter group.
802 * Group 63 indicates all groups. Only valid on Set() operation with
803 * clr bit set.
804 * 0x0: IEEE 802.3 Counters
805 * 0x1: RFC 2863 Counters
806 * 0x2: RFC 2819 Counters
807 * 0x3: RFC 3635 Counters
808 * 0x5: Ethernet Extended Counters
809 * 0x8: Link Level Retransmission Counters
810 * 0x10: Per Priority Counters
811 * 0x11: Per Traffic Class Counters
812 * 0x12: Physical Layer Counters
813 * Access: Index
814 */
815MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
816
817/* reg_ppcnt_clr
818 * Clear counters. Setting the clr bit will reset the counter value
819 * for all counters in the counter group. This bit can be set
820 * for both Set() and Get() operation.
821 * Access: OP
822 */
823MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
824
825/* reg_ppcnt_prio_tc
826 * Priority for counter set that support per priority, valid values: 0-7.
827 * Traffic class for counter set that support per traffic class,
828 * valid values: 0- cap_max_tclass-1 .
829 * For HCA: cap_max_tclass is always 8.
830 * Otherwise must be 0.
831 * Access: Index
832 */
833MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
834
835/* reg_ppcnt_a_frames_transmitted_ok
836 * Access: RO
837 */
838MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
839 0x08 + 0x00, 0, 64);
840
841/* reg_ppcnt_a_frames_received_ok
842 * Access: RO
843 */
844MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
845 0x08 + 0x08, 0, 64);
846
847/* reg_ppcnt_a_frame_check_sequence_errors
848 * Access: RO
849 */
850MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
851 0x08 + 0x10, 0, 64);
852
853/* reg_ppcnt_a_alignment_errors
854 * Access: RO
855 */
856MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
857 0x08 + 0x18, 0, 64);
858
859/* reg_ppcnt_a_octets_transmitted_ok
860 * Access: RO
861 */
862MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
863 0x08 + 0x20, 0, 64);
864
865/* reg_ppcnt_a_octets_received_ok
866 * Access: RO
867 */
868MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
869 0x08 + 0x28, 0, 64);
870
871/* reg_ppcnt_a_multicast_frames_xmitted_ok
872 * Access: RO
873 */
874MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
875 0x08 + 0x30, 0, 64);
876
877/* reg_ppcnt_a_broadcast_frames_xmitted_ok
878 * Access: RO
879 */
880MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
881 0x08 + 0x38, 0, 64);
882
883/* reg_ppcnt_a_multicast_frames_received_ok
884 * Access: RO
885 */
886MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
887 0x08 + 0x40, 0, 64);
888
889/* reg_ppcnt_a_broadcast_frames_received_ok
890 * Access: RO
891 */
892MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
893 0x08 + 0x48, 0, 64);
894
895/* reg_ppcnt_a_in_range_length_errors
896 * Access: RO
897 */
898MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
899 0x08 + 0x50, 0, 64);
900
901/* reg_ppcnt_a_out_of_range_length_field
902 * Access: RO
903 */
904MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
905 0x08 + 0x58, 0, 64);
906
907/* reg_ppcnt_a_frame_too_long_errors
908 * Access: RO
909 */
910MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
911 0x08 + 0x60, 0, 64);
912
913/* reg_ppcnt_a_symbol_error_during_carrier
914 * Access: RO
915 */
916MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
917 0x08 + 0x68, 0, 64);
918
919/* reg_ppcnt_a_mac_control_frames_transmitted
920 * Access: RO
921 */
922MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
923 0x08 + 0x70, 0, 64);
924
925/* reg_ppcnt_a_mac_control_frames_received
926 * Access: RO
927 */
928MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
929 0x08 + 0x78, 0, 64);
930
931/* reg_ppcnt_a_unsupported_opcodes_received
932 * Access: RO
933 */
934MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
935 0x08 + 0x80, 0, 64);
936
937/* reg_ppcnt_a_pause_mac_ctrl_frames_received
938 * Access: RO
939 */
940MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
941 0x08 + 0x88, 0, 64);
942
943/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
944 * Access: RO
945 */
946MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
947 0x08 + 0x90, 0, 64);
948
949static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
950{
951 MLXSW_REG_ZERO(ppcnt, payload);
952 mlxsw_reg_ppcnt_swid_set(payload, 0);
953 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
954 mlxsw_reg_ppcnt_pnat_set(payload, 0);
955 mlxsw_reg_ppcnt_grp_set(payload, 0);
956 mlxsw_reg_ppcnt_clr_set(payload, 0);
957 mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
958}
959
960/* PSPA - Port Switch Partition Allocation
961 * ---------------------------------------
962 * Controls the association of a port with a switch partition and enables
963 * configuring ports as stacking ports.
964 */
3f0effd1 965#define MLXSW_REG_PSPA_ID 0x500D
4ec14b76
IS		 966#define MLXSW_REG_PSPA_LEN 0x8
967
968static const struct mlxsw_reg_info mlxsw_reg_pspa = {
969 .id = MLXSW_REG_PSPA_ID,
970 .len = MLXSW_REG_PSPA_LEN,
971};
972
973/* reg_pspa_swid
974 * Switch partition ID.
975 * Access: RW
976 */
977MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
978
979/* reg_pspa_local_port
980 * Local port number.
981 * Access: Index
982 */
983MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
984
985/* reg_pspa_sub_port
986 * Virtual port within the local port. Set to 0 when virtual ports are
987 * disabled on the local port.
988 * Access: Index
989 */
990MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
991
992static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
993{
994 MLXSW_REG_ZERO(pspa, payload);
995 mlxsw_reg_pspa_swid_set(payload, swid);
996 mlxsw_reg_pspa_local_port_set(payload, local_port);
997 mlxsw_reg_pspa_sub_port_set(payload, 0);
998}
999
1000/* HTGT - Host Trap Group Table
1001 * ----------------------------
1002 * Configures the properties for forwarding to CPU.
1003 */
1004#define MLXSW_REG_HTGT_ID 0x7002
1005#define MLXSW_REG_HTGT_LEN 0x100
1006
1007static const struct mlxsw_reg_info mlxsw_reg_htgt = {
1008 .id = MLXSW_REG_HTGT_ID,
1009 .len = MLXSW_REG_HTGT_LEN,
1010};
1011
1012/* reg_htgt_swid
1013 * Switch partition ID.
1014 * Access: Index
1015 */
1016MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
1017
1018#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
1019
1020/* reg_htgt_type
1021 * CPU path type.
1022 * Access: RW
1023 */
1024MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
1025
1026#define MLXSW_REG_HTGT_TRAP_GROUP_EMAD 0x0
1027#define MLXSW_REG_HTGT_TRAP_GROUP_RX 0x1
1028
1029/* reg_htgt_trap_group
1030 * Trap group number. User defined number specifying which trap groups
1031 * should be forwarded to the CPU. The mapping between trap IDs and trap
1032 * groups is configured using HPKT register.
1033 * Access: Index
1034 */
1035MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
1036
1037enum {
1038 MLXSW_REG_HTGT_POLICER_DISABLE,
1039 MLXSW_REG_HTGT_POLICER_ENABLE,
1040};
1041
1042/* reg_htgt_pide
1043 * Enable policer ID specified using 'pid' field.
1044 * Access: RW
1045 */
1046MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
1047
1048/* reg_htgt_pid
1049 * Policer ID for the trap group.
1050 * Access: RW
1051 */
1052MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
1053
1054#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
1055
1056/* reg_htgt_mirror_action
1057 * Mirror action to use.
1058 * 0 - Trap to CPU.
1059 * 1 - Trap to CPU and mirror to a mirroring agent.
1060 * 2 - Mirror to a mirroring agent and do not trap to CPU.
1061 * Access: RW
1062 *
1063 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
1064 */
1065MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
1066
1067/* reg_htgt_mirroring_agent
1068 * Mirroring agent.
1069 * Access: RW
1070 */
1071MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
1072
1073/* reg_htgt_priority
1074 * Trap group priority.
1075 * In case a packet matches multiple classification rules, the packet will
1076 * only be trapped once, based on the trap ID associated with the group (via
1077 * register HPKT) with the highest priority.
1078 * Supported values are 0-7, with 7 represnting the highest priority.
1079 * Access: RW
1080 *
1081 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
1082 * by the 'trap_group' field.
1083 */
1084MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
1085
1086/* reg_htgt_local_path_cpu_tclass
1087 * CPU ingress traffic class for the trap group.
1088 * Access: RW
1089 */
1090MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1091
1092#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
1093#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
1094
1095/* reg_htgt_local_path_rdq
1096 * Receive descriptor queue (RDQ) to use for the trap group.
1097 * Access: RW
1098 */
1099MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
1100
1101static inline void mlxsw_reg_htgt_pack(char *payload, u8 trap_group)
1102{
1103 u8 swid, rdq;
1104
1105 MLXSW_REG_ZERO(htgt, payload);
1106 if (MLXSW_REG_HTGT_TRAP_GROUP_EMAD == trap_group) {
1107 swid = MLXSW_PORT_SWID_ALL_SWIDS;
1108 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
1109 } else {
1110 swid = 0;
1111 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
1112 }
1113 mlxsw_reg_htgt_swid_set(payload, swid);
1114 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
1115 mlxsw_reg_htgt_trap_group_set(payload, trap_group);
1116 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
1117 mlxsw_reg_htgt_pid_set(payload, 0);
1118 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
1119 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
1120 mlxsw_reg_htgt_priority_set(payload, 0);
1121 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
1122 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
1123}
1124
1125/* HPKT - Host Packet Trap
1126 * -----------------------
1127 * Configures trap IDs inside trap groups.
1128 */
1129#define MLXSW_REG_HPKT_ID 0x7003
1130#define MLXSW_REG_HPKT_LEN 0x10
1131
1132static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
1133 .id = MLXSW_REG_HPKT_ID,
1134 .len = MLXSW_REG_HPKT_LEN,
1135};
1136
1137enum {
1138 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
1139 MLXSW_REG_HPKT_ACK_REQUIRED,
1140};
1141
1142/* reg_hpkt_ack
1143 * Require acknowledgements from the host for events.
1144 * If set, then the device will wait for the event it sent to be acknowledged
1145 * by the host. This option is only relevant for event trap IDs.
1146 * Access: RW
1147 *
1148 * Note: Currently not supported by firmware.
1149 */
1150MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
1151
1152enum mlxsw_reg_hpkt_action {
1153 MLXSW_REG_HPKT_ACTION_FORWARD,
1154 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1155 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
1156 MLXSW_REG_HPKT_ACTION_DISCARD,
1157 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
1158 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
1159};
1160
1161/* reg_hpkt_action
1162 * Action to perform on packet when trapped.
1163 * 0 - No action. Forward to CPU based on switching rules.
1164 * 1 - Trap to CPU (CPU receives sole copy).
1165 * 2 - Mirror to CPU (CPU receives a replica of the packet).
1166 * 3 - Discard.
1167 * 4 - Soft discard (allow other traps to act on the packet).
1168 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
1169 * Access: RW
1170 *
1171 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
1172 * addressed to the CPU.
1173 */
1174MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
1175
1176/* reg_hpkt_trap_group
1177 * Trap group to associate the trap with.
1178 * Access: RW
1179 */
1180MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
1181
1182/* reg_hpkt_trap_id
1183 * Trap ID.
1184 * Access: Index
1185 *
1186 * Note: A trap ID can only be associated with a single trap group. The device
1187 * will associate the trap ID with the last trap group configured.
1188 */
1189MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
1190
1191enum {
1192 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
1193 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
1194 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
1195};
1196
1197/* reg_hpkt_ctrl
1198 * Configure dedicated buffer resources for control packets.
1199 * 0 - Keep factory defaults.
1200 * 1 - Do not use control buffer for this trap ID.
1201 * 2 - Use control buffer for this trap ID.
1202 * Access: RW
1203 */
1204MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
1205
1206static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action,
1207 u8 trap_group, u16 trap_id)
1208{
1209 MLXSW_REG_ZERO(hpkt, payload);
1210 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
1211 mlxsw_reg_hpkt_action_set(payload, action);
1212 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
1213 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
1214 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
1215}
1216
1217static inline const char *mlxsw_reg_id_str(u16 reg_id)
1218{
1219 switch (reg_id) {
1220 case MLXSW_REG_SGCR_ID:
1221 return "SGCR";
1222 case MLXSW_REG_SPAD_ID:
1223 return "SPAD";
e61011b5
IS		 1224 case MLXSW_REG_SSPR_ID:
1225 return "SSPR";
4ec14b76
IS		 1226 case MLXSW_REG_SPMS_ID:
1227 return "SPMS";
1228 case MLXSW_REG_SFGC_ID:
1229 return "SFGC";
1230 case MLXSW_REG_SFTR_ID:
1231 return "SFTR";
1232 case MLXSW_REG_SPMLR_ID:
1233 return "SPMLR";
1234 case MLXSW_REG_PMLP_ID:
1235 return "PMLP";
1236 case MLXSW_REG_PMTU_ID:
1237 return "PMTU";
1238 case MLXSW_REG_PTYS_ID:
1239 return "PTYS";
1240 case MLXSW_REG_PPAD_ID:
1241 return "PPAD";
1242 case MLXSW_REG_PAOS_ID:
1243 return "PAOS";
1244 case MLXSW_REG_PPCNT_ID:
1245 return "PPCNT";
1246 case MLXSW_REG_PSPA_ID:
1247 return "PSPA";
1248 case MLXSW_REG_HTGT_ID:
1249 return "HTGT";
1250 case MLXSW_REG_HPKT_ID:
1251 return "HPKT";
1252 default:
1253 return "*UNKNOWN*";
1254 }
1255}
1256
1257/* PUDE - Port Up / Down Event
1258 * ---------------------------
1259 * Reports the operational state change of a port.
1260 */
1261#define MLXSW_REG_PUDE_LEN 0x10
1262
1263/* reg_pude_swid
1264 * Switch partition ID with which to associate the port.
1265 * Access: Index
1266 */
1267MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
1268
1269/* reg_pude_local_port
1270 * Local port number.
1271 * Access: Index
1272 */
1273MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
1274
1275/* reg_pude_admin_status
1276 * Port administrative state (the desired state).
1277 * 1 - Up.
1278 * 2 - Down.
1279 * 3 - Up once. This means that in case of link failure, the port won't go
1280 * into polling mode, but will wait to be re-enabled by software.
1281 * 4 - Disabled by system. Can only be set by hardware.
1282 * Access: RO
1283 */
1284MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
1285
1286/* reg_pude_oper_status
1287 * Port operatioanl state.
1288 * 1 - Up.
1289 * 2 - Down.
1290 * 3 - Down by port failure. This means that the device will not let the
1291 * port up again until explicitly specified by software.
1292 * Access: RO
1293 */
1294MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
1295
1296#endif
Linux kernel - Deliverables
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