projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mlxsw: reg: Add QoS ETS Element Configuration register
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlxsw / reg.h
CommitLineData
4ec14b76
IS		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_REG_H
38#define _MLXSW_REG_H
39
40#include <linux/string.h>
41#include <linux/bitops.h>
42#include <linux/if_vlan.h>
43
44#include "item.h"
45#include "port.h"
46
47struct mlxsw_reg_info {
48 u16 id;
49 u16 len; /* In u8 */
50};
51
52#define MLXSW_REG(type) (&mlxsw_reg_##type)
53#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
54#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
55
56/* SGCR - Switch General Configuration Register
57 * --------------------------------------------
58 * This register is used for configuration of the switch capabilities.
59 */
60#define MLXSW_REG_SGCR_ID 0x2000
61#define MLXSW_REG_SGCR_LEN 0x10
62
63static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
64 .id = MLXSW_REG_SGCR_ID,
65 .len = MLXSW_REG_SGCR_LEN,
66};
67
68/* reg_sgcr_llb
69 * Link Local Broadcast (Default=0)
70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
71 * packets and ignore the IGMP snooping entries.
72 * Access: RW
73 */
74MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
75
76static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
77{
78 MLXSW_REG_ZERO(sgcr, payload);
79 mlxsw_reg_sgcr_llb_set(payload, !!llb);
80}
81
82/* SPAD - Switch Physical Address Register
83 * ---------------------------------------
84 * The SPAD register configures the switch physical MAC address.
85 */
86#define MLXSW_REG_SPAD_ID 0x2002
87#define MLXSW_REG_SPAD_LEN 0x10
88
89static const struct mlxsw_reg_info mlxsw_reg_spad = {
90 .id = MLXSW_REG_SPAD_ID,
91 .len = MLXSW_REG_SPAD_LEN,
92};
93
94/* reg_spad_base_mac
95 * Base MAC address for the switch partitions.
96 * Per switch partition MAC address is equal to:
97 * base_mac + swid
98 * Access: RW
99 */
100MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
101
fabe5483
ER		 102/* SMID - Switch Multicast ID
103 * --------------------------
104 * The MID record maps from a MID (Multicast ID), which is a unique identifier
105 * of the multicast group within the stacking domain, into a list of local
106 * ports into which the packet is replicated.
107 */
108#define MLXSW_REG_SMID_ID 0x2007
109#define MLXSW_REG_SMID_LEN 0x240
110
111static const struct mlxsw_reg_info mlxsw_reg_smid = {
112 .id = MLXSW_REG_SMID_ID,
113 .len = MLXSW_REG_SMID_LEN,
114};
115
116/* reg_smid_swid
117 * Switch partition ID.
118 * Access: Index
119 */
120MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
121
122/* reg_smid_mid
123 * Multicast identifier - global identifier that represents the multicast group
124 * across all devices.
125 * Access: Index
126 */
127MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
128
129/* reg_smid_port
130 * Local port memebership (1 bit per port).
131 * Access: RW
132 */
133MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
134
135/* reg_smid_port_mask
136 * Local port mask (1 bit per port).
137 * Access: W
138 */
139MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
140
141static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
142 u8 port, bool set)
143{
144 MLXSW_REG_ZERO(smid, payload);
145 mlxsw_reg_smid_swid_set(payload, 0);
146 mlxsw_reg_smid_mid_set(payload, mid);
147 mlxsw_reg_smid_port_set(payload, port, set);
148 mlxsw_reg_smid_port_mask_set(payload, port, 1);
149}
150
e61011b5
IS		 151/* SSPR - Switch System Port Record Register
152 * -----------------------------------------
153 * Configures the system port to local port mapping.
154 */
155#define MLXSW_REG_SSPR_ID 0x2008
156#define MLXSW_REG_SSPR_LEN 0x8
157
158static const struct mlxsw_reg_info mlxsw_reg_sspr = {
159 .id = MLXSW_REG_SSPR_ID,
160 .len = MLXSW_REG_SSPR_LEN,
161};
162
163/* reg_sspr_m
164 * Master - if set, then the record describes the master system port.
165 * This is needed in case a local port is mapped into several system ports
166 * (for multipathing). That number will be reported as the source system
167 * port when packets are forwarded to the CPU. Only one master port is allowed
168 * per local port.
169 *
170 * Note: Must be set for Spectrum.
171 * Access: RW
172 */
173MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
174
175/* reg_sspr_local_port
176 * Local port number.
177 *
178 * Access: RW
179 */
180MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
181
182/* reg_sspr_sub_port
183 * Virtual port within the physical port.
184 * Should be set to 0 when virtual ports are not enabled on the port.
185 *
186 * Access: RW
187 */
188MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
189
190/* reg_sspr_system_port
191 * Unique identifier within the stacking domain that represents all the ports
192 * that are available in the system (external ports).
193 *
194 * Currently, only single-ASIC configurations are supported, so we default to
195 * 1:1 mapping between system ports and local ports.
196 * Access: Index
197 */
198MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
199
200static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
201{
202 MLXSW_REG_ZERO(sspr, payload);
203 mlxsw_reg_sspr_m_set(payload, 1);
204 mlxsw_reg_sspr_local_port_set(payload, local_port);
205 mlxsw_reg_sspr_sub_port_set(payload, 0);
206 mlxsw_reg_sspr_system_port_set(payload, local_port);
207}
208
e534a56a
JP		 209/* SFDAT - Switch Filtering Database Aging Time
210 * --------------------------------------------
211 * Controls the Switch aging time. Aging time is able to be set per Switch
212 * Partition.
213 */
214#define MLXSW_REG_SFDAT_ID 0x2009
215#define MLXSW_REG_SFDAT_LEN 0x8
216
217static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
218 .id = MLXSW_REG_SFDAT_ID,
219 .len = MLXSW_REG_SFDAT_LEN,
220};
221
222/* reg_sfdat_swid
223 * Switch partition ID.
224 * Access: Index
225 */
226MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
227
228/* reg_sfdat_age_time
229 * Aging time in seconds
230 * Min - 10 seconds
231 * Max - 1,000,000 seconds
232 * Default is 300 seconds.
233 * Access: RW
234 */
235MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
236
237static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
238{
239 MLXSW_REG_ZERO(sfdat, payload);
240 mlxsw_reg_sfdat_swid_set(payload, 0);
241 mlxsw_reg_sfdat_age_time_set(payload, age_time);
242}
243
236033b3
JP		 244/* SFD - Switch Filtering Database
245 * -------------------------------
246 * The following register defines the access to the filtering database.
247 * The register supports querying, adding, removing and modifying the database.
248 * The access is optimized for bulk updates in which case more than one
249 * FDB record is present in the same command.
250 */
251#define MLXSW_REG_SFD_ID 0x200A
252#define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
253#define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
254#define MLXSW_REG_SFD_REC_MAX_COUNT 64
255#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
256 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
257
258static const struct mlxsw_reg_info mlxsw_reg_sfd = {
259 .id = MLXSW_REG_SFD_ID,
260 .len = MLXSW_REG_SFD_LEN,
261};
262
263/* reg_sfd_swid
264 * Switch partition ID for queries. Reserved on Write.
265 * Access: Index
266 */
267MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
268
269enum mlxsw_reg_sfd_op {
270 /* Dump entire FDB a (process according to record_locator) */
271 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
272 /* Query records by {MAC, VID/FID} value */
273 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
274 /* Query and clear activity. Query records by {MAC, VID/FID} value */
275 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
276 /* Test. Response indicates if each of the records could be
277 * added to the FDB.
278 */
279 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
280 /* Add/modify. Aged-out records cannot be added. This command removes
281 * the learning notification of the {MAC, VID/FID}. Response includes
282 * the entries that were added to the FDB.
283 */
284 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
285 /* Remove record by {MAC, VID/FID}. This command also removes
286 * the learning notification and aged-out notifications
287 * of the {MAC, VID/FID}. The response provides current (pre-removal)
288 * entries as non-aged-out.
289 */
290 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
291 /* Remove learned notification by {MAC, VID/FID}. The response provides
292 * the removed learning notification.
293 */
294 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
295};
296
297/* reg_sfd_op
298 * Operation.
299 * Access: OP
300 */
301MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
302
303/* reg_sfd_record_locator
304 * Used for querying the FDB. Use record_locator=0 to initiate the
305 * query. When a record is returned, a new record_locator is
306 * returned to be used in the subsequent query.
307 * Reserved for database update.
308 * Access: Index
309 */
310MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
311
312/* reg_sfd_num_rec
313 * Request: Number of records to read/add/modify/remove
314 * Response: Number of records read/added/replaced/removed
315 * See above description for more details.
316 * Ranges 0..64
317 * Access: RW
318 */
319MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
320
321static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
322 u32 record_locator)
323{
324 MLXSW_REG_ZERO(sfd, payload);
325 mlxsw_reg_sfd_op_set(payload, op);
326 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
327}
328
329/* reg_sfd_rec_swid
330 * Switch partition ID.
331 * Access: Index
332 */
333MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
334 MLXSW_REG_SFD_REC_LEN, 0x00, false);
335
336enum mlxsw_reg_sfd_rec_type {
337 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
e4bfbae2 338 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
5230b25f 339 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
236033b3
JP		 340};
341
342/* reg_sfd_rec_type
343 * FDB record type.
344 * Access: RW
345 */
346MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
347 MLXSW_REG_SFD_REC_LEN, 0x00, false);
348
349enum mlxsw_reg_sfd_rec_policy {
350 /* Replacement disabled, aging disabled. */
351 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
352 /* (mlag remote): Replacement enabled, aging disabled,
353 * learning notification enabled on this port.
354 */
355 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
356 /* (ingress device): Replacement enabled, aging enabled. */
357 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
358};
359
360/* reg_sfd_rec_policy
361 * Policy.
362 * Access: RW
363 */
364MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
365 MLXSW_REG_SFD_REC_LEN, 0x00, false);
366
367/* reg_sfd_rec_a
368 * Activity. Set for new static entries. Set for static entries if a frame SMAC
369 * lookup hits on the entry.
370 * To clear the a bit, use "query and clear activity" op.
371 * Access: RO
372 */
373MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
374 MLXSW_REG_SFD_REC_LEN, 0x00, false);
375
376/* reg_sfd_rec_mac
377 * MAC address.
378 * Access: Index
379 */
380MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
381 MLXSW_REG_SFD_REC_LEN, 0x02);
382
383enum mlxsw_reg_sfd_rec_action {
384 /* forward */
385 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
386 /* forward and trap, trap_id is FDB_TRAP */
387 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
388 /* trap and do not forward, trap_id is FDB_TRAP */
389 MLXSW_REG_SFD_REC_ACTION_TRAP = 3,
390 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
391};
392
393/* reg_sfd_rec_action
394 * Action to apply on the packet.
395 * Note: Dynamic entries can only be configured with NOP action.
396 * Access: RW
397 */
398MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
399 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
400
401/* reg_sfd_uc_sub_port
4e9ec083
JP		 402 * VEPA channel on local port.
403 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
404 * VEPA is not enabled.
236033b3
JP		 405 * Access: RW
406 */
407MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
408 MLXSW_REG_SFD_REC_LEN, 0x08, false);
409
410/* reg_sfd_uc_fid_vid
411 * Filtering ID or VLAN ID
412 * For SwitchX and SwitchX-2:
413 * - Dynamic entries (policy 2,3) use FID
414 * - Static entries (policy 0) use VID
415 * - When independent learning is configured, VID=FID
416 * For Spectrum: use FID for both Dynamic and Static entries.
417 * VID should not be used.
418 * Access: Index
419 */
420MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
421 MLXSW_REG_SFD_REC_LEN, 0x08, false);
422
423/* reg_sfd_uc_system_port
424 * Unique port identifier for the final destination of the packet.
425 * Access: RW
426 */
427MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
428 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
429
e4bfbae2
JP		 430static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
431 enum mlxsw_reg_sfd_rec_type rec_type,
e4bfbae2
JP		 432 const char *mac,
433 enum mlxsw_reg_sfd_rec_action action)
236033b3
JP		 434{
435 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
436
437 if (rec_index >= num_rec)
438 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
439 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
e4bfbae2 440 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
236033b3 441 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
e4bfbae2
JP		 442 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
443}
444
445static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
446 enum mlxsw_reg_sfd_rec_policy policy,
9de6a80e 447 const char *mac, u16 fid_vid,
e4bfbae2
JP		 448 enum mlxsw_reg_sfd_rec_action action,
449 u8 local_port)
450{
451 mlxsw_reg_sfd_rec_pack(payload, rec_index,
5230b25f
ER		 452 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
453 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
236033b3 454 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
9de6a80e 455 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
236033b3
JP		 456 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
457}
458
75c09280 459static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
9de6a80e 460 char *mac, u16 *p_fid_vid,
75c09280 461 u8 *p_local_port)
236033b3
JP		 462{
463 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
9de6a80e 464 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
236033b3
JP		 465 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
466}
467
e4bfbae2
JP		 468/* reg_sfd_uc_lag_sub_port
469 * LAG sub port.
470 * Must be 0 if multichannel VEPA is not enabled.
471 * Access: RW
472 */
473MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
474 MLXSW_REG_SFD_REC_LEN, 0x08, false);
475
476/* reg_sfd_uc_lag_fid_vid
477 * Filtering ID or VLAN ID
478 * For SwitchX and SwitchX-2:
479 * - Dynamic entries (policy 2,3) use FID
480 * - Static entries (policy 0) use VID
481 * - When independent learning is configured, VID=FID
482 * For Spectrum: use FID for both Dynamic and Static entries.
483 * VID should not be used.
484 * Access: Index
485 */
486MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
487 MLXSW_REG_SFD_REC_LEN, 0x08, false);
488
afd7f979
IS		 489/* reg_sfd_uc_lag_lag_vid
490 * Indicates VID in case of vFIDs. Reserved for FIDs.
491 * Access: RW
492 */
493MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
494 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
495
e4bfbae2
JP		 496/* reg_sfd_uc_lag_lag_id
497 * LAG Identifier - pointer into the LAG descriptor table.
498 * Access: RW
499 */
500MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
501 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
502
503static inline void
504mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
505 enum mlxsw_reg_sfd_rec_policy policy,
9de6a80e 506 const char *mac, u16 fid_vid,
afd7f979 507 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
e4bfbae2
JP		 508 u16 lag_id)
509{
510 mlxsw_reg_sfd_rec_pack(payload, rec_index,
511 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
5230b25f
ER		 512 mac, action);
513 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
e4bfbae2 514 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
9de6a80e 515 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
afd7f979 516 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
e4bfbae2
JP		 517 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
518}
519
520static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
521 char *mac, u16 *p_vid,
522 u16 *p_lag_id)
523{
524 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
525 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
526 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
527}
528
5230b25f
ER		 529/* reg_sfd_mc_pgi
530 *
531 * Multicast port group index - index into the port group table.
532 * Value 0x1FFF indicates the pgi should point to the MID entry.
533 * For Spectrum this value must be set to 0x1FFF
534 * Access: RW
535 */
536MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
537 MLXSW_REG_SFD_REC_LEN, 0x08, false);
538
539/* reg_sfd_mc_fid_vid
540 *
541 * Filtering ID or VLAN ID
542 * Access: Index
543 */
544MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
545 MLXSW_REG_SFD_REC_LEN, 0x08, false);
546
547/* reg_sfd_mc_mid
548 *
549 * Multicast identifier - global identifier that represents the multicast
550 * group across all devices.
551 * Access: RW
552 */
553MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
554 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
555
556static inline void
557mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
558 const char *mac, u16 fid_vid,
559 enum mlxsw_reg_sfd_rec_action action, u16 mid)
560{
561 mlxsw_reg_sfd_rec_pack(payload, rec_index,
562 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
563 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
564 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
565 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
566}
567
f5d88f58
JP		 568/* SFN - Switch FDB Notification Register
569 * -------------------------------------------
570 * The switch provides notifications on newly learned FDB entries and
571 * aged out entries. The notifications can be polled by software.
572 */
573#define MLXSW_REG_SFN_ID 0x200B
574#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
575#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
576#define MLXSW_REG_SFN_REC_MAX_COUNT 64
577#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
578 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
579
580static const struct mlxsw_reg_info mlxsw_reg_sfn = {
581 .id = MLXSW_REG_SFN_ID,
582 .len = MLXSW_REG_SFN_LEN,
583};
584
585/* reg_sfn_swid
586 * Switch partition ID.
587 * Access: Index
588 */
589MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
590
591/* reg_sfn_num_rec
592 * Request: Number of learned notifications and aged-out notification
593 * records requested.
594 * Response: Number of notification records returned (must be smaller
595 * than or equal to the value requested)
596 * Ranges 0..64
597 * Access: OP
598 */
599MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
600
601static inline void mlxsw_reg_sfn_pack(char *payload)
602{
603 MLXSW_REG_ZERO(sfn, payload);
604 mlxsw_reg_sfn_swid_set(payload, 0);
605 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
606}
607
608/* reg_sfn_rec_swid
609 * Switch partition ID.
610 * Access: RO
611 */
612MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
613 MLXSW_REG_SFN_REC_LEN, 0x00, false);
614
615enum mlxsw_reg_sfn_rec_type {
616 /* MAC addresses learned on a regular port. */
617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
3b71571c
JP		 618 /* MAC addresses learned on a LAG port. */
619 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
620 /* Aged-out MAC address on a regular port. */
f5d88f58 621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
3b71571c
JP		 622 /* Aged-out MAC address on a LAG port. */
623 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
f5d88f58
JP		 624};
625
626/* reg_sfn_rec_type
627 * Notification record type.
628 * Access: RO
629 */
630MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
631 MLXSW_REG_SFN_REC_LEN, 0x00, false);
632
633/* reg_sfn_rec_mac
634 * MAC address.
635 * Access: RO
636 */
637MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
638 MLXSW_REG_SFN_REC_LEN, 0x02);
639
8316f087 640/* reg_sfn_mac_sub_port
f5d88f58
JP		 641 * VEPA channel on the local port.
642 * 0 if multichannel VEPA is not enabled.
643 * Access: RO
644 */
645MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
646 MLXSW_REG_SFN_REC_LEN, 0x08, false);
647
8316f087 648/* reg_sfn_mac_fid
f5d88f58
JP		 649 * Filtering identifier.
650 * Access: RO
651 */
652MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
653 MLXSW_REG_SFN_REC_LEN, 0x08, false);
654
8316f087 655/* reg_sfn_mac_system_port
f5d88f58
JP		 656 * Unique port identifier for the final destination of the packet.
657 * Access: RO
658 */
659MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
660 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
661
662static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
663 char *mac, u16 *p_vid,
664 u8 *p_local_port)
665{
666 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
667 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
668 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
669}
670
3b71571c
JP		 671/* reg_sfn_mac_lag_lag_id
672 * LAG ID (pointer into the LAG descriptor table).
673 * Access: RO
674 */
675MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
676 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
677
678static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
679 char *mac, u16 *p_vid,
680 u16 *p_lag_id)
681{
682 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
683 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
684 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
685}
686
4ec14b76
IS		 687/* SPMS - Switch Port MSTP/RSTP State Register
688 * -------------------------------------------
689 * Configures the spanning tree state of a physical port.
690 */
3f0effd1 691#define MLXSW_REG_SPMS_ID 0x200D
4ec14b76
IS		 692#define MLXSW_REG_SPMS_LEN 0x404
693
694static const struct mlxsw_reg_info mlxsw_reg_spms = {
695 .id = MLXSW_REG_SPMS_ID,
696 .len = MLXSW_REG_SPMS_LEN,
697};
698
699/* reg_spms_local_port
700 * Local port number.
701 * Access: Index
702 */
703MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
704
705enum mlxsw_reg_spms_state {
706 MLXSW_REG_SPMS_STATE_NO_CHANGE,
707 MLXSW_REG_SPMS_STATE_DISCARDING,
708 MLXSW_REG_SPMS_STATE_LEARNING,
709 MLXSW_REG_SPMS_STATE_FORWARDING,
710};
711
712/* reg_spms_state
713 * Spanning tree state of each VLAN ID (VID) of the local port.
714 * 0 - Do not change spanning tree state (used only when writing).
715 * 1 - Discarding. No learning or forwarding to/from this port (default).
716 * 2 - Learning. Port is learning, but not forwarding.
717 * 3 - Forwarding. Port is learning and forwarding.
718 * Access: RW
719 */
720MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
721
ebb7963f 722static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
4ec14b76
IS		 723{
724 MLXSW_REG_ZERO(spms, payload);
725 mlxsw_reg_spms_local_port_set(payload, local_port);
ebb7963f
JP		 726}
727
728static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
729 enum mlxsw_reg_spms_state state)
730{
4ec14b76
IS		 731 mlxsw_reg_spms_state_set(payload, vid, state);
732}
733
b2e345f9
ER		 734/* SPVID - Switch Port VID
735 * -----------------------
736 * The switch port VID configures the default VID for a port.
737 */
738#define MLXSW_REG_SPVID_ID 0x200E
739#define MLXSW_REG_SPVID_LEN 0x08
740
741static const struct mlxsw_reg_info mlxsw_reg_spvid = {
742 .id = MLXSW_REG_SPVID_ID,
743 .len = MLXSW_REG_SPVID_LEN,
744};
745
746/* reg_spvid_local_port
747 * Local port number.
748 * Access: Index
749 */
750MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
751
752/* reg_spvid_sub_port
753 * Virtual port within the physical port.
754 * Should be set to 0 when virtual ports are not enabled on the port.
755 * Access: Index
756 */
757MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
758
759/* reg_spvid_pvid
760 * Port default VID
761 * Access: RW
762 */
763MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
764
765static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
766{
767 MLXSW_REG_ZERO(spvid, payload);
768 mlxsw_reg_spvid_local_port_set(payload, local_port);
769 mlxsw_reg_spvid_pvid_set(payload, pvid);
770}
771
772/* SPVM - Switch Port VLAN Membership
773 * ----------------------------------
774 * The Switch Port VLAN Membership register configures the VLAN membership
775 * of a port in a VLAN denoted by VID. VLAN membership is managed per
776 * virtual port. The register can be used to add and remove VID(s) from a port.
777 */
778#define MLXSW_REG_SPVM_ID 0x200F
779#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
780#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
781#define MLXSW_REG_SPVM_REC_MAX_COUNT 256
782#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
783 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
784
785static const struct mlxsw_reg_info mlxsw_reg_spvm = {
786 .id = MLXSW_REG_SPVM_ID,
787 .len = MLXSW_REG_SPVM_LEN,
788};
789
790/* reg_spvm_pt
791 * Priority tagged. If this bit is set, packets forwarded to the port with
792 * untagged VLAN membership (u bit is set) will be tagged with priority tag
793 * (VID=0)
794 * Access: RW
795 */
796MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
797
798/* reg_spvm_pte
799 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
800 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
801 * Access: WO
802 */
803MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
804
805/* reg_spvm_local_port
806 * Local port number.
807 * Access: Index
808 */
809MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
810
811/* reg_spvm_sub_port
812 * Virtual port within the physical port.
813 * Should be set to 0 when virtual ports are not enabled on the port.
814 * Access: Index
815 */
816MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
817
818/* reg_spvm_num_rec
819 * Number of records to update. Each record contains: i, e, u, vid.
820 * Access: OP
821 */
822MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
823
824/* reg_spvm_rec_i
825 * Ingress membership in VLAN ID.
826 * Access: Index
827 */
828MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
829 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
830 MLXSW_REG_SPVM_REC_LEN, 0, false);
831
832/* reg_spvm_rec_e
833 * Egress membership in VLAN ID.
834 * Access: Index
835 */
836MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
837 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
838 MLXSW_REG_SPVM_REC_LEN, 0, false);
839
840/* reg_spvm_rec_u
841 * Untagged - port is an untagged member - egress transmission uses untagged
842 * frames on VID<n>
843 * Access: Index
844 */
845MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
846 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
847 MLXSW_REG_SPVM_REC_LEN, 0, false);
848
849/* reg_spvm_rec_vid
850 * Egress membership in VLAN ID.
851 * Access: Index
852 */
853MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
854 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
855 MLXSW_REG_SPVM_REC_LEN, 0, false);
856
857static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
858 u16 vid_begin, u16 vid_end,
859 bool is_member, bool untagged)
860{
861 int size = vid_end - vid_begin + 1;
862 int i;
863
864 MLXSW_REG_ZERO(spvm, payload);
865 mlxsw_reg_spvm_local_port_set(payload, local_port);
866 mlxsw_reg_spvm_num_rec_set(payload, size);
867
868 for (i = 0; i < size; i++) {
869 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
870 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
871 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
872 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
873 }
874}
875
148f472d
IS		 876/* SPAFT - Switch Port Acceptable Frame Types
877 * ------------------------------------------
878 * The Switch Port Acceptable Frame Types register configures the frame
879 * admittance of the port.
880 */
881#define MLXSW_REG_SPAFT_ID 0x2010
882#define MLXSW_REG_SPAFT_LEN 0x08
883
884static const struct mlxsw_reg_info mlxsw_reg_spaft = {
885 .id = MLXSW_REG_SPAFT_ID,
886 .len = MLXSW_REG_SPAFT_LEN,
887};
888
889/* reg_spaft_local_port
890 * Local port number.
891 * Access: Index
892 *
893 * Note: CPU port is not supported (all tag types are allowed).
894 */
895MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
896
897/* reg_spaft_sub_port
898 * Virtual port within the physical port.
899 * Should be set to 0 when virtual ports are not enabled on the port.
900 * Access: RW
901 */
902MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
903
904/* reg_spaft_allow_untagged
905 * When set, untagged frames on the ingress are allowed (default).
906 * Access: RW
907 */
908MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
909
910/* reg_spaft_allow_prio_tagged
911 * When set, priority tagged frames on the ingress are allowed (default).
912 * Access: RW
913 */
914MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
915
916/* reg_spaft_allow_tagged
917 * When set, tagged frames on the ingress are allowed (default).
918 * Access: RW
919 */
920MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
921
922static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
923 bool allow_untagged)
924{
925 MLXSW_REG_ZERO(spaft, payload);
926 mlxsw_reg_spaft_local_port_set(payload, local_port);
927 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
928 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
929 mlxsw_reg_spaft_allow_tagged_set(payload, true);
930}
931
4ec14b76
IS		 932/* SFGC - Switch Flooding Group Configuration
933 * ------------------------------------------
934 * The following register controls the association of flooding tables and MIDs
935 * to packet types used for flooding.
936 */
36b78e8a 937#define MLXSW_REG_SFGC_ID 0x2011
4ec14b76
IS		 938#define MLXSW_REG_SFGC_LEN 0x10
939
940static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
941 .id = MLXSW_REG_SFGC_ID,
942 .len = MLXSW_REG_SFGC_LEN,
943};
944
945enum mlxsw_reg_sfgc_type {
fa6ad058
IS		 946 MLXSW_REG_SFGC_TYPE_BROADCAST,
947 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
948 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
949 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
950 MLXSW_REG_SFGC_TYPE_RESERVED,
951 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
952 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
953 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
954 MLXSW_REG_SFGC_TYPE_MAX,
4ec14b76
IS		 955};
956
957/* reg_sfgc_type
958 * The traffic type to reach the flooding table.
959 * Access: Index
960 */
961MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
962
963enum mlxsw_reg_sfgc_bridge_type {
964 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
965 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
966};
967
968/* reg_sfgc_bridge_type
969 * Access: Index
970 *
971 * Note: SwitchX-2 only supports 802.1Q mode.
972 */
973MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
974
975enum mlxsw_flood_table_type {
976 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
977 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
978 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
979 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
980 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
981};
982
983/* reg_sfgc_table_type
984 * See mlxsw_flood_table_type
985 * Access: RW
986 *
987 * Note: FID offset and FID types are not supported in SwitchX-2.
988 */
989MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
990
991/* reg_sfgc_flood_table
992 * Flooding table index to associate with the specific type on the specific
993 * switch partition.
994 * Access: RW
995 */
996MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
997
998/* reg_sfgc_mid
999 * The multicast ID for the swid. Not supported for Spectrum
1000 * Access: RW
1001 */
1002MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1003
1004/* reg_sfgc_counter_set_type
1005 * Counter Set Type for flow counters.
1006 * Access: RW
1007 */
1008MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1009
1010/* reg_sfgc_counter_index
1011 * Counter Index for flow counters.
1012 * Access: RW
1013 */
1014MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1015
1016static inline void
1017mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1018 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1019 enum mlxsw_flood_table_type table_type,
1020 unsigned int flood_table)
1021{
1022 MLXSW_REG_ZERO(sfgc, payload);
1023 mlxsw_reg_sfgc_type_set(payload, type);
1024 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1025 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1026 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1027 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1028}
1029
1030/* SFTR - Switch Flooding Table Register
1031 * -------------------------------------
1032 * The switch flooding table is used for flooding packet replication. The table
1033 * defines a bit mask of ports for packet replication.
1034 */
1035#define MLXSW_REG_SFTR_ID 0x2012
1036#define MLXSW_REG_SFTR_LEN 0x420
1037
1038static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1039 .id = MLXSW_REG_SFTR_ID,
1040 .len = MLXSW_REG_SFTR_LEN,
1041};
1042
1043/* reg_sftr_swid
1044 * Switch partition ID with which to associate the port.
1045 * Access: Index
1046 */
1047MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1048
1049/* reg_sftr_flood_table
1050 * Flooding table index to associate with the specific type on the specific
1051 * switch partition.
1052 * Access: Index
1053 */
1054MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1055
1056/* reg_sftr_index
1057 * Index. Used as an index into the Flooding Table in case the table is
1058 * configured to use VID / FID or FID Offset.
1059 * Access: Index
1060 */
1061MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1062
1063/* reg_sftr_table_type
1064 * See mlxsw_flood_table_type
1065 * Access: RW
1066 */
1067MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1068
1069/* reg_sftr_range
1070 * Range of entries to update
1071 * Access: Index
1072 */
1073MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1074
1075/* reg_sftr_port
1076 * Local port membership (1 bit per port).
1077 * Access: RW
1078 */
1079MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1080
1081/* reg_sftr_cpu_port_mask
1082 * CPU port mask (1 bit per port).
1083 * Access: W
1084 */
1085MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1086
1087static inline void mlxsw_reg_sftr_pack(char *payload,
1088 unsigned int flood_table,
1089 unsigned int index,
1090 enum mlxsw_flood_table_type table_type,
bc2055f8 1091 unsigned int range, u8 port, bool set)
4ec14b76
IS		 1092{
1093 MLXSW_REG_ZERO(sftr, payload);
1094 mlxsw_reg_sftr_swid_set(payload, 0);
1095 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1096 mlxsw_reg_sftr_index_set(payload, index);
1097 mlxsw_reg_sftr_table_type_set(payload, table_type);
1098 mlxsw_reg_sftr_range_set(payload, range);
bc2055f8
IS		 1099 mlxsw_reg_sftr_port_set(payload, port, set);
1100 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
4ec14b76
IS		 1101}
1102
41933271
IS		 1103/* SFDF - Switch Filtering DB Flush
1104 * --------------------------------
1105 * The switch filtering DB flush register is used to flush the FDB.
1106 * Note that FDB notifications are flushed as well.
1107 */
1108#define MLXSW_REG_SFDF_ID 0x2013
1109#define MLXSW_REG_SFDF_LEN 0x14
1110
1111static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1112 .id = MLXSW_REG_SFDF_ID,
1113 .len = MLXSW_REG_SFDF_LEN,
1114};
1115
1116/* reg_sfdf_swid
1117 * Switch partition ID.
1118 * Access: Index
1119 */
1120MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1121
1122enum mlxsw_reg_sfdf_flush_type {
1123 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1124 MLXSW_REG_SFDF_FLUSH_PER_FID,
1125 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1126 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1127 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1128 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1129};
1130
1131/* reg_sfdf_flush_type
1132 * Flush type.
1133 * 0 - All SWID dynamic entries are flushed.
1134 * 1 - All FID dynamic entries are flushed.
1135 * 2 - All dynamic entries pointing to port are flushed.
1136 * 3 - All FID dynamic entries pointing to port are flushed.
1137 * 4 - All dynamic entries pointing to LAG are flushed.
1138 * 5 - All FID dynamic entries pointing to LAG are flushed.
1139 * Access: RW
1140 */
1141MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1142
1143/* reg_sfdf_flush_static
1144 * Static.
1145 * 0 - Flush only dynamic entries.
1146 * 1 - Flush both dynamic and static entries.
1147 * Access: RW
1148 */
1149MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1150
1151static inline void mlxsw_reg_sfdf_pack(char *payload,
1152 enum mlxsw_reg_sfdf_flush_type type)
1153{
1154 MLXSW_REG_ZERO(sfdf, payload);
1155 mlxsw_reg_sfdf_flush_type_set(payload, type);
1156 mlxsw_reg_sfdf_flush_static_set(payload, true);
1157}
1158
1159/* reg_sfdf_fid
1160 * FID to flush.
1161 * Access: RW
1162 */
1163MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1164
1165/* reg_sfdf_system_port
1166 * Port to flush.
1167 * Access: RW
1168 */
1169MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1170
1171/* reg_sfdf_port_fid_system_port
1172 * Port to flush, pointed to by FID.
1173 * Access: RW
1174 */
1175MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1176
1177/* reg_sfdf_lag_id
1178 * LAG ID to flush.
1179 * Access: RW
1180 */
1181MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1182
1183/* reg_sfdf_lag_fid_lag_id
1184 * LAG ID to flush, pointed to by FID.
1185 * Access: RW
1186 */
1187MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1188
d1d40be0
JP		 1189/* SLDR - Switch LAG Descriptor Register
1190 * -----------------------------------------
1191 * The switch LAG descriptor register is populated by LAG descriptors.
1192 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1193 * max_lag-1.
1194 */
1195#define MLXSW_REG_SLDR_ID 0x2014
1196#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1197
1198static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1199 .id = MLXSW_REG_SLDR_ID,
1200 .len = MLXSW_REG_SLDR_LEN,
1201};
1202
1203enum mlxsw_reg_sldr_op {
1204 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1205 MLXSW_REG_SLDR_OP_LAG_CREATE,
1206 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1207 /* Ports that appear in the list have the Distributor enabled */
1208 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1209 /* Removes ports from the disributor list */
1210 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1211};
1212
1213/* reg_sldr_op
1214 * Operation.
1215 * Access: RW
1216 */
1217MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1218
1219/* reg_sldr_lag_id
1220 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1221 * Access: Index
1222 */
1223MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1224
1225static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1226{
1227 MLXSW_REG_ZERO(sldr, payload);
1228 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1229 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1230}
1231
1232static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1233{
1234 MLXSW_REG_ZERO(sldr, payload);
1235 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1236 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1237}
1238
1239/* reg_sldr_num_ports
1240 * The number of member ports of the LAG.
1241 * Reserved for Create / Destroy operations
1242 * For Add / Remove operations - indicates the number of ports in the list.
1243 * Access: RW
1244 */
1245MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1246
1247/* reg_sldr_system_port
1248 * System port.
1249 * Access: RW
1250 */
1251MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1252
1253static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1254 u8 local_port)
1255{
1256 MLXSW_REG_ZERO(sldr, payload);
1257 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1258 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1259 mlxsw_reg_sldr_num_ports_set(payload, 1);
1260 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1261}
1262
1263static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1264 u8 local_port)
1265{
1266 MLXSW_REG_ZERO(sldr, payload);
1267 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1268 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1269 mlxsw_reg_sldr_num_ports_set(payload, 1);
1270 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1271}
1272
1273/* SLCR - Switch LAG Configuration 2 Register
1274 * -------------------------------------------
1275 * The Switch LAG Configuration register is used for configuring the
1276 * LAG properties of the switch.
1277 */
1278#define MLXSW_REG_SLCR_ID 0x2015
1279#define MLXSW_REG_SLCR_LEN 0x10
1280
1281static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1282 .id = MLXSW_REG_SLCR_ID,
1283 .len = MLXSW_REG_SLCR_LEN,
1284};
1285
1286enum mlxsw_reg_slcr_pp {
1287 /* Global Configuration (for all ports) */
1288 MLXSW_REG_SLCR_PP_GLOBAL,
1289 /* Per port configuration, based on local_port field */
1290 MLXSW_REG_SLCR_PP_PER_PORT,
1291};
1292
1293/* reg_slcr_pp
1294 * Per Port Configuration
1295 * Note: Reading at Global mode results in reading port 1 configuration.
1296 * Access: Index
1297 */
1298MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1299
1300/* reg_slcr_local_port
1301 * Local port number
1302 * Supported from CPU port
1303 * Not supported from router port
1304 * Reserved when pp = Global Configuration
1305 * Access: Index
1306 */
1307MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1308
1309enum mlxsw_reg_slcr_type {
1310 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1311 MLXSW_REG_SLCR_TYPE_XOR,
1312 MLXSW_REG_SLCR_TYPE_RANDOM,
1313};
1314
1315/* reg_slcr_type
1316 * Hash type
1317 * Access: RW
1318 */
1319MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1320
1321/* Ingress port */
1322#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1323/* SMAC - for IPv4 and IPv6 packets */
1324#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1325/* SMAC - for non-IP packets */
1326#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1327#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1328 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1329 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1330/* DMAC - for IPv4 and IPv6 packets */
1331#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1332/* DMAC - for non-IP packets */
1333#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1334#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1335 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1336 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1337/* Ethertype - for IPv4 and IPv6 packets */
1338#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1339/* Ethertype - for non-IP packets */
1340#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1341#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1342 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1343 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1344/* VLAN ID - for IPv4 and IPv6 packets */
1345#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1346/* VLAN ID - for non-IP packets */
1347#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1348#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1349 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1350 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1351/* Source IP address (can be IPv4 or IPv6) */
1352#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1353/* Destination IP address (can be IPv4 or IPv6) */
1354#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1355/* TCP/UDP source port */
1356#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1357/* TCP/UDP destination port*/
1358#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1359/* IPv4 Protocol/IPv6 Next Header */
1360#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1361/* IPv6 Flow label */
1362#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1363/* SID - FCoE source ID */
1364#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1365/* DID - FCoE destination ID */
1366#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1367/* OXID - FCoE originator exchange ID */
1368#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1369/* Destination QP number - for RoCE packets */
1370#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1371
1372/* reg_slcr_lag_hash
1373 * LAG hashing configuration. This is a bitmask, in which each set
1374 * bit includes the corresponding item in the LAG hash calculation.
1375 * The default lag_hash contains SMAC, DMAC, VLANID and
1376 * Ethertype (for all packet types).
1377 * Access: RW
1378 */
1379MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1380
1381static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1382{
1383 MLXSW_REG_ZERO(slcr, payload);
1384 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1385 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1386 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1387}
1388
1389/* SLCOR - Switch LAG Collector Register
1390 * -------------------------------------
1391 * The Switch LAG Collector register controls the Local Port membership
1392 * in a LAG and enablement of the collector.
1393 */
1394#define MLXSW_REG_SLCOR_ID 0x2016
1395#define MLXSW_REG_SLCOR_LEN 0x10
1396
1397static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1398 .id = MLXSW_REG_SLCOR_ID,
1399 .len = MLXSW_REG_SLCOR_LEN,
1400};
1401
1402enum mlxsw_reg_slcor_col {
1403 /* Port is added with collector disabled */
1404 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1405 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1406 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1407 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1408};
1409
1410/* reg_slcor_col
1411 * Collector configuration
1412 * Access: RW
1413 */
1414MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1415
1416/* reg_slcor_local_port
1417 * Local port number
1418 * Not supported for CPU port
1419 * Access: Index
1420 */
1421MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1422
1423/* reg_slcor_lag_id
1424 * LAG Identifier. Index into the LAG descriptor table.
1425 * Access: Index
1426 */
1427MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1428
1429/* reg_slcor_port_index
1430 * Port index in the LAG list. Only valid on Add Port to LAG col.
1431 * Valid range is from 0 to cap_max_lag_members-1
1432 * Access: RW
1433 */
1434MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1435
1436static inline void mlxsw_reg_slcor_pack(char *payload,
1437 u8 local_port, u16 lag_id,
1438 enum mlxsw_reg_slcor_col col)
1439{
1440 MLXSW_REG_ZERO(slcor, payload);
1441 mlxsw_reg_slcor_col_set(payload, col);
1442 mlxsw_reg_slcor_local_port_set(payload, local_port);
1443 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1444}
1445
1446static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1447 u8 local_port, u16 lag_id,
1448 u8 port_index)
1449{
1450 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1451 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1452 mlxsw_reg_slcor_port_index_set(payload, port_index);
1453}
1454
1455static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1456 u8 local_port, u16 lag_id)
1457{
1458 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1459 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1460}
1461
1462static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1463 u8 local_port, u16 lag_id)
1464{
1465 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1466 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1467}
1468
1469static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1470 u8 local_port, u16 lag_id)
1471{
1472 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1474}
1475
4ec14b76
IS		 1476/* SPMLR - Switch Port MAC Learning Register
1477 * -----------------------------------------
1478 * Controls the Switch MAC learning policy per port.
1479 */
1480#define MLXSW_REG_SPMLR_ID 0x2018
1481#define MLXSW_REG_SPMLR_LEN 0x8
1482
1483static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1484 .id = MLXSW_REG_SPMLR_ID,
1485 .len = MLXSW_REG_SPMLR_LEN,
1486};
1487
1488/* reg_spmlr_local_port
1489 * Local port number.
1490 * Access: Index
1491 */
1492MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1493
1494/* reg_spmlr_sub_port
1495 * Virtual port within the physical port.
1496 * Should be set to 0 when virtual ports are not enabled on the port.
1497 * Access: Index
1498 */
1499MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1500
1501enum mlxsw_reg_spmlr_learn_mode {
1502 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1503 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1504 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1505};
1506
1507/* reg_spmlr_learn_mode
1508 * Learning mode on the port.
1509 * 0 - Learning disabled.
1510 * 2 - Learning enabled.
1511 * 3 - Security mode.
1512 *
1513 * In security mode the switch does not learn MACs on the port, but uses the
1514 * SMAC to see if it exists on another ingress port. If so, the packet is
1515 * classified as a bad packet and is discarded unless the software registers
1516 * to receive port security error packets usign HPKT.
1517 */
1518MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1519
1520static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1521 enum mlxsw_reg_spmlr_learn_mode mode)
1522{
1523 MLXSW_REG_ZERO(spmlr, payload);
1524 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1525 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1526 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1527}
1528
64790239
IS		 1529/* SVFA - Switch VID to FID Allocation Register
1530 * --------------------------------------------
1531 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1532 * virtualized ports.
1533 */
1534#define MLXSW_REG_SVFA_ID 0x201C
1535#define MLXSW_REG_SVFA_LEN 0x10
1536
1537static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1538 .id = MLXSW_REG_SVFA_ID,
1539 .len = MLXSW_REG_SVFA_LEN,
1540};
1541
1542/* reg_svfa_swid
1543 * Switch partition ID.
1544 * Access: Index
1545 */
1546MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1547
1548/* reg_svfa_local_port
1549 * Local port number.
1550 * Access: Index
1551 *
1552 * Note: Reserved for 802.1Q FIDs.
1553 */
1554MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1555
1556enum mlxsw_reg_svfa_mt {
1557 MLXSW_REG_SVFA_MT_VID_TO_FID,
1558 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1559};
1560
1561/* reg_svfa_mapping_table
1562 * Mapping table:
1563 * 0 - VID to FID
1564 * 1 - {Port, VID} to FID
1565 * Access: Index
1566 *
1567 * Note: Reserved for SwitchX-2.
1568 */
1569MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1570
1571/* reg_svfa_v
1572 * Valid.
1573 * Valid if set.
1574 * Access: RW
1575 *
1576 * Note: Reserved for SwitchX-2.
1577 */
1578MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1579
1580/* reg_svfa_fid
1581 * Filtering ID.
1582 * Access: RW
1583 */
1584MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1585
1586/* reg_svfa_vid
1587 * VLAN ID.
1588 * Access: Index
1589 */
1590MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1591
1592/* reg_svfa_counter_set_type
1593 * Counter set type for flow counters.
1594 * Access: RW
1595 *
1596 * Note: Reserved for SwitchX-2.
1597 */
1598MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1599
1600/* reg_svfa_counter_index
1601 * Counter index for flow counters.
1602 * Access: RW
1603 *
1604 * Note: Reserved for SwitchX-2.
1605 */
1606MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1607
1608static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1609 enum mlxsw_reg_svfa_mt mt, bool valid,
1610 u16 fid, u16 vid)
1611{
1612 MLXSW_REG_ZERO(svfa, payload);
1613 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1614 mlxsw_reg_svfa_swid_set(payload, 0);
1615 mlxsw_reg_svfa_local_port_set(payload, local_port);
1616 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1617 mlxsw_reg_svfa_v_set(payload, valid);
1618 mlxsw_reg_svfa_fid_set(payload, fid);
1619 mlxsw_reg_svfa_vid_set(payload, vid);
1620}
1621
1f65da74
IS		 1622/* SVPE - Switch Virtual-Port Enabling Register
1623 * --------------------------------------------
1624 * Enables port virtualization.
1625 */
1626#define MLXSW_REG_SVPE_ID 0x201E
1627#define MLXSW_REG_SVPE_LEN 0x4
1628
1629static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1630 .id = MLXSW_REG_SVPE_ID,
1631 .len = MLXSW_REG_SVPE_LEN,
1632};
1633
1634/* reg_svpe_local_port
1635 * Local port number
1636 * Access: Index
1637 *
1638 * Note: CPU port is not supported (uses VLAN mode only).
1639 */
1640MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1641
1642/* reg_svpe_vp_en
1643 * Virtual port enable.
1644 * 0 - Disable, VLAN mode (VID to FID).
1645 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1646 * Access: RW
1647 */
1648MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1649
1650static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1651 bool enable)
1652{
1653 MLXSW_REG_ZERO(svpe, payload);
1654 mlxsw_reg_svpe_local_port_set(payload, local_port);
1655 mlxsw_reg_svpe_vp_en_set(payload, enable);
1656}
1657
f1fb693a
IS		 1658/* SFMR - Switch FID Management Register
1659 * -------------------------------------
1660 * Creates and configures FIDs.
1661 */
1662#define MLXSW_REG_SFMR_ID 0x201F
1663#define MLXSW_REG_SFMR_LEN 0x18
1664
1665static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1666 .id = MLXSW_REG_SFMR_ID,
1667 .len = MLXSW_REG_SFMR_LEN,
1668};
1669
1670enum mlxsw_reg_sfmr_op {
1671 MLXSW_REG_SFMR_OP_CREATE_FID,
1672 MLXSW_REG_SFMR_OP_DESTROY_FID,
1673};
1674
1675/* reg_sfmr_op
1676 * Operation.
1677 * 0 - Create or edit FID.
1678 * 1 - Destroy FID.
1679 * Access: WO
1680 */
1681MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1682
1683/* reg_sfmr_fid
1684 * Filtering ID.
1685 * Access: Index
1686 */
1687MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1688
1689/* reg_sfmr_fid_offset
1690 * FID offset.
1691 * Used to point into the flooding table selected by SFGC register if
1692 * the table is of type FID-Offset. Otherwise, this field is reserved.
1693 * Access: RW
1694 */
1695MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1696
1697/* reg_sfmr_vtfp
1698 * Valid Tunnel Flood Pointer.
1699 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1700 * Access: RW
1701 *
1702 * Note: Reserved for 802.1Q FIDs.
1703 */
1704MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1705
1706/* reg_sfmr_nve_tunnel_flood_ptr
1707 * Underlay Flooding and BC Pointer.
1708 * Used as a pointer to the first entry of the group based link lists of
1709 * flooding or BC entries (for NVE tunnels).
1710 * Access: RW
1711 */
1712MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1713
1714/* reg_sfmr_vv
1715 * VNI Valid.
1716 * If not set, then vni is reserved.
1717 * Access: RW
1718 *
1719 * Note: Reserved for 802.1Q FIDs.
1720 */
1721MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1722
1723/* reg_sfmr_vni
1724 * Virtual Network Identifier.
1725 * Access: RW
1726 *
1727 * Note: A given VNI can only be assigned to one FID.
1728 */
1729MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1730
1731static inline void mlxsw_reg_sfmr_pack(char *payload,
1732 enum mlxsw_reg_sfmr_op op, u16 fid,
1733 u16 fid_offset)
1734{
1735 MLXSW_REG_ZERO(sfmr, payload);
1736 mlxsw_reg_sfmr_op_set(payload, op);
1737 mlxsw_reg_sfmr_fid_set(payload, fid);
1738 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1739 mlxsw_reg_sfmr_vtfp_set(payload, false);
1740 mlxsw_reg_sfmr_vv_set(payload, false);
1741}
1742
a4feea74
IS		 1743/* SPVMLR - Switch Port VLAN MAC Learning Register
1744 * -----------------------------------------------
1745 * Controls the switch MAC learning policy per {Port, VID}.
1746 */
1747#define MLXSW_REG_SPVMLR_ID 0x2020
1748#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1749#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1750#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1751#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1752 MLXSW_REG_SPVMLR_REC_LEN * \
1753 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1754
1755static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1756 .id = MLXSW_REG_SPVMLR_ID,
1757 .len = MLXSW_REG_SPVMLR_LEN,
1758};
1759
1760/* reg_spvmlr_local_port
1761 * Local ingress port.
1762 * Access: Index
1763 *
1764 * Note: CPU port is not supported.
1765 */
1766MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1767
1768/* reg_spvmlr_num_rec
1769 * Number of records to update.
1770 * Access: OP
1771 */
1772MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1773
1774/* reg_spvmlr_rec_learn_enable
1775 * 0 - Disable learning for {Port, VID}.
1776 * 1 - Enable learning for {Port, VID}.
1777 * Access: RW
1778 */
1779MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1780 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1781
1782/* reg_spvmlr_rec_vid
1783 * VLAN ID to be added/removed from port or for querying.
1784 * Access: Index
1785 */
1786MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1787 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1788
1789static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1790 u16 vid_begin, u16 vid_end,
1791 bool learn_enable)
1792{
1793 int num_rec = vid_end - vid_begin + 1;
1794 int i;
1795
1796 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1797
1798 MLXSW_REG_ZERO(spvmlr, payload);
1799 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1800 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1801
1802 for (i = 0; i < num_rec; i++) {
1803 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1804 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1805 }
1806}
1807
b9b7cee4
IS		 1808/* QEEC - QoS ETS Element Configuration Register
1809 * ---------------------------------------------
1810 * Configures the ETS elements.
1811 */
1812#define MLXSW_REG_QEEC_ID 0x400D
1813#define MLXSW_REG_QEEC_LEN 0x1C
1814
1815static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1816 .id = MLXSW_REG_QEEC_ID,
1817 .len = MLXSW_REG_QEEC_LEN,
1818};
1819
1820/* reg_qeec_local_port
1821 * Local port number.
1822 * Access: Index
1823 *
1824 * Note: CPU port is supported.
1825 */
1826MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1827
1828enum mlxsw_reg_qeec_hr {
1829 MLXSW_REG_QEEC_HIERARCY_PORT,
1830 MLXSW_REG_QEEC_HIERARCY_GROUP,
1831 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1832 MLXSW_REG_QEEC_HIERARCY_TC,
1833};
1834
1835/* reg_qeec_element_hierarchy
1836 * 0 - Port
1837 * 1 - Group
1838 * 2 - Subgroup
1839 * 3 - Traffic Class
1840 * Access: Index
1841 */
1842MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1843
1844/* reg_qeec_element_index
1845 * The index of the element in the hierarchy.
1846 * Access: Index
1847 */
1848MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1849
1850/* reg_qeec_next_element_index
1851 * The index of the next (lower) element in the hierarchy.
1852 * Access: RW
1853 *
1854 * Note: Reserved for element_hierarchy 0.
1855 */
1856MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1857
1858enum {
1859 MLXSW_REG_QEEC_BYTES_MODE,
1860 MLXSW_REG_QEEC_PACKETS_MODE,
1861};
1862
1863/* reg_qeec_pb
1864 * Packets or bytes mode.
1865 * 0 - Bytes mode
1866 * 1 - Packets mode
1867 * Access: RW
1868 *
1869 * Note: Used for max shaper configuration. For Spectrum, packets mode
1870 * is supported only for traffic classes of CPU port.
1871 */
1872MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1873
1874/* reg_qeec_mase
1875 * Max shaper configuration enable. Enables configuration of the max
1876 * shaper on this ETS element.
1877 * 0 - Disable
1878 * 1 - Enable
1879 * Access: RW
1880 */
1881MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1882
1883/* A large max rate will disable the max shaper. */
1884#define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
1885
1886/* reg_qeec_max_shaper_rate
1887 * Max shaper information rate.
1888 * For CPU port, can only be configured for port hierarchy.
1889 * When in bytes mode, value is specified in units of 1000bps.
1890 * Access: RW
1891 */
1892MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1893
1894/* reg_qeec_de
1895 * DWRR configuration enable. Enables configuration of the dwrr and
1896 * dwrr_weight.
1897 * 0 - Disable
1898 * 1 - Enable
1899 * Access: RW
1900 */
1901MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1902
1903/* reg_qeec_dwrr
1904 * Transmission selection algorithm to use on the link going down from
1905 * the ETS element.
1906 * 0 - Strict priority
1907 * 1 - DWRR
1908 * Access: RW
1909 */
1910MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1911
1912/* reg_qeec_dwrr_weight
1913 * DWRR weight on the link going down from the ETS element. The
1914 * percentage of bandwidth guaranteed to an ETS element within
1915 * its hierarchy. The sum of all weights across all ETS elements
1916 * within one hierarchy should be equal to 100. Reserved when
1917 * transmission selection algorithm is strict priority.
1918 * Access: RW
1919 */
1920MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1921
1922static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1923 enum mlxsw_reg_qeec_hr hr, u8 index,
1924 u8 next_index)
1925{
1926 MLXSW_REG_ZERO(qeec, payload);
1927 mlxsw_reg_qeec_local_port_set(payload, local_port);
1928 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1929 mlxsw_reg_qeec_element_index_set(payload, index);
1930 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1931}
1932
4ec14b76
IS		 1933/* PMLP - Ports Module to Local Port Register
1934 * ------------------------------------------
1935 * Configures the assignment of modules to local ports.
1936 */
1937#define MLXSW_REG_PMLP_ID 0x5002
1938#define MLXSW_REG_PMLP_LEN 0x40
1939
1940static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1941 .id = MLXSW_REG_PMLP_ID,
1942 .len = MLXSW_REG_PMLP_LEN,
1943};
1944
1945/* reg_pmlp_rxtx
1946 * 0 - Tx value is used for both Tx and Rx.
1947 * 1 - Rx value is taken from a separte field.
1948 * Access: RW
1949 */
1950MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
1951
1952/* reg_pmlp_local_port
1953 * Local port number.
1954 * Access: Index
1955 */
1956MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
1957
1958/* reg_pmlp_width
1959 * 0 - Unmap local port.
1960 * 1 - Lane 0 is used.
1961 * 2 - Lanes 0 and 1 are used.
1962 * 4 - Lanes 0, 1, 2 and 3 are used.
1963 * Access: RW
1964 */
1965MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
1966
1967/* reg_pmlp_module
1968 * Module number.
1969 * Access: RW
1970 */
bbeeda27 1971MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4ec14b76
IS		 1972
1973/* reg_pmlp_tx_lane
1974 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
1975 * Access: RW
1976 */
bbeeda27 1977MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
4ec14b76
IS		 1978
1979/* reg_pmlp_rx_lane
1980 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
1981 * equal to Tx lane.
1982 * Access: RW
1983 */
bbeeda27 1984MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
4ec14b76
IS		 1985
1986static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
1987{
1988 MLXSW_REG_ZERO(pmlp, payload);
1989 mlxsw_reg_pmlp_local_port_set(payload, local_port);
1990}
1991
1992/* PMTU - Port MTU Register
1993 * ------------------------
1994 * Configures and reports the port MTU.
1995 */
1996#define MLXSW_REG_PMTU_ID 0x5003
1997#define MLXSW_REG_PMTU_LEN 0x10
1998
1999static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2000 .id = MLXSW_REG_PMTU_ID,
2001 .len = MLXSW_REG_PMTU_LEN,
2002};
2003
2004/* reg_pmtu_local_port
2005 * Local port number.
2006 * Access: Index
2007 */
2008MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2009
2010/* reg_pmtu_max_mtu
2011 * Maximum MTU.
2012 * When port type (e.g. Ethernet) is configured, the relevant MTU is
2013 * reported, otherwise the minimum between the max_mtu of the different
2014 * types is reported.
2015 * Access: RO
2016 */
2017MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2018
2019/* reg_pmtu_admin_mtu
2020 * MTU value to set port to. Must be smaller or equal to max_mtu.
2021 * Note: If port type is Infiniband, then port must be disabled, when its
2022 * MTU is set.
2023 * Access: RW
2024 */
2025MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2026
2027/* reg_pmtu_oper_mtu
2028 * The actual MTU configured on the port. Packets exceeding this size
2029 * will be dropped.
2030 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2031 * oper_mtu might be smaller than admin_mtu.
2032 * Access: RO
2033 */
2034MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2035
2036static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2037 u16 new_mtu)
2038{
2039 MLXSW_REG_ZERO(pmtu, payload);
2040 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2041 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2042 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2043 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2044}
2045
2046/* PTYS - Port Type and Speed Register
2047 * -----------------------------------
2048 * Configures and reports the port speed type.
2049 *
2050 * Note: When set while the link is up, the changes will not take effect
2051 * until the port transitions from down to up state.
2052 */
2053#define MLXSW_REG_PTYS_ID 0x5004
2054#define MLXSW_REG_PTYS_LEN 0x40
2055
2056static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2057 .id = MLXSW_REG_PTYS_ID,
2058 .len = MLXSW_REG_PTYS_LEN,
2059};
2060
2061/* reg_ptys_local_port
2062 * Local port number.
2063 * Access: Index
2064 */
2065MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2066
2067#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2068
2069/* reg_ptys_proto_mask
2070 * Protocol mask. Indicates which protocol is used.
2071 * 0 - Infiniband.
2072 * 1 - Fibre Channel.
2073 * 2 - Ethernet.
2074 * Access: Index
2075 */
2076MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2077
2078#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2079#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2080#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2081#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2082#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2083#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2084#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2085#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2086#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2087#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2088#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2089#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2090#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2091#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2092#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2093#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2094#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2095#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2096#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2097#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2098#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2099#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2100#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2101#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2102#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2103#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2104#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2105
2106/* reg_ptys_eth_proto_cap
2107 * Ethernet port supported speeds and protocols.
2108 * Access: RO
2109 */
2110MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2111
2112/* reg_ptys_eth_proto_admin
2113 * Speed and protocol to set port to.
2114 * Access: RW
2115 */
2116MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2117
2118/* reg_ptys_eth_proto_oper
2119 * The current speed and protocol configured for the port.
2120 * Access: RO
2121 */
2122MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2123
2124static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2125 u32 proto_admin)
2126{
2127 MLXSW_REG_ZERO(ptys, payload);
2128 mlxsw_reg_ptys_local_port_set(payload, local_port);
2129 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2130 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2131}
2132
2133static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2134 u32 *p_eth_proto_adm,
2135 u32 *p_eth_proto_oper)
2136{
2137 if (p_eth_proto_cap)
2138 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2139 if (p_eth_proto_adm)
2140 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2141 if (p_eth_proto_oper)
2142 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2143}
2144
2145/* PPAD - Port Physical Address Register
2146 * -------------------------------------
2147 * The PPAD register configures the per port physical MAC address.
2148 */
2149#define MLXSW_REG_PPAD_ID 0x5005
2150#define MLXSW_REG_PPAD_LEN 0x10
2151
2152static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2153 .id = MLXSW_REG_PPAD_ID,
2154 .len = MLXSW_REG_PPAD_LEN,
2155};
2156
2157/* reg_ppad_single_base_mac
2158 * 0: base_mac, local port should be 0 and mac[7:0] is
2159 * reserved. HW will set incremental
2160 * 1: single_mac - mac of the local_port
2161 * Access: RW
2162 */
2163MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2164
2165/* reg_ppad_local_port
2166 * port number, if single_base_mac = 0 then local_port is reserved
2167 * Access: RW
2168 */
2169MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2170
2171/* reg_ppad_mac
2172 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2173 * If single_base_mac = 1 - the per port MAC address
2174 * Access: RW
2175 */
2176MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2177
2178static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2179 u8 local_port)
2180{
2181 MLXSW_REG_ZERO(ppad, payload);
2182 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2183 mlxsw_reg_ppad_local_port_set(payload, local_port);
2184}
2185
2186/* PAOS - Ports Administrative and Operational Status Register
2187 * -----------------------------------------------------------
2188 * Configures and retrieves per port administrative and operational status.
2189 */
2190#define MLXSW_REG_PAOS_ID 0x5006
2191#define MLXSW_REG_PAOS_LEN 0x10
2192
2193static const struct mlxsw_reg_info mlxsw_reg_paos = {
2194 .id = MLXSW_REG_PAOS_ID,
2195 .len = MLXSW_REG_PAOS_LEN,
2196};
2197
2198/* reg_paos_swid
2199 * Switch partition ID with which to associate the port.
2200 * Note: while external ports uses unique local port numbers (and thus swid is
2201 * redundant), router ports use the same local port number where swid is the
2202 * only indication for the relevant port.
2203 * Access: Index
2204 */
2205MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2206
2207/* reg_paos_local_port
2208 * Local port number.
2209 * Access: Index
2210 */
2211MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2212
2213/* reg_paos_admin_status
2214 * Port administrative state (the desired state of the port):
2215 * 1 - Up.
2216 * 2 - Down.
2217 * 3 - Up once. This means that in case of link failure, the port won't go
2218 * into polling mode, but will wait to be re-enabled by software.
2219 * 4 - Disabled by system. Can only be set by hardware.
2220 * Access: RW
2221 */
2222MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2223
2224/* reg_paos_oper_status
2225 * Port operational state (the current state):
2226 * 1 - Up.
2227 * 2 - Down.
2228 * 3 - Down by port failure. This means that the device will not let the
2229 * port up again until explicitly specified by software.
2230 * Access: RO
2231 */
2232MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2233
2234/* reg_paos_ase
2235 * Admin state update enabled.
2236 * Access: WO
2237 */
2238MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2239
2240/* reg_paos_ee
2241 * Event update enable. If this bit is set, event generation will be
2242 * updated based on the e field.
2243 * Access: WO
2244 */
2245MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2246
2247/* reg_paos_e
2248 * Event generation on operational state change:
2249 * 0 - Do not generate event.
2250 * 1 - Generate Event.
2251 * 2 - Generate Single Event.
2252 * Access: RW
2253 */
2254MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2255
2256static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2257 enum mlxsw_port_admin_status status)
2258{
2259 MLXSW_REG_ZERO(paos, payload);
2260 mlxsw_reg_paos_swid_set(payload, 0);
2261 mlxsw_reg_paos_local_port_set(payload, local_port);
2262 mlxsw_reg_paos_admin_status_set(payload, status);
2263 mlxsw_reg_paos_oper_status_set(payload, 0);
2264 mlxsw_reg_paos_ase_set(payload, 1);
2265 mlxsw_reg_paos_ee_set(payload, 1);
2266 mlxsw_reg_paos_e_set(payload, 1);
2267}
2268
2269/* PPCNT - Ports Performance Counters Register
2270 * -------------------------------------------
2271 * The PPCNT register retrieves per port performance counters.
2272 */
2273#define MLXSW_REG_PPCNT_ID 0x5008
2274#define MLXSW_REG_PPCNT_LEN 0x100
2275
2276static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2277 .id = MLXSW_REG_PPCNT_ID,
2278 .len = MLXSW_REG_PPCNT_LEN,
2279};
2280
2281/* reg_ppcnt_swid
2282 * For HCA: must be always 0.
2283 * Switch partition ID to associate port with.
2284 * Switch partitions are numbered from 0 to 7 inclusively.
2285 * Switch partition 254 indicates stacking ports.
2286 * Switch partition 255 indicates all switch partitions.
2287 * Only valid on Set() operation with local_port=255.
2288 * Access: Index
2289 */
2290MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2291
2292/* reg_ppcnt_local_port
2293 * Local port number.
2294 * 255 indicates all ports on the device, and is only allowed
2295 * for Set() operation.
2296 * Access: Index
2297 */
2298MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2299
2300/* reg_ppcnt_pnat
2301 * Port number access type:
2302 * 0 - Local port number
2303 * 1 - IB port number
2304 * Access: Index
2305 */
2306MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2307
2308/* reg_ppcnt_grp
2309 * Performance counter group.
2310 * Group 63 indicates all groups. Only valid on Set() operation with
2311 * clr bit set.
2312 * 0x0: IEEE 802.3 Counters
2313 * 0x1: RFC 2863 Counters
2314 * 0x2: RFC 2819 Counters
2315 * 0x3: RFC 3635 Counters
2316 * 0x5: Ethernet Extended Counters
2317 * 0x8: Link Level Retransmission Counters
2318 * 0x10: Per Priority Counters
2319 * 0x11: Per Traffic Class Counters
2320 * 0x12: Physical Layer Counters
2321 * Access: Index
2322 */
2323MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2324
2325/* reg_ppcnt_clr
2326 * Clear counters. Setting the clr bit will reset the counter value
2327 * for all counters in the counter group. This bit can be set
2328 * for both Set() and Get() operation.
2329 * Access: OP
2330 */
2331MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2332
2333/* reg_ppcnt_prio_tc
2334 * Priority for counter set that support per priority, valid values: 0-7.
2335 * Traffic class for counter set that support per traffic class,
2336 * valid values: 0- cap_max_tclass-1 .
2337 * For HCA: cap_max_tclass is always 8.
2338 * Otherwise must be 0.
2339 * Access: Index
2340 */
2341MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2342
2343/* reg_ppcnt_a_frames_transmitted_ok
2344 * Access: RO
2345 */
2346MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2347 0x08 + 0x00, 0, 64);
2348
2349/* reg_ppcnt_a_frames_received_ok
2350 * Access: RO
2351 */
2352MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2353 0x08 + 0x08, 0, 64);
2354
2355/* reg_ppcnt_a_frame_check_sequence_errors
2356 * Access: RO
2357 */
2358MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2359 0x08 + 0x10, 0, 64);
2360
2361/* reg_ppcnt_a_alignment_errors
2362 * Access: RO
2363 */
2364MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2365 0x08 + 0x18, 0, 64);
2366
2367/* reg_ppcnt_a_octets_transmitted_ok
2368 * Access: RO
2369 */
2370MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2371 0x08 + 0x20, 0, 64);
2372
2373/* reg_ppcnt_a_octets_received_ok
2374 * Access: RO
2375 */
2376MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2377 0x08 + 0x28, 0, 64);
2378
2379/* reg_ppcnt_a_multicast_frames_xmitted_ok
2380 * Access: RO
2381 */
2382MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2383 0x08 + 0x30, 0, 64);
2384
2385/* reg_ppcnt_a_broadcast_frames_xmitted_ok
2386 * Access: RO
2387 */
2388MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2389 0x08 + 0x38, 0, 64);
2390
2391/* reg_ppcnt_a_multicast_frames_received_ok
2392 * Access: RO
2393 */
2394MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2395 0x08 + 0x40, 0, 64);
2396
2397/* reg_ppcnt_a_broadcast_frames_received_ok
2398 * Access: RO
2399 */
2400MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2401 0x08 + 0x48, 0, 64);
2402
2403/* reg_ppcnt_a_in_range_length_errors
2404 * Access: RO
2405 */
2406MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2407 0x08 + 0x50, 0, 64);
2408
2409/* reg_ppcnt_a_out_of_range_length_field
2410 * Access: RO
2411 */
2412MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2413 0x08 + 0x58, 0, 64);
2414
2415/* reg_ppcnt_a_frame_too_long_errors
2416 * Access: RO
2417 */
2418MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2419 0x08 + 0x60, 0, 64);
2420
2421/* reg_ppcnt_a_symbol_error_during_carrier
2422 * Access: RO
2423 */
2424MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2425 0x08 + 0x68, 0, 64);
2426
2427/* reg_ppcnt_a_mac_control_frames_transmitted
2428 * Access: RO
2429 */
2430MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2431 0x08 + 0x70, 0, 64);
2432
2433/* reg_ppcnt_a_mac_control_frames_received
2434 * Access: RO
2435 */
2436MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2437 0x08 + 0x78, 0, 64);
2438
2439/* reg_ppcnt_a_unsupported_opcodes_received
2440 * Access: RO
2441 */
2442MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2443 0x08 + 0x80, 0, 64);
2444
2445/* reg_ppcnt_a_pause_mac_ctrl_frames_received
2446 * Access: RO
2447 */
2448MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2449 0x08 + 0x88, 0, 64);
2450
2451/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2452 * Access: RO
2453 */
2454MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2455 0x08 + 0x90, 0, 64);
2456
2457static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
2458{
2459 MLXSW_REG_ZERO(ppcnt, payload);
2460 mlxsw_reg_ppcnt_swid_set(payload, 0);
2461 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2462 mlxsw_reg_ppcnt_pnat_set(payload, 0);
2463 mlxsw_reg_ppcnt_grp_set(payload, 0);
2464 mlxsw_reg_ppcnt_clr_set(payload, 0);
2465 mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
2466}
2467
b98ff151
IS		 2468/* PPTB - Port Prio To Buffer Register
2469 * -----------------------------------
2470 * Configures the switch priority to buffer table.
2471 */
2472#define MLXSW_REG_PPTB_ID 0x500B
2473#define MLXSW_REG_PPTB_LEN 0x0C
2474
2475static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2476 .id = MLXSW_REG_PPTB_ID,
2477 .len = MLXSW_REG_PPTB_LEN,
2478};
2479
2480enum {
2481 MLXSW_REG_PPTB_MM_UM,
2482 MLXSW_REG_PPTB_MM_UNICAST,
2483 MLXSW_REG_PPTB_MM_MULTICAST,
2484};
2485
2486/* reg_pptb_mm
2487 * Mapping mode.
2488 * 0 - Map both unicast and multicast packets to the same buffer.
2489 * 1 - Map only unicast packets.
2490 * 2 - Map only multicast packets.
2491 * Access: Index
2492 *
2493 * Note: SwitchX-2 only supports the first option.
2494 */
2495MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2496
2497/* reg_pptb_local_port
2498 * Local port number.
2499 * Access: Index
2500 */
2501MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2502
2503/* reg_pptb_um
2504 * Enables the update of the untagged_buf field.
2505 * Access: RW
2506 */
2507MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2508
2509/* reg_pptb_pm
2510 * Enables the update of the prio_to_buff field.
2511 * Bit <i> is a flag for updating the mapping for switch priority <i>.
2512 * Access: RW
2513 */
2514MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2515
2516/* reg_pptb_prio_to_buff
2517 * Mapping of switch priority <i> to one of the allocated receive port
2518 * buffers.
2519 * Access: RW
2520 */
2521MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2522
2523/* reg_pptb_pm_msb
2524 * Enables the update of the prio_to_buff field.
2525 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2526 * Access: RW
2527 */
2528MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2529
2530/* reg_pptb_untagged_buff
2531 * Mapping of untagged frames to one of the allocated receive port buffers.
2532 * Access: RW
2533 *
2534 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2535 * Spectrum, as it maps untagged packets based on the default switch priority.
2536 */
2537MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2538
2539#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2540
2541static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2542{
2543 MLXSW_REG_ZERO(pptb, payload);
2544 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2545 mlxsw_reg_pptb_local_port_set(payload, local_port);
2546 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2547}
2548
e0594369
JP		 2549/* PBMC - Port Buffer Management Control Register
2550 * ----------------------------------------------
2551 * The PBMC register configures and retrieves the port packet buffer
2552 * allocation for different Prios, and the Pause threshold management.
2553 */
2554#define MLXSW_REG_PBMC_ID 0x500C
7ad7cd61 2555#define MLXSW_REG_PBMC_LEN 0x6C
e0594369
JP		 2556
2557static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2558 .id = MLXSW_REG_PBMC_ID,
2559 .len = MLXSW_REG_PBMC_LEN,
2560};
2561
2562/* reg_pbmc_local_port
2563 * Local port number.
2564 * Access: Index
2565 */
2566MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2567
2568/* reg_pbmc_xoff_timer_value
2569 * When device generates a pause frame, it uses this value as the pause
2570 * timer (time for the peer port to pause in quota-512 bit time).
2571 * Access: RW
2572 */
2573MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2574
2575/* reg_pbmc_xoff_refresh
2576 * The time before a new pause frame should be sent to refresh the pause RW
2577 * state. Using the same units as xoff_timer_value above (in quota-512 bit
2578 * time).
2579 * Access: RW
2580 */
2581MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2582
d6b7c13b
IS		 2583#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2584
e0594369
JP		 2585/* reg_pbmc_buf_lossy
2586 * The field indicates if the buffer is lossy.
2587 * 0 - Lossless
2588 * 1 - Lossy
2589 * Access: RW
2590 */
2591MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2592
2593/* reg_pbmc_buf_epsb
2594 * Eligible for Port Shared buffer.
2595 * If epsb is set, packets assigned to buffer are allowed to insert the port
2596 * shared buffer.
2597 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2598 * Access: RW
2599 */
2600MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2601
2602/* reg_pbmc_buf_size
2603 * The part of the packet buffer array is allocated for the specific buffer.
2604 * Units are represented in cells.
2605 * Access: RW
2606 */
2607MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2608
2609static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2610 u16 xoff_timer_value, u16 xoff_refresh)
2611{
2612 MLXSW_REG_ZERO(pbmc, payload);
2613 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2614 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2615 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2616}
2617
2618static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2619 int buf_index,
2620 u16 size)
2621{
2622 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2623 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2624 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2625}
2626
4ec14b76
IS		 2627/* PSPA - Port Switch Partition Allocation
2628 * ---------------------------------------
2629 * Controls the association of a port with a switch partition and enables
2630 * configuring ports as stacking ports.
2631 */
3f0effd1 2632#define MLXSW_REG_PSPA_ID 0x500D
4ec14b76
IS		 2633#define MLXSW_REG_PSPA_LEN 0x8
2634
2635static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2636 .id = MLXSW_REG_PSPA_ID,
2637 .len = MLXSW_REG_PSPA_LEN,
2638};
2639
2640/* reg_pspa_swid
2641 * Switch partition ID.
2642 * Access: RW
2643 */
2644MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2645
2646/* reg_pspa_local_port
2647 * Local port number.
2648 * Access: Index
2649 */
2650MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2651
2652/* reg_pspa_sub_port
2653 * Virtual port within the local port. Set to 0 when virtual ports are
2654 * disabled on the local port.
2655 * Access: Index
2656 */
2657MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2658
2659static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2660{
2661 MLXSW_REG_ZERO(pspa, payload);
2662 mlxsw_reg_pspa_swid_set(payload, swid);
2663 mlxsw_reg_pspa_local_port_set(payload, local_port);
2664 mlxsw_reg_pspa_sub_port_set(payload, 0);
2665}
2666
2667/* HTGT - Host Trap Group Table
2668 * ----------------------------
2669 * Configures the properties for forwarding to CPU.
2670 */
2671#define MLXSW_REG_HTGT_ID 0x7002
2672#define MLXSW_REG_HTGT_LEN 0x100
2673
2674static const struct mlxsw_reg_info mlxsw_reg_htgt = {
2675 .id = MLXSW_REG_HTGT_ID,
2676 .len = MLXSW_REG_HTGT_LEN,
2677};
2678
2679/* reg_htgt_swid
2680 * Switch partition ID.
2681 * Access: Index
2682 */
2683MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
2684
2685#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
2686
2687/* reg_htgt_type
2688 * CPU path type.
2689 * Access: RW
2690 */
2691MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
2692
801bd3de
IS		 2693enum mlxsw_reg_htgt_trap_group {
2694 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
2695 MLXSW_REG_HTGT_TRAP_GROUP_RX,
2696 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
2697};
4ec14b76
IS		 2698
2699/* reg_htgt_trap_group
2700 * Trap group number. User defined number specifying which trap groups
2701 * should be forwarded to the CPU. The mapping between trap IDs and trap
2702 * groups is configured using HPKT register.
2703 * Access: Index
2704 */
2705MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
2706
2707enum {
2708 MLXSW_REG_HTGT_POLICER_DISABLE,
2709 MLXSW_REG_HTGT_POLICER_ENABLE,
2710};
2711
2712/* reg_htgt_pide
2713 * Enable policer ID specified using 'pid' field.
2714 * Access: RW
2715 */
2716MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
2717
2718/* reg_htgt_pid
2719 * Policer ID for the trap group.
2720 * Access: RW
2721 */
2722MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
2723
2724#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
2725
2726/* reg_htgt_mirror_action
2727 * Mirror action to use.
2728 * 0 - Trap to CPU.
2729 * 1 - Trap to CPU and mirror to a mirroring agent.
2730 * 2 - Mirror to a mirroring agent and do not trap to CPU.
2731 * Access: RW
2732 *
2733 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
2734 */
2735MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
2736
2737/* reg_htgt_mirroring_agent
2738 * Mirroring agent.
2739 * Access: RW
2740 */
2741MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
2742
2743/* reg_htgt_priority
2744 * Trap group priority.
2745 * In case a packet matches multiple classification rules, the packet will
2746 * only be trapped once, based on the trap ID associated with the group (via
2747 * register HPKT) with the highest priority.
2748 * Supported values are 0-7, with 7 represnting the highest priority.
2749 * Access: RW
2750 *
2751 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
2752 * by the 'trap_group' field.
2753 */
2754MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
2755
2756/* reg_htgt_local_path_cpu_tclass
2757 * CPU ingress traffic class for the trap group.
2758 * Access: RW
2759 */
2760MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
2761
2762#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
2763#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
801bd3de 2764#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
4ec14b76
IS		 2765
2766/* reg_htgt_local_path_rdq
2767 * Receive descriptor queue (RDQ) to use for the trap group.
2768 * Access: RW
2769 */
2770MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
2771
801bd3de
IS		 2772static inline void mlxsw_reg_htgt_pack(char *payload,
2773 enum mlxsw_reg_htgt_trap_group group)
4ec14b76
IS		 2774{
2775 u8 swid, rdq;
2776
2777 MLXSW_REG_ZERO(htgt, payload);
801bd3de
IS		 2778 switch (group) {
2779 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
4ec14b76
IS		 2780 swid = MLXSW_PORT_SWID_ALL_SWIDS;
2781 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
801bd3de
IS		 2782 break;
2783 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
4ec14b76
IS		 2784 swid = 0;
2785 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
801bd3de
IS		 2786 break;
2787 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
2788 swid = 0;
2789 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
2790 break;
4ec14b76
IS		 2791 }
2792 mlxsw_reg_htgt_swid_set(payload, swid);
2793 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
801bd3de 2794 mlxsw_reg_htgt_trap_group_set(payload, group);
4ec14b76
IS		 2795 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
2796 mlxsw_reg_htgt_pid_set(payload, 0);
2797 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
2798 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
2799 mlxsw_reg_htgt_priority_set(payload, 0);
2800 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
2801 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
2802}
2803
2804/* HPKT - Host Packet Trap
2805 * -----------------------
2806 * Configures trap IDs inside trap groups.
2807 */
2808#define MLXSW_REG_HPKT_ID 0x7003
2809#define MLXSW_REG_HPKT_LEN 0x10
2810
2811static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
2812 .id = MLXSW_REG_HPKT_ID,
2813 .len = MLXSW_REG_HPKT_LEN,
2814};
2815
2816enum {
2817 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
2818 MLXSW_REG_HPKT_ACK_REQUIRED,
2819};
2820
2821/* reg_hpkt_ack
2822 * Require acknowledgements from the host for events.
2823 * If set, then the device will wait for the event it sent to be acknowledged
2824 * by the host. This option is only relevant for event trap IDs.
2825 * Access: RW
2826 *
2827 * Note: Currently not supported by firmware.
2828 */
2829MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
2830
2831enum mlxsw_reg_hpkt_action {
2832 MLXSW_REG_HPKT_ACTION_FORWARD,
2833 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2834 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
2835 MLXSW_REG_HPKT_ACTION_DISCARD,
2836 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
2837 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
2838};
2839
2840/* reg_hpkt_action
2841 * Action to perform on packet when trapped.
2842 * 0 - No action. Forward to CPU based on switching rules.
2843 * 1 - Trap to CPU (CPU receives sole copy).
2844 * 2 - Mirror to CPU (CPU receives a replica of the packet).
2845 * 3 - Discard.
2846 * 4 - Soft discard (allow other traps to act on the packet).
2847 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
2848 * Access: RW
2849 *
2850 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
2851 * addressed to the CPU.
2852 */
2853MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
2854
2855/* reg_hpkt_trap_group
2856 * Trap group to associate the trap with.
2857 * Access: RW
2858 */
2859MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
2860
2861/* reg_hpkt_trap_id
2862 * Trap ID.
2863 * Access: Index
2864 *
2865 * Note: A trap ID can only be associated with a single trap group. The device
2866 * will associate the trap ID with the last trap group configured.
2867 */
2868MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
2869
2870enum {
2871 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
2872 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
2873 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
2874};
2875
2876/* reg_hpkt_ctrl
2877 * Configure dedicated buffer resources for control packets.
2878 * 0 - Keep factory defaults.
2879 * 1 - Do not use control buffer for this trap ID.
2880 * 2 - Use control buffer for this trap ID.
2881 * Access: RW
2882 */
2883MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
2884
f24af330 2885static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
4ec14b76 2886{
801bd3de 2887 enum mlxsw_reg_htgt_trap_group trap_group;
f24af330 2888
4ec14b76
IS		 2889 MLXSW_REG_ZERO(hpkt, payload);
2890 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
2891 mlxsw_reg_hpkt_action_set(payload, action);
f24af330
IS		 2892 switch (trap_id) {
2893 case MLXSW_TRAP_ID_ETHEMAD:
2894 case MLXSW_TRAP_ID_PUDE:
2895 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
2896 break;
2897 default:
2898 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
2899 break;
2900 }
4ec14b76
IS		 2901 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
2902 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
2903 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
2904}
2905
5246f2e2
JP		 2906/* MFCR - Management Fan Control Register
2907 * --------------------------------------
2908 * This register controls the settings of the Fan Speed PWM mechanism.
2909 */
2910#define MLXSW_REG_MFCR_ID 0x9001
2911#define MLXSW_REG_MFCR_LEN 0x08
2912
2913static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
2914 .id = MLXSW_REG_MFCR_ID,
2915 .len = MLXSW_REG_MFCR_LEN,
2916};
2917
2918enum mlxsw_reg_mfcr_pwm_frequency {
2919 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
2920 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
2921 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
2922 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
2923 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
2924 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
2925 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
2926 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
2927};
2928
2929/* reg_mfcr_pwm_frequency
2930 * Controls the frequency of the PWM signal.
2931 * Access: RW
2932 */
2933MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
2934
2935#define MLXSW_MFCR_TACHOS_MAX 10
2936
2937/* reg_mfcr_tacho_active
2938 * Indicates which of the tachometer is active (bit per tachometer).
2939 * Access: RO
2940 */
2941MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
2942
2943#define MLXSW_MFCR_PWMS_MAX 5
2944
2945/* reg_mfcr_pwm_active
2946 * Indicates which of the PWM control is active (bit per PWM).
2947 * Access: RO
2948 */
2949MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
2950
2951static inline void
2952mlxsw_reg_mfcr_pack(char *payload,
2953 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
2954{
2955 MLXSW_REG_ZERO(mfcr, payload);
2956 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
2957}
2958
2959static inline void
2960mlxsw_reg_mfcr_unpack(char *payload,
2961 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
2962 u16 *p_tacho_active, u8 *p_pwm_active)
2963{
2964 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
2965 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
2966 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
2967}
2968
2969/* MFSC - Management Fan Speed Control Register
2970 * --------------------------------------------
2971 * This register controls the settings of the Fan Speed PWM mechanism.
2972 */
2973#define MLXSW_REG_MFSC_ID 0x9002
2974#define MLXSW_REG_MFSC_LEN 0x08
2975
2976static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
2977 .id = MLXSW_REG_MFSC_ID,
2978 .len = MLXSW_REG_MFSC_LEN,
2979};
2980
2981/* reg_mfsc_pwm
2982 * Fan pwm to control / monitor.
2983 * Access: Index
2984 */
2985MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
2986
2987/* reg_mfsc_pwm_duty_cycle
2988 * Controls the duty cycle of the PWM. Value range from 0..255 to
2989 * represent duty cycle of 0%...100%.
2990 * Access: RW
2991 */
2992MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
2993
2994static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
2995 u8 pwm_duty_cycle)
2996{
2997 MLXSW_REG_ZERO(mfsc, payload);
2998 mlxsw_reg_mfsc_pwm_set(payload, pwm);
2999 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
3000}
3001
3002/* MFSM - Management Fan Speed Measurement
3003 * ---------------------------------------
3004 * This register controls the settings of the Tacho measurements and
3005 * enables reading the Tachometer measurements.
3006 */
3007#define MLXSW_REG_MFSM_ID 0x9003
3008#define MLXSW_REG_MFSM_LEN 0x08
3009
3010static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
3011 .id = MLXSW_REG_MFSM_ID,
3012 .len = MLXSW_REG_MFSM_LEN,
3013};
3014
3015/* reg_mfsm_tacho
3016 * Fan tachometer index.
3017 * Access: Index
3018 */
3019MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
3020
3021/* reg_mfsm_rpm
3022 * Fan speed (round per minute).
3023 * Access: RO
3024 */
3025MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
3026
3027static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
3028{
3029 MLXSW_REG_ZERO(mfsm, payload);
3030 mlxsw_reg_mfsm_tacho_set(payload, tacho);
3031}
3032
85926f87
JP		 3033/* MTCAP - Management Temperature Capabilities
3034 * -------------------------------------------
3035 * This register exposes the capabilities of the device and
3036 * system temperature sensing.
3037 */
3038#define MLXSW_REG_MTCAP_ID 0x9009
3039#define MLXSW_REG_MTCAP_LEN 0x08
3040
3041static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
3042 .id = MLXSW_REG_MTCAP_ID,
3043 .len = MLXSW_REG_MTCAP_LEN,
3044};
3045
3046/* reg_mtcap_sensor_count
3047 * Number of sensors supported by the device.
3048 * This includes the QSFP module sensors (if exists in the QSFP module).
3049 * Access: RO
3050 */
3051MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
3052
3053/* MTMP - Management Temperature
3054 * -----------------------------
3055 * This register controls the settings of the temperature measurements
3056 * and enables reading the temperature measurements. Note that temperature
3057 * is in 0.125 degrees Celsius.
3058 */
3059#define MLXSW_REG_MTMP_ID 0x900A
3060#define MLXSW_REG_MTMP_LEN 0x20
3061
3062static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
3063 .id = MLXSW_REG_MTMP_ID,
3064 .len = MLXSW_REG_MTMP_LEN,
3065};
3066
3067/* reg_mtmp_sensor_index
3068 * Sensors index to access.
3069 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
3070 * (module 0 is mapped to sensor_index 64).
3071 * Access: Index
3072 */
3073MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
3074
3075/* Convert to milli degrees Celsius */
3076#define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
3077
3078/* reg_mtmp_temperature
3079 * Temperature reading from the sensor. Reading is in 0.125 Celsius
3080 * degrees units.
3081 * Access: RO
3082 */
3083MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
3084
3085/* reg_mtmp_mte
3086 * Max Temperature Enable - enables measuring the max temperature on a sensor.
3087 * Access: RW
3088 */
3089MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
3090
3091/* reg_mtmp_mtr
3092 * Max Temperature Reset - clears the value of the max temperature register.
3093 * Access: WO
3094 */
3095MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
3096
3097/* reg_mtmp_max_temperature
3098 * The highest measured temperature from the sensor.
3099 * When the bit mte is cleared, the field max_temperature is reserved.
3100 * Access: RO
3101 */
3102MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
3103
3104#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
3105
3106/* reg_mtmp_sensor_name
3107 * Sensor Name
3108 * Access: RO
3109 */
3110MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
3111
3112static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
3113 bool max_temp_enable,
3114 bool max_temp_reset)
3115{
3116 MLXSW_REG_ZERO(mtmp, payload);
3117 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
3118 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
3119 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
3120}
3121
3122static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
3123 unsigned int *p_max_temp,
3124 char *sensor_name)
3125{
3126 u16 temp;
3127
3128 if (p_temp) {
3129 temp = mlxsw_reg_mtmp_temperature_get(payload);
3130 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
3131 }
3132 if (p_max_temp) {
acf35a4e 3133 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
85926f87
JP		 3134 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
3135 }
3136 if (sensor_name)
3137 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
3138}
3139
3161c159
IS		 3140/* MLCR - Management LED Control Register
3141 * --------------------------------------
3142 * Controls the system LEDs.
3143 */
3144#define MLXSW_REG_MLCR_ID 0x902B
3145#define MLXSW_REG_MLCR_LEN 0x0C
3146
3147static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
3148 .id = MLXSW_REG_MLCR_ID,
3149 .len = MLXSW_REG_MLCR_LEN,
3150};
3151
3152/* reg_mlcr_local_port
3153 * Local port number.
3154 * Access: RW
3155 */
3156MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
3157
3158#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
3159
3160/* reg_mlcr_beacon_duration
3161 * Duration of the beacon to be active, in seconds.
3162 * 0x0 - Will turn off the beacon.
3163 * 0xFFFF - Will turn on the beacon until explicitly turned off.
3164 * Access: RW
3165 */
3166MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
3167
3168/* reg_mlcr_beacon_remain
3169 * Remaining duration of the beacon, in seconds.
3170 * 0xFFFF indicates an infinite amount of time.
3171 * Access: RO
3172 */
3173MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
3174
3175static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
3176 bool active)
3177{
3178 MLXSW_REG_ZERO(mlcr, payload);
3179 mlxsw_reg_mlcr_local_port_set(payload, local_port);
3180 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
3181 MLXSW_REG_MLCR_DURATION_MAX : 0);
3182}
3183
e0594369
JP		 3184/* SBPR - Shared Buffer Pools Register
3185 * -----------------------------------
3186 * The SBPR configures and retrieves the shared buffer pools and configuration.
3187 */
3188#define MLXSW_REG_SBPR_ID 0xB001
3189#define MLXSW_REG_SBPR_LEN 0x14
3190
3191static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
3192 .id = MLXSW_REG_SBPR_ID,
3193 .len = MLXSW_REG_SBPR_LEN,
3194};
3195
3196enum mlxsw_reg_sbpr_dir {
3197 MLXSW_REG_SBPR_DIR_INGRESS,
3198 MLXSW_REG_SBPR_DIR_EGRESS,
3199};
3200
3201/* reg_sbpr_dir
3202 * Direction.
3203 * Access: Index
3204 */
3205MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
3206
3207/* reg_sbpr_pool
3208 * Pool index.
3209 * Access: Index
3210 */
3211MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
3212
3213/* reg_sbpr_size
3214 * Pool size in buffer cells.
3215 * Access: RW
3216 */
3217MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
3218
3219enum mlxsw_reg_sbpr_mode {
3220 MLXSW_REG_SBPR_MODE_STATIC,
3221 MLXSW_REG_SBPR_MODE_DYNAMIC,
3222};
3223
3224/* reg_sbpr_mode
3225 * Pool quota calculation mode.
3226 * Access: RW
3227 */
3228MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
3229
3230static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
3231 enum mlxsw_reg_sbpr_dir dir,
3232 enum mlxsw_reg_sbpr_mode mode, u32 size)
3233{
3234 MLXSW_REG_ZERO(sbpr, payload);
3235 mlxsw_reg_sbpr_pool_set(payload, pool);
3236 mlxsw_reg_sbpr_dir_set(payload, dir);
3237 mlxsw_reg_sbpr_mode_set(payload, mode);
3238 mlxsw_reg_sbpr_size_set(payload, size);
3239}
3240
3241/* SBCM - Shared Buffer Class Management Register
3242 * ----------------------------------------------
3243 * The SBCM register configures and retrieves the shared buffer allocation
3244 * and configuration according to Port-PG, including the binding to pool
3245 * and definition of the associated quota.
3246 */
3247#define MLXSW_REG_SBCM_ID 0xB002
3248#define MLXSW_REG_SBCM_LEN 0x28
3249
3250static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
3251 .id = MLXSW_REG_SBCM_ID,
3252 .len = MLXSW_REG_SBCM_LEN,
3253};
3254
3255/* reg_sbcm_local_port
3256 * Local port number.
3257 * For Ingress: excludes CPU port and Router port
3258 * For Egress: excludes IP Router
3259 * Access: Index
3260 */
3261MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
3262
3263/* reg_sbcm_pg_buff
3264 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
3265 * For PG buffer: range is 0..cap_max_pg_buffers - 1
3266 * For traffic class: range is 0..cap_max_tclass - 1
3267 * Note that when traffic class is in MC aware mode then the traffic
3268 * classes which are MC aware cannot be configured.
3269 * Access: Index
3270 */
3271MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
3272
3273enum mlxsw_reg_sbcm_dir {
3274 MLXSW_REG_SBCM_DIR_INGRESS,
3275 MLXSW_REG_SBCM_DIR_EGRESS,
3276};
3277
3278/* reg_sbcm_dir
3279 * Direction.
3280 * Access: Index
3281 */
3282MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
3283
3284/* reg_sbcm_min_buff
3285 * Minimum buffer size for the limiter, in cells.
3286 * Access: RW
3287 */
3288MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
3289
3290/* reg_sbcm_max_buff
3291 * When the pool associated to the port-pg/tclass is configured to
3292 * static, Maximum buffer size for the limiter configured in cells.
3293 * When the pool associated to the port-pg/tclass is configured to
3294 * dynamic, the max_buff holds the "alpha" parameter, supporting
3295 * the following values:
3296 * 0: 0
3297 * i: (1/128)*2^(i-1), for i=1..14
3298 * 0xFF: Infinity
3299 * Access: RW
3300 */
3301MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
3302
3303/* reg_sbcm_pool
3304 * Association of the port-priority to a pool.
3305 * Access: RW
3306 */
3307MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
3308
3309static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
3310 enum mlxsw_reg_sbcm_dir dir,
3311 u32 min_buff, u32 max_buff, u8 pool)
3312{
3313 MLXSW_REG_ZERO(sbcm, payload);
3314 mlxsw_reg_sbcm_local_port_set(payload, local_port);
3315 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
3316 mlxsw_reg_sbcm_dir_set(payload, dir);
3317 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
3318 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
3319 mlxsw_reg_sbcm_pool_set(payload, pool);
3320}
3321
3322/* SBPM - Shared Buffer Class Management Register
3323 * ----------------------------------------------
3324 * The SBPM register configures and retrieves the shared buffer allocation
3325 * and configuration according to Port-Pool, including the definition
3326 * of the associated quota.
3327 */
3328#define MLXSW_REG_SBPM_ID 0xB003
3329#define MLXSW_REG_SBPM_LEN 0x28
3330
3331static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
3332 .id = MLXSW_REG_SBPM_ID,
3333 .len = MLXSW_REG_SBPM_LEN,
3334};
3335
3336/* reg_sbpm_local_port
3337 * Local port number.
3338 * For Ingress: excludes CPU port and Router port
3339 * For Egress: excludes IP Router
3340 * Access: Index
3341 */
3342MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
3343
3344/* reg_sbpm_pool
3345 * The pool associated to quota counting on the local_port.
3346 * Access: Index
3347 */
3348MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
3349
3350enum mlxsw_reg_sbpm_dir {
3351 MLXSW_REG_SBPM_DIR_INGRESS,
3352 MLXSW_REG_SBPM_DIR_EGRESS,
3353};
3354
3355/* reg_sbpm_dir
3356 * Direction.
3357 * Access: Index
3358 */
3359MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
3360
3361/* reg_sbpm_min_buff
3362 * Minimum buffer size for the limiter, in cells.
3363 * Access: RW
3364 */
3365MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
3366
3367/* reg_sbpm_max_buff
3368 * When the pool associated to the port-pg/tclass is configured to
3369 * static, Maximum buffer size for the limiter configured in cells.
3370 * When the pool associated to the port-pg/tclass is configured to
3371 * dynamic, the max_buff holds the "alpha" parameter, supporting
3372 * the following values:
3373 * 0: 0
3374 * i: (1/128)*2^(i-1), for i=1..14
3375 * 0xFF: Infinity
3376 * Access: RW
3377 */
3378MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
3379
3380static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
3381 enum mlxsw_reg_sbpm_dir dir,
3382 u32 min_buff, u32 max_buff)
3383{
3384 MLXSW_REG_ZERO(sbpm, payload);
3385 mlxsw_reg_sbpm_local_port_set(payload, local_port);
3386 mlxsw_reg_sbpm_pool_set(payload, pool);
3387 mlxsw_reg_sbpm_dir_set(payload, dir);
3388 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
3389 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
3390}
3391
3392/* SBMM - Shared Buffer Multicast Management Register
3393 * --------------------------------------------------
3394 * The SBMM register configures and retrieves the shared buffer allocation
3395 * and configuration for MC packets according to Switch-Priority, including
3396 * the binding to pool and definition of the associated quota.
3397 */
3398#define MLXSW_REG_SBMM_ID 0xB004
3399#define MLXSW_REG_SBMM_LEN 0x28
3400
3401static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
3402 .id = MLXSW_REG_SBMM_ID,
3403 .len = MLXSW_REG_SBMM_LEN,
3404};
3405
3406/* reg_sbmm_prio
3407 * Switch Priority.
3408 * Access: Index
3409 */
3410MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
3411
3412/* reg_sbmm_min_buff
3413 * Minimum buffer size for the limiter, in cells.
3414 * Access: RW
3415 */
3416MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
3417
3418/* reg_sbmm_max_buff
3419 * When the pool associated to the port-pg/tclass is configured to
3420 * static, Maximum buffer size for the limiter configured in cells.
3421 * When the pool associated to the port-pg/tclass is configured to
3422 * dynamic, the max_buff holds the "alpha" parameter, supporting
3423 * the following values:
3424 * 0: 0
3425 * i: (1/128)*2^(i-1), for i=1..14
3426 * 0xFF: Infinity
3427 * Access: RW
3428 */
3429MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
3430
3431/* reg_sbmm_pool
3432 * Association of the port-priority to a pool.
3433 * Access: RW
3434 */
3435MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
3436
3437static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
3438 u32 max_buff, u8 pool)
3439{
3440 MLXSW_REG_ZERO(sbmm, payload);
3441 mlxsw_reg_sbmm_prio_set(payload, prio);
3442 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
3443 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
3444 mlxsw_reg_sbmm_pool_set(payload, pool);
3445}
3446
4ec14b76
IS		 3447static inline const char *mlxsw_reg_id_str(u16 reg_id)
3448{
3449 switch (reg_id) {
3450 case MLXSW_REG_SGCR_ID:
3451 return "SGCR";
3452 case MLXSW_REG_SPAD_ID:
3453 return "SPAD";
fabe5483
ER		 3454 case MLXSW_REG_SMID_ID:
3455 return "SMID";
e61011b5
IS		 3456 case MLXSW_REG_SSPR_ID:
3457 return "SSPR";
e534a56a
JP		 3458 case MLXSW_REG_SFDAT_ID:
3459 return "SFDAT";
236033b3
JP		 3460 case MLXSW_REG_SFD_ID:
3461 return "SFD";
f5d88f58
JP		 3462 case MLXSW_REG_SFN_ID:
3463 return "SFN";
4ec14b76
IS		 3464 case MLXSW_REG_SPMS_ID:
3465 return "SPMS";
b2e345f9
ER		 3466 case MLXSW_REG_SPVID_ID:
3467 return "SPVID";
3468 case MLXSW_REG_SPVM_ID:
3469 return "SPVM";
148f472d
IS		 3470 case MLXSW_REG_SPAFT_ID:
3471 return "SPAFT";
4ec14b76
IS		 3472 case MLXSW_REG_SFGC_ID:
3473 return "SFGC";
3474 case MLXSW_REG_SFTR_ID:
3475 return "SFTR";
41933271
IS		 3476 case MLXSW_REG_SFDF_ID:
3477 return "SFDF";
d1d40be0
JP		 3478 case MLXSW_REG_SLDR_ID:
3479 return "SLDR";
3480 case MLXSW_REG_SLCR_ID:
3481 return "SLCR";
3482 case MLXSW_REG_SLCOR_ID:
3483 return "SLCOR";
4ec14b76
IS		 3484 case MLXSW_REG_SPMLR_ID:
3485 return "SPMLR";
64790239
IS		 3486 case MLXSW_REG_SVFA_ID:
3487 return "SVFA";
1f65da74
IS		 3488 case MLXSW_REG_SVPE_ID:
3489 return "SVPE";
f1fb693a
IS		 3490 case MLXSW_REG_SFMR_ID:
3491 return "SFMR";
a4feea74
IS		 3492 case MLXSW_REG_SPVMLR_ID:
3493 return "SPVMLR";
b9b7cee4
IS		 3494 case MLXSW_REG_QEEC_ID:
3495 return "QEEC";
4ec14b76
IS		 3496 case MLXSW_REG_PMLP_ID:
3497 return "PMLP";
3498 case MLXSW_REG_PMTU_ID:
3499 return "PMTU";
3500 case MLXSW_REG_PTYS_ID:
3501 return "PTYS";
3502 case MLXSW_REG_PPAD_ID:
3503 return "PPAD";
3504 case MLXSW_REG_PAOS_ID:
3505 return "PAOS";
3506 case MLXSW_REG_PPCNT_ID:
3507 return "PPCNT";
b98ff151
IS		 3508 case MLXSW_REG_PPTB_ID:
3509 return "PPTB";
e0594369
JP		 3510 case MLXSW_REG_PBMC_ID:
3511 return "PBMC";
4ec14b76
IS		 3512 case MLXSW_REG_PSPA_ID:
3513 return "PSPA";
3514 case MLXSW_REG_HTGT_ID:
3515 return "HTGT";
3516 case MLXSW_REG_HPKT_ID:
3517 return "HPKT";
5246f2e2
JP		 3518 case MLXSW_REG_MFCR_ID:
3519 return "MFCR";
3520 case MLXSW_REG_MFSC_ID:
3521 return "MFSC";
3522 case MLXSW_REG_MFSM_ID:
3523 return "MFSM";
85926f87
JP		 3524 case MLXSW_REG_MTCAP_ID:
3525 return "MTCAP";
3526 case MLXSW_REG_MTMP_ID:
3527 return "MTMP";
3161c159
IS		 3528 case MLXSW_REG_MLCR_ID:
3529 return "MLCR";
e0594369
JP		 3530 case MLXSW_REG_SBPR_ID:
3531 return "SBPR";
3532 case MLXSW_REG_SBCM_ID:
3533 return "SBCM";
3534 case MLXSW_REG_SBPM_ID:
3535 return "SBPM";
3536 case MLXSW_REG_SBMM_ID:
3537 return "SBMM";
4ec14b76
IS		 3538 default:
3539 return "*UNKNOWN*";
3540 }
3541}
3542
3543/* PUDE - Port Up / Down Event
3544 * ---------------------------
3545 * Reports the operational state change of a port.
3546 */
3547#define MLXSW_REG_PUDE_LEN 0x10
3548
3549/* reg_pude_swid
3550 * Switch partition ID with which to associate the port.
3551 * Access: Index
3552 */
3553MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
3554
3555/* reg_pude_local_port
3556 * Local port number.
3557 * Access: Index
3558 */
3559MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
3560
3561/* reg_pude_admin_status
3562 * Port administrative state (the desired state).
3563 * 1 - Up.
3564 * 2 - Down.
3565 * 3 - Up once. This means that in case of link failure, the port won't go
3566 * into polling mode, but will wait to be re-enabled by software.
3567 * 4 - Disabled by system. Can only be set by hardware.
3568 * Access: RO
3569 */
3570MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
3571
3572/* reg_pude_oper_status
3573 * Port operatioanl state.
3574 * 1 - Up.
3575 * 2 - Down.
3576 * 3 - Down by port failure. This means that the device will not let the
3577 * port up again until explicitly specified by software.
3578 * Access: RO
3579 */
3580MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
3581
3582#endif
Linux kernel - Deliverables
This page took 0.228529 seconds and 5 git commands to generate.