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mlxsw: Introduce mlxsw_reg_spms_vid_pack helper and use it
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlxsw / reg.h
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4ec14b76
IS		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_REG_H
38#define _MLXSW_REG_H
39
40#include <linux/string.h>
41#include <linux/bitops.h>
42#include <linux/if_vlan.h>
43
44#include "item.h"
45#include "port.h"
46
47struct mlxsw_reg_info {
48 u16 id;
49 u16 len; /* In u8 */
50};
51
52#define MLXSW_REG(type) (&mlxsw_reg_##type)
53#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
54#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
55
56/* SGCR - Switch General Configuration Register
57 * --------------------------------------------
58 * This register is used for configuration of the switch capabilities.
59 */
60#define MLXSW_REG_SGCR_ID 0x2000
61#define MLXSW_REG_SGCR_LEN 0x10
62
63static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
64 .id = MLXSW_REG_SGCR_ID,
65 .len = MLXSW_REG_SGCR_LEN,
66};
67
68/* reg_sgcr_llb
69 * Link Local Broadcast (Default=0)
70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
71 * packets and ignore the IGMP snooping entries.
72 * Access: RW
73 */
74MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
75
76static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
77{
78 MLXSW_REG_ZERO(sgcr, payload);
79 mlxsw_reg_sgcr_llb_set(payload, !!llb);
80}
81
82/* SPAD - Switch Physical Address Register
83 * ---------------------------------------
84 * The SPAD register configures the switch physical MAC address.
85 */
86#define MLXSW_REG_SPAD_ID 0x2002
87#define MLXSW_REG_SPAD_LEN 0x10
88
89static const struct mlxsw_reg_info mlxsw_reg_spad = {
90 .id = MLXSW_REG_SPAD_ID,
91 .len = MLXSW_REG_SPAD_LEN,
92};
93
94/* reg_spad_base_mac
95 * Base MAC address for the switch partitions.
96 * Per switch partition MAC address is equal to:
97 * base_mac + swid
98 * Access: RW
99 */
100MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
101
e61011b5
IS		 102/* SSPR - Switch System Port Record Register
103 * -----------------------------------------
104 * Configures the system port to local port mapping.
105 */
106#define MLXSW_REG_SSPR_ID 0x2008
107#define MLXSW_REG_SSPR_LEN 0x8
108
109static const struct mlxsw_reg_info mlxsw_reg_sspr = {
110 .id = MLXSW_REG_SSPR_ID,
111 .len = MLXSW_REG_SSPR_LEN,
112};
113
114/* reg_sspr_m
115 * Master - if set, then the record describes the master system port.
116 * This is needed in case a local port is mapped into several system ports
117 * (for multipathing). That number will be reported as the source system
118 * port when packets are forwarded to the CPU. Only one master port is allowed
119 * per local port.
120 *
121 * Note: Must be set for Spectrum.
122 * Access: RW
123 */
124MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
125
126/* reg_sspr_local_port
127 * Local port number.
128 *
129 * Access: RW
130 */
131MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
132
133/* reg_sspr_sub_port
134 * Virtual port within the physical port.
135 * Should be set to 0 when virtual ports are not enabled on the port.
136 *
137 * Access: RW
138 */
139MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
140
141/* reg_sspr_system_port
142 * Unique identifier within the stacking domain that represents all the ports
143 * that are available in the system (external ports).
144 *
145 * Currently, only single-ASIC configurations are supported, so we default to
146 * 1:1 mapping between system ports and local ports.
147 * Access: Index
148 */
149MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
150
151static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
152{
153 MLXSW_REG_ZERO(sspr, payload);
154 mlxsw_reg_sspr_m_set(payload, 1);
155 mlxsw_reg_sspr_local_port_set(payload, local_port);
156 mlxsw_reg_sspr_sub_port_set(payload, 0);
157 mlxsw_reg_sspr_system_port_set(payload, local_port);
158}
159
4ec14b76
IS		 160/* SPMS - Switch Port MSTP/RSTP State Register
161 * -------------------------------------------
162 * Configures the spanning tree state of a physical port.
163 */
3f0effd1 164#define MLXSW_REG_SPMS_ID 0x200D
4ec14b76
IS		 165#define MLXSW_REG_SPMS_LEN 0x404
166
167static const struct mlxsw_reg_info mlxsw_reg_spms = {
168 .id = MLXSW_REG_SPMS_ID,
169 .len = MLXSW_REG_SPMS_LEN,
170};
171
172/* reg_spms_local_port
173 * Local port number.
174 * Access: Index
175 */
176MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
177
178enum mlxsw_reg_spms_state {
179 MLXSW_REG_SPMS_STATE_NO_CHANGE,
180 MLXSW_REG_SPMS_STATE_DISCARDING,
181 MLXSW_REG_SPMS_STATE_LEARNING,
182 MLXSW_REG_SPMS_STATE_FORWARDING,
183};
184
185/* reg_spms_state
186 * Spanning tree state of each VLAN ID (VID) of the local port.
187 * 0 - Do not change spanning tree state (used only when writing).
188 * 1 - Discarding. No learning or forwarding to/from this port (default).
189 * 2 - Learning. Port is learning, but not forwarding.
190 * 3 - Forwarding. Port is learning and forwarding.
191 * Access: RW
192 */
193MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
194
ebb7963f 195static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
4ec14b76
IS		 196{
197 MLXSW_REG_ZERO(spms, payload);
198 mlxsw_reg_spms_local_port_set(payload, local_port);
ebb7963f
JP		 199}
200
201static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
202 enum mlxsw_reg_spms_state state)
203{
4ec14b76
IS		 204 mlxsw_reg_spms_state_set(payload, vid, state);
205}
206
207/* SFGC - Switch Flooding Group Configuration
208 * ------------------------------------------
209 * The following register controls the association of flooding tables and MIDs
210 * to packet types used for flooding.
211 */
36b78e8a 212#define MLXSW_REG_SFGC_ID 0x2011
4ec14b76
IS		 213#define MLXSW_REG_SFGC_LEN 0x10
214
215static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
216 .id = MLXSW_REG_SFGC_ID,
217 .len = MLXSW_REG_SFGC_LEN,
218};
219
220enum mlxsw_reg_sfgc_type {
fa6ad058
IS		 221 MLXSW_REG_SFGC_TYPE_BROADCAST,
222 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
223 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
224 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
225 MLXSW_REG_SFGC_TYPE_RESERVED,
226 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
227 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
228 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
229 MLXSW_REG_SFGC_TYPE_MAX,
4ec14b76
IS		 230};
231
232/* reg_sfgc_type
233 * The traffic type to reach the flooding table.
234 * Access: Index
235 */
236MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
237
238enum mlxsw_reg_sfgc_bridge_type {
239 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
240 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
241};
242
243/* reg_sfgc_bridge_type
244 * Access: Index
245 *
246 * Note: SwitchX-2 only supports 802.1Q mode.
247 */
248MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
249
250enum mlxsw_flood_table_type {
251 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
252 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
253 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
254 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
255 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
256};
257
258/* reg_sfgc_table_type
259 * See mlxsw_flood_table_type
260 * Access: RW
261 *
262 * Note: FID offset and FID types are not supported in SwitchX-2.
263 */
264MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
265
266/* reg_sfgc_flood_table
267 * Flooding table index to associate with the specific type on the specific
268 * switch partition.
269 * Access: RW
270 */
271MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
272
273/* reg_sfgc_mid
274 * The multicast ID for the swid. Not supported for Spectrum
275 * Access: RW
276 */
277MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
278
279/* reg_sfgc_counter_set_type
280 * Counter Set Type for flow counters.
281 * Access: RW
282 */
283MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
284
285/* reg_sfgc_counter_index
286 * Counter Index for flow counters.
287 * Access: RW
288 */
289MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
290
291static inline void
292mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
293 enum mlxsw_reg_sfgc_bridge_type bridge_type,
294 enum mlxsw_flood_table_type table_type,
295 unsigned int flood_table)
296{
297 MLXSW_REG_ZERO(sfgc, payload);
298 mlxsw_reg_sfgc_type_set(payload, type);
299 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
300 mlxsw_reg_sfgc_table_type_set(payload, table_type);
301 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
302 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
303}
304
305/* SFTR - Switch Flooding Table Register
306 * -------------------------------------
307 * The switch flooding table is used for flooding packet replication. The table
308 * defines a bit mask of ports for packet replication.
309 */
310#define MLXSW_REG_SFTR_ID 0x2012
311#define MLXSW_REG_SFTR_LEN 0x420
312
313static const struct mlxsw_reg_info mlxsw_reg_sftr = {
314 .id = MLXSW_REG_SFTR_ID,
315 .len = MLXSW_REG_SFTR_LEN,
316};
317
318/* reg_sftr_swid
319 * Switch partition ID with which to associate the port.
320 * Access: Index
321 */
322MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
323
324/* reg_sftr_flood_table
325 * Flooding table index to associate with the specific type on the specific
326 * switch partition.
327 * Access: Index
328 */
329MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
330
331/* reg_sftr_index
332 * Index. Used as an index into the Flooding Table in case the table is
333 * configured to use VID / FID or FID Offset.
334 * Access: Index
335 */
336MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
337
338/* reg_sftr_table_type
339 * See mlxsw_flood_table_type
340 * Access: RW
341 */
342MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
343
344/* reg_sftr_range
345 * Range of entries to update
346 * Access: Index
347 */
348MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
349
350/* reg_sftr_port
351 * Local port membership (1 bit per port).
352 * Access: RW
353 */
354MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
355
356/* reg_sftr_cpu_port_mask
357 * CPU port mask (1 bit per port).
358 * Access: W
359 */
360MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
361
362static inline void mlxsw_reg_sftr_pack(char *payload,
363 unsigned int flood_table,
364 unsigned int index,
365 enum mlxsw_flood_table_type table_type,
366 unsigned int range)
367{
368 MLXSW_REG_ZERO(sftr, payload);
369 mlxsw_reg_sftr_swid_set(payload, 0);
370 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
371 mlxsw_reg_sftr_index_set(payload, index);
372 mlxsw_reg_sftr_table_type_set(payload, table_type);
373 mlxsw_reg_sftr_range_set(payload, range);
374 mlxsw_reg_sftr_port_set(payload, MLXSW_PORT_CPU_PORT, 1);
375 mlxsw_reg_sftr_port_mask_set(payload, MLXSW_PORT_CPU_PORT, 1);
376}
377
378/* SPMLR - Switch Port MAC Learning Register
379 * -----------------------------------------
380 * Controls the Switch MAC learning policy per port.
381 */
382#define MLXSW_REG_SPMLR_ID 0x2018
383#define MLXSW_REG_SPMLR_LEN 0x8
384
385static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
386 .id = MLXSW_REG_SPMLR_ID,
387 .len = MLXSW_REG_SPMLR_LEN,
388};
389
390/* reg_spmlr_local_port
391 * Local port number.
392 * Access: Index
393 */
394MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
395
396/* reg_spmlr_sub_port
397 * Virtual port within the physical port.
398 * Should be set to 0 when virtual ports are not enabled on the port.
399 * Access: Index
400 */
401MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
402
403enum mlxsw_reg_spmlr_learn_mode {
404 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
405 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
406 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
407};
408
409/* reg_spmlr_learn_mode
410 * Learning mode on the port.
411 * 0 - Learning disabled.
412 * 2 - Learning enabled.
413 * 3 - Security mode.
414 *
415 * In security mode the switch does not learn MACs on the port, but uses the
416 * SMAC to see if it exists on another ingress port. If so, the packet is
417 * classified as a bad packet and is discarded unless the software registers
418 * to receive port security error packets usign HPKT.
419 */
420MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
421
422static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
423 enum mlxsw_reg_spmlr_learn_mode mode)
424{
425 MLXSW_REG_ZERO(spmlr, payload);
426 mlxsw_reg_spmlr_local_port_set(payload, local_port);
427 mlxsw_reg_spmlr_sub_port_set(payload, 0);
428 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
429}
430
431/* PMLP - Ports Module to Local Port Register
432 * ------------------------------------------
433 * Configures the assignment of modules to local ports.
434 */
435#define MLXSW_REG_PMLP_ID 0x5002
436#define MLXSW_REG_PMLP_LEN 0x40
437
438static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
439 .id = MLXSW_REG_PMLP_ID,
440 .len = MLXSW_REG_PMLP_LEN,
441};
442
443/* reg_pmlp_rxtx
444 * 0 - Tx value is used for both Tx and Rx.
445 * 1 - Rx value is taken from a separte field.
446 * Access: RW
447 */
448MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
449
450/* reg_pmlp_local_port
451 * Local port number.
452 * Access: Index
453 */
454MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
455
456/* reg_pmlp_width
457 * 0 - Unmap local port.
458 * 1 - Lane 0 is used.
459 * 2 - Lanes 0 and 1 are used.
460 * 4 - Lanes 0, 1, 2 and 3 are used.
461 * Access: RW
462 */
463MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
464
465/* reg_pmlp_module
466 * Module number.
467 * Access: RW
468 */
469MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false);
470
471/* reg_pmlp_tx_lane
472 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
473 * Access: RW
474 */
475MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false);
476
477/* reg_pmlp_rx_lane
478 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
479 * equal to Tx lane.
480 * Access: RW
481 */
482MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false);
483
484static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
485{
486 MLXSW_REG_ZERO(pmlp, payload);
487 mlxsw_reg_pmlp_local_port_set(payload, local_port);
488}
489
490/* PMTU - Port MTU Register
491 * ------------------------
492 * Configures and reports the port MTU.
493 */
494#define MLXSW_REG_PMTU_ID 0x5003
495#define MLXSW_REG_PMTU_LEN 0x10
496
497static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
498 .id = MLXSW_REG_PMTU_ID,
499 .len = MLXSW_REG_PMTU_LEN,
500};
501
502/* reg_pmtu_local_port
503 * Local port number.
504 * Access: Index
505 */
506MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
507
508/* reg_pmtu_max_mtu
509 * Maximum MTU.
510 * When port type (e.g. Ethernet) is configured, the relevant MTU is
511 * reported, otherwise the minimum between the max_mtu of the different
512 * types is reported.
513 * Access: RO
514 */
515MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
516
517/* reg_pmtu_admin_mtu
518 * MTU value to set port to. Must be smaller or equal to max_mtu.
519 * Note: If port type is Infiniband, then port must be disabled, when its
520 * MTU is set.
521 * Access: RW
522 */
523MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
524
525/* reg_pmtu_oper_mtu
526 * The actual MTU configured on the port. Packets exceeding this size
527 * will be dropped.
528 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
529 * oper_mtu might be smaller than admin_mtu.
530 * Access: RO
531 */
532MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
533
534static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
535 u16 new_mtu)
536{
537 MLXSW_REG_ZERO(pmtu, payload);
538 mlxsw_reg_pmtu_local_port_set(payload, local_port);
539 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
540 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
541 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
542}
543
544/* PTYS - Port Type and Speed Register
545 * -----------------------------------
546 * Configures and reports the port speed type.
547 *
548 * Note: When set while the link is up, the changes will not take effect
549 * until the port transitions from down to up state.
550 */
551#define MLXSW_REG_PTYS_ID 0x5004
552#define MLXSW_REG_PTYS_LEN 0x40
553
554static const struct mlxsw_reg_info mlxsw_reg_ptys = {
555 .id = MLXSW_REG_PTYS_ID,
556 .len = MLXSW_REG_PTYS_LEN,
557};
558
559/* reg_ptys_local_port
560 * Local port number.
561 * Access: Index
562 */
563MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
564
565#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
566
567/* reg_ptys_proto_mask
568 * Protocol mask. Indicates which protocol is used.
569 * 0 - Infiniband.
570 * 1 - Fibre Channel.
571 * 2 - Ethernet.
572 * Access: Index
573 */
574MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
575
576#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
577#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
578#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
579#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
580#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
581#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
582#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
583#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
584#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
585#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
586#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
587#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
588#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
589#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
590#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
591#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
592#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
593#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
594#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
595#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
596#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
597#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
598#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
599#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
600#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
601#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
602#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
603
604/* reg_ptys_eth_proto_cap
605 * Ethernet port supported speeds and protocols.
606 * Access: RO
607 */
608MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
609
610/* reg_ptys_eth_proto_admin
611 * Speed and protocol to set port to.
612 * Access: RW
613 */
614MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
615
616/* reg_ptys_eth_proto_oper
617 * The current speed and protocol configured for the port.
618 * Access: RO
619 */
620MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
621
622static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
623 u32 proto_admin)
624{
625 MLXSW_REG_ZERO(ptys, payload);
626 mlxsw_reg_ptys_local_port_set(payload, local_port);
627 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
628 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
629}
630
631static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
632 u32 *p_eth_proto_adm,
633 u32 *p_eth_proto_oper)
634{
635 if (p_eth_proto_cap)
636 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
637 if (p_eth_proto_adm)
638 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
639 if (p_eth_proto_oper)
640 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
641}
642
643/* PPAD - Port Physical Address Register
644 * -------------------------------------
645 * The PPAD register configures the per port physical MAC address.
646 */
647#define MLXSW_REG_PPAD_ID 0x5005
648#define MLXSW_REG_PPAD_LEN 0x10
649
650static const struct mlxsw_reg_info mlxsw_reg_ppad = {
651 .id = MLXSW_REG_PPAD_ID,
652 .len = MLXSW_REG_PPAD_LEN,
653};
654
655/* reg_ppad_single_base_mac
656 * 0: base_mac, local port should be 0 and mac[7:0] is
657 * reserved. HW will set incremental
658 * 1: single_mac - mac of the local_port
659 * Access: RW
660 */
661MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
662
663/* reg_ppad_local_port
664 * port number, if single_base_mac = 0 then local_port is reserved
665 * Access: RW
666 */
667MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
668
669/* reg_ppad_mac
670 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
671 * If single_base_mac = 1 - the per port MAC address
672 * Access: RW
673 */
674MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
675
676static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
677 u8 local_port)
678{
679 MLXSW_REG_ZERO(ppad, payload);
680 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
681 mlxsw_reg_ppad_local_port_set(payload, local_port);
682}
683
684/* PAOS - Ports Administrative and Operational Status Register
685 * -----------------------------------------------------------
686 * Configures and retrieves per port administrative and operational status.
687 */
688#define MLXSW_REG_PAOS_ID 0x5006
689#define MLXSW_REG_PAOS_LEN 0x10
690
691static const struct mlxsw_reg_info mlxsw_reg_paos = {
692 .id = MLXSW_REG_PAOS_ID,
693 .len = MLXSW_REG_PAOS_LEN,
694};
695
696/* reg_paos_swid
697 * Switch partition ID with which to associate the port.
698 * Note: while external ports uses unique local port numbers (and thus swid is
699 * redundant), router ports use the same local port number where swid is the
700 * only indication for the relevant port.
701 * Access: Index
702 */
703MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
704
705/* reg_paos_local_port
706 * Local port number.
707 * Access: Index
708 */
709MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
710
711/* reg_paos_admin_status
712 * Port administrative state (the desired state of the port):
713 * 1 - Up.
714 * 2 - Down.
715 * 3 - Up once. This means that in case of link failure, the port won't go
716 * into polling mode, but will wait to be re-enabled by software.
717 * 4 - Disabled by system. Can only be set by hardware.
718 * Access: RW
719 */
720MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
721
722/* reg_paos_oper_status
723 * Port operational state (the current state):
724 * 1 - Up.
725 * 2 - Down.
726 * 3 - Down by port failure. This means that the device will not let the
727 * port up again until explicitly specified by software.
728 * Access: RO
729 */
730MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
731
732/* reg_paos_ase
733 * Admin state update enabled.
734 * Access: WO
735 */
736MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
737
738/* reg_paos_ee
739 * Event update enable. If this bit is set, event generation will be
740 * updated based on the e field.
741 * Access: WO
742 */
743MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
744
745/* reg_paos_e
746 * Event generation on operational state change:
747 * 0 - Do not generate event.
748 * 1 - Generate Event.
749 * 2 - Generate Single Event.
750 * Access: RW
751 */
752MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
753
754static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
755 enum mlxsw_port_admin_status status)
756{
757 MLXSW_REG_ZERO(paos, payload);
758 mlxsw_reg_paos_swid_set(payload, 0);
759 mlxsw_reg_paos_local_port_set(payload, local_port);
760 mlxsw_reg_paos_admin_status_set(payload, status);
761 mlxsw_reg_paos_oper_status_set(payload, 0);
762 mlxsw_reg_paos_ase_set(payload, 1);
763 mlxsw_reg_paos_ee_set(payload, 1);
764 mlxsw_reg_paos_e_set(payload, 1);
765}
766
767/* PPCNT - Ports Performance Counters Register
768 * -------------------------------------------
769 * The PPCNT register retrieves per port performance counters.
770 */
771#define MLXSW_REG_PPCNT_ID 0x5008
772#define MLXSW_REG_PPCNT_LEN 0x100
773
774static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
775 .id = MLXSW_REG_PPCNT_ID,
776 .len = MLXSW_REG_PPCNT_LEN,
777};
778
779/* reg_ppcnt_swid
780 * For HCA: must be always 0.
781 * Switch partition ID to associate port with.
782 * Switch partitions are numbered from 0 to 7 inclusively.
783 * Switch partition 254 indicates stacking ports.
784 * Switch partition 255 indicates all switch partitions.
785 * Only valid on Set() operation with local_port=255.
786 * Access: Index
787 */
788MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
789
790/* reg_ppcnt_local_port
791 * Local port number.
792 * 255 indicates all ports on the device, and is only allowed
793 * for Set() operation.
794 * Access: Index
795 */
796MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
797
798/* reg_ppcnt_pnat
799 * Port number access type:
800 * 0 - Local port number
801 * 1 - IB port number
802 * Access: Index
803 */
804MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
805
806/* reg_ppcnt_grp
807 * Performance counter group.
808 * Group 63 indicates all groups. Only valid on Set() operation with
809 * clr bit set.
810 * 0x0: IEEE 802.3 Counters
811 * 0x1: RFC 2863 Counters
812 * 0x2: RFC 2819 Counters
813 * 0x3: RFC 3635 Counters
814 * 0x5: Ethernet Extended Counters
815 * 0x8: Link Level Retransmission Counters
816 * 0x10: Per Priority Counters
817 * 0x11: Per Traffic Class Counters
818 * 0x12: Physical Layer Counters
819 * Access: Index
820 */
821MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
822
823/* reg_ppcnt_clr
824 * Clear counters. Setting the clr bit will reset the counter value
825 * for all counters in the counter group. This bit can be set
826 * for both Set() and Get() operation.
827 * Access: OP
828 */
829MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
830
831/* reg_ppcnt_prio_tc
832 * Priority for counter set that support per priority, valid values: 0-7.
833 * Traffic class for counter set that support per traffic class,
834 * valid values: 0- cap_max_tclass-1 .
835 * For HCA: cap_max_tclass is always 8.
836 * Otherwise must be 0.
837 * Access: Index
838 */
839MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
840
841/* reg_ppcnt_a_frames_transmitted_ok
842 * Access: RO
843 */
844MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
845 0x08 + 0x00, 0, 64);
846
847/* reg_ppcnt_a_frames_received_ok
848 * Access: RO
849 */
850MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
851 0x08 + 0x08, 0, 64);
852
853/* reg_ppcnt_a_frame_check_sequence_errors
854 * Access: RO
855 */
856MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
857 0x08 + 0x10, 0, 64);
858
859/* reg_ppcnt_a_alignment_errors
860 * Access: RO
861 */
862MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
863 0x08 + 0x18, 0, 64);
864
865/* reg_ppcnt_a_octets_transmitted_ok
866 * Access: RO
867 */
868MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
869 0x08 + 0x20, 0, 64);
870
871/* reg_ppcnt_a_octets_received_ok
872 * Access: RO
873 */
874MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
875 0x08 + 0x28, 0, 64);
876
877/* reg_ppcnt_a_multicast_frames_xmitted_ok
878 * Access: RO
879 */
880MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
881 0x08 + 0x30, 0, 64);
882
883/* reg_ppcnt_a_broadcast_frames_xmitted_ok
884 * Access: RO
885 */
886MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
887 0x08 + 0x38, 0, 64);
888
889/* reg_ppcnt_a_multicast_frames_received_ok
890 * Access: RO
891 */
892MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
893 0x08 + 0x40, 0, 64);
894
895/* reg_ppcnt_a_broadcast_frames_received_ok
896 * Access: RO
897 */
898MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
899 0x08 + 0x48, 0, 64);
900
901/* reg_ppcnt_a_in_range_length_errors
902 * Access: RO
903 */
904MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
905 0x08 + 0x50, 0, 64);
906
907/* reg_ppcnt_a_out_of_range_length_field
908 * Access: RO
909 */
910MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
911 0x08 + 0x58, 0, 64);
912
913/* reg_ppcnt_a_frame_too_long_errors
914 * Access: RO
915 */
916MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
917 0x08 + 0x60, 0, 64);
918
919/* reg_ppcnt_a_symbol_error_during_carrier
920 * Access: RO
921 */
922MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
923 0x08 + 0x68, 0, 64);
924
925/* reg_ppcnt_a_mac_control_frames_transmitted
926 * Access: RO
927 */
928MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
929 0x08 + 0x70, 0, 64);
930
931/* reg_ppcnt_a_mac_control_frames_received
932 * Access: RO
933 */
934MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
935 0x08 + 0x78, 0, 64);
936
937/* reg_ppcnt_a_unsupported_opcodes_received
938 * Access: RO
939 */
940MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
941 0x08 + 0x80, 0, 64);
942
943/* reg_ppcnt_a_pause_mac_ctrl_frames_received
944 * Access: RO
945 */
946MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
947 0x08 + 0x88, 0, 64);
948
949/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
950 * Access: RO
951 */
952MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
953 0x08 + 0x90, 0, 64);
954
955static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
956{
957 MLXSW_REG_ZERO(ppcnt, payload);
958 mlxsw_reg_ppcnt_swid_set(payload, 0);
959 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
960 mlxsw_reg_ppcnt_pnat_set(payload, 0);
961 mlxsw_reg_ppcnt_grp_set(payload, 0);
962 mlxsw_reg_ppcnt_clr_set(payload, 0);
963 mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
964}
965
966/* PSPA - Port Switch Partition Allocation
967 * ---------------------------------------
968 * Controls the association of a port with a switch partition and enables
969 * configuring ports as stacking ports.
970 */
3f0effd1 971#define MLXSW_REG_PSPA_ID 0x500D
4ec14b76
IS		 972#define MLXSW_REG_PSPA_LEN 0x8
973
974static const struct mlxsw_reg_info mlxsw_reg_pspa = {
975 .id = MLXSW_REG_PSPA_ID,
976 .len = MLXSW_REG_PSPA_LEN,
977};
978
979/* reg_pspa_swid
980 * Switch partition ID.
981 * Access: RW
982 */
983MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
984
985/* reg_pspa_local_port
986 * Local port number.
987 * Access: Index
988 */
989MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
990
991/* reg_pspa_sub_port
992 * Virtual port within the local port. Set to 0 when virtual ports are
993 * disabled on the local port.
994 * Access: Index
995 */
996MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
997
998static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
999{
1000 MLXSW_REG_ZERO(pspa, payload);
1001 mlxsw_reg_pspa_swid_set(payload, swid);
1002 mlxsw_reg_pspa_local_port_set(payload, local_port);
1003 mlxsw_reg_pspa_sub_port_set(payload, 0);
1004}
1005
1006/* HTGT - Host Trap Group Table
1007 * ----------------------------
1008 * Configures the properties for forwarding to CPU.
1009 */
1010#define MLXSW_REG_HTGT_ID 0x7002
1011#define MLXSW_REG_HTGT_LEN 0x100
1012
1013static const struct mlxsw_reg_info mlxsw_reg_htgt = {
1014 .id = MLXSW_REG_HTGT_ID,
1015 .len = MLXSW_REG_HTGT_LEN,
1016};
1017
1018/* reg_htgt_swid
1019 * Switch partition ID.
1020 * Access: Index
1021 */
1022MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
1023
1024#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
1025
1026/* reg_htgt_type
1027 * CPU path type.
1028 * Access: RW
1029 */
1030MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
1031
1032#define MLXSW_REG_HTGT_TRAP_GROUP_EMAD 0x0
1033#define MLXSW_REG_HTGT_TRAP_GROUP_RX 0x1
1034
1035/* reg_htgt_trap_group
1036 * Trap group number. User defined number specifying which trap groups
1037 * should be forwarded to the CPU. The mapping between trap IDs and trap
1038 * groups is configured using HPKT register.
1039 * Access: Index
1040 */
1041MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
1042
1043enum {
1044 MLXSW_REG_HTGT_POLICER_DISABLE,
1045 MLXSW_REG_HTGT_POLICER_ENABLE,
1046};
1047
1048/* reg_htgt_pide
1049 * Enable policer ID specified using 'pid' field.
1050 * Access: RW
1051 */
1052MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
1053
1054/* reg_htgt_pid
1055 * Policer ID for the trap group.
1056 * Access: RW
1057 */
1058MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
1059
1060#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
1061
1062/* reg_htgt_mirror_action
1063 * Mirror action to use.
1064 * 0 - Trap to CPU.
1065 * 1 - Trap to CPU and mirror to a mirroring agent.
1066 * 2 - Mirror to a mirroring agent and do not trap to CPU.
1067 * Access: RW
1068 *
1069 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
1070 */
1071MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
1072
1073/* reg_htgt_mirroring_agent
1074 * Mirroring agent.
1075 * Access: RW
1076 */
1077MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
1078
1079/* reg_htgt_priority
1080 * Trap group priority.
1081 * In case a packet matches multiple classification rules, the packet will
1082 * only be trapped once, based on the trap ID associated with the group (via
1083 * register HPKT) with the highest priority.
1084 * Supported values are 0-7, with 7 represnting the highest priority.
1085 * Access: RW
1086 *
1087 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
1088 * by the 'trap_group' field.
1089 */
1090MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
1091
1092/* reg_htgt_local_path_cpu_tclass
1093 * CPU ingress traffic class for the trap group.
1094 * Access: RW
1095 */
1096MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1097
1098#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
1099#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
1100
1101/* reg_htgt_local_path_rdq
1102 * Receive descriptor queue (RDQ) to use for the trap group.
1103 * Access: RW
1104 */
1105MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
1106
1107static inline void mlxsw_reg_htgt_pack(char *payload, u8 trap_group)
1108{
1109 u8 swid, rdq;
1110
1111 MLXSW_REG_ZERO(htgt, payload);
1112 if (MLXSW_REG_HTGT_TRAP_GROUP_EMAD == trap_group) {
1113 swid = MLXSW_PORT_SWID_ALL_SWIDS;
1114 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
1115 } else {
1116 swid = 0;
1117 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
1118 }
1119 mlxsw_reg_htgt_swid_set(payload, swid);
1120 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
1121 mlxsw_reg_htgt_trap_group_set(payload, trap_group);
1122 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
1123 mlxsw_reg_htgt_pid_set(payload, 0);
1124 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
1125 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
1126 mlxsw_reg_htgt_priority_set(payload, 0);
1127 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
1128 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
1129}
1130
1131/* HPKT - Host Packet Trap
1132 * -----------------------
1133 * Configures trap IDs inside trap groups.
1134 */
1135#define MLXSW_REG_HPKT_ID 0x7003
1136#define MLXSW_REG_HPKT_LEN 0x10
1137
1138static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
1139 .id = MLXSW_REG_HPKT_ID,
1140 .len = MLXSW_REG_HPKT_LEN,
1141};
1142
1143enum {
1144 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
1145 MLXSW_REG_HPKT_ACK_REQUIRED,
1146};
1147
1148/* reg_hpkt_ack
1149 * Require acknowledgements from the host for events.
1150 * If set, then the device will wait for the event it sent to be acknowledged
1151 * by the host. This option is only relevant for event trap IDs.
1152 * Access: RW
1153 *
1154 * Note: Currently not supported by firmware.
1155 */
1156MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
1157
1158enum mlxsw_reg_hpkt_action {
1159 MLXSW_REG_HPKT_ACTION_FORWARD,
1160 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1161 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
1162 MLXSW_REG_HPKT_ACTION_DISCARD,
1163 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
1164 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
1165};
1166
1167/* reg_hpkt_action
1168 * Action to perform on packet when trapped.
1169 * 0 - No action. Forward to CPU based on switching rules.
1170 * 1 - Trap to CPU (CPU receives sole copy).
1171 * 2 - Mirror to CPU (CPU receives a replica of the packet).
1172 * 3 - Discard.
1173 * 4 - Soft discard (allow other traps to act on the packet).
1174 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
1175 * Access: RW
1176 *
1177 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
1178 * addressed to the CPU.
1179 */
1180MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
1181
1182/* reg_hpkt_trap_group
1183 * Trap group to associate the trap with.
1184 * Access: RW
1185 */
1186MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
1187
1188/* reg_hpkt_trap_id
1189 * Trap ID.
1190 * Access: Index
1191 *
1192 * Note: A trap ID can only be associated with a single trap group. The device
1193 * will associate the trap ID with the last trap group configured.
1194 */
1195MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
1196
1197enum {
1198 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
1199 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
1200 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
1201};
1202
1203/* reg_hpkt_ctrl
1204 * Configure dedicated buffer resources for control packets.
1205 * 0 - Keep factory defaults.
1206 * 1 - Do not use control buffer for this trap ID.
1207 * 2 - Use control buffer for this trap ID.
1208 * Access: RW
1209 */
1210MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
1211
1212static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action,
1213 u8 trap_group, u16 trap_id)
1214{
1215 MLXSW_REG_ZERO(hpkt, payload);
1216 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
1217 mlxsw_reg_hpkt_action_set(payload, action);
1218 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
1219 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
1220 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
1221}
1222
1223static inline const char *mlxsw_reg_id_str(u16 reg_id)
1224{
1225 switch (reg_id) {
1226 case MLXSW_REG_SGCR_ID:
1227 return "SGCR";
1228 case MLXSW_REG_SPAD_ID:
1229 return "SPAD";
e61011b5
IS		 1230 case MLXSW_REG_SSPR_ID:
1231 return "SSPR";
4ec14b76
IS		 1232 case MLXSW_REG_SPMS_ID:
1233 return "SPMS";
1234 case MLXSW_REG_SFGC_ID:
1235 return "SFGC";
1236 case MLXSW_REG_SFTR_ID:
1237 return "SFTR";
1238 case MLXSW_REG_SPMLR_ID:
1239 return "SPMLR";
1240 case MLXSW_REG_PMLP_ID:
1241 return "PMLP";
1242 case MLXSW_REG_PMTU_ID:
1243 return "PMTU";
1244 case MLXSW_REG_PTYS_ID:
1245 return "PTYS";
1246 case MLXSW_REG_PPAD_ID:
1247 return "PPAD";
1248 case MLXSW_REG_PAOS_ID:
1249 return "PAOS";
1250 case MLXSW_REG_PPCNT_ID:
1251 return "PPCNT";
1252 case MLXSW_REG_PSPA_ID:
1253 return "PSPA";
1254 case MLXSW_REG_HTGT_ID:
1255 return "HTGT";
1256 case MLXSW_REG_HPKT_ID:
1257 return "HPKT";
1258 default:
1259 return "*UNKNOWN*";
1260 }
1261}
1262
1263/* PUDE - Port Up / Down Event
1264 * ---------------------------
1265 * Reports the operational state change of a port.
1266 */
1267#define MLXSW_REG_PUDE_LEN 0x10
1268
1269/* reg_pude_swid
1270 * Switch partition ID with which to associate the port.
1271 * Access: Index
1272 */
1273MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
1274
1275/* reg_pude_local_port
1276 * Local port number.
1277 * Access: Index
1278 */
1279MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
1280
1281/* reg_pude_admin_status
1282 * Port administrative state (the desired state).
1283 * 1 - Up.
1284 * 2 - Down.
1285 * 3 - Up once. This means that in case of link failure, the port won't go
1286 * into polling mode, but will wait to be re-enabled by software.
1287 * 4 - Disabled by system. Can only be set by hardware.
1288 * Access: RO
1289 */
1290MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
1291
1292/* reg_pude_oper_status
1293 * Port operatioanl state.
1294 * 1 - Up.
1295 * 2 - Down.
1296 * 3 - Down by port failure. This means that the device will not let the
1297 * port up again until explicitly specified by software.
1298 * Access: RO
1299 */
1300MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
1301
1302#endif
Linux kernel - Deliverables
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