Commit | Line | Data |
---|---|---|
7a3c66e2 DS |
1 | /* |
2 | * Micrel KS8695 (Centaur) Ethernet. | |
3 | * | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Daniel Silverstone <dsilvers@simtec.co.uk> | |
6 | * Vincent Sanders <vince@simtec.co.uk> | |
7 | */ | |
8 | ||
9 | #ifndef KS8695NET_H | |
10 | #define KS8695NET_H | |
11 | ||
12 | /* Receive descriptor flags */ | |
13 | #define RDES_OWN (1 << 31) /* Ownership */ | |
14 | #define RDES_FS (1 << 30) /* First Descriptor */ | |
15 | #define RDES_LS (1 << 29) /* Last Descriptor */ | |
16 | #define RDES_IPE (1 << 28) /* IP Checksum error */ | |
17 | #define RDES_TCPE (1 << 27) /* TCP Checksum error */ | |
18 | #define RDES_UDPE (1 << 26) /* UDP Checksum error */ | |
19 | #define RDES_ES (1 << 25) /* Error summary */ | |
20 | #define RDES_MF (1 << 24) /* Multicast Frame */ | |
21 | #define RDES_RE (1 << 19) /* MII Error reported */ | |
22 | #define RDES_TL (1 << 18) /* Frame too Long */ | |
23 | #define RDES_RF (1 << 17) /* Runt Frame */ | |
24 | #define RDES_CE (1 << 16) /* CRC error */ | |
25 | #define RDES_FT (1 << 15) /* Frame Type */ | |
26 | #define RDES_FLEN (0x7ff) /* Frame Length */ | |
27 | ||
28 | #define RDES_RER (1 << 25) /* Receive End of Ring */ | |
29 | #define RDES_RBS (0x7ff) /* Receive Buffer Size */ | |
30 | ||
31 | /* Transmit descriptor flags */ | |
32 | ||
33 | #define TDES_OWN (1 << 31) /* Ownership */ | |
34 | ||
35 | #define TDES_IC (1 << 31) /* Interrupt on Completion */ | |
36 | #define TDES_FS (1 << 30) /* First Segment */ | |
37 | #define TDES_LS (1 << 29) /* Last Segment */ | |
38 | #define TDES_IPCKG (1 << 28) /* IP Checksum generate */ | |
39 | #define TDES_TCPCKG (1 << 27) /* TCP Checksum generate */ | |
40 | #define TDES_UDPCKG (1 << 26) /* UDP Checksum generate */ | |
41 | #define TDES_TER (1 << 25) /* Transmit End of Ring */ | |
42 | #define TDES_TBS (0x7ff) /* Transmit Buffer Size */ | |
43 | ||
44 | /* | |
45 | * Network controller register offsets | |
46 | */ | |
47 | #define KS8695_DTXC (0x00) /* DMA Transmit Control */ | |
48 | #define KS8695_DRXC (0x04) /* DMA Receive Control */ | |
49 | #define KS8695_DTSC (0x08) /* DMA Transmit Start Command */ | |
50 | #define KS8695_DRSC (0x0c) /* DMA Receive Start Command */ | |
51 | #define KS8695_TDLB (0x10) /* Transmit Descriptor List | |
52 | * Base Address | |
53 | */ | |
54 | #define KS8695_RDLB (0x14) /* Receive Descriptor List | |
55 | * Base Address | |
56 | */ | |
57 | #define KS8695_MAL (0x18) /* MAC Station Address Low */ | |
58 | #define KS8695_MAH (0x1c) /* MAC Station Address High */ | |
59 | #define KS8695_AAL_(n) (0x80 + ((n)*8)) /* MAC Additional | |
60 | * Station Address | |
61 | * (0..15) Low | |
62 | */ | |
63 | #define KS8695_AAH_(n) (0x84 + ((n)*8)) /* MAC Additional | |
64 | * Station Address | |
65 | * (0..15) High | |
66 | */ | |
67 | ||
68 | ||
69 | /* DMA Transmit Control Register */ | |
70 | #define DTXC_TRST (1 << 31) /* Soft Reset */ | |
71 | #define DTXC_TBS (0x3f << 24) /* Transmit Burst Size */ | |
72 | #define DTXC_TUCG (1 << 18) /* Transmit UDP | |
73 | * Checksum Generate | |
74 | */ | |
75 | #define DTXC_TTCG (1 << 17) /* Transmit TCP | |
76 | * Checksum Generate | |
77 | */ | |
78 | #define DTXC_TICG (1 << 16) /* Transmit IP | |
79 | * Checksum Generate | |
80 | */ | |
81 | #define DTXC_TFCE (1 << 9) /* Transmit Flow | |
82 | * Control Enable | |
83 | */ | |
84 | #define DTXC_TLB (1 << 8) /* Loopback mode */ | |
85 | #define DTXC_TEP (1 << 2) /* Transmit Enable Padding */ | |
86 | #define DTXC_TAC (1 << 1) /* Transmit Add CRC */ | |
87 | #define DTXC_TE (1 << 0) /* TX Enable */ | |
88 | ||
89 | /* DMA Receive Control Register */ | |
90 | #define DRXC_RBS (0x3f << 24) /* Receive Burst Size */ | |
91 | #define DRXC_RUCC (1 << 18) /* Receive UDP Checksum check */ | |
92 | #define DRXC_RTCG (1 << 17) /* Receive TCP Checksum check */ | |
93 | #define DRXC_RICG (1 << 16) /* Receive IP Checksum check */ | |
94 | #define DRXC_RFCE (1 << 9) /* Receive Flow Control | |
95 | * Enable | |
96 | */ | |
97 | #define DRXC_RB (1 << 6) /* Receive Broadcast */ | |
98 | #define DRXC_RM (1 << 5) /* Receive Multicast */ | |
99 | #define DRXC_RU (1 << 4) /* Receive Unicast */ | |
100 | #define DRXC_RERR (1 << 3) /* Receive Error Frame */ | |
101 | #define DRXC_RA (1 << 2) /* Receive All */ | |
102 | #define DRXC_RE (1 << 0) /* RX Enable */ | |
103 | ||
104 | /* Additional Station Address High */ | |
105 | #define AAH_E (1 << 31) /* Address Enabled */ | |
106 | ||
107 | #endif /* KS8695NET_H */ |