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3ec9c11d CL |
1 | /* |
2 | * Microchip ENC28J60 ethernet driver (MAC + PHY) | |
3 | * | |
4 | * Copyright (C) 2007 Eurek srl | |
5 | * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com> | |
6 | * based on enc28j60.c written by David Anders for 2.4 kernel version | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $ | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/fcntl.h> | |
20 | #include <linux/interrupt.h> | |
3ec9c11d CL |
21 | #include <linux/string.h> |
22 | #include <linux/errno.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/ethtool.h> | |
27 | #include <linux/tcp.h> | |
28 | #include <linux/skbuff.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/spi/spi.h> | |
2dd355a0 | 31 | #include <linux/of_net.h> |
3ec9c11d CL |
32 | |
33 | #include "enc28j60_hw.h" | |
34 | ||
35 | #define DRV_NAME "enc28j60" | |
2dd355a0 | 36 | #define DRV_VERSION "1.02" |
3ec9c11d CL |
37 | |
38 | #define SPI_OPLEN 1 | |
39 | ||
40 | #define ENC28J60_MSG_DEFAULT \ | |
41 | (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK) | |
42 | ||
43 | /* Buffer size required for the largest SPI transfer (i.e., reading a | |
44 | * frame). */ | |
45 | #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN) | |
46 | ||
47 | #define TX_TIMEOUT (4 * HZ) | |
48 | ||
49 | /* Max TX retries in case of collision as suggested by errata datasheet */ | |
50 | #define MAX_TX_RETRYCOUNT 16 | |
51 | ||
52 | enum { | |
53 | RXFILTER_NORMAL, | |
54 | RXFILTER_MULTI, | |
55 | RXFILTER_PROMISC | |
56 | }; | |
57 | ||
58 | /* Driver local data */ | |
59 | struct enc28j60_net { | |
60 | struct net_device *netdev; | |
61 | struct spi_device *spi; | |
62 | struct mutex lock; | |
63 | struct sk_buff *tx_skb; | |
64 | struct work_struct tx_work; | |
65 | struct work_struct irq_work; | |
66 | struct work_struct setrx_work; | |
67 | struct work_struct restart_work; | |
68 | u8 bank; /* current register bank selected */ | |
69 | u16 next_pk_ptr; /* next packet pointer within FIFO */ | |
70 | u16 max_pk_counter; /* statistics: max packet counter */ | |
71 | u16 tx_retry_count; | |
72 | bool hw_enable; | |
73 | bool full_duplex; | |
74 | int rxfilter; | |
75 | u32 msg_enable; | |
76 | u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN]; | |
77 | }; | |
78 | ||
79 | /* use ethtool to change the level for any given device */ | |
80 | static struct { | |
81 | u32 msg_enable; | |
82 | } debug = { -1 }; | |
83 | ||
84 | /* | |
85 | * SPI read buffer | |
86 | * wait for the SPI transfer and copy received data to destination | |
87 | */ | |
88 | static int | |
89 | spi_read_buf(struct enc28j60_net *priv, int len, u8 *data) | |
90 | { | |
91 | u8 *rx_buf = priv->spi_transfer_buf + 4; | |
92 | u8 *tx_buf = priv->spi_transfer_buf; | |
2957a28a | 93 | struct spi_transfer tx = { |
3ec9c11d | 94 | .tx_buf = tx_buf, |
2957a28a MH |
95 | .len = SPI_OPLEN, |
96 | }; | |
97 | struct spi_transfer rx = { | |
3ec9c11d | 98 | .rx_buf = rx_buf, |
2957a28a | 99 | .len = len, |
3ec9c11d CL |
100 | }; |
101 | struct spi_message msg; | |
102 | int ret; | |
103 | ||
104 | tx_buf[0] = ENC28J60_READ_BUF_MEM; | |
3ec9c11d CL |
105 | |
106 | spi_message_init(&msg); | |
2957a28a MH |
107 | spi_message_add_tail(&tx, &msg); |
108 | spi_message_add_tail(&rx, &msg); | |
109 | ||
3ec9c11d CL |
110 | ret = spi_sync(priv->spi, &msg); |
111 | if (ret == 0) { | |
2957a28a | 112 | memcpy(data, rx_buf, len); |
3ec9c11d CL |
113 | ret = msg.status; |
114 | } | |
115 | if (ret && netif_msg_drv(priv)) | |
116 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 117 | __func__, ret); |
3ec9c11d CL |
118 | |
119 | return ret; | |
120 | } | |
121 | ||
122 | /* | |
123 | * SPI write buffer | |
124 | */ | |
125 | static int spi_write_buf(struct enc28j60_net *priv, int len, | |
126 | const u8 *data) | |
127 | { | |
128 | int ret; | |
129 | ||
130 | if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0) | |
131 | ret = -EINVAL; | |
132 | else { | |
133 | priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM; | |
134 | memcpy(&priv->spi_transfer_buf[1], data, len); | |
135 | ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1); | |
136 | if (ret && netif_msg_drv(priv)) | |
137 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 138 | __func__, ret); |
3ec9c11d CL |
139 | } |
140 | return ret; | |
141 | } | |
142 | ||
143 | /* | |
144 | * basic SPI read operation | |
145 | */ | |
146 | static u8 spi_read_op(struct enc28j60_net *priv, u8 op, | |
147 | u8 addr) | |
148 | { | |
149 | u8 tx_buf[2]; | |
150 | u8 rx_buf[4]; | |
151 | u8 val = 0; | |
152 | int ret; | |
153 | int slen = SPI_OPLEN; | |
154 | ||
155 | /* do dummy read if needed */ | |
156 | if (addr & SPRD_MASK) | |
157 | slen++; | |
158 | ||
159 | tx_buf[0] = op | (addr & ADDR_MASK); | |
160 | ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen); | |
161 | if (ret) | |
162 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 163 | __func__, ret); |
3ec9c11d CL |
164 | else |
165 | val = rx_buf[slen - 1]; | |
166 | ||
167 | return val; | |
168 | } | |
169 | ||
170 | /* | |
171 | * basic SPI write operation | |
172 | */ | |
173 | static int spi_write_op(struct enc28j60_net *priv, u8 op, | |
174 | u8 addr, u8 val) | |
175 | { | |
176 | int ret; | |
177 | ||
178 | priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); | |
179 | priv->spi_transfer_buf[1] = val; | |
180 | ret = spi_write(priv->spi, priv->spi_transfer_buf, 2); | |
181 | if (ret && netif_msg_drv(priv)) | |
182 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 183 | __func__, ret); |
3ec9c11d CL |
184 | return ret; |
185 | } | |
186 | ||
187 | static void enc28j60_soft_reset(struct enc28j60_net *priv) | |
188 | { | |
189 | if (netif_msg_hw(priv)) | |
b39d66a8 | 190 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
191 | |
192 | spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); | |
193 | /* Errata workaround #1, CLKRDY check is unreliable, | |
194 | * delay at least 1 mS instead */ | |
195 | udelay(2000); | |
196 | } | |
197 | ||
198 | /* | |
199 | * select the current register bank if necessary | |
200 | */ | |
201 | static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr) | |
202 | { | |
5664dd55 | 203 | u8 b = (addr & BANK_MASK) >> 5; |
3ec9c11d | 204 | |
5664dd55 BS |
205 | /* These registers (EIE, EIR, ESTAT, ECON2, ECON1) |
206 | * are present in all banks, no need to switch bank | |
207 | */ | |
208 | if (addr >= EIE && addr <= ECON1) | |
209 | return; | |
210 | ||
211 | /* Clear or set each bank selection bit as needed */ | |
212 | if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) { | |
213 | if (b & ECON1_BSEL0) | |
214 | spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, | |
215 | ECON1_BSEL0); | |
216 | else | |
217 | spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, | |
218 | ECON1_BSEL0); | |
219 | } | |
220 | if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) { | |
221 | if (b & ECON1_BSEL1) | |
222 | spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, | |
223 | ECON1_BSEL1); | |
224 | else | |
3ec9c11d | 225 | spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, |
5664dd55 | 226 | ECON1_BSEL1); |
3ec9c11d | 227 | } |
5664dd55 | 228 | priv->bank = b; |
3ec9c11d CL |
229 | } |
230 | ||
231 | /* | |
232 | * Register access routines through the SPI bus. | |
233 | * Every register access comes in two flavours: | |
234 | * - nolock_xxx: caller needs to invoke mutex_lock, usually to access | |
235 | * atomically more than one register | |
236 | * - locked_xxx: caller doesn't need to invoke mutex_lock, single access | |
237 | * | |
238 | * Some registers can be accessed through the bit field clear and | |
239 | * bit field set to avoid a read modify write cycle. | |
240 | */ | |
241 | ||
242 | /* | |
243 | * Register bit field Set | |
244 | */ | |
245 | static void nolock_reg_bfset(struct enc28j60_net *priv, | |
246 | u8 addr, u8 mask) | |
247 | { | |
248 | enc28j60_set_bank(priv, addr); | |
249 | spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask); | |
250 | } | |
251 | ||
252 | static void locked_reg_bfset(struct enc28j60_net *priv, | |
253 | u8 addr, u8 mask) | |
254 | { | |
255 | mutex_lock(&priv->lock); | |
256 | nolock_reg_bfset(priv, addr, mask); | |
257 | mutex_unlock(&priv->lock); | |
258 | } | |
259 | ||
260 | /* | |
261 | * Register bit field Clear | |
262 | */ | |
263 | static void nolock_reg_bfclr(struct enc28j60_net *priv, | |
264 | u8 addr, u8 mask) | |
265 | { | |
266 | enc28j60_set_bank(priv, addr); | |
267 | spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask); | |
268 | } | |
269 | ||
270 | static void locked_reg_bfclr(struct enc28j60_net *priv, | |
271 | u8 addr, u8 mask) | |
272 | { | |
273 | mutex_lock(&priv->lock); | |
274 | nolock_reg_bfclr(priv, addr, mask); | |
275 | mutex_unlock(&priv->lock); | |
276 | } | |
277 | ||
278 | /* | |
279 | * Register byte read | |
280 | */ | |
281 | static int nolock_regb_read(struct enc28j60_net *priv, | |
282 | u8 address) | |
283 | { | |
284 | enc28j60_set_bank(priv, address); | |
285 | return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); | |
286 | } | |
287 | ||
288 | static int locked_regb_read(struct enc28j60_net *priv, | |
289 | u8 address) | |
290 | { | |
291 | int ret; | |
292 | ||
293 | mutex_lock(&priv->lock); | |
294 | ret = nolock_regb_read(priv, address); | |
295 | mutex_unlock(&priv->lock); | |
296 | ||
297 | return ret; | |
298 | } | |
299 | ||
300 | /* | |
301 | * Register word read | |
302 | */ | |
303 | static int nolock_regw_read(struct enc28j60_net *priv, | |
304 | u8 address) | |
305 | { | |
306 | int rl, rh; | |
307 | ||
308 | enc28j60_set_bank(priv, address); | |
309 | rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); | |
310 | rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1); | |
311 | ||
312 | return (rh << 8) | rl; | |
313 | } | |
314 | ||
315 | static int locked_regw_read(struct enc28j60_net *priv, | |
316 | u8 address) | |
317 | { | |
318 | int ret; | |
319 | ||
320 | mutex_lock(&priv->lock); | |
321 | ret = nolock_regw_read(priv, address); | |
322 | mutex_unlock(&priv->lock); | |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
327 | /* | |
328 | * Register byte write | |
329 | */ | |
330 | static void nolock_regb_write(struct enc28j60_net *priv, | |
331 | u8 address, u8 data) | |
332 | { | |
333 | enc28j60_set_bank(priv, address); | |
334 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data); | |
335 | } | |
336 | ||
337 | static void locked_regb_write(struct enc28j60_net *priv, | |
338 | u8 address, u8 data) | |
339 | { | |
340 | mutex_lock(&priv->lock); | |
341 | nolock_regb_write(priv, address, data); | |
342 | mutex_unlock(&priv->lock); | |
343 | } | |
344 | ||
345 | /* | |
346 | * Register word write | |
347 | */ | |
348 | static void nolock_regw_write(struct enc28j60_net *priv, | |
349 | u8 address, u16 data) | |
350 | { | |
351 | enc28j60_set_bank(priv, address); | |
352 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data); | |
353 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1, | |
354 | (u8) (data >> 8)); | |
355 | } | |
356 | ||
357 | static void locked_regw_write(struct enc28j60_net *priv, | |
358 | u8 address, u16 data) | |
359 | { | |
360 | mutex_lock(&priv->lock); | |
361 | nolock_regw_write(priv, address, data); | |
362 | mutex_unlock(&priv->lock); | |
363 | } | |
364 | ||
365 | /* | |
366 | * Buffer memory read | |
367 | * Select the starting address and execute a SPI buffer read | |
368 | */ | |
369 | static void enc28j60_mem_read(struct enc28j60_net *priv, | |
370 | u16 addr, int len, u8 *data) | |
371 | { | |
372 | mutex_lock(&priv->lock); | |
373 | nolock_regw_write(priv, ERDPTL, addr); | |
374 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
375 | if (netif_msg_drv(priv)) { | |
376 | u16 reg; | |
377 | reg = nolock_regw_read(priv, ERDPTL); | |
378 | if (reg != addr) | |
379 | printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT " | |
b39d66a8 | 380 | "(0x%04x - 0x%04x)\n", __func__, reg, addr); |
3ec9c11d CL |
381 | } |
382 | #endif | |
383 | spi_read_buf(priv, len, data); | |
384 | mutex_unlock(&priv->lock); | |
385 | } | |
386 | ||
387 | /* | |
388 | * Write packet to enc28j60 TX buffer memory | |
389 | */ | |
390 | static void | |
391 | enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data) | |
392 | { | |
393 | mutex_lock(&priv->lock); | |
394 | /* Set the write pointer to start of transmit buffer area */ | |
395 | nolock_regw_write(priv, EWRPTL, TXSTART_INIT); | |
396 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
397 | if (netif_msg_drv(priv)) { | |
398 | u16 reg; | |
399 | reg = nolock_regw_read(priv, EWRPTL); | |
400 | if (reg != TXSTART_INIT) | |
401 | printk(KERN_DEBUG DRV_NAME | |
402 | ": %s() ERWPT:0x%04x != 0x%04x\n", | |
b39d66a8 | 403 | __func__, reg, TXSTART_INIT); |
3ec9c11d CL |
404 | } |
405 | #endif | |
406 | /* Set the TXND pointer to correspond to the packet size given */ | |
407 | nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len); | |
408 | /* write per-packet control byte */ | |
409 | spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00); | |
410 | if (netif_msg_hw(priv)) | |
411 | printk(KERN_DEBUG DRV_NAME | |
412 | ": %s() after control byte ERWPT:0x%04x\n", | |
b39d66a8 | 413 | __func__, nolock_regw_read(priv, EWRPTL)); |
3ec9c11d CL |
414 | /* copy the packet into the transmit buffer */ |
415 | spi_write_buf(priv, len, data); | |
416 | if (netif_msg_hw(priv)) | |
417 | printk(KERN_DEBUG DRV_NAME | |
418 | ": %s() after write packet ERWPT:0x%04x, len=%d\n", | |
b39d66a8 | 419 | __func__, nolock_regw_read(priv, EWRPTL), len); |
3ec9c11d CL |
420 | mutex_unlock(&priv->lock); |
421 | } | |
422 | ||
7dac6f8d DB |
423 | static unsigned long msec20_to_jiffies; |
424 | ||
425 | static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val) | |
3ec9c11d | 426 | { |
7dac6f8d | 427 | unsigned long timeout = jiffies + msec20_to_jiffies; |
3ec9c11d CL |
428 | |
429 | /* 20 msec timeout read */ | |
7dac6f8d | 430 | while ((nolock_regb_read(priv, reg) & mask) != val) { |
3ec9c11d CL |
431 | if (time_after(jiffies, timeout)) { |
432 | if (netif_msg_drv(priv)) | |
7dac6f8d DB |
433 | dev_dbg(&priv->spi->dev, |
434 | "reg %02x ready timeout!\n", reg); | |
435 | return -ETIMEDOUT; | |
3ec9c11d CL |
436 | } |
437 | cpu_relax(); | |
438 | } | |
7dac6f8d DB |
439 | return 0; |
440 | } | |
441 | ||
442 | /* | |
443 | * Wait until the PHY operation is complete. | |
444 | */ | |
445 | static int wait_phy_ready(struct enc28j60_net *priv) | |
446 | { | |
447 | return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1; | |
3ec9c11d CL |
448 | } |
449 | ||
450 | /* | |
451 | * PHY register read | |
452 | * PHY registers are not accessed directly, but through the MII | |
453 | */ | |
454 | static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address) | |
455 | { | |
456 | u16 ret; | |
457 | ||
458 | mutex_lock(&priv->lock); | |
459 | /* set the PHY register address */ | |
460 | nolock_regb_write(priv, MIREGADR, address); | |
461 | /* start the register read operation */ | |
462 | nolock_regb_write(priv, MICMD, MICMD_MIIRD); | |
463 | /* wait until the PHY read completes */ | |
464 | wait_phy_ready(priv); | |
465 | /* quit reading */ | |
466 | nolock_regb_write(priv, MICMD, 0x00); | |
467 | /* return the data */ | |
468 | ret = nolock_regw_read(priv, MIRDL); | |
469 | mutex_unlock(&priv->lock); | |
470 | ||
471 | return ret; | |
472 | } | |
473 | ||
474 | static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data) | |
475 | { | |
476 | int ret; | |
477 | ||
478 | mutex_lock(&priv->lock); | |
479 | /* set the PHY register address */ | |
480 | nolock_regb_write(priv, MIREGADR, address); | |
481 | /* write the PHY data */ | |
482 | nolock_regw_write(priv, MIWRL, data); | |
483 | /* wait until the PHY write completes and return */ | |
484 | ret = wait_phy_ready(priv); | |
485 | mutex_unlock(&priv->lock); | |
486 | ||
487 | return ret; | |
488 | } | |
489 | ||
490 | /* | |
491 | * Program the hardware MAC address from dev->dev_addr. | |
492 | */ | |
493 | static int enc28j60_set_hw_macaddr(struct net_device *ndev) | |
494 | { | |
495 | int ret; | |
496 | struct enc28j60_net *priv = netdev_priv(ndev); | |
497 | ||
498 | mutex_lock(&priv->lock); | |
499 | if (!priv->hw_enable) { | |
e174961c | 500 | if (netif_msg_drv(priv)) |
3ec9c11d | 501 | printk(KERN_INFO DRV_NAME |
e174961c JB |
502 | ": %s: Setting MAC address to %pM\n", |
503 | ndev->name, ndev->dev_addr); | |
3ec9c11d CL |
504 | /* NOTE: MAC address in ENC28J60 is byte-backward */ |
505 | nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]); | |
506 | nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]); | |
507 | nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]); | |
508 | nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]); | |
509 | nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]); | |
510 | nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]); | |
511 | ret = 0; | |
512 | } else { | |
513 | if (netif_msg_drv(priv)) | |
514 | printk(KERN_DEBUG DRV_NAME | |
515 | ": %s() Hardware must be disabled to set " | |
b39d66a8 | 516 | "Mac address\n", __func__); |
3ec9c11d CL |
517 | ret = -EBUSY; |
518 | } | |
519 | mutex_unlock(&priv->lock); | |
520 | return ret; | |
521 | } | |
522 | ||
523 | /* | |
524 | * Store the new hardware address in dev->dev_addr, and update the MAC. | |
525 | */ | |
526 | static int enc28j60_set_mac_address(struct net_device *dev, void *addr) | |
527 | { | |
528 | struct sockaddr *address = addr; | |
529 | ||
530 | if (netif_running(dev)) | |
531 | return -EBUSY; | |
532 | if (!is_valid_ether_addr(address->sa_data)) | |
533 | return -EADDRNOTAVAIL; | |
534 | ||
535 | memcpy(dev->dev_addr, address->sa_data, dev->addr_len); | |
536 | return enc28j60_set_hw_macaddr(dev); | |
537 | } | |
538 | ||
539 | /* | |
540 | * Debug routine to dump useful register contents | |
541 | */ | |
542 | static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg) | |
543 | { | |
544 | mutex_lock(&priv->lock); | |
545 | printk(KERN_DEBUG DRV_NAME " %s\n" | |
546 | "HwRevID: 0x%02x\n" | |
547 | "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n" | |
548 | " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" | |
549 | "MAC : MACON1 MACON3 MACON4\n" | |
550 | " 0x%02x 0x%02x 0x%02x\n" | |
551 | "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n" | |
552 | " 0x%04x 0x%04x 0x%04x 0x%04x " | |
553 | "0x%02x 0x%02x 0x%04x\n" | |
554 | "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n" | |
555 | " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n", | |
556 | msg, nolock_regb_read(priv, EREVID), | |
557 | nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2), | |
558 | nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR), | |
559 | nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1), | |
560 | nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4), | |
561 | nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL), | |
562 | nolock_regw_read(priv, ERXWRPTL), | |
563 | nolock_regw_read(priv, ERXRDPTL), | |
564 | nolock_regb_read(priv, ERXFCON), | |
565 | nolock_regb_read(priv, EPKTCNT), | |
566 | nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL), | |
567 | nolock_regw_read(priv, ETXNDL), | |
568 | nolock_regb_read(priv, MACLCON1), | |
569 | nolock_regb_read(priv, MACLCON2), | |
570 | nolock_regb_read(priv, MAPHSUP)); | |
571 | mutex_unlock(&priv->lock); | |
572 | } | |
573 | ||
574 | /* | |
575 | * ERXRDPT need to be set always at odd addresses, refer to errata datasheet | |
576 | */ | |
577 | static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end) | |
578 | { | |
579 | u16 erxrdpt; | |
580 | ||
581 | if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end)) | |
582 | erxrdpt = end; | |
583 | else | |
584 | erxrdpt = next_packet_ptr - 1; | |
585 | ||
586 | return erxrdpt; | |
587 | } | |
588 | ||
5176da7e BS |
589 | /* |
590 | * Calculate wrap around when reading beyond the end of the RX buffer | |
591 | */ | |
592 | static u16 rx_packet_start(u16 ptr) | |
593 | { | |
594 | if (ptr + RSV_SIZE > RXEND_INIT) | |
595 | return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1); | |
596 | else | |
597 | return ptr + RSV_SIZE; | |
598 | } | |
599 | ||
3ec9c11d CL |
600 | static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end) |
601 | { | |
602 | u16 erxrdpt; | |
603 | ||
604 | if (start > 0x1FFF || end > 0x1FFF || start > end) { | |
605 | if (netif_msg_drv(priv)) | |
606 | printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO " | |
b39d66a8 | 607 | "bad parameters!\n", __func__, start, end); |
3ec9c11d CL |
608 | return; |
609 | } | |
610 | /* set receive buffer start + end */ | |
611 | priv->next_pk_ptr = start; | |
612 | nolock_regw_write(priv, ERXSTL, start); | |
613 | erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end); | |
614 | nolock_regw_write(priv, ERXRDPTL, erxrdpt); | |
615 | nolock_regw_write(priv, ERXNDL, end); | |
616 | } | |
617 | ||
618 | static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end) | |
619 | { | |
620 | if (start > 0x1FFF || end > 0x1FFF || start > end) { | |
621 | if (netif_msg_drv(priv)) | |
622 | printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO " | |
b39d66a8 | 623 | "bad parameters!\n", __func__, start, end); |
3ec9c11d CL |
624 | return; |
625 | } | |
626 | /* set transmit buffer start + end */ | |
627 | nolock_regw_write(priv, ETXSTL, start); | |
628 | nolock_regw_write(priv, ETXNDL, end); | |
629 | } | |
630 | ||
7dac6f8d DB |
631 | /* |
632 | * Low power mode shrinks power consumption about 100x, so we'd like | |
633 | * the chip to be in that mode whenever it's inactive. (However, we | |
634 | * can't stay in lowpower mode during suspend with WOL active.) | |
635 | */ | |
636 | static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low) | |
637 | { | |
638 | if (netif_msg_drv(priv)) | |
639 | dev_dbg(&priv->spi->dev, "%s power...\n", | |
640 | is_low ? "low" : "high"); | |
641 | ||
642 | mutex_lock(&priv->lock); | |
643 | if (is_low) { | |
644 | nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); | |
645 | poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0); | |
646 | poll_ready(priv, ECON1, ECON1_TXRTS, 0); | |
647 | /* ECON2_VRPS was set during initialization */ | |
648 | nolock_reg_bfset(priv, ECON2, ECON2_PWRSV); | |
649 | } else { | |
650 | nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV); | |
651 | poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY); | |
652 | /* caller sets ECON1_RXEN */ | |
653 | } | |
654 | mutex_unlock(&priv->lock); | |
655 | } | |
656 | ||
3ec9c11d CL |
657 | static int enc28j60_hw_init(struct enc28j60_net *priv) |
658 | { | |
659 | u8 reg; | |
660 | ||
661 | if (netif_msg_drv(priv)) | |
b39d66a8 | 662 | printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__, |
3ec9c11d CL |
663 | priv->full_duplex ? "FullDuplex" : "HalfDuplex"); |
664 | ||
665 | mutex_lock(&priv->lock); | |
666 | /* first reset the chip */ | |
667 | enc28j60_soft_reset(priv); | |
668 | /* Clear ECON1 */ | |
669 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00); | |
670 | priv->bank = 0; | |
671 | priv->hw_enable = false; | |
672 | priv->tx_retry_count = 0; | |
673 | priv->max_pk_counter = 0; | |
674 | priv->rxfilter = RXFILTER_NORMAL; | |
7dac6f8d DB |
675 | /* enable address auto increment and voltage regulator powersave */ |
676 | nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS); | |
3ec9c11d CL |
677 | |
678 | nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); | |
679 | nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); | |
680 | mutex_unlock(&priv->lock); | |
681 | ||
682 | /* | |
683 | * Check the RevID. | |
684 | * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or | |
685 | * damaged | |
686 | */ | |
687 | reg = locked_regb_read(priv, EREVID); | |
688 | if (netif_msg_drv(priv)) | |
689 | printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg); | |
690 | if (reg == 0x00 || reg == 0xff) { | |
691 | if (netif_msg_drv(priv)) | |
692 | printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n", | |
b39d66a8 | 693 | __func__, reg); |
3ec9c11d CL |
694 | return 0; |
695 | } | |
696 | ||
697 | /* default filter mode: (unicast OR broadcast) AND crc valid */ | |
698 | locked_regb_write(priv, ERXFCON, | |
699 | ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); | |
700 | ||
701 | /* enable MAC receive */ | |
702 | locked_regb_write(priv, MACON1, | |
703 | MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); | |
704 | /* enable automatic padding and CRC operations */ | |
705 | if (priv->full_duplex) { | |
706 | locked_regb_write(priv, MACON3, | |
707 | MACON3_PADCFG0 | MACON3_TXCRCEN | | |
708 | MACON3_FRMLNEN | MACON3_FULDPX); | |
709 | /* set inter-frame gap (non-back-to-back) */ | |
710 | locked_regb_write(priv, MAIPGL, 0x12); | |
711 | /* set inter-frame gap (back-to-back) */ | |
712 | locked_regb_write(priv, MABBIPG, 0x15); | |
713 | } else { | |
714 | locked_regb_write(priv, MACON3, | |
715 | MACON3_PADCFG0 | MACON3_TXCRCEN | | |
716 | MACON3_FRMLNEN); | |
717 | locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */ | |
718 | /* set inter-frame gap (non-back-to-back) */ | |
719 | locked_regw_write(priv, MAIPGL, 0x0C12); | |
720 | /* set inter-frame gap (back-to-back) */ | |
721 | locked_regb_write(priv, MABBIPG, 0x12); | |
722 | } | |
723 | /* | |
724 | * MACLCON1 (default) | |
725 | * MACLCON2 (default) | |
726 | * Set the maximum packet size which the controller will accept | |
727 | */ | |
728 | locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN); | |
729 | ||
730 | /* Configure LEDs */ | |
731 | if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE)) | |
732 | return 0; | |
733 | ||
734 | if (priv->full_duplex) { | |
735 | if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD)) | |
736 | return 0; | |
737 | if (!enc28j60_phy_write(priv, PHCON2, 0x00)) | |
738 | return 0; | |
739 | } else { | |
740 | if (!enc28j60_phy_write(priv, PHCON1, 0x00)) | |
741 | return 0; | |
742 | if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS)) | |
743 | return 0; | |
744 | } | |
745 | if (netif_msg_hw(priv)) | |
746 | enc28j60_dump_regs(priv, "Hw initialized."); | |
747 | ||
748 | return 1; | |
749 | } | |
750 | ||
751 | static void enc28j60_hw_enable(struct enc28j60_net *priv) | |
752 | { | |
7dac6f8d | 753 | /* enable interrupts */ |
3ec9c11d CL |
754 | if (netif_msg_hw(priv)) |
755 | printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n", | |
b39d66a8 | 756 | __func__); |
3ec9c11d CL |
757 | |
758 | enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE); | |
759 | ||
760 | mutex_lock(&priv->lock); | |
761 | nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF | | |
762 | EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF); | |
763 | nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE | | |
764 | EIE_TXIE | EIE_TXERIE | EIE_RXERIE); | |
765 | ||
766 | /* enable receive logic */ | |
767 | nolock_reg_bfset(priv, ECON1, ECON1_RXEN); | |
768 | priv->hw_enable = true; | |
769 | mutex_unlock(&priv->lock); | |
770 | } | |
771 | ||
772 | static void enc28j60_hw_disable(struct enc28j60_net *priv) | |
773 | { | |
774 | mutex_lock(&priv->lock); | |
775 | /* disable interrutps and packet reception */ | |
776 | nolock_regb_write(priv, EIE, 0x00); | |
777 | nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); | |
778 | priv->hw_enable = false; | |
779 | mutex_unlock(&priv->lock); | |
780 | } | |
781 | ||
782 | static int | |
783 | enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex) | |
784 | { | |
785 | struct enc28j60_net *priv = netdev_priv(ndev); | |
786 | int ret = 0; | |
787 | ||
788 | if (!priv->hw_enable) { | |
7dac6f8d DB |
789 | /* link is in low power mode now; duplex setting |
790 | * will take effect on next enc28j60_hw_init(). | |
791 | */ | |
792 | if (autoneg == AUTONEG_DISABLE && speed == SPEED_10) | |
3ec9c11d | 793 | priv->full_duplex = (duplex == DUPLEX_FULL); |
7dac6f8d | 794 | else { |
3ec9c11d CL |
795 | if (netif_msg_link(priv)) |
796 | dev_warn(&ndev->dev, | |
797 | "unsupported link setting\n"); | |
798 | ret = -EOPNOTSUPP; | |
799 | } | |
800 | } else { | |
801 | if (netif_msg_link(priv)) | |
802 | dev_warn(&ndev->dev, "Warning: hw must be disabled " | |
803 | "to set link mode\n"); | |
804 | ret = -EBUSY; | |
805 | } | |
806 | return ret; | |
807 | } | |
808 | ||
809 | /* | |
810 | * Read the Transmit Status Vector | |
811 | */ | |
812 | static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE]) | |
813 | { | |
814 | int endptr; | |
815 | ||
816 | endptr = locked_regw_read(priv, ETXNDL); | |
817 | if (netif_msg_hw(priv)) | |
818 | printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n", | |
819 | endptr + 1); | |
fca540ab | 820 | enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv); |
3ec9c11d CL |
821 | } |
822 | ||
823 | static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg, | |
824 | u8 tsv[TSV_SIZE]) | |
825 | { | |
826 | u16 tmp1, tmp2; | |
827 | ||
828 | printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg); | |
829 | tmp1 = tsv[1]; | |
830 | tmp1 <<= 8; | |
831 | tmp1 |= tsv[0]; | |
832 | ||
833 | tmp2 = tsv[5]; | |
834 | tmp2 <<= 8; | |
835 | tmp2 |= tsv[4]; | |
836 | ||
837 | printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d," | |
838 | " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2); | |
839 | printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d," | |
840 | " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE), | |
841 | TSV_GETBIT(tsv, TSV_TXCRCERROR), | |
842 | TSV_GETBIT(tsv, TSV_TXLENCHKERROR), | |
843 | TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE)); | |
844 | printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, " | |
845 | "PacketDefer: %d, ExDefer: %d\n", | |
846 | TSV_GETBIT(tsv, TSV_TXMULTICAST), | |
847 | TSV_GETBIT(tsv, TSV_TXBROADCAST), | |
848 | TSV_GETBIT(tsv, TSV_TXPACKETDEFER), | |
849 | TSV_GETBIT(tsv, TSV_TXEXDEFER)); | |
850 | printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, " | |
851 | "Giant: %d, Underrun: %d\n", | |
852 | TSV_GETBIT(tsv, TSV_TXEXCOLLISION), | |
853 | TSV_GETBIT(tsv, TSV_TXLATECOLLISION), | |
854 | TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN)); | |
855 | printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, " | |
856 | "BackPressApp: %d, VLanTagFrame: %d\n", | |
857 | TSV_GETBIT(tsv, TSV_TXCONTROLFRAME), | |
858 | TSV_GETBIT(tsv, TSV_TXPAUSEFRAME), | |
859 | TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP), | |
860 | TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME)); | |
861 | } | |
862 | ||
863 | /* | |
864 | * Receive Status vector | |
865 | */ | |
866 | static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg, | |
867 | u16 pk_ptr, int len, u16 sts) | |
868 | { | |
869 | printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n", | |
870 | msg, pk_ptr); | |
871 | printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len, | |
872 | RSV_GETBIT(sts, RSV_DRIBBLENIBBLE)); | |
873 | printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d," | |
874 | " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK), | |
875 | RSV_GETBIT(sts, RSV_CRCERROR), | |
876 | RSV_GETBIT(sts, RSV_LENCHECKERR), | |
877 | RSV_GETBIT(sts, RSV_LENOUTOFRANGE)); | |
878 | printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, " | |
879 | "LongDropEvent: %d, CarrierEvent: %d\n", | |
880 | RSV_GETBIT(sts, RSV_RXMULTICAST), | |
881 | RSV_GETBIT(sts, RSV_RXBROADCAST), | |
882 | RSV_GETBIT(sts, RSV_RXLONGEVDROPEV), | |
883 | RSV_GETBIT(sts, RSV_CARRIEREV)); | |
884 | printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d," | |
885 | " UnknownOp: %d, VLanTagFrame: %d\n", | |
886 | RSV_GETBIT(sts, RSV_RXCONTROLFRAME), | |
887 | RSV_GETBIT(sts, RSV_RXPAUSEFRAME), | |
888 | RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE), | |
889 | RSV_GETBIT(sts, RSV_RXTYPEVLAN)); | |
890 | } | |
891 | ||
892 | static void dump_packet(const char *msg, int len, const char *data) | |
893 | { | |
894 | printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len); | |
895 | print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1, | |
896 | data, len, true); | |
897 | } | |
898 | ||
899 | /* | |
900 | * Hardware receive function. | |
901 | * Read the buffer memory, update the FIFO pointer to free the buffer, | |
902 | * check the status vector and decrement the packet counter. | |
903 | */ | |
904 | static void enc28j60_hw_rx(struct net_device *ndev) | |
905 | { | |
906 | struct enc28j60_net *priv = netdev_priv(ndev); | |
907 | struct sk_buff *skb = NULL; | |
908 | u16 erxrdpt, next_packet, rxstat; | |
909 | u8 rsv[RSV_SIZE]; | |
910 | int len; | |
911 | ||
912 | if (netif_msg_rx_status(priv)) | |
913 | printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n", | |
914 | priv->next_pk_ptr); | |
915 | ||
916 | if (unlikely(priv->next_pk_ptr > RXEND_INIT)) { | |
917 | if (netif_msg_rx_err(priv)) | |
918 | dev_err(&ndev->dev, | |
919 | "%s() Invalid packet address!! 0x%04x\n", | |
b39d66a8 | 920 | __func__, priv->next_pk_ptr); |
3ec9c11d CL |
921 | /* packet address corrupted: reset RX logic */ |
922 | mutex_lock(&priv->lock); | |
923 | nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); | |
924 | nolock_reg_bfset(priv, ECON1, ECON1_RXRST); | |
925 | nolock_reg_bfclr(priv, ECON1, ECON1_RXRST); | |
926 | nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); | |
927 | nolock_reg_bfclr(priv, EIR, EIR_RXERIF); | |
928 | nolock_reg_bfset(priv, ECON1, ECON1_RXEN); | |
929 | mutex_unlock(&priv->lock); | |
930 | ndev->stats.rx_errors++; | |
931 | return; | |
932 | } | |
933 | /* Read next packet pointer and rx status vector */ | |
934 | enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv); | |
935 | ||
936 | next_packet = rsv[1]; | |
937 | next_packet <<= 8; | |
938 | next_packet |= rsv[0]; | |
939 | ||
940 | len = rsv[3]; | |
941 | len <<= 8; | |
942 | len |= rsv[2]; | |
943 | ||
944 | rxstat = rsv[5]; | |
945 | rxstat <<= 8; | |
946 | rxstat |= rsv[4]; | |
947 | ||
948 | if (netif_msg_rx_status(priv)) | |
b39d66a8 | 949 | enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat); |
3ec9c11d | 950 | |
22692018 | 951 | if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) { |
3ec9c11d CL |
952 | if (netif_msg_rx_err(priv)) |
953 | dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat); | |
954 | ndev->stats.rx_errors++; | |
955 | if (RSV_GETBIT(rxstat, RSV_CRCERROR)) | |
956 | ndev->stats.rx_crc_errors++; | |
957 | if (RSV_GETBIT(rxstat, RSV_LENCHECKERR)) | |
958 | ndev->stats.rx_frame_errors++; | |
22692018 BS |
959 | if (len > MAX_FRAMELEN) |
960 | ndev->stats.rx_over_errors++; | |
3ec9c11d | 961 | } else { |
c056b734 | 962 | skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN); |
3ec9c11d CL |
963 | if (!skb) { |
964 | if (netif_msg_rx_err(priv)) | |
965 | dev_err(&ndev->dev, | |
966 | "out of memory for Rx'd frame\n"); | |
967 | ndev->stats.rx_dropped++; | |
968 | } else { | |
02ff05c4 | 969 | skb_reserve(skb, NET_IP_ALIGN); |
3ec9c11d | 970 | /* copy the packet from the receive buffer */ |
5176da7e BS |
971 | enc28j60_mem_read(priv, |
972 | rx_packet_start(priv->next_pk_ptr), | |
973 | len, skb_put(skb, len)); | |
3ec9c11d | 974 | if (netif_msg_pktdata(priv)) |
b39d66a8 | 975 | dump_packet(__func__, skb->len, skb->data); |
3ec9c11d CL |
976 | skb->protocol = eth_type_trans(skb, ndev); |
977 | /* update statistics */ | |
978 | ndev->stats.rx_packets++; | |
979 | ndev->stats.rx_bytes += len; | |
2c413a64 | 980 | netif_rx_ni(skb); |
3ec9c11d CL |
981 | } |
982 | } | |
983 | /* | |
984 | * Move the RX read pointer to the start of the next | |
985 | * received packet. | |
986 | * This frees the memory we just read out | |
987 | */ | |
988 | erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT); | |
989 | if (netif_msg_hw(priv)) | |
990 | printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n", | |
b39d66a8 | 991 | __func__, erxrdpt); |
3ec9c11d CL |
992 | |
993 | mutex_lock(&priv->lock); | |
994 | nolock_regw_write(priv, ERXRDPTL, erxrdpt); | |
995 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
996 | if (netif_msg_drv(priv)) { | |
997 | u16 reg; | |
998 | reg = nolock_regw_read(priv, ERXRDPTL); | |
999 | if (reg != erxrdpt) | |
1000 | printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify " | |
b39d66a8 | 1001 | "error (0x%04x - 0x%04x)\n", __func__, |
3ec9c11d CL |
1002 | reg, erxrdpt); |
1003 | } | |
1004 | #endif | |
1005 | priv->next_pk_ptr = next_packet; | |
1006 | /* we are done with this packet, decrement the packet counter */ | |
1007 | nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC); | |
1008 | mutex_unlock(&priv->lock); | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * Calculate free space in RxFIFO | |
1013 | */ | |
1014 | static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv) | |
1015 | { | |
1016 | int epkcnt, erxst, erxnd, erxwr, erxrd; | |
1017 | int free_space; | |
1018 | ||
1019 | mutex_lock(&priv->lock); | |
1020 | epkcnt = nolock_regb_read(priv, EPKTCNT); | |
1021 | if (epkcnt >= 255) | |
1022 | free_space = -1; | |
1023 | else { | |
1024 | erxst = nolock_regw_read(priv, ERXSTL); | |
1025 | erxnd = nolock_regw_read(priv, ERXNDL); | |
1026 | erxwr = nolock_regw_read(priv, ERXWRPTL); | |
1027 | erxrd = nolock_regw_read(priv, ERXRDPTL); | |
1028 | ||
1029 | if (erxwr > erxrd) | |
1030 | free_space = (erxnd - erxst) - (erxwr - erxrd); | |
1031 | else if (erxwr == erxrd) | |
1032 | free_space = (erxnd - erxst); | |
1033 | else | |
1034 | free_space = erxrd - erxwr - 1; | |
1035 | } | |
1036 | mutex_unlock(&priv->lock); | |
1037 | if (netif_msg_rx_status(priv)) | |
1038 | printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n", | |
b39d66a8 | 1039 | __func__, free_space); |
3ec9c11d CL |
1040 | return free_space; |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Access the PHY to determine link status | |
1045 | */ | |
1046 | static void enc28j60_check_link_status(struct net_device *ndev) | |
1047 | { | |
1048 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1049 | u16 reg; | |
1050 | int duplex; | |
1051 | ||
1052 | reg = enc28j60_phy_read(priv, PHSTAT2); | |
1053 | if (netif_msg_hw(priv)) | |
1054 | printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, " | |
b39d66a8 | 1055 | "PHSTAT2: %04x\n", __func__, |
3ec9c11d CL |
1056 | enc28j60_phy_read(priv, PHSTAT1), reg); |
1057 | duplex = reg & PHSTAT2_DPXSTAT; | |
1058 | ||
1059 | if (reg & PHSTAT2_LSTAT) { | |
1060 | netif_carrier_on(ndev); | |
1061 | if (netif_msg_ifup(priv)) | |
1062 | dev_info(&ndev->dev, "link up - %s\n", | |
1063 | duplex ? "Full duplex" : "Half duplex"); | |
1064 | } else { | |
1065 | if (netif_msg_ifdown(priv)) | |
1066 | dev_info(&ndev->dev, "link down\n"); | |
1067 | netif_carrier_off(ndev); | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | static void enc28j60_tx_clear(struct net_device *ndev, bool err) | |
1072 | { | |
1073 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1074 | ||
1075 | if (err) | |
1076 | ndev->stats.tx_errors++; | |
1077 | else | |
1078 | ndev->stats.tx_packets++; | |
1079 | ||
1080 | if (priv->tx_skb) { | |
1081 | if (!err) | |
1082 | ndev->stats.tx_bytes += priv->tx_skb->len; | |
1083 | dev_kfree_skb(priv->tx_skb); | |
1084 | priv->tx_skb = NULL; | |
1085 | } | |
1086 | locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); | |
1087 | netif_wake_queue(ndev); | |
1088 | } | |
1089 | ||
1090 | /* | |
1091 | * RX handler | |
1092 | * ignore PKTIF because is unreliable! (look at the errata datasheet) | |
1093 | * check EPKTCNT is the suggested workaround. | |
1094 | * We don't need to clear interrupt flag, automatically done when | |
1095 | * enc28j60_hw_rx() decrements the packet counter. | |
1096 | * Returns how many packet processed. | |
1097 | */ | |
1098 | static int enc28j60_rx_interrupt(struct net_device *ndev) | |
1099 | { | |
1100 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1101 | int pk_counter, ret; | |
1102 | ||
1103 | pk_counter = locked_regb_read(priv, EPKTCNT); | |
1104 | if (pk_counter && netif_msg_intr(priv)) | |
1105 | printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter); | |
1106 | if (pk_counter > priv->max_pk_counter) { | |
1107 | /* update statistics */ | |
1108 | priv->max_pk_counter = pk_counter; | |
1109 | if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1) | |
1110 | printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n", | |
1111 | priv->max_pk_counter); | |
1112 | } | |
1113 | ret = pk_counter; | |
1114 | while (pk_counter-- > 0) | |
1115 | enc28j60_hw_rx(ndev); | |
1116 | ||
1117 | return ret; | |
1118 | } | |
1119 | ||
1120 | static void enc28j60_irq_work_handler(struct work_struct *work) | |
1121 | { | |
1122 | struct enc28j60_net *priv = | |
1123 | container_of(work, struct enc28j60_net, irq_work); | |
1124 | struct net_device *ndev = priv->netdev; | |
1125 | int intflags, loop; | |
1126 | ||
1127 | if (netif_msg_intr(priv)) | |
b39d66a8 | 1128 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1129 | /* disable further interrupts */ |
1130 | locked_reg_bfclr(priv, EIE, EIE_INTIE); | |
1131 | ||
1132 | do { | |
1133 | loop = 0; | |
1134 | intflags = locked_regb_read(priv, EIR); | |
1135 | /* DMA interrupt handler (not currently used) */ | |
1136 | if ((intflags & EIR_DMAIF) != 0) { | |
1137 | loop++; | |
1138 | if (netif_msg_intr(priv)) | |
1139 | printk(KERN_DEBUG DRV_NAME | |
1140 | ": intDMA(%d)\n", loop); | |
1141 | locked_reg_bfclr(priv, EIR, EIR_DMAIF); | |
1142 | } | |
1143 | /* LINK changed handler */ | |
1144 | if ((intflags & EIR_LINKIF) != 0) { | |
1145 | loop++; | |
1146 | if (netif_msg_intr(priv)) | |
1147 | printk(KERN_DEBUG DRV_NAME | |
1148 | ": intLINK(%d)\n", loop); | |
1149 | enc28j60_check_link_status(ndev); | |
1150 | /* read PHIR to clear the flag */ | |
1151 | enc28j60_phy_read(priv, PHIR); | |
1152 | } | |
1153 | /* TX complete handler */ | |
1154 | if ((intflags & EIR_TXIF) != 0) { | |
1155 | bool err = false; | |
1156 | loop++; | |
1157 | if (netif_msg_intr(priv)) | |
1158 | printk(KERN_DEBUG DRV_NAME | |
1159 | ": intTX(%d)\n", loop); | |
1160 | priv->tx_retry_count = 0; | |
1161 | if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) { | |
1162 | if (netif_msg_tx_err(priv)) | |
1163 | dev_err(&ndev->dev, | |
1164 | "Tx Error (aborted)\n"); | |
1165 | err = true; | |
1166 | } | |
1167 | if (netif_msg_tx_done(priv)) { | |
1168 | u8 tsv[TSV_SIZE]; | |
1169 | enc28j60_read_tsv(priv, tsv); | |
1170 | enc28j60_dump_tsv(priv, "Tx Done", tsv); | |
1171 | } | |
1172 | enc28j60_tx_clear(ndev, err); | |
1173 | locked_reg_bfclr(priv, EIR, EIR_TXIF); | |
1174 | } | |
1175 | /* TX Error handler */ | |
1176 | if ((intflags & EIR_TXERIF) != 0) { | |
1177 | u8 tsv[TSV_SIZE]; | |
1178 | ||
1179 | loop++; | |
1180 | if (netif_msg_intr(priv)) | |
1181 | printk(KERN_DEBUG DRV_NAME | |
1182 | ": intTXErr(%d)\n", loop); | |
1183 | locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); | |
1184 | enc28j60_read_tsv(priv, tsv); | |
1185 | if (netif_msg_tx_err(priv)) | |
1186 | enc28j60_dump_tsv(priv, "Tx Error", tsv); | |
1187 | /* Reset TX logic */ | |
1188 | mutex_lock(&priv->lock); | |
1189 | nolock_reg_bfset(priv, ECON1, ECON1_TXRST); | |
1190 | nolock_reg_bfclr(priv, ECON1, ECON1_TXRST); | |
1191 | nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); | |
1192 | mutex_unlock(&priv->lock); | |
1193 | /* Transmit Late collision check for retransmit */ | |
1194 | if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) { | |
1195 | if (netif_msg_tx_err(priv)) | |
1196 | printk(KERN_DEBUG DRV_NAME | |
1197 | ": LateCollision TXErr (%d)\n", | |
1198 | priv->tx_retry_count); | |
1199 | if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT) | |
1200 | locked_reg_bfset(priv, ECON1, | |
1201 | ECON1_TXRTS); | |
1202 | else | |
1203 | enc28j60_tx_clear(ndev, true); | |
1204 | } else | |
1205 | enc28j60_tx_clear(ndev, true); | |
1206 | locked_reg_bfclr(priv, EIR, EIR_TXERIF); | |
1207 | } | |
1208 | /* RX Error handler */ | |
1209 | if ((intflags & EIR_RXERIF) != 0) { | |
1210 | loop++; | |
1211 | if (netif_msg_intr(priv)) | |
1212 | printk(KERN_DEBUG DRV_NAME | |
1213 | ": intRXErr(%d)\n", loop); | |
1214 | /* Check free FIFO space to flag RX overrun */ | |
1215 | if (enc28j60_get_free_rxfifo(priv) <= 0) { | |
1216 | if (netif_msg_rx_err(priv)) | |
1217 | printk(KERN_DEBUG DRV_NAME | |
1218 | ": RX Overrun\n"); | |
1219 | ndev->stats.rx_dropped++; | |
1220 | } | |
1221 | locked_reg_bfclr(priv, EIR, EIR_RXERIF); | |
1222 | } | |
1223 | /* RX handler */ | |
1224 | if (enc28j60_rx_interrupt(ndev)) | |
1225 | loop++; | |
1226 | } while (loop); | |
1227 | ||
1228 | /* re-enable interrupts */ | |
1229 | locked_reg_bfset(priv, EIE, EIE_INTIE); | |
1230 | if (netif_msg_intr(priv)) | |
b39d66a8 | 1231 | printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__); |
3ec9c11d CL |
1232 | } |
1233 | ||
1234 | /* | |
1235 | * Hardware transmit function. | |
1236 | * Fill the buffer memory and send the contents of the transmit buffer | |
1237 | * onto the network | |
1238 | */ | |
1239 | static void enc28j60_hw_tx(struct enc28j60_net *priv) | |
1240 | { | |
1241 | if (netif_msg_tx_queued(priv)) | |
1242 | printk(KERN_DEBUG DRV_NAME | |
1243 | ": Tx Packet Len:%d\n", priv->tx_skb->len); | |
1244 | ||
1245 | if (netif_msg_pktdata(priv)) | |
b39d66a8 | 1246 | dump_packet(__func__, |
3ec9c11d CL |
1247 | priv->tx_skb->len, priv->tx_skb->data); |
1248 | enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data); | |
1249 | ||
1250 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
1251 | /* readback and verify written data */ | |
1252 | if (netif_msg_drv(priv)) { | |
1253 | int test_len, k; | |
1254 | u8 test_buf[64]; /* limit the test to the first 64 bytes */ | |
1255 | int okflag; | |
1256 | ||
1257 | test_len = priv->tx_skb->len; | |
1258 | if (test_len > sizeof(test_buf)) | |
1259 | test_len = sizeof(test_buf); | |
1260 | ||
1261 | /* + 1 to skip control byte */ | |
1262 | enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf); | |
1263 | okflag = 1; | |
1264 | for (k = 0; k < test_len; k++) { | |
1265 | if (priv->tx_skb->data[k] != test_buf[k]) { | |
1266 | printk(KERN_DEBUG DRV_NAME | |
1267 | ": Error, %d location differ: " | |
1268 | "0x%02x-0x%02x\n", k, | |
1269 | priv->tx_skb->data[k], test_buf[k]); | |
1270 | okflag = 0; | |
1271 | } | |
1272 | } | |
1273 | if (!okflag) | |
1274 | printk(KERN_DEBUG DRV_NAME ": Tx write buffer, " | |
1275 | "verify ERROR!\n"); | |
1276 | } | |
1277 | #endif | |
1278 | /* set TX request flag */ | |
1279 | locked_reg_bfset(priv, ECON1, ECON1_TXRTS); | |
1280 | } | |
1281 | ||
61357325 SH |
1282 | static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb, |
1283 | struct net_device *dev) | |
3ec9c11d CL |
1284 | { |
1285 | struct enc28j60_net *priv = netdev_priv(dev); | |
1286 | ||
1287 | if (netif_msg_tx_queued(priv)) | |
b39d66a8 | 1288 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1289 | |
1290 | /* If some error occurs while trying to transmit this | |
1291 | * packet, you should return '1' from this function. | |
1292 | * In such a case you _may not_ do anything to the | |
1293 | * SKB, it is still owned by the network queueing | |
1294 | * layer when an error is returned. This means you | |
1295 | * may not modify any SKB fields, you may not free | |
1296 | * the SKB, etc. | |
1297 | */ | |
1298 | netif_stop_queue(dev); | |
1299 | ||
3ec9c11d CL |
1300 | /* Remember the skb for deferred processing */ |
1301 | priv->tx_skb = skb; | |
1302 | schedule_work(&priv->tx_work); | |
1303 | ||
6ed10654 | 1304 | return NETDEV_TX_OK; |
3ec9c11d CL |
1305 | } |
1306 | ||
1307 | static void enc28j60_tx_work_handler(struct work_struct *work) | |
1308 | { | |
1309 | struct enc28j60_net *priv = | |
1310 | container_of(work, struct enc28j60_net, tx_work); | |
1311 | ||
1312 | /* actual delivery of data */ | |
1313 | enc28j60_hw_tx(priv); | |
1314 | } | |
1315 | ||
1316 | static irqreturn_t enc28j60_irq(int irq, void *dev_id) | |
1317 | { | |
1318 | struct enc28j60_net *priv = dev_id; | |
1319 | ||
1320 | /* | |
1321 | * Can't do anything in interrupt context because we need to | |
1322 | * block (spi_sync() is blocking) so fire of the interrupt | |
1323 | * handling workqueue. | |
1324 | * Remember that we access enc28j60 registers through SPI bus | |
1325 | * via spi_sync() call. | |
1326 | */ | |
1327 | schedule_work(&priv->irq_work); | |
1328 | ||
1329 | return IRQ_HANDLED; | |
1330 | } | |
1331 | ||
1332 | static void enc28j60_tx_timeout(struct net_device *ndev) | |
1333 | { | |
1334 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1335 | ||
1336 | if (netif_msg_timer(priv)) | |
1337 | dev_err(&ndev->dev, DRV_NAME " tx timeout\n"); | |
1338 | ||
1339 | ndev->stats.tx_errors++; | |
1340 | /* can't restart safely under softirq */ | |
1341 | schedule_work(&priv->restart_work); | |
1342 | } | |
1343 | ||
1344 | /* | |
1345 | * Open/initialize the board. This is called (in the current kernel) | |
1346 | * sometime after booting when the 'ifconfig' program is run. | |
1347 | * | |
1348 | * This routine should set everything up anew at each open, even | |
1349 | * registers that "should" only need to be set once at boot, so that | |
1350 | * there is non-reboot way to recover if something goes wrong. | |
1351 | */ | |
1352 | static int enc28j60_net_open(struct net_device *dev) | |
1353 | { | |
1354 | struct enc28j60_net *priv = netdev_priv(dev); | |
1355 | ||
1356 | if (netif_msg_drv(priv)) | |
b39d66a8 | 1357 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1358 | |
1359 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
e174961c JB |
1360 | if (netif_msg_ifup(priv)) |
1361 | dev_err(&dev->dev, "invalid MAC address %pM\n", | |
1362 | dev->dev_addr); | |
3ec9c11d CL |
1363 | return -EADDRNOTAVAIL; |
1364 | } | |
7dac6f8d DB |
1365 | /* Reset the hardware here (and take it out of low power mode) */ |
1366 | enc28j60_lowpower(priv, false); | |
3ec9c11d CL |
1367 | enc28j60_hw_disable(priv); |
1368 | if (!enc28j60_hw_init(priv)) { | |
1369 | if (netif_msg_ifup(priv)) | |
1370 | dev_err(&dev->dev, "hw_reset() failed\n"); | |
1371 | return -EINVAL; | |
1372 | } | |
1373 | /* Update the MAC address (in case user has changed it) */ | |
1374 | enc28j60_set_hw_macaddr(dev); | |
1375 | /* Enable interrupts */ | |
1376 | enc28j60_hw_enable(priv); | |
1377 | /* check link status */ | |
1378 | enc28j60_check_link_status(dev); | |
1379 | /* We are now ready to accept transmit requests from | |
1380 | * the queueing layer of the networking. | |
1381 | */ | |
1382 | netif_start_queue(dev); | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | /* The inverse routine to net_open(). */ | |
1388 | static int enc28j60_net_close(struct net_device *dev) | |
1389 | { | |
1390 | struct enc28j60_net *priv = netdev_priv(dev); | |
1391 | ||
1392 | if (netif_msg_drv(priv)) | |
b39d66a8 | 1393 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1394 | |
1395 | enc28j60_hw_disable(priv); | |
7dac6f8d | 1396 | enc28j60_lowpower(priv, true); |
3ec9c11d CL |
1397 | netif_stop_queue(dev); |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | /* | |
1403 | * Set or clear the multicast filter for this adapter | |
1404 | * num_addrs == -1 Promiscuous mode, receive all packets | |
1405 | * num_addrs == 0 Normal mode, filter out multicast packets | |
1406 | * num_addrs > 0 Multicast mode, receive normal and MC packets | |
1407 | */ | |
1408 | static void enc28j60_set_multicast_list(struct net_device *dev) | |
1409 | { | |
1410 | struct enc28j60_net *priv = netdev_priv(dev); | |
1411 | int oldfilter = priv->rxfilter; | |
1412 | ||
1413 | if (dev->flags & IFF_PROMISC) { | |
1414 | if (netif_msg_link(priv)) | |
1415 | dev_info(&dev->dev, "promiscuous mode\n"); | |
1416 | priv->rxfilter = RXFILTER_PROMISC; | |
4cd24eaf | 1417 | } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) { |
3ec9c11d CL |
1418 | if (netif_msg_link(priv)) |
1419 | dev_info(&dev->dev, "%smulticast mode\n", | |
1420 | (dev->flags & IFF_ALLMULTI) ? "all-" : ""); | |
1421 | priv->rxfilter = RXFILTER_MULTI; | |
1422 | } else { | |
1423 | if (netif_msg_link(priv)) | |
1424 | dev_info(&dev->dev, "normal mode\n"); | |
1425 | priv->rxfilter = RXFILTER_NORMAL; | |
1426 | } | |
1427 | ||
1428 | if (oldfilter != priv->rxfilter) | |
1429 | schedule_work(&priv->setrx_work); | |
1430 | } | |
1431 | ||
1432 | static void enc28j60_setrx_work_handler(struct work_struct *work) | |
1433 | { | |
1434 | struct enc28j60_net *priv = | |
1435 | container_of(work, struct enc28j60_net, setrx_work); | |
1436 | ||
1437 | if (priv->rxfilter == RXFILTER_PROMISC) { | |
1438 | if (netif_msg_drv(priv)) | |
1439 | printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n"); | |
1440 | locked_regb_write(priv, ERXFCON, 0x00); | |
1441 | } else if (priv->rxfilter == RXFILTER_MULTI) { | |
1442 | if (netif_msg_drv(priv)) | |
1443 | printk(KERN_DEBUG DRV_NAME ": multicast mode\n"); | |
1444 | locked_regb_write(priv, ERXFCON, | |
1445 | ERXFCON_UCEN | ERXFCON_CRCEN | | |
1446 | ERXFCON_BCEN | ERXFCON_MCEN); | |
1447 | } else { | |
1448 | if (netif_msg_drv(priv)) | |
1449 | printk(KERN_DEBUG DRV_NAME ": normal mode\n"); | |
1450 | locked_regb_write(priv, ERXFCON, | |
1451 | ERXFCON_UCEN | ERXFCON_CRCEN | | |
1452 | ERXFCON_BCEN); | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | static void enc28j60_restart_work_handler(struct work_struct *work) | |
1457 | { | |
1458 | struct enc28j60_net *priv = | |
1459 | container_of(work, struct enc28j60_net, restart_work); | |
1460 | struct net_device *ndev = priv->netdev; | |
1461 | int ret; | |
1462 | ||
1463 | rtnl_lock(); | |
1464 | if (netif_running(ndev)) { | |
1465 | enc28j60_net_close(ndev); | |
1466 | ret = enc28j60_net_open(ndev); | |
1467 | if (unlikely(ret)) { | |
1468 | dev_info(&ndev->dev, " could not restart %d\n", ret); | |
1469 | dev_close(ndev); | |
1470 | } | |
1471 | } | |
1472 | rtnl_unlock(); | |
1473 | } | |
1474 | ||
1475 | /* ......................... ETHTOOL SUPPORT ........................... */ | |
1476 | ||
1477 | static void | |
1478 | enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1479 | { | |
1480 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); | |
1481 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1482 | strlcpy(info->bus_info, | |
fb28ad35 | 1483 | dev_name(dev->dev.parent), sizeof(info->bus_info)); |
3ec9c11d CL |
1484 | } |
1485 | ||
1486 | static int | |
1487 | enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1488 | { | |
1489 | struct enc28j60_net *priv = netdev_priv(dev); | |
1490 | ||
1491 | cmd->transceiver = XCVR_INTERNAL; | |
1492 | cmd->supported = SUPPORTED_10baseT_Half | |
1493 | | SUPPORTED_10baseT_Full | |
1494 | | SUPPORTED_TP; | |
70739497 | 1495 | ethtool_cmd_speed_set(cmd, SPEED_10); |
3ec9c11d CL |
1496 | cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; |
1497 | cmd->port = PORT_TP; | |
1498 | cmd->autoneg = AUTONEG_DISABLE; | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | static int | |
1504 | enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1505 | { | |
25db0338 DD |
1506 | return enc28j60_setlink(dev, cmd->autoneg, |
1507 | ethtool_cmd_speed(cmd), cmd->duplex); | |
3ec9c11d CL |
1508 | } |
1509 | ||
1510 | static u32 enc28j60_get_msglevel(struct net_device *dev) | |
1511 | { | |
1512 | struct enc28j60_net *priv = netdev_priv(dev); | |
1513 | return priv->msg_enable; | |
1514 | } | |
1515 | ||
1516 | static void enc28j60_set_msglevel(struct net_device *dev, u32 val) | |
1517 | { | |
1518 | struct enc28j60_net *priv = netdev_priv(dev); | |
1519 | priv->msg_enable = val; | |
1520 | } | |
1521 | ||
1522 | static const struct ethtool_ops enc28j60_ethtool_ops = { | |
1523 | .get_settings = enc28j60_get_settings, | |
1524 | .set_settings = enc28j60_set_settings, | |
1525 | .get_drvinfo = enc28j60_get_drvinfo, | |
1526 | .get_msglevel = enc28j60_get_msglevel, | |
1527 | .set_msglevel = enc28j60_set_msglevel, | |
1528 | }; | |
1529 | ||
1530 | static int enc28j60_chipset_init(struct net_device *dev) | |
1531 | { | |
1532 | struct enc28j60_net *priv = netdev_priv(dev); | |
1533 | ||
1534 | return enc28j60_hw_init(priv); | |
1535 | } | |
1536 | ||
1f5ec79b SH |
1537 | static const struct net_device_ops enc28j60_netdev_ops = { |
1538 | .ndo_open = enc28j60_net_open, | |
1539 | .ndo_stop = enc28j60_net_close, | |
1540 | .ndo_start_xmit = enc28j60_send_packet, | |
afc4b13d | 1541 | .ndo_set_rx_mode = enc28j60_set_multicast_list, |
1f5ec79b SH |
1542 | .ndo_set_mac_address = enc28j60_set_mac_address, |
1543 | .ndo_tx_timeout = enc28j60_tx_timeout, | |
1544 | .ndo_change_mtu = eth_change_mtu, | |
1545 | .ndo_validate_addr = eth_validate_addr, | |
1546 | }; | |
1547 | ||
19d1b44a | 1548 | static int enc28j60_probe(struct spi_device *spi) |
3ec9c11d CL |
1549 | { |
1550 | struct net_device *dev; | |
1551 | struct enc28j60_net *priv; | |
2dd355a0 | 1552 | const void *macaddr; |
3ec9c11d CL |
1553 | int ret = 0; |
1554 | ||
1555 | if (netif_msg_drv(&debug)) | |
1556 | dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n", | |
1557 | DRV_VERSION); | |
1558 | ||
1559 | dev = alloc_etherdev(sizeof(struct enc28j60_net)); | |
1560 | if (!dev) { | |
3ec9c11d CL |
1561 | ret = -ENOMEM; |
1562 | goto error_alloc; | |
1563 | } | |
1564 | priv = netdev_priv(dev); | |
1565 | ||
1566 | priv->netdev = dev; /* priv to netdev reference */ | |
1567 | priv->spi = spi; /* priv to spi reference */ | |
1568 | priv->msg_enable = netif_msg_init(debug.msg_enable, | |
1569 | ENC28J60_MSG_DEFAULT); | |
1570 | mutex_init(&priv->lock); | |
1571 | INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler); | |
1572 | INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler); | |
1573 | INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler); | |
1574 | INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler); | |
57437561 | 1575 | spi_set_drvdata(spi, priv); /* spi to priv reference */ |
3ec9c11d CL |
1576 | SET_NETDEV_DEV(dev, &spi->dev); |
1577 | ||
1578 | if (!enc28j60_chipset_init(dev)) { | |
1579 | if (netif_msg_probe(priv)) | |
1580 | dev_info(&spi->dev, DRV_NAME " chip not found\n"); | |
1581 | ret = -EIO; | |
1582 | goto error_irq; | |
1583 | } | |
2dd355a0 MH |
1584 | |
1585 | macaddr = of_get_mac_address(spi->dev.of_node); | |
1586 | if (macaddr) | |
1587 | ether_addr_copy(dev->dev_addr, macaddr); | |
1588 | else | |
1589 | eth_hw_addr_random(dev); | |
3ec9c11d CL |
1590 | enc28j60_set_hw_macaddr(dev); |
1591 | ||
c7b7b042 DB |
1592 | /* Board setup must set the relevant edge trigger type; |
1593 | * level triggers won't currently work. | |
1594 | */ | |
1595 | ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv); | |
3ec9c11d CL |
1596 | if (ret < 0) { |
1597 | if (netif_msg_probe(priv)) | |
1598 | dev_err(&spi->dev, DRV_NAME ": request irq %d failed " | |
1599 | "(ret = %d)\n", spi->irq, ret); | |
1600 | goto error_irq; | |
1601 | } | |
1602 | ||
1603 | dev->if_port = IF_PORT_10BASET; | |
1604 | dev->irq = spi->irq; | |
1f5ec79b | 1605 | dev->netdev_ops = &enc28j60_netdev_ops; |
3ec9c11d | 1606 | dev->watchdog_timeo = TX_TIMEOUT; |
7ad24ea4 | 1607 | dev->ethtool_ops = &enc28j60_ethtool_ops; |
3ec9c11d | 1608 | |
7dac6f8d DB |
1609 | enc28j60_lowpower(priv, true); |
1610 | ||
3ec9c11d CL |
1611 | ret = register_netdev(dev); |
1612 | if (ret) { | |
1613 | if (netif_msg_probe(priv)) | |
1614 | dev_err(&spi->dev, "register netdev " DRV_NAME | |
1615 | " failed (ret = %d)\n", ret); | |
1616 | goto error_register; | |
1617 | } | |
1618 | dev_info(&dev->dev, DRV_NAME " driver registered\n"); | |
1619 | ||
1620 | return 0; | |
1621 | ||
1622 | error_register: | |
1623 | free_irq(spi->irq, priv); | |
1624 | error_irq: | |
1625 | free_netdev(dev); | |
1626 | error_alloc: | |
1627 | return ret; | |
1628 | } | |
1629 | ||
19d1b44a | 1630 | static int enc28j60_remove(struct spi_device *spi) |
3ec9c11d | 1631 | { |
57437561 | 1632 | struct enc28j60_net *priv = spi_get_drvdata(spi); |
3ec9c11d CL |
1633 | |
1634 | if (netif_msg_drv(priv)) | |
1635 | printk(KERN_DEBUG DRV_NAME ": remove\n"); | |
1636 | ||
1637 | unregister_netdev(priv->netdev); | |
1638 | free_irq(spi->irq, priv); | |
1639 | free_netdev(priv->netdev); | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
2dd355a0 MH |
1644 | static const struct of_device_id enc28j60_dt_ids[] = { |
1645 | { .compatible = "microchip,enc28j60" }, | |
1646 | { /* sentinel */ } | |
1647 | }; | |
1648 | MODULE_DEVICE_TABLE(of, enc28j60_dt_ids); | |
1649 | ||
3ec9c11d CL |
1650 | static struct spi_driver enc28j60_driver = { |
1651 | .driver = { | |
2dd355a0 MH |
1652 | .name = DRV_NAME, |
1653 | .of_match_table = enc28j60_dt_ids, | |
6fd65882 | 1654 | }, |
3ec9c11d | 1655 | .probe = enc28j60_probe, |
19d1b44a | 1656 | .remove = enc28j60_remove, |
3ec9c11d CL |
1657 | }; |
1658 | ||
1659 | static int __init enc28j60_init(void) | |
1660 | { | |
7dac6f8d DB |
1661 | msec20_to_jiffies = msecs_to_jiffies(20); |
1662 | ||
3ec9c11d CL |
1663 | return spi_register_driver(&enc28j60_driver); |
1664 | } | |
1665 | ||
1666 | module_init(enc28j60_init); | |
1667 | ||
1668 | static void __exit enc28j60_exit(void) | |
1669 | { | |
1670 | spi_unregister_driver(&enc28j60_driver); | |
1671 | } | |
1672 | ||
1673 | module_exit(enc28j60_exit); | |
1674 | ||
1675 | MODULE_DESCRIPTION(DRV_NAME " ethernet driver"); | |
1676 | MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>"); | |
1677 | MODULE_LICENSE("GPL"); | |
1678 | module_param_named(debug, debug.msg_enable, int, 0); | |
1679 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)"); | |
e0626e38 | 1680 | MODULE_ALIAS("spi:" DRV_NAME); |