Commit | Line | Data |
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77555ee7 MO |
1 | /* |
2 | * Copyright (C) 1999 - 2010 Intel Corporation. | |
1a0bdadb | 3 | * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD. |
77555ee7 MO |
4 | * |
5 | * This code was derived from the Intel e1000e Linux driver. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include "pch_gbe.h" | |
22 | #include "pch_gbe_api.h" | |
9d9779e7 | 23 | #include <linux/module.h> |
1a0bdadb TS |
24 | #ifdef CONFIG_PCH_PTP |
25 | #include <linux/net_tstamp.h> | |
26 | #include <linux/ptp_classify.h> | |
27 | #endif | |
77555ee7 MO |
28 | |
29 | #define DRV_VERSION "1.00" | |
30 | const char pch_driver_version[] = DRV_VERSION; | |
31 | ||
32 | #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */ | |
33 | #define PCH_GBE_MAR_ENTRIES 16 | |
34 | #define PCH_GBE_SHORT_PKT 64 | |
35 | #define DSC_INIT16 0xC000 | |
36 | #define PCH_GBE_DMA_ALIGN 0 | |
ac096642 | 37 | #define PCH_GBE_DMA_PADDING 2 |
77555ee7 MO |
38 | #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */ |
39 | #define PCH_GBE_COPYBREAK_DEFAULT 256 | |
40 | #define PCH_GBE_PCI_BAR 1 | |
124d770a | 41 | #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */ |
77555ee7 | 42 | |
b0e6baf5 T |
43 | /* Macros for ML7223 */ |
44 | #define PCI_VENDOR_ID_ROHM 0x10db | |
45 | #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 | |
46 | ||
7756332f TO |
47 | /* Macros for ML7831 */ |
48 | #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802 | |
49 | ||
77555ee7 MO |
50 | #define PCH_GBE_TX_WEIGHT 64 |
51 | #define PCH_GBE_RX_WEIGHT 64 | |
52 | #define PCH_GBE_RX_BUFFER_WRITE 16 | |
53 | ||
54 | /* Initialize the wake-on-LAN settings */ | |
55 | #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP) | |
56 | ||
57 | #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \ | |
58 | PCH_GBE_CHIP_TYPE_INTERNAL | \ | |
ce3dad0f | 59 | PCH_GBE_RGMII_MODE_RGMII \ |
77555ee7 MO |
60 | ) |
61 | ||
62 | /* Ethertype field values */ | |
124d770a | 63 | #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880 |
77555ee7 MO |
64 | #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 |
65 | #define PCH_GBE_FRAME_SIZE_2048 2048 | |
66 | #define PCH_GBE_FRAME_SIZE_4096 4096 | |
67 | #define PCH_GBE_FRAME_SIZE_8192 8192 | |
68 | ||
69 | #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) | |
70 | #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc) | |
71 | #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc) | |
72 | #define PCH_GBE_DESC_UNUSED(R) \ | |
73 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ | |
74 | (R)->next_to_clean - (R)->next_to_use - 1) | |
75 | ||
76 | /* Pause packet value */ | |
77 | #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001 | |
78 | #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100 | |
79 | #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888 | |
80 | #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF | |
81 | ||
82 | #define PCH_GBE_ETH_ALEN 6 | |
83 | ||
84 | /* This defines the bits that are set in the Interrupt Mask | |
85 | * Set/Read Register. Each bit is documented below: | |
86 | * o RXT0 = Receiver Timer Interrupt (ring 0) | |
87 | * o TXDW = Transmit Descriptor Written Back | |
88 | * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) | |
89 | * o RXSEQ = Receive Sequence Error | |
90 | * o LSC = Link Status Change | |
91 | */ | |
92 | #define PCH_GBE_INT_ENABLE_MASK ( \ | |
93 | PCH_GBE_INT_RX_DMA_CMPLT | \ | |
94 | PCH_GBE_INT_RX_DSC_EMP | \ | |
124d770a | 95 | PCH_GBE_INT_RX_FIFO_ERR | \ |
77555ee7 MO |
96 | PCH_GBE_INT_WOL_DET | \ |
97 | PCH_GBE_INT_TX_CMPLT \ | |
98 | ) | |
99 | ||
124d770a | 100 | #define PCH_GBE_INT_DISABLE_ALL 0 |
77555ee7 | 101 | |
1a0bdadb TS |
102 | #ifdef CONFIG_PCH_PTP |
103 | /* Macros for ieee1588 */ | |
1a0bdadb TS |
104 | /* 0x40 Time Synchronization Channel Control Register Bits */ |
105 | #define MASTER_MODE (1<<0) | |
106 | #define SLAVE_MODE (0<<0) | |
107 | #define V2_MODE (1<<31) | |
108 | #define CAP_MODE0 (0<<16) | |
109 | #define CAP_MODE2 (1<<17) | |
110 | ||
111 | /* 0x44 Time Synchronization Channel Event Register Bits */ | |
112 | #define TX_SNAPSHOT_LOCKED (1<<0) | |
113 | #define RX_SNAPSHOT_LOCKED (1<<1) | |
114 | #endif | |
115 | ||
77555ee7 MO |
116 | static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; |
117 | ||
191cc687 | 118 | static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg); |
119 | static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg, | |
120 | int data); | |
98200ec2 | 121 | |
1a0bdadb TS |
122 | #ifdef CONFIG_PCH_PTP |
123 | static struct sock_filter ptp_filter[] = { | |
124 | PTP_FILTER | |
125 | }; | |
126 | ||
127 | static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) | |
128 | { | |
129 | u8 *data = skb->data; | |
130 | unsigned int offset; | |
131 | u16 *hi, *id; | |
132 | u32 lo; | |
133 | ||
134 | if ((sk_run_filter(skb, ptp_filter) != PTP_CLASS_V2_IPV4) && | |
135 | (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)) { | |
136 | return 0; | |
137 | } | |
138 | ||
139 | offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; | |
140 | ||
141 | if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) | |
142 | return 0; | |
143 | ||
144 | hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); | |
145 | id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); | |
146 | ||
147 | memcpy(&lo, &hi[1], sizeof(lo)); | |
148 | ||
149 | return (uid_hi == *hi && | |
150 | uid_lo == lo && | |
151 | seqid == *id); | |
152 | } | |
153 | ||
154 | static void pch_rx_timestamp( | |
155 | struct pch_gbe_adapter *adapter, struct sk_buff *skb) | |
156 | { | |
157 | struct skb_shared_hwtstamps *shhwtstamps; | |
158 | struct pci_dev *pdev; | |
159 | u64 ns; | |
160 | u32 hi, lo, val; | |
161 | u16 uid, seq; | |
162 | ||
163 | if (!adapter->hwts_rx_en) | |
164 | return; | |
165 | ||
166 | /* Get ieee1588's dev information */ | |
167 | pdev = adapter->ptp_pdev; | |
168 | ||
169 | val = pch_ch_event_read(pdev); | |
170 | ||
171 | if (!(val & RX_SNAPSHOT_LOCKED)) | |
172 | return; | |
173 | ||
174 | lo = pch_src_uuid_lo_read(pdev); | |
175 | hi = pch_src_uuid_hi_read(pdev); | |
176 | ||
177 | uid = hi & 0xffff; | |
178 | seq = (hi >> 16) & 0xffff; | |
179 | ||
180 | if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) | |
181 | goto out; | |
182 | ||
183 | ns = pch_rx_snap_read(pdev); | |
1a0bdadb TS |
184 | |
185 | shhwtstamps = skb_hwtstamps(skb); | |
186 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
187 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
188 | out: | |
189 | pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED); | |
190 | } | |
191 | ||
192 | static void pch_tx_timestamp( | |
193 | struct pch_gbe_adapter *adapter, struct sk_buff *skb) | |
194 | { | |
195 | struct skb_shared_hwtstamps shhwtstamps; | |
196 | struct pci_dev *pdev; | |
197 | struct skb_shared_info *shtx; | |
198 | u64 ns; | |
199 | u32 cnt, val; | |
200 | ||
201 | shtx = skb_shinfo(skb); | |
5481c8cd | 202 | if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en))) |
1a0bdadb TS |
203 | return; |
204 | ||
5481c8cd TS |
205 | shtx->tx_flags |= SKBTX_IN_PROGRESS; |
206 | ||
1a0bdadb TS |
207 | /* Get ieee1588's dev information */ |
208 | pdev = adapter->ptp_pdev; | |
209 | ||
210 | /* | |
211 | * This really stinks, but we have to poll for the Tx time stamp. | |
212 | * Usually, the time stamp is ready after 4 to 6 microseconds. | |
213 | */ | |
214 | for (cnt = 0; cnt < 100; cnt++) { | |
215 | val = pch_ch_event_read(pdev); | |
216 | if (val & TX_SNAPSHOT_LOCKED) | |
217 | break; | |
218 | udelay(1); | |
219 | } | |
220 | if (!(val & TX_SNAPSHOT_LOCKED)) { | |
221 | shtx->tx_flags &= ~SKBTX_IN_PROGRESS; | |
222 | return; | |
223 | } | |
224 | ||
225 | ns = pch_tx_snap_read(pdev); | |
1a0bdadb TS |
226 | |
227 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
228 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
229 | skb_tstamp_tx(skb, &shhwtstamps); | |
230 | ||
231 | pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED); | |
232 | } | |
233 | ||
234 | static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
235 | { | |
236 | struct hwtstamp_config cfg; | |
237 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
238 | struct pci_dev *pdev; | |
239 | ||
240 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | |
241 | return -EFAULT; | |
242 | ||
243 | if (cfg.flags) /* reserved for future extensions */ | |
244 | return -EINVAL; | |
245 | ||
246 | /* Get ieee1588's dev information */ | |
247 | pdev = adapter->ptp_pdev; | |
248 | ||
249 | switch (cfg.tx_type) { | |
250 | case HWTSTAMP_TX_OFF: | |
251 | adapter->hwts_tx_en = 0; | |
252 | break; | |
253 | case HWTSTAMP_TX_ON: | |
254 | adapter->hwts_tx_en = 1; | |
255 | break; | |
256 | default: | |
257 | return -ERANGE; | |
258 | } | |
259 | ||
260 | switch (cfg.rx_filter) { | |
261 | case HWTSTAMP_FILTER_NONE: | |
262 | adapter->hwts_rx_en = 0; | |
263 | break; | |
264 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
265 | adapter->hwts_rx_en = 0; | |
266 | pch_ch_control_write(pdev, (SLAVE_MODE | CAP_MODE0)); | |
267 | break; | |
268 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
269 | adapter->hwts_rx_en = 1; | |
270 | pch_ch_control_write(pdev, (MASTER_MODE | CAP_MODE0)); | |
271 | break; | |
272 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
273 | adapter->hwts_rx_en = 1; | |
274 | pch_ch_control_write(pdev, (V2_MODE | CAP_MODE2)); | |
275 | break; | |
276 | default: | |
277 | return -ERANGE; | |
278 | } | |
279 | ||
280 | /* Clear out any old time stamps. */ | |
281 | pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED); | |
282 | ||
283 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
284 | } | |
285 | #endif | |
286 | ||
98200ec2 TO |
287 | inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw) |
288 | { | |
289 | iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD); | |
290 | } | |
291 | ||
77555ee7 MO |
292 | /** |
293 | * pch_gbe_mac_read_mac_addr - Read MAC address | |
294 | * @hw: Pointer to the HW structure | |
295 | * Returns | |
296 | * 0: Successful. | |
297 | */ | |
298 | s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw) | |
299 | { | |
300 | u32 adr1a, adr1b; | |
301 | ||
302 | adr1a = ioread32(&hw->reg->mac_adr[0].high); | |
303 | adr1b = ioread32(&hw->reg->mac_adr[0].low); | |
304 | ||
305 | hw->mac.addr[0] = (u8)(adr1a & 0xFF); | |
306 | hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF); | |
307 | hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF); | |
308 | hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF); | |
309 | hw->mac.addr[4] = (u8)(adr1b & 0xFF); | |
310 | hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF); | |
311 | ||
312 | pr_debug("hw->mac.addr : %pM\n", hw->mac.addr); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | /** | |
317 | * pch_gbe_wait_clr_bit - Wait to clear a bit | |
318 | * @reg: Pointer of register | |
319 | * @busy: Busy bit | |
320 | */ | |
191cc687 | 321 | static void pch_gbe_wait_clr_bit(void *reg, u32 bit) |
77555ee7 MO |
322 | { |
323 | u32 tmp; | |
324 | /* wait busy */ | |
325 | tmp = 1000; | |
326 | while ((ioread32(reg) & bit) && --tmp) | |
327 | cpu_relax(); | |
328 | if (!tmp) | |
329 | pr_err("Error: busy bit is not cleared\n"); | |
330 | } | |
124d770a TO |
331 | |
332 | /** | |
333 | * pch_gbe_wait_clr_bit_irq - Wait to clear a bit for interrupt context | |
334 | * @reg: Pointer of register | |
335 | * @busy: Busy bit | |
336 | */ | |
337 | static int pch_gbe_wait_clr_bit_irq(void *reg, u32 bit) | |
338 | { | |
339 | u32 tmp; | |
340 | int ret = -1; | |
341 | /* wait busy */ | |
342 | tmp = 20; | |
343 | while ((ioread32(reg) & bit) && --tmp) | |
344 | udelay(5); | |
345 | if (!tmp) | |
346 | pr_err("Error: busy bit is not cleared\n"); | |
347 | else | |
348 | ret = 0; | |
349 | return ret; | |
350 | } | |
351 | ||
77555ee7 MO |
352 | /** |
353 | * pch_gbe_mac_mar_set - Set MAC address register | |
354 | * @hw: Pointer to the HW structure | |
355 | * @addr: Pointer to the MAC address | |
356 | * @index: MAC address array register | |
357 | */ | |
191cc687 | 358 | static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index) |
77555ee7 MO |
359 | { |
360 | u32 mar_low, mar_high, adrmask; | |
361 | ||
362 | pr_debug("index : 0x%x\n", index); | |
363 | ||
364 | /* | |
365 | * HW expects these in little endian so we reverse the byte order | |
366 | * from network order (big endian) to little endian | |
367 | */ | |
368 | mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
369 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
370 | mar_low = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
371 | /* Stop the MAC Address of index. */ | |
372 | adrmask = ioread32(&hw->reg->ADDR_MASK); | |
373 | iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); | |
374 | /* wait busy */ | |
375 | pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); | |
376 | /* Set the MAC address to the MAC address 1A/1B register */ | |
377 | iowrite32(mar_high, &hw->reg->mac_adr[index].high); | |
378 | iowrite32(mar_low, &hw->reg->mac_adr[index].low); | |
379 | /* Start the MAC address of index */ | |
380 | iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); | |
381 | /* wait busy */ | |
382 | pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); | |
383 | } | |
384 | ||
eefc48b0 TS |
385 | /** |
386 | * pch_gbe_mac_save_mac_addr_regs - Save MAC addresse registers | |
387 | * @hw: Pointer to the HW structure | |
388 | * @addr: Pointer to the MAC address | |
389 | * @index: MAC address array register | |
390 | */ | |
391 | static void | |
392 | pch_gbe_mac_save_mac_addr_regs(struct pch_gbe_hw *hw, | |
393 | struct pch_gbe_regs_mac_adr *mac_adr, u32 index) | |
394 | { | |
395 | mac_adr->high = ioread32(&hw->reg->mac_adr[index].high); | |
396 | mac_adr->low = ioread32(&hw->reg->mac_adr[index].low); | |
397 | } | |
398 | ||
399 | /** | |
400 | * pch_gbe_mac_store_mac_addr_regs - Store MAC addresse registers | |
401 | * @hw: Pointer to the HW structure | |
402 | * @addr: Pointer to the MAC address | |
403 | * @index: MAC address array register | |
404 | */ | |
405 | static void | |
406 | pch_gbe_mac_store_mac_addr_regs(struct pch_gbe_hw *hw, | |
407 | struct pch_gbe_regs_mac_adr *mac_adr, u32 index) | |
408 | { | |
409 | u32 adrmask; | |
410 | ||
411 | adrmask = ioread32(&hw->reg->ADDR_MASK); | |
412 | iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); | |
413 | /* wait busy */ | |
414 | pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); | |
415 | /* Set the MAC address to the MAC address xA/xB register */ | |
416 | iowrite32(mac_adr->high, &hw->reg->mac_adr[index].high); | |
417 | iowrite32(mac_adr->low, &hw->reg->mac_adr[index].low); | |
418 | iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); | |
419 | /* wait busy */ | |
420 | pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); | |
421 | } | |
422 | ||
423 | #define MAC_ADDR_LIST_NUM 16 | |
77555ee7 MO |
424 | /** |
425 | * pch_gbe_mac_reset_hw - Reset hardware | |
426 | * @hw: Pointer to the HW structure | |
427 | */ | |
191cc687 | 428 | static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) |
77555ee7 | 429 | { |
eefc48b0 TS |
430 | struct pch_gbe_regs_mac_adr mac_addr_list[MAC_ADDR_LIST_NUM]; |
431 | int i; | |
432 | ||
77555ee7 MO |
433 | /* Read the MAC address. and store to the private data */ |
434 | pch_gbe_mac_read_mac_addr(hw); | |
eefc48b0 TS |
435 | /* Read other MAC addresses */ |
436 | for (i = 1; i < MAC_ADDR_LIST_NUM; i++) | |
437 | pch_gbe_mac_save_mac_addr_regs(hw, &mac_addr_list[i], i); | |
77555ee7 MO |
438 | iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET); |
439 | #ifdef PCH_GBE_MAC_IFOP_RGMII | |
440 | iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); | |
441 | #endif | |
442 | pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); | |
eefc48b0 | 443 | /* Setup the receive addresses */ |
77555ee7 | 444 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); |
eefc48b0 TS |
445 | for (i = 1; i < MAC_ADDR_LIST_NUM; i++) |
446 | pch_gbe_mac_store_mac_addr_regs(hw, &mac_addr_list[i], i); | |
77555ee7 MO |
447 | return; |
448 | } | |
449 | ||
124d770a TO |
450 | static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw) |
451 | { | |
eefc48b0 TS |
452 | struct pch_gbe_regs_mac_adr mac_addr_list[MAC_ADDR_LIST_NUM]; |
453 | int i; | |
454 | ||
455 | /* Read the MAC addresses. and store to the private data */ | |
124d770a | 456 | pch_gbe_mac_read_mac_addr(hw); |
eefc48b0 TS |
457 | for (i = 1; i < MAC_ADDR_LIST_NUM; i++) |
458 | pch_gbe_mac_save_mac_addr_regs(hw, &mac_addr_list[i], i); | |
124d770a TO |
459 | iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET); |
460 | pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST); | |
eefc48b0 | 461 | /* Setup the MAC addresses */ |
124d770a | 462 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); |
eefc48b0 TS |
463 | for (i = 1; i < MAC_ADDR_LIST_NUM; i++) |
464 | pch_gbe_mac_store_mac_addr_regs(hw, &mac_addr_list[i], i); | |
124d770a TO |
465 | return; |
466 | } | |
467 | ||
77555ee7 MO |
468 | /** |
469 | * pch_gbe_mac_init_rx_addrs - Initialize receive address's | |
470 | * @hw: Pointer to the HW structure | |
471 | * @mar_count: Receive address registers | |
472 | */ | |
191cc687 | 473 | static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count) |
77555ee7 MO |
474 | { |
475 | u32 i; | |
476 | ||
477 | /* Setup the receive address */ | |
478 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); | |
479 | ||
480 | /* Zero out the other receive addresses */ | |
481 | for (i = 1; i < mar_count; i++) { | |
482 | iowrite32(0, &hw->reg->mac_adr[i].high); | |
483 | iowrite32(0, &hw->reg->mac_adr[i].low); | |
484 | } | |
485 | iowrite32(0xFFFE, &hw->reg->ADDR_MASK); | |
486 | /* wait busy */ | |
487 | pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); | |
488 | } | |
489 | ||
490 | ||
491 | /** | |
492 | * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses | |
493 | * @hw: Pointer to the HW structure | |
494 | * @mc_addr_list: Array of multicast addresses to program | |
495 | * @mc_addr_count: Number of multicast addresses to program | |
496 | * @mar_used_count: The first MAC Address register free to program | |
497 | * @mar_total_num: Total number of supported MAC Address Registers | |
498 | */ | |
191cc687 | 499 | static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw, |
500 | u8 *mc_addr_list, u32 mc_addr_count, | |
501 | u32 mar_used_count, u32 mar_total_num) | |
77555ee7 MO |
502 | { |
503 | u32 i, adrmask; | |
504 | ||
505 | /* Load the first set of multicast addresses into the exact | |
506 | * filters (RAR). If there are not enough to fill the RAR | |
507 | * array, clear the filters. | |
508 | */ | |
509 | for (i = mar_used_count; i < mar_total_num; i++) { | |
510 | if (mc_addr_count) { | |
511 | pch_gbe_mac_mar_set(hw, mc_addr_list, i); | |
512 | mc_addr_count--; | |
513 | mc_addr_list += PCH_GBE_ETH_ALEN; | |
514 | } else { | |
515 | /* Clear MAC address mask */ | |
516 | adrmask = ioread32(&hw->reg->ADDR_MASK); | |
517 | iowrite32((adrmask | (0x0001 << i)), | |
518 | &hw->reg->ADDR_MASK); | |
519 | /* wait busy */ | |
520 | pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); | |
521 | /* Clear MAC address */ | |
522 | iowrite32(0, &hw->reg->mac_adr[i].high); | |
523 | iowrite32(0, &hw->reg->mac_adr[i].low); | |
524 | } | |
525 | } | |
526 | } | |
527 | ||
528 | /** | |
529 | * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings | |
530 | * @hw: Pointer to the HW structure | |
531 | * Returns | |
532 | * 0: Successful. | |
533 | * Negative value: Failed. | |
534 | */ | |
535 | s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw) | |
536 | { | |
537 | struct pch_gbe_mac_info *mac = &hw->mac; | |
538 | u32 rx_fctrl; | |
539 | ||
540 | pr_debug("mac->fc = %u\n", mac->fc); | |
541 | ||
542 | rx_fctrl = ioread32(&hw->reg->RX_FCTRL); | |
543 | ||
544 | switch (mac->fc) { | |
545 | case PCH_GBE_FC_NONE: | |
546 | rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; | |
547 | mac->tx_fc_enable = false; | |
548 | break; | |
549 | case PCH_GBE_FC_RX_PAUSE: | |
550 | rx_fctrl |= PCH_GBE_FL_CTRL_EN; | |
551 | mac->tx_fc_enable = false; | |
552 | break; | |
553 | case PCH_GBE_FC_TX_PAUSE: | |
554 | rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; | |
555 | mac->tx_fc_enable = true; | |
556 | break; | |
557 | case PCH_GBE_FC_FULL: | |
558 | rx_fctrl |= PCH_GBE_FL_CTRL_EN; | |
559 | mac->tx_fc_enable = true; | |
560 | break; | |
561 | default: | |
562 | pr_err("Flow control param set incorrectly\n"); | |
563 | return -EINVAL; | |
564 | } | |
565 | if (mac->link_duplex == DUPLEX_HALF) | |
566 | rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; | |
567 | iowrite32(rx_fctrl, &hw->reg->RX_FCTRL); | |
568 | pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n", | |
569 | ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable); | |
570 | return 0; | |
571 | } | |
572 | ||
573 | /** | |
574 | * pch_gbe_mac_set_wol_event - Set wake-on-lan event | |
575 | * @hw: Pointer to the HW structure | |
576 | * @wu_evt: Wake up event | |
577 | */ | |
191cc687 | 578 | static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt) |
77555ee7 MO |
579 | { |
580 | u32 addr_mask; | |
581 | ||
582 | pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n", | |
583 | wu_evt, ioread32(&hw->reg->ADDR_MASK)); | |
584 | ||
585 | if (wu_evt) { | |
586 | /* Set Wake-On-Lan address mask */ | |
587 | addr_mask = ioread32(&hw->reg->ADDR_MASK); | |
588 | iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK); | |
589 | /* wait busy */ | |
590 | pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY); | |
591 | iowrite32(0, &hw->reg->WOL_ST); | |
592 | iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL); | |
593 | iowrite32(0x02, &hw->reg->TCPIP_ACC); | |
594 | iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); | |
595 | } else { | |
596 | iowrite32(0, &hw->reg->WOL_CTRL); | |
597 | iowrite32(0, &hw->reg->WOL_ST); | |
598 | } | |
599 | return; | |
600 | } | |
601 | ||
602 | /** | |
603 | * pch_gbe_mac_ctrl_miim - Control MIIM interface | |
604 | * @hw: Pointer to the HW structure | |
605 | * @addr: Address of PHY | |
606 | * @dir: Operetion. (Write or Read) | |
607 | * @reg: Access register of PHY | |
608 | * @data: Write data. | |
609 | * | |
610 | * Returns: Read date. | |
611 | */ | |
612 | u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, | |
613 | u16 data) | |
614 | { | |
615 | u32 data_out = 0; | |
616 | unsigned int i; | |
617 | unsigned long flags; | |
618 | ||
619 | spin_lock_irqsave(&hw->miim_lock, flags); | |
620 | ||
621 | for (i = 100; i; --i) { | |
622 | if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY)) | |
623 | break; | |
624 | udelay(20); | |
625 | } | |
626 | if (i == 0) { | |
627 | pr_err("pch-gbe.miim won't go Ready\n"); | |
628 | spin_unlock_irqrestore(&hw->miim_lock, flags); | |
629 | return 0; /* No way to indicate timeout error */ | |
630 | } | |
631 | iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | | |
632 | (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | | |
633 | dir | data), &hw->reg->MIIM); | |
634 | for (i = 0; i < 100; i++) { | |
635 | udelay(20); | |
636 | data_out = ioread32(&hw->reg->MIIM); | |
637 | if ((data_out & PCH_GBE_MIIM_OPER_READY)) | |
638 | break; | |
639 | } | |
640 | spin_unlock_irqrestore(&hw->miim_lock, flags); | |
641 | ||
642 | pr_debug("PHY %s: reg=%d, data=0x%04X\n", | |
643 | dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg, | |
644 | dir == PCH_GBE_MIIM_OPER_READ ? data_out : data); | |
645 | return (u16) data_out; | |
646 | } | |
647 | ||
648 | /** | |
649 | * pch_gbe_mac_set_pause_packet - Set pause packet | |
650 | * @hw: Pointer to the HW structure | |
651 | */ | |
191cc687 | 652 | static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw) |
77555ee7 MO |
653 | { |
654 | unsigned long tmp2, tmp3; | |
655 | ||
656 | /* Set Pause packet */ | |
657 | tmp2 = hw->mac.addr[1]; | |
658 | tmp2 = (tmp2 << 8) | hw->mac.addr[0]; | |
659 | tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16); | |
660 | ||
661 | tmp3 = hw->mac.addr[5]; | |
662 | tmp3 = (tmp3 << 8) | hw->mac.addr[4]; | |
663 | tmp3 = (tmp3 << 8) | hw->mac.addr[3]; | |
664 | tmp3 = (tmp3 << 8) | hw->mac.addr[2]; | |
665 | ||
666 | iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1); | |
667 | iowrite32(tmp2, &hw->reg->PAUSE_PKT2); | |
668 | iowrite32(tmp3, &hw->reg->PAUSE_PKT3); | |
669 | iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4); | |
670 | iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5); | |
671 | ||
672 | /* Transmit Pause Packet */ | |
673 | iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ); | |
674 | ||
675 | pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
676 | ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2), | |
677 | ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4), | |
678 | ioread32(&hw->reg->PAUSE_PKT5)); | |
679 | ||
680 | return; | |
681 | } | |
682 | ||
683 | ||
684 | /** | |
685 | * pch_gbe_alloc_queues - Allocate memory for all rings | |
686 | * @adapter: Board private structure to initialize | |
687 | * Returns | |
688 | * 0: Successfully | |
689 | * Negative value: Failed | |
690 | */ | |
691 | static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter) | |
692 | { | |
693 | int size; | |
694 | ||
695 | size = (int)sizeof(struct pch_gbe_tx_ring); | |
696 | adapter->tx_ring = kzalloc(size, GFP_KERNEL); | |
697 | if (!adapter->tx_ring) | |
698 | return -ENOMEM; | |
699 | size = (int)sizeof(struct pch_gbe_rx_ring); | |
700 | adapter->rx_ring = kzalloc(size, GFP_KERNEL); | |
701 | if (!adapter->rx_ring) { | |
702 | kfree(adapter->tx_ring); | |
703 | return -ENOMEM; | |
704 | } | |
705 | return 0; | |
706 | } | |
707 | ||
708 | /** | |
709 | * pch_gbe_init_stats - Initialize status | |
710 | * @adapter: Board private structure to initialize | |
711 | */ | |
712 | static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter) | |
713 | { | |
714 | memset(&adapter->stats, 0, sizeof(adapter->stats)); | |
715 | return; | |
716 | } | |
717 | ||
718 | /** | |
719 | * pch_gbe_init_phy - Initialize PHY | |
720 | * @adapter: Board private structure to initialize | |
721 | * Returns | |
722 | * 0: Successfully | |
723 | * Negative value: Failed | |
724 | */ | |
725 | static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter) | |
726 | { | |
727 | struct net_device *netdev = adapter->netdev; | |
728 | u32 addr; | |
729 | u16 bmcr, stat; | |
730 | ||
731 | /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */ | |
732 | for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { | |
733 | adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr; | |
734 | bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR); | |
735 | stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); | |
736 | stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); | |
737 | if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0)))) | |
738 | break; | |
739 | } | |
740 | adapter->hw.phy.addr = adapter->mii.phy_id; | |
741 | pr_debug("phy_addr = %d\n", adapter->mii.phy_id); | |
742 | if (addr == 32) | |
743 | return -EAGAIN; | |
744 | /* Selected the phy and isolate the rest */ | |
745 | for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { | |
746 | if (addr != adapter->mii.phy_id) { | |
747 | pch_gbe_mdio_write(netdev, addr, MII_BMCR, | |
748 | BMCR_ISOLATE); | |
749 | } else { | |
750 | bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR); | |
751 | pch_gbe_mdio_write(netdev, addr, MII_BMCR, | |
752 | bmcr & ~BMCR_ISOLATE); | |
753 | } | |
754 | } | |
755 | ||
756 | /* MII setup */ | |
757 | adapter->mii.phy_id_mask = 0x1F; | |
758 | adapter->mii.reg_num_mask = 0x1F; | |
759 | adapter->mii.dev = adapter->netdev; | |
760 | adapter->mii.mdio_read = pch_gbe_mdio_read; | |
761 | adapter->mii.mdio_write = pch_gbe_mdio_write; | |
762 | adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii); | |
763 | return 0; | |
764 | } | |
765 | ||
766 | /** | |
767 | * pch_gbe_mdio_read - The read function for mii | |
768 | * @netdev: Network interface device structure | |
769 | * @addr: Phy ID | |
770 | * @reg: Access location | |
771 | * Returns | |
772 | * 0: Successfully | |
773 | * Negative value: Failed | |
774 | */ | |
191cc687 | 775 | static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg) |
77555ee7 MO |
776 | { |
777 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
778 | struct pch_gbe_hw *hw = &adapter->hw; | |
779 | ||
780 | return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg, | |
781 | (u16) 0); | |
782 | } | |
783 | ||
784 | /** | |
785 | * pch_gbe_mdio_write - The write function for mii | |
786 | * @netdev: Network interface device structure | |
787 | * @addr: Phy ID (not used) | |
788 | * @reg: Access location | |
789 | * @data: Write data | |
790 | */ | |
191cc687 | 791 | static void pch_gbe_mdio_write(struct net_device *netdev, |
792 | int addr, int reg, int data) | |
77555ee7 MO |
793 | { |
794 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
795 | struct pch_gbe_hw *hw = &adapter->hw; | |
796 | ||
797 | pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data); | |
798 | } | |
799 | ||
800 | /** | |
801 | * pch_gbe_reset_task - Reset processing at the time of transmission timeout | |
802 | * @work: Pointer of board private structure | |
803 | */ | |
804 | static void pch_gbe_reset_task(struct work_struct *work) | |
805 | { | |
806 | struct pch_gbe_adapter *adapter; | |
807 | adapter = container_of(work, struct pch_gbe_adapter, reset_task); | |
808 | ||
75d1a752 | 809 | rtnl_lock(); |
77555ee7 | 810 | pch_gbe_reinit_locked(adapter); |
75d1a752 | 811 | rtnl_unlock(); |
77555ee7 MO |
812 | } |
813 | ||
814 | /** | |
815 | * pch_gbe_reinit_locked- Re-initialization | |
816 | * @adapter: Board private structure | |
817 | */ | |
818 | void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter) | |
819 | { | |
75d1a752 TO |
820 | pch_gbe_down(adapter); |
821 | pch_gbe_up(adapter); | |
77555ee7 MO |
822 | } |
823 | ||
824 | /** | |
825 | * pch_gbe_reset - Reset GbE | |
826 | * @adapter: Board private structure | |
827 | */ | |
828 | void pch_gbe_reset(struct pch_gbe_adapter *adapter) | |
829 | { | |
830 | pch_gbe_mac_reset_hw(&adapter->hw); | |
831 | /* Setup the receive address. */ | |
832 | pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES); | |
833 | if (pch_gbe_hal_init_hw(&adapter->hw)) | |
834 | pr_err("Hardware Error\n"); | |
835 | } | |
836 | ||
837 | /** | |
838 | * pch_gbe_free_irq - Free an interrupt | |
839 | * @adapter: Board private structure | |
840 | */ | |
841 | static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter) | |
842 | { | |
843 | struct net_device *netdev = adapter->netdev; | |
844 | ||
845 | free_irq(adapter->pdev->irq, netdev); | |
846 | if (adapter->have_msi) { | |
847 | pci_disable_msi(adapter->pdev); | |
848 | pr_debug("call pci_disable_msi\n"); | |
849 | } | |
850 | } | |
851 | ||
852 | /** | |
853 | * pch_gbe_irq_disable - Mask off interrupt generation on the NIC | |
854 | * @adapter: Board private structure | |
855 | */ | |
856 | static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter) | |
857 | { | |
858 | struct pch_gbe_hw *hw = &adapter->hw; | |
859 | ||
860 | atomic_inc(&adapter->irq_sem); | |
861 | iowrite32(0, &hw->reg->INT_EN); | |
862 | ioread32(&hw->reg->INT_ST); | |
863 | synchronize_irq(adapter->pdev->irq); | |
864 | ||
865 | pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN)); | |
866 | } | |
867 | ||
868 | /** | |
869 | * pch_gbe_irq_enable - Enable default interrupt generation settings | |
870 | * @adapter: Board private structure | |
871 | */ | |
872 | static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter) | |
873 | { | |
874 | struct pch_gbe_hw *hw = &adapter->hw; | |
875 | ||
876 | if (likely(atomic_dec_and_test(&adapter->irq_sem))) | |
877 | iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); | |
878 | ioread32(&hw->reg->INT_ST); | |
879 | pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN)); | |
880 | } | |
881 | ||
882 | ||
883 | ||
884 | /** | |
885 | * pch_gbe_setup_tctl - configure the Transmit control registers | |
886 | * @adapter: Board private structure | |
887 | */ | |
888 | static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter) | |
889 | { | |
890 | struct pch_gbe_hw *hw = &adapter->hw; | |
891 | u32 tx_mode, tcpip; | |
892 | ||
893 | tx_mode = PCH_GBE_TM_LONG_PKT | | |
894 | PCH_GBE_TM_ST_AND_FD | | |
895 | PCH_GBE_TM_SHORT_PKT | | |
896 | PCH_GBE_TM_TH_TX_STRT_8 | | |
897 | PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8; | |
898 | ||
899 | iowrite32(tx_mode, &hw->reg->TX_MODE); | |
900 | ||
901 | tcpip = ioread32(&hw->reg->TCPIP_ACC); | |
902 | tcpip |= PCH_GBE_TX_TCPIPACC_EN; | |
903 | iowrite32(tcpip, &hw->reg->TCPIP_ACC); | |
904 | return; | |
905 | } | |
906 | ||
907 | /** | |
908 | * pch_gbe_configure_tx - Configure Transmit Unit after Reset | |
909 | * @adapter: Board private structure | |
910 | */ | |
911 | static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter) | |
912 | { | |
913 | struct pch_gbe_hw *hw = &adapter->hw; | |
914 | u32 tdba, tdlen, dctrl; | |
915 | ||
916 | pr_debug("dma addr = 0x%08llx size = 0x%08x\n", | |
917 | (unsigned long long)adapter->tx_ring->dma, | |
918 | adapter->tx_ring->size); | |
919 | ||
920 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
921 | tdba = adapter->tx_ring->dma; | |
922 | tdlen = adapter->tx_ring->size - 0x10; | |
923 | iowrite32(tdba, &hw->reg->TX_DSC_BASE); | |
924 | iowrite32(tdlen, &hw->reg->TX_DSC_SIZE); | |
925 | iowrite32(tdba, &hw->reg->TX_DSC_SW_P); | |
926 | ||
927 | /* Enables Transmission DMA */ | |
928 | dctrl = ioread32(&hw->reg->DMA_CTRL); | |
929 | dctrl |= PCH_GBE_TX_DMA_EN; | |
930 | iowrite32(dctrl, &hw->reg->DMA_CTRL); | |
931 | } | |
932 | ||
933 | /** | |
934 | * pch_gbe_setup_rctl - Configure the receive control registers | |
935 | * @adapter: Board private structure | |
936 | */ | |
937 | static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter) | |
938 | { | |
939 | struct pch_gbe_hw *hw = &adapter->hw; | |
940 | u32 rx_mode, tcpip; | |
941 | ||
942 | rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN | | |
943 | PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8; | |
944 | ||
945 | iowrite32(rx_mode, &hw->reg->RX_MODE); | |
946 | ||
947 | tcpip = ioread32(&hw->reg->TCPIP_ACC); | |
948 | ||
124d770a TO |
949 | tcpip |= PCH_GBE_RX_TCPIPACC_OFF; |
950 | tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; | |
77555ee7 MO |
951 | iowrite32(tcpip, &hw->reg->TCPIP_ACC); |
952 | return; | |
953 | } | |
954 | ||
955 | /** | |
956 | * pch_gbe_configure_rx - Configure Receive Unit after Reset | |
957 | * @adapter: Board private structure | |
958 | */ | |
959 | static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter) | |
960 | { | |
961 | struct pch_gbe_hw *hw = &adapter->hw; | |
962 | u32 rdba, rdlen, rctl, rxdma; | |
963 | ||
964 | pr_debug("dma adr = 0x%08llx size = 0x%08x\n", | |
965 | (unsigned long long)adapter->rx_ring->dma, | |
966 | adapter->rx_ring->size); | |
967 | ||
968 | pch_gbe_mac_force_mac_fc(hw); | |
969 | ||
970 | /* Disables Receive MAC */ | |
971 | rctl = ioread32(&hw->reg->MAC_RX_EN); | |
972 | iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); | |
973 | ||
974 | /* Disables Receive DMA */ | |
975 | rxdma = ioread32(&hw->reg->DMA_CTRL); | |
976 | rxdma &= ~PCH_GBE_RX_DMA_EN; | |
977 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | |
978 | ||
979 | pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n", | |
980 | ioread32(&hw->reg->MAC_RX_EN), | |
981 | ioread32(&hw->reg->DMA_CTRL)); | |
982 | ||
983 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
984 | * the Base and Length of the Rx Descriptor Ring */ | |
985 | rdba = adapter->rx_ring->dma; | |
986 | rdlen = adapter->rx_ring->size - 0x10; | |
987 | iowrite32(rdba, &hw->reg->RX_DSC_BASE); | |
988 | iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); | |
989 | iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); | |
77555ee7 MO |
990 | } |
991 | ||
992 | /** | |
993 | * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer | |
994 | * @adapter: Board private structure | |
995 | * @buffer_info: Buffer information structure | |
996 | */ | |
997 | static void pch_gbe_unmap_and_free_tx_resource( | |
998 | struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info) | |
999 | { | |
1000 | if (buffer_info->mapped) { | |
1001 | dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, | |
1002 | buffer_info->length, DMA_TO_DEVICE); | |
1003 | buffer_info->mapped = false; | |
1004 | } | |
1005 | if (buffer_info->skb) { | |
1006 | dev_kfree_skb_any(buffer_info->skb); | |
1007 | buffer_info->skb = NULL; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | /** | |
1012 | * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer | |
1013 | * @adapter: Board private structure | |
1014 | * @buffer_info: Buffer information structure | |
1015 | */ | |
1016 | static void pch_gbe_unmap_and_free_rx_resource( | |
1017 | struct pch_gbe_adapter *adapter, | |
1018 | struct pch_gbe_buffer *buffer_info) | |
1019 | { | |
1020 | if (buffer_info->mapped) { | |
1021 | dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, | |
1022 | buffer_info->length, DMA_FROM_DEVICE); | |
1023 | buffer_info->mapped = false; | |
1024 | } | |
1025 | if (buffer_info->skb) { | |
1026 | dev_kfree_skb_any(buffer_info->skb); | |
1027 | buffer_info->skb = NULL; | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | /** | |
1032 | * pch_gbe_clean_tx_ring - Free Tx Buffers | |
1033 | * @adapter: Board private structure | |
1034 | * @tx_ring: Ring to be cleaned | |
1035 | */ | |
1036 | static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter, | |
1037 | struct pch_gbe_tx_ring *tx_ring) | |
1038 | { | |
1039 | struct pch_gbe_hw *hw = &adapter->hw; | |
1040 | struct pch_gbe_buffer *buffer_info; | |
1041 | unsigned long size; | |
1042 | unsigned int i; | |
1043 | ||
1044 | /* Free all the Tx ring sk_buffs */ | |
1045 | for (i = 0; i < tx_ring->count; i++) { | |
1046 | buffer_info = &tx_ring->buffer_info[i]; | |
1047 | pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info); | |
1048 | } | |
1049 | pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i); | |
1050 | ||
1051 | size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count; | |
1052 | memset(tx_ring->buffer_info, 0, size); | |
1053 | ||
1054 | /* Zero out the descriptor ring */ | |
1055 | memset(tx_ring->desc, 0, tx_ring->size); | |
1056 | tx_ring->next_to_use = 0; | |
1057 | tx_ring->next_to_clean = 0; | |
1058 | iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P); | |
1059 | iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE); | |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * pch_gbe_clean_rx_ring - Free Rx Buffers | |
1064 | * @adapter: Board private structure | |
1065 | * @rx_ring: Ring to free buffers from | |
1066 | */ | |
1067 | static void | |
1068 | pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter, | |
1069 | struct pch_gbe_rx_ring *rx_ring) | |
1070 | { | |
1071 | struct pch_gbe_hw *hw = &adapter->hw; | |
1072 | struct pch_gbe_buffer *buffer_info; | |
1073 | unsigned long size; | |
1074 | unsigned int i; | |
1075 | ||
1076 | /* Free all the Rx ring sk_buffs */ | |
1077 | for (i = 0; i < rx_ring->count; i++) { | |
1078 | buffer_info = &rx_ring->buffer_info[i]; | |
1079 | pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info); | |
1080 | } | |
1081 | pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i); | |
1082 | size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count; | |
1083 | memset(rx_ring->buffer_info, 0, size); | |
1084 | ||
1085 | /* Zero out the descriptor ring */ | |
1086 | memset(rx_ring->desc, 0, rx_ring->size); | |
1087 | rx_ring->next_to_clean = 0; | |
1088 | rx_ring->next_to_use = 0; | |
1089 | iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P); | |
1090 | iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE); | |
1091 | } | |
1092 | ||
1093 | static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed, | |
1094 | u16 duplex) | |
1095 | { | |
1096 | struct pch_gbe_hw *hw = &adapter->hw; | |
1097 | unsigned long rgmii = 0; | |
1098 | ||
1099 | /* Set the RGMII control. */ | |
1100 | #ifdef PCH_GBE_MAC_IFOP_RGMII | |
1101 | switch (speed) { | |
1102 | case SPEED_10: | |
1103 | rgmii = (PCH_GBE_RGMII_RATE_2_5M | | |
1104 | PCH_GBE_MAC_RGMII_CTRL_SETTING); | |
1105 | break; | |
1106 | case SPEED_100: | |
1107 | rgmii = (PCH_GBE_RGMII_RATE_25M | | |
1108 | PCH_GBE_MAC_RGMII_CTRL_SETTING); | |
1109 | break; | |
1110 | case SPEED_1000: | |
1111 | rgmii = (PCH_GBE_RGMII_RATE_125M | | |
1112 | PCH_GBE_MAC_RGMII_CTRL_SETTING); | |
1113 | break; | |
1114 | } | |
1115 | iowrite32(rgmii, &hw->reg->RGMII_CTRL); | |
1116 | #else /* GMII */ | |
1117 | rgmii = 0; | |
1118 | iowrite32(rgmii, &hw->reg->RGMII_CTRL); | |
1119 | #endif | |
1120 | } | |
1121 | static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed, | |
1122 | u16 duplex) | |
1123 | { | |
1124 | struct net_device *netdev = adapter->netdev; | |
1125 | struct pch_gbe_hw *hw = &adapter->hw; | |
1126 | unsigned long mode = 0; | |
1127 | ||
1128 | /* Set the communication mode */ | |
1129 | switch (speed) { | |
1130 | case SPEED_10: | |
1131 | mode = PCH_GBE_MODE_MII_ETHER; | |
1132 | netdev->tx_queue_len = 10; | |
1133 | break; | |
1134 | case SPEED_100: | |
1135 | mode = PCH_GBE_MODE_MII_ETHER; | |
1136 | netdev->tx_queue_len = 100; | |
1137 | break; | |
1138 | case SPEED_1000: | |
1139 | mode = PCH_GBE_MODE_GMII_ETHER; | |
1140 | break; | |
1141 | } | |
1142 | if (duplex == DUPLEX_FULL) | |
1143 | mode |= PCH_GBE_MODE_FULL_DUPLEX; | |
1144 | else | |
1145 | mode |= PCH_GBE_MODE_HALF_DUPLEX; | |
1146 | iowrite32(mode, &hw->reg->MODE); | |
1147 | } | |
1148 | ||
1149 | /** | |
1150 | * pch_gbe_watchdog - Watchdog process | |
1151 | * @data: Board private structure | |
1152 | */ | |
1153 | static void pch_gbe_watchdog(unsigned long data) | |
1154 | { | |
1155 | struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data; | |
1156 | struct net_device *netdev = adapter->netdev; | |
1157 | struct pch_gbe_hw *hw = &adapter->hw; | |
77555ee7 MO |
1158 | |
1159 | pr_debug("right now = %ld\n", jiffies); | |
1160 | ||
1161 | pch_gbe_update_stats(adapter); | |
1162 | if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) { | |
8ae6daca | 1163 | struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; |
77555ee7 MO |
1164 | netdev->tx_queue_len = adapter->tx_queue_len; |
1165 | /* mii library handles link maintenance tasks */ | |
1166 | if (mii_ethtool_gset(&adapter->mii, &cmd)) { | |
1167 | pr_err("ethtool get setting Error\n"); | |
1168 | mod_timer(&adapter->watchdog_timer, | |
1169 | round_jiffies(jiffies + | |
1170 | PCH_GBE_WATCHDOG_PERIOD)); | |
1171 | return; | |
1172 | } | |
8ae6daca | 1173 | hw->mac.link_speed = ethtool_cmd_speed(&cmd); |
77555ee7 MO |
1174 | hw->mac.link_duplex = cmd.duplex; |
1175 | /* Set the RGMII control. */ | |
1176 | pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, | |
1177 | hw->mac.link_duplex); | |
1178 | /* Set the communication mode */ | |
1179 | pch_gbe_set_mode(adapter, hw->mac.link_speed, | |
1180 | hw->mac.link_duplex); | |
1181 | netdev_dbg(netdev, | |
1182 | "Link is Up %d Mbps %s-Duplex\n", | |
8ae6daca | 1183 | hw->mac.link_speed, |
77555ee7 MO |
1184 | cmd.duplex == DUPLEX_FULL ? "Full" : "Half"); |
1185 | netif_carrier_on(netdev); | |
1186 | netif_wake_queue(netdev); | |
1187 | } else if ((!mii_link_ok(&adapter->mii)) && | |
1188 | (netif_carrier_ok(netdev))) { | |
1189 | netdev_dbg(netdev, "NIC Link is Down\n"); | |
1190 | hw->mac.link_speed = SPEED_10; | |
1191 | hw->mac.link_duplex = DUPLEX_HALF; | |
1192 | netif_carrier_off(netdev); | |
1193 | netif_stop_queue(netdev); | |
1194 | } | |
1195 | mod_timer(&adapter->watchdog_timer, | |
1196 | round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD)); | |
1197 | } | |
1198 | ||
1199 | /** | |
1200 | * pch_gbe_tx_queue - Carry out queuing of the transmission data | |
1201 | * @adapter: Board private structure | |
1202 | * @tx_ring: Tx descriptor ring structure | |
1203 | * @skb: Sockt buffer structure | |
1204 | */ | |
1205 | static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter, | |
1206 | struct pch_gbe_tx_ring *tx_ring, | |
1207 | struct sk_buff *skb) | |
1208 | { | |
1209 | struct pch_gbe_hw *hw = &adapter->hw; | |
1210 | struct pch_gbe_tx_desc *tx_desc; | |
1211 | struct pch_gbe_buffer *buffer_info; | |
1212 | struct sk_buff *tmp_skb; | |
1213 | unsigned int frame_ctrl; | |
1214 | unsigned int ring_num; | |
1215 | unsigned long flags; | |
1216 | ||
1217 | /*-- Set frame control --*/ | |
1218 | frame_ctrl = 0; | |
1219 | if (unlikely(skb->len < PCH_GBE_SHORT_PKT)) | |
1220 | frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; | |
756a6b03 | 1221 | if (skb->ip_summed == CHECKSUM_NONE) |
77555ee7 MO |
1222 | frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; |
1223 | ||
1224 | /* Performs checksum processing */ | |
1225 | /* | |
1226 | * It is because the hardware accelerator does not support a checksum, | |
1227 | * when the received data size is less than 64 bytes. | |
1228 | */ | |
756a6b03 | 1229 | if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) { |
77555ee7 MO |
1230 | frame_ctrl |= PCH_GBE_TXD_CTRL_APAD | |
1231 | PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; | |
1232 | if (skb->protocol == htons(ETH_P_IP)) { | |
1233 | struct iphdr *iph = ip_hdr(skb); | |
1234 | unsigned int offset; | |
1235 | iph->check = 0; | |
1236 | iph->check = ip_fast_csum((u8 *) iph, iph->ihl); | |
1237 | offset = skb_transport_offset(skb); | |
1238 | if (iph->protocol == IPPROTO_TCP) { | |
1239 | skb->csum = 0; | |
1240 | tcp_hdr(skb)->check = 0; | |
1241 | skb->csum = skb_checksum(skb, offset, | |
1242 | skb->len - offset, 0); | |
1243 | tcp_hdr(skb)->check = | |
1244 | csum_tcpudp_magic(iph->saddr, | |
1245 | iph->daddr, | |
1246 | skb->len - offset, | |
1247 | IPPROTO_TCP, | |
1248 | skb->csum); | |
1249 | } else if (iph->protocol == IPPROTO_UDP) { | |
1250 | skb->csum = 0; | |
1251 | udp_hdr(skb)->check = 0; | |
1252 | skb->csum = | |
1253 | skb_checksum(skb, offset, | |
1254 | skb->len - offset, 0); | |
1255 | udp_hdr(skb)->check = | |
1256 | csum_tcpudp_magic(iph->saddr, | |
1257 | iph->daddr, | |
1258 | skb->len - offset, | |
1259 | IPPROTO_UDP, | |
1260 | skb->csum); | |
1261 | } | |
1262 | } | |
1263 | } | |
1264 | spin_lock_irqsave(&tx_ring->tx_lock, flags); | |
1265 | ring_num = tx_ring->next_to_use; | |
1266 | if (unlikely((ring_num + 1) == tx_ring->count)) | |
1267 | tx_ring->next_to_use = 0; | |
1268 | else | |
1269 | tx_ring->next_to_use = ring_num + 1; | |
1270 | ||
1271 | spin_unlock_irqrestore(&tx_ring->tx_lock, flags); | |
1272 | buffer_info = &tx_ring->buffer_info[ring_num]; | |
1273 | tmp_skb = buffer_info->skb; | |
1274 | ||
1275 | /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */ | |
1276 | memcpy(tmp_skb->data, skb->data, ETH_HLEN); | |
1277 | tmp_skb->data[ETH_HLEN] = 0x00; | |
1278 | tmp_skb->data[ETH_HLEN + 1] = 0x00; | |
1279 | tmp_skb->len = skb->len; | |
1280 | memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN], | |
1281 | (skb->len - ETH_HLEN)); | |
25985edc | 1282 | /*-- Set Buffer information --*/ |
77555ee7 MO |
1283 | buffer_info->length = tmp_skb->len; |
1284 | buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data, | |
1285 | buffer_info->length, | |
1286 | DMA_TO_DEVICE); | |
1287 | if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { | |
1288 | pr_err("TX DMA map failed\n"); | |
1289 | buffer_info->dma = 0; | |
1290 | buffer_info->time_stamp = 0; | |
1291 | tx_ring->next_to_use = ring_num; | |
1292 | return; | |
1293 | } | |
1294 | buffer_info->mapped = true; | |
1295 | buffer_info->time_stamp = jiffies; | |
1296 | ||
1297 | /*-- Set Tx descriptor --*/ | |
1298 | tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num); | |
1299 | tx_desc->buffer_addr = (buffer_info->dma); | |
1300 | tx_desc->length = (tmp_skb->len); | |
1301 | tx_desc->tx_words_eob = ((tmp_skb->len + 3)); | |
1302 | tx_desc->tx_frame_ctrl = (frame_ctrl); | |
1303 | tx_desc->gbec_status = (DSC_INIT16); | |
1304 | ||
1305 | if (unlikely(++ring_num == tx_ring->count)) | |
1306 | ring_num = 0; | |
1307 | ||
1308 | /* Update software pointer of TX descriptor */ | |
1309 | iowrite32(tx_ring->dma + | |
1310 | (int)sizeof(struct pch_gbe_tx_desc) * ring_num, | |
1311 | &hw->reg->TX_DSC_SW_P); | |
1a0bdadb TS |
1312 | |
1313 | #ifdef CONFIG_PCH_PTP | |
1314 | pch_tx_timestamp(adapter, skb); | |
1315 | #endif | |
1316 | ||
77555ee7 MO |
1317 | dev_kfree_skb_any(skb); |
1318 | } | |
1319 | ||
1320 | /** | |
1321 | * pch_gbe_update_stats - Update the board statistics counters | |
1322 | * @adapter: Board private structure | |
1323 | */ | |
1324 | void pch_gbe_update_stats(struct pch_gbe_adapter *adapter) | |
1325 | { | |
1326 | struct net_device *netdev = adapter->netdev; | |
1327 | struct pci_dev *pdev = adapter->pdev; | |
1328 | struct pch_gbe_hw_stats *stats = &adapter->stats; | |
1329 | unsigned long flags; | |
1330 | ||
1331 | /* | |
1332 | * Prevent stats update while adapter is being reset, or if the pci | |
1333 | * connection is down. | |
1334 | */ | |
1335 | if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal)) | |
1336 | return; | |
1337 | ||
1338 | spin_lock_irqsave(&adapter->stats_lock, flags); | |
1339 | ||
1340 | /* Update device status "adapter->stats" */ | |
1341 | stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; | |
1342 | stats->tx_errors = stats->tx_length_errors + | |
1343 | stats->tx_aborted_errors + | |
1344 | stats->tx_carrier_errors + stats->tx_timeout_count; | |
1345 | ||
1346 | /* Update network device status "adapter->net_stats" */ | |
1347 | netdev->stats.rx_packets = stats->rx_packets; | |
1348 | netdev->stats.rx_bytes = stats->rx_bytes; | |
1349 | netdev->stats.rx_dropped = stats->rx_dropped; | |
1350 | netdev->stats.tx_packets = stats->tx_packets; | |
1351 | netdev->stats.tx_bytes = stats->tx_bytes; | |
1352 | netdev->stats.tx_dropped = stats->tx_dropped; | |
1353 | /* Fill out the OS statistics structure */ | |
1354 | netdev->stats.multicast = stats->multicast; | |
1355 | netdev->stats.collisions = stats->collisions; | |
1356 | /* Rx Errors */ | |
1357 | netdev->stats.rx_errors = stats->rx_errors; | |
1358 | netdev->stats.rx_crc_errors = stats->rx_crc_errors; | |
1359 | netdev->stats.rx_frame_errors = stats->rx_frame_errors; | |
1360 | /* Tx Errors */ | |
1361 | netdev->stats.tx_errors = stats->tx_errors; | |
1362 | netdev->stats.tx_aborted_errors = stats->tx_aborted_errors; | |
1363 | netdev->stats.tx_carrier_errors = stats->tx_carrier_errors; | |
1364 | ||
1365 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1366 | } | |
1367 | ||
124d770a TO |
1368 | static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter) |
1369 | { | |
1370 | struct pch_gbe_hw *hw = &adapter->hw; | |
1371 | u32 rxdma; | |
1372 | u16 value; | |
1373 | int ret; | |
1374 | ||
1375 | /* Disable Receive DMA */ | |
1376 | rxdma = ioread32(&hw->reg->DMA_CTRL); | |
1377 | rxdma &= ~PCH_GBE_RX_DMA_EN; | |
1378 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | |
1379 | /* Wait Rx DMA BUS is IDLE */ | |
1380 | ret = pch_gbe_wait_clr_bit_irq(&hw->reg->RX_DMA_ST, PCH_GBE_IDLE_CHECK); | |
1381 | if (ret) { | |
1382 | /* Disable Bus master */ | |
1383 | pci_read_config_word(adapter->pdev, PCI_COMMAND, &value); | |
1384 | value &= ~PCI_COMMAND_MASTER; | |
1385 | pci_write_config_word(adapter->pdev, PCI_COMMAND, value); | |
1386 | /* Stop Receive */ | |
1387 | pch_gbe_mac_reset_rx(hw); | |
1388 | /* Enable Bus master */ | |
1389 | value |= PCI_COMMAND_MASTER; | |
1390 | pci_write_config_word(adapter->pdev, PCI_COMMAND, value); | |
1391 | } else { | |
1392 | /* Stop Receive */ | |
1393 | pch_gbe_mac_reset_rx(hw); | |
1394 | } | |
1395 | } | |
1396 | ||
5229d87e TO |
1397 | static void pch_gbe_start_receive(struct pch_gbe_hw *hw) |
1398 | { | |
1399 | u32 rxdma; | |
1400 | ||
1401 | /* Enables Receive DMA */ | |
1402 | rxdma = ioread32(&hw->reg->DMA_CTRL); | |
1403 | rxdma |= PCH_GBE_RX_DMA_EN; | |
1404 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | |
1405 | /* Enables Receive */ | |
1406 | iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN); | |
1407 | return; | |
1408 | } | |
1409 | ||
77555ee7 MO |
1410 | /** |
1411 | * pch_gbe_intr - Interrupt Handler | |
1412 | * @irq: Interrupt number | |
1413 | * @data: Pointer to a network interface device structure | |
1414 | * Returns | |
1415 | * - IRQ_HANDLED: Our interrupt | |
1416 | * - IRQ_NONE: Not our interrupt | |
1417 | */ | |
1418 | static irqreturn_t pch_gbe_intr(int irq, void *data) | |
1419 | { | |
1420 | struct net_device *netdev = data; | |
1421 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
1422 | struct pch_gbe_hw *hw = &adapter->hw; | |
1423 | u32 int_st; | |
1424 | u32 int_en; | |
1425 | ||
1426 | /* Check request status */ | |
1427 | int_st = ioread32(&hw->reg->INT_ST); | |
1428 | int_st = int_st & ioread32(&hw->reg->INT_EN); | |
1429 | /* When request status is no interruption factor */ | |
1430 | if (unlikely(!int_st)) | |
1431 | return IRQ_NONE; /* Not our interrupt. End processing. */ | |
1432 | pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st); | |
1433 | if (int_st & PCH_GBE_INT_RX_FRAME_ERR) | |
1434 | adapter->stats.intr_rx_frame_err_count++; | |
1435 | if (int_st & PCH_GBE_INT_RX_FIFO_ERR) | |
124d770a TO |
1436 | if (!adapter->rx_stop_flag) { |
1437 | adapter->stats.intr_rx_fifo_err_count++; | |
1438 | pr_debug("Rx fifo over run\n"); | |
1439 | adapter->rx_stop_flag = true; | |
1440 | int_en = ioread32(&hw->reg->INT_EN); | |
1441 | iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR), | |
1442 | &hw->reg->INT_EN); | |
1443 | pch_gbe_stop_receive(adapter); | |
805e969f TO |
1444 | int_st |= ioread32(&hw->reg->INT_ST); |
1445 | int_st = int_st & ioread32(&hw->reg->INT_EN); | |
124d770a | 1446 | } |
77555ee7 MO |
1447 | if (int_st & PCH_GBE_INT_RX_DMA_ERR) |
1448 | adapter->stats.intr_rx_dma_err_count++; | |
1449 | if (int_st & PCH_GBE_INT_TX_FIFO_ERR) | |
1450 | adapter->stats.intr_tx_fifo_err_count++; | |
1451 | if (int_st & PCH_GBE_INT_TX_DMA_ERR) | |
1452 | adapter->stats.intr_tx_dma_err_count++; | |
1453 | if (int_st & PCH_GBE_INT_TCPIP_ERR) | |
1454 | adapter->stats.intr_tcpip_err_count++; | |
1455 | /* When Rx descriptor is empty */ | |
1456 | if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { | |
1457 | adapter->stats.intr_rx_dsc_empty_count++; | |
124d770a | 1458 | pr_debug("Rx descriptor is empty\n"); |
77555ee7 MO |
1459 | int_en = ioread32(&hw->reg->INT_EN); |
1460 | iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); | |
1461 | if (hw->mac.tx_fc_enable) { | |
1462 | /* Set Pause packet */ | |
1463 | pch_gbe_mac_set_pause_packet(hw); | |
1464 | } | |
77555ee7 MO |
1465 | } |
1466 | ||
1467 | /* When request status is Receive interruption */ | |
805e969f | 1468 | if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) || |
23677ce3 | 1469 | (adapter->rx_stop_flag)) { |
77555ee7 MO |
1470 | if (likely(napi_schedule_prep(&adapter->napi))) { |
1471 | /* Enable only Rx Descriptor empty */ | |
1472 | atomic_inc(&adapter->irq_sem); | |
1473 | int_en = ioread32(&hw->reg->INT_EN); | |
1474 | int_en &= | |
1475 | ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT); | |
1476 | iowrite32(int_en, &hw->reg->INT_EN); | |
1477 | /* Start polling for NAPI */ | |
1478 | __napi_schedule(&adapter->napi); | |
1479 | } | |
1480 | } | |
1481 | pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n", | |
1482 | IRQ_HANDLED, ioread32(&hw->reg->INT_EN)); | |
1483 | return IRQ_HANDLED; | |
1484 | } | |
1485 | ||
1486 | /** | |
1487 | * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended | |
1488 | * @adapter: Board private structure | |
1489 | * @rx_ring: Rx descriptor ring | |
1490 | * @cleaned_count: Cleaned count | |
1491 | */ | |
1492 | static void | |
1493 | pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, | |
1494 | struct pch_gbe_rx_ring *rx_ring, int cleaned_count) | |
1495 | { | |
1496 | struct net_device *netdev = adapter->netdev; | |
1497 | struct pci_dev *pdev = adapter->pdev; | |
1498 | struct pch_gbe_hw *hw = &adapter->hw; | |
1499 | struct pch_gbe_rx_desc *rx_desc; | |
1500 | struct pch_gbe_buffer *buffer_info; | |
1501 | struct sk_buff *skb; | |
1502 | unsigned int i; | |
1503 | unsigned int bufsz; | |
1504 | ||
124d770a | 1505 | bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; |
77555ee7 MO |
1506 | i = rx_ring->next_to_use; |
1507 | ||
1508 | while ((cleaned_count--)) { | |
1509 | buffer_info = &rx_ring->buffer_info[i]; | |
124d770a TO |
1510 | skb = netdev_alloc_skb(netdev, bufsz); |
1511 | if (unlikely(!skb)) { | |
1512 | /* Better luck next round */ | |
1513 | adapter->stats.rx_alloc_buff_failed++; | |
1514 | break; | |
77555ee7 | 1515 | } |
124d770a TO |
1516 | /* align */ |
1517 | skb_reserve(skb, NET_IP_ALIGN); | |
1518 | buffer_info->skb = skb; | |
1519 | ||
77555ee7 | 1520 | buffer_info->dma = dma_map_single(&pdev->dev, |
124d770a | 1521 | buffer_info->rx_buffer, |
77555ee7 MO |
1522 | buffer_info->length, |
1523 | DMA_FROM_DEVICE); | |
1524 | if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { | |
1525 | dev_kfree_skb(skb); | |
1526 | buffer_info->skb = NULL; | |
1527 | buffer_info->dma = 0; | |
1528 | adapter->stats.rx_alloc_buff_failed++; | |
1529 | break; /* while !buffer_info->skb */ | |
1530 | } | |
1531 | buffer_info->mapped = true; | |
1532 | rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); | |
1533 | rx_desc->buffer_addr = (buffer_info->dma); | |
1534 | rx_desc->gbec_status = DSC_INIT16; | |
1535 | ||
1536 | pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n", | |
1537 | i, (unsigned long long)buffer_info->dma, | |
1538 | buffer_info->length); | |
1539 | ||
1540 | if (unlikely(++i == rx_ring->count)) | |
1541 | i = 0; | |
1542 | } | |
1543 | if (likely(rx_ring->next_to_use != i)) { | |
1544 | rx_ring->next_to_use = i; | |
1545 | if (unlikely(i-- == 0)) | |
1546 | i = (rx_ring->count - 1); | |
1547 | iowrite32(rx_ring->dma + | |
1548 | (int)sizeof(struct pch_gbe_rx_desc) * i, | |
1549 | &hw->reg->RX_DSC_SW_P); | |
1550 | } | |
1551 | return; | |
1552 | } | |
1553 | ||
124d770a TO |
1554 | static int |
1555 | pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter, | |
1556 | struct pch_gbe_rx_ring *rx_ring, int cleaned_count) | |
1557 | { | |
1558 | struct pci_dev *pdev = adapter->pdev; | |
1559 | struct pch_gbe_buffer *buffer_info; | |
1560 | unsigned int i; | |
1561 | unsigned int bufsz; | |
1562 | unsigned int size; | |
1563 | ||
1564 | bufsz = adapter->rx_buffer_len; | |
1565 | ||
1566 | size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY; | |
1567 | rx_ring->rx_buff_pool = dma_alloc_coherent(&pdev->dev, size, | |
1568 | &rx_ring->rx_buff_pool_logic, | |
1569 | GFP_KERNEL); | |
1570 | if (!rx_ring->rx_buff_pool) { | |
1571 | pr_err("Unable to allocate memory for the receive poll buffer\n"); | |
1572 | return -ENOMEM; | |
1573 | } | |
1574 | memset(rx_ring->rx_buff_pool, 0, size); | |
1575 | rx_ring->rx_buff_pool_size = size; | |
1576 | for (i = 0; i < rx_ring->count; i++) { | |
1577 | buffer_info = &rx_ring->buffer_info[i]; | |
1578 | buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i; | |
1579 | buffer_info->length = bufsz; | |
1580 | } | |
1581 | return 0; | |
1582 | } | |
1583 | ||
77555ee7 MO |
1584 | /** |
1585 | * pch_gbe_alloc_tx_buffers - Allocate transmit buffers | |
1586 | * @adapter: Board private structure | |
1587 | * @tx_ring: Tx descriptor ring | |
1588 | */ | |
1589 | static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter, | |
1590 | struct pch_gbe_tx_ring *tx_ring) | |
1591 | { | |
1592 | struct pch_gbe_buffer *buffer_info; | |
1593 | struct sk_buff *skb; | |
1594 | unsigned int i; | |
1595 | unsigned int bufsz; | |
1596 | struct pch_gbe_tx_desc *tx_desc; | |
1597 | ||
1598 | bufsz = | |
1599 | adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN; | |
1600 | ||
1601 | for (i = 0; i < tx_ring->count; i++) { | |
1602 | buffer_info = &tx_ring->buffer_info[i]; | |
1603 | skb = netdev_alloc_skb(adapter->netdev, bufsz); | |
1604 | skb_reserve(skb, PCH_GBE_DMA_ALIGN); | |
1605 | buffer_info->skb = skb; | |
1606 | tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); | |
1607 | tx_desc->gbec_status = (DSC_INIT16); | |
1608 | } | |
1609 | return; | |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * pch_gbe_clean_tx - Reclaim resources after transmit completes | |
1614 | * @adapter: Board private structure | |
1615 | * @tx_ring: Tx descriptor ring | |
1616 | * Returns | |
1617 | * true: Cleaned the descriptor | |
1618 | * false: Not cleaned the descriptor | |
1619 | */ | |
1620 | static bool | |
1621 | pch_gbe_clean_tx(struct pch_gbe_adapter *adapter, | |
1622 | struct pch_gbe_tx_ring *tx_ring) | |
1623 | { | |
1624 | struct pch_gbe_tx_desc *tx_desc; | |
1625 | struct pch_gbe_buffer *buffer_info; | |
1626 | struct sk_buff *skb; | |
1627 | unsigned int i; | |
1628 | unsigned int cleaned_count = 0; | |
805e969f | 1629 | bool cleaned = true; |
77555ee7 MO |
1630 | |
1631 | pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean); | |
1632 | ||
1633 | i = tx_ring->next_to_clean; | |
1634 | tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); | |
1635 | pr_debug("gbec_status:0x%04x dma_status:0x%04x\n", | |
1636 | tx_desc->gbec_status, tx_desc->dma_status); | |
1637 | ||
1638 | while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) { | |
1639 | pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status); | |
77555ee7 MO |
1640 | buffer_info = &tx_ring->buffer_info[i]; |
1641 | skb = buffer_info->skb; | |
1642 | ||
1643 | if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) { | |
1644 | adapter->stats.tx_aborted_errors++; | |
1645 | pr_err("Transfer Abort Error\n"); | |
1646 | } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER) | |
1647 | ) { | |
1648 | adapter->stats.tx_carrier_errors++; | |
1649 | pr_err("Transfer Carrier Sense Error\n"); | |
1650 | } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL) | |
1651 | ) { | |
1652 | adapter->stats.tx_aborted_errors++; | |
1653 | pr_err("Transfer Collision Abort Error\n"); | |
1654 | } else if ((tx_desc->gbec_status & | |
1655 | (PCH_GBE_TXD_GMAC_STAT_SNGCOL | | |
1656 | PCH_GBE_TXD_GMAC_STAT_MLTCOL))) { | |
1657 | adapter->stats.collisions++; | |
1658 | adapter->stats.tx_packets++; | |
1659 | adapter->stats.tx_bytes += skb->len; | |
1660 | pr_debug("Transfer Collision\n"); | |
1661 | } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT) | |
1662 | ) { | |
1663 | adapter->stats.tx_packets++; | |
1664 | adapter->stats.tx_bytes += skb->len; | |
1665 | } | |
1666 | if (buffer_info->mapped) { | |
1667 | pr_debug("unmap buffer_info->dma : %d\n", i); | |
1668 | dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, | |
1669 | buffer_info->length, DMA_TO_DEVICE); | |
1670 | buffer_info->mapped = false; | |
1671 | } | |
1672 | if (buffer_info->skb) { | |
1673 | pr_debug("trim buffer_info->skb : %d\n", i); | |
1674 | skb_trim(buffer_info->skb, 0); | |
1675 | } | |
1676 | tx_desc->gbec_status = DSC_INIT16; | |
1677 | if (unlikely(++i == tx_ring->count)) | |
1678 | i = 0; | |
1679 | tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); | |
1680 | ||
1681 | /* weight of a sort for tx, to avoid endless transmit cleanup */ | |
805e969f TO |
1682 | if (cleaned_count++ == PCH_GBE_TX_WEIGHT) { |
1683 | cleaned = false; | |
77555ee7 | 1684 | break; |
805e969f | 1685 | } |
77555ee7 MO |
1686 | } |
1687 | pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n", | |
1688 | cleaned_count); | |
1689 | /* Recover from running out of Tx resources in xmit_frame */ | |
1690 | if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) { | |
1691 | netif_wake_queue(adapter->netdev); | |
1692 | adapter->stats.tx_restart_count++; | |
1693 | pr_debug("Tx wake queue\n"); | |
1694 | } | |
1695 | spin_lock(&adapter->tx_queue_lock); | |
1696 | tx_ring->next_to_clean = i; | |
1697 | spin_unlock(&adapter->tx_queue_lock); | |
1698 | pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean); | |
1699 | return cleaned; | |
1700 | } | |
1701 | ||
1702 | /** | |
1703 | * pch_gbe_clean_rx - Send received data up the network stack; legacy | |
1704 | * @adapter: Board private structure | |
1705 | * @rx_ring: Rx descriptor ring | |
1706 | * @work_done: Completed count | |
1707 | * @work_to_do: Request count | |
1708 | * Returns | |
1709 | * true: Cleaned the descriptor | |
1710 | * false: Not cleaned the descriptor | |
1711 | */ | |
1712 | static bool | |
1713 | pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |
1714 | struct pch_gbe_rx_ring *rx_ring, | |
1715 | int *work_done, int work_to_do) | |
1716 | { | |
1717 | struct net_device *netdev = adapter->netdev; | |
1718 | struct pci_dev *pdev = adapter->pdev; | |
1719 | struct pch_gbe_buffer *buffer_info; | |
1720 | struct pch_gbe_rx_desc *rx_desc; | |
1721 | u32 length; | |
77555ee7 MO |
1722 | unsigned int i; |
1723 | unsigned int cleaned_count = 0; | |
1724 | bool cleaned = false; | |
124d770a | 1725 | struct sk_buff *skb; |
77555ee7 MO |
1726 | u8 dma_status; |
1727 | u16 gbec_status; | |
1728 | u32 tcp_ip_status; | |
77555ee7 MO |
1729 | |
1730 | i = rx_ring->next_to_clean; | |
1731 | ||
1732 | while (*work_done < work_to_do) { | |
1733 | /* Check Rx descriptor status */ | |
1734 | rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); | |
1735 | if (rx_desc->gbec_status == DSC_INIT16) | |
1736 | break; | |
1737 | cleaned = true; | |
1738 | cleaned_count++; | |
1739 | ||
1740 | dma_status = rx_desc->dma_status; | |
1741 | gbec_status = rx_desc->gbec_status; | |
1742 | tcp_ip_status = rx_desc->tcp_ip_status; | |
1743 | rx_desc->gbec_status = DSC_INIT16; | |
1744 | buffer_info = &rx_ring->buffer_info[i]; | |
1745 | skb = buffer_info->skb; | |
124d770a | 1746 | buffer_info->skb = NULL; |
77555ee7 MO |
1747 | |
1748 | /* unmap dma */ | |
1749 | dma_unmap_single(&pdev->dev, buffer_info->dma, | |
1750 | buffer_info->length, DMA_FROM_DEVICE); | |
1751 | buffer_info->mapped = false; | |
77555ee7 MO |
1752 | |
1753 | pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x " | |
1754 | "TCP:0x%08x] BufInf = 0x%p\n", | |
1755 | i, dma_status, gbec_status, tcp_ip_status, | |
1756 | buffer_info); | |
1757 | /* Error check */ | |
1758 | if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) { | |
1759 | adapter->stats.rx_frame_errors++; | |
1760 | pr_err("Receive Not Octal Error\n"); | |
1761 | } else if (unlikely(gbec_status & | |
1762 | PCH_GBE_RXD_GMAC_STAT_NBLERR)) { | |
1763 | adapter->stats.rx_frame_errors++; | |
1764 | pr_err("Receive Nibble Error\n"); | |
1765 | } else if (unlikely(gbec_status & | |
1766 | PCH_GBE_RXD_GMAC_STAT_CRCERR)) { | |
1767 | adapter->stats.rx_crc_errors++; | |
1768 | pr_err("Receive CRC Error\n"); | |
1769 | } else { | |
1770 | /* get receive length */ | |
124d770a TO |
1771 | /* length convert[-3], length includes FCS length */ |
1772 | length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN; | |
1773 | if (rx_desc->rx_words_eob & 0x02) | |
1774 | length = length - 4; | |
1775 | /* | |
1776 | * buffer_info->rx_buffer: [Header:14][payload] | |
1777 | * skb->data: [Reserve:2][Header:14][payload] | |
1778 | */ | |
1779 | memcpy(skb->data, buffer_info->rx_buffer, length); | |
1780 | ||
77555ee7 MO |
1781 | /* update status of driver */ |
1782 | adapter->stats.rx_bytes += length; | |
1783 | adapter->stats.rx_packets++; | |
1784 | if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT)) | |
1785 | adapter->stats.multicast++; | |
1786 | /* Write meta date of skb */ | |
1787 | skb_put(skb, length); | |
1a0bdadb TS |
1788 | |
1789 | #ifdef CONFIG_PCH_PTP | |
1790 | pch_rx_timestamp(adapter, skb); | |
1791 | #endif | |
1792 | ||
77555ee7 | 1793 | skb->protocol = eth_type_trans(skb, netdev); |
5d05a04d | 1794 | if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) |
77555ee7 | 1795 | skb->ip_summed = CHECKSUM_NONE; |
5d05a04d TO |
1796 | else |
1797 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1798 | ||
77555ee7 MO |
1799 | napi_gro_receive(&adapter->napi, skb); |
1800 | (*work_done)++; | |
1801 | pr_debug("Receive skb->ip_summed: %d length: %d\n", | |
1802 | skb->ip_summed, length); | |
1803 | } | |
77555ee7 MO |
1804 | /* return some buffers to hardware, one at a time is too slow */ |
1805 | if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { | |
1806 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, | |
1807 | cleaned_count); | |
1808 | cleaned_count = 0; | |
1809 | } | |
1810 | if (++i == rx_ring->count) | |
1811 | i = 0; | |
1812 | } | |
1813 | rx_ring->next_to_clean = i; | |
1814 | if (cleaned_count) | |
1815 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
1816 | return cleaned; | |
1817 | } | |
1818 | ||
1819 | /** | |
1820 | * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors) | |
1821 | * @adapter: Board private structure | |
1822 | * @tx_ring: Tx descriptor ring (for a specific queue) to setup | |
1823 | * Returns | |
1824 | * 0: Successfully | |
1825 | * Negative value: Failed | |
1826 | */ | |
1827 | int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter, | |
1828 | struct pch_gbe_tx_ring *tx_ring) | |
1829 | { | |
1830 | struct pci_dev *pdev = adapter->pdev; | |
1831 | struct pch_gbe_tx_desc *tx_desc; | |
1832 | int size; | |
1833 | int desNo; | |
1834 | ||
1835 | size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count; | |
89bf67f1 | 1836 | tx_ring->buffer_info = vzalloc(size); |
e404decb | 1837 | if (!tx_ring->buffer_info) |
77555ee7 | 1838 | return -ENOMEM; |
77555ee7 MO |
1839 | |
1840 | tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc); | |
1841 | ||
1842 | tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, | |
1843 | &tx_ring->dma, GFP_KERNEL); | |
1844 | if (!tx_ring->desc) { | |
1845 | vfree(tx_ring->buffer_info); | |
1846 | pr_err("Unable to allocate memory for the transmit descriptor ring\n"); | |
1847 | return -ENOMEM; | |
1848 | } | |
1849 | memset(tx_ring->desc, 0, tx_ring->size); | |
1850 | ||
1851 | tx_ring->next_to_use = 0; | |
1852 | tx_ring->next_to_clean = 0; | |
1853 | spin_lock_init(&tx_ring->tx_lock); | |
1854 | ||
1855 | for (desNo = 0; desNo < tx_ring->count; desNo++) { | |
1856 | tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo); | |
1857 | tx_desc->gbec_status = DSC_INIT16; | |
1858 | } | |
1859 | pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n" | |
1860 | "next_to_clean = 0x%08x next_to_use = 0x%08x\n", | |
1861 | tx_ring->desc, (unsigned long long)tx_ring->dma, | |
1862 | tx_ring->next_to_clean, tx_ring->next_to_use); | |
1863 | return 0; | |
1864 | } | |
1865 | ||
1866 | /** | |
1867 | * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors) | |
1868 | * @adapter: Board private structure | |
1869 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
1870 | * Returns | |
1871 | * 0: Successfully | |
1872 | * Negative value: Failed | |
1873 | */ | |
1874 | int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter, | |
1875 | struct pch_gbe_rx_ring *rx_ring) | |
1876 | { | |
1877 | struct pci_dev *pdev = adapter->pdev; | |
1878 | struct pch_gbe_rx_desc *rx_desc; | |
1879 | int size; | |
1880 | int desNo; | |
1881 | ||
1882 | size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count; | |
89bf67f1 | 1883 | rx_ring->buffer_info = vzalloc(size); |
e404decb | 1884 | if (!rx_ring->buffer_info) |
77555ee7 | 1885 | return -ENOMEM; |
e404decb | 1886 | |
77555ee7 MO |
1887 | rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc); |
1888 | rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, | |
1889 | &rx_ring->dma, GFP_KERNEL); | |
1890 | ||
1891 | if (!rx_ring->desc) { | |
1892 | pr_err("Unable to allocate memory for the receive descriptor ring\n"); | |
1893 | vfree(rx_ring->buffer_info); | |
1894 | return -ENOMEM; | |
1895 | } | |
1896 | memset(rx_ring->desc, 0, rx_ring->size); | |
1897 | rx_ring->next_to_clean = 0; | |
1898 | rx_ring->next_to_use = 0; | |
1899 | for (desNo = 0; desNo < rx_ring->count; desNo++) { | |
1900 | rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo); | |
1901 | rx_desc->gbec_status = DSC_INIT16; | |
1902 | } | |
1903 | pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx " | |
1904 | "next_to_clean = 0x%08x next_to_use = 0x%08x\n", | |
1905 | rx_ring->desc, (unsigned long long)rx_ring->dma, | |
1906 | rx_ring->next_to_clean, rx_ring->next_to_use); | |
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | /** | |
1911 | * pch_gbe_free_tx_resources - Free Tx Resources | |
1912 | * @adapter: Board private structure | |
1913 | * @tx_ring: Tx descriptor ring for a specific queue | |
1914 | */ | |
1915 | void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter, | |
1916 | struct pch_gbe_tx_ring *tx_ring) | |
1917 | { | |
1918 | struct pci_dev *pdev = adapter->pdev; | |
1919 | ||
1920 | pch_gbe_clean_tx_ring(adapter, tx_ring); | |
1921 | vfree(tx_ring->buffer_info); | |
1922 | tx_ring->buffer_info = NULL; | |
1923 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
1924 | tx_ring->desc = NULL; | |
1925 | } | |
1926 | ||
1927 | /** | |
1928 | * pch_gbe_free_rx_resources - Free Rx Resources | |
1929 | * @adapter: Board private structure | |
1930 | * @rx_ring: Ring to clean the resources from | |
1931 | */ | |
1932 | void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter, | |
1933 | struct pch_gbe_rx_ring *rx_ring) | |
1934 | { | |
1935 | struct pci_dev *pdev = adapter->pdev; | |
1936 | ||
1937 | pch_gbe_clean_rx_ring(adapter, rx_ring); | |
1938 | vfree(rx_ring->buffer_info); | |
1939 | rx_ring->buffer_info = NULL; | |
1940 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
1941 | rx_ring->desc = NULL; | |
1942 | } | |
1943 | ||
1944 | /** | |
1945 | * pch_gbe_request_irq - Allocate an interrupt line | |
1946 | * @adapter: Board private structure | |
1947 | * Returns | |
1948 | * 0: Successfully | |
1949 | * Negative value: Failed | |
1950 | */ | |
1951 | static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter) | |
1952 | { | |
1953 | struct net_device *netdev = adapter->netdev; | |
1954 | int err; | |
1955 | int flags; | |
1956 | ||
1957 | flags = IRQF_SHARED; | |
1958 | adapter->have_msi = false; | |
1959 | err = pci_enable_msi(adapter->pdev); | |
1960 | pr_debug("call pci_enable_msi\n"); | |
1961 | if (err) { | |
1962 | pr_debug("call pci_enable_msi - Error: %d\n", err); | |
1963 | } else { | |
1964 | flags = 0; | |
1965 | adapter->have_msi = true; | |
1966 | } | |
1967 | err = request_irq(adapter->pdev->irq, &pch_gbe_intr, | |
1968 | flags, netdev->name, netdev); | |
1969 | if (err) | |
1970 | pr_err("Unable to allocate interrupt Error: %d\n", err); | |
1971 | pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n", | |
1972 | adapter->have_msi, flags, err); | |
1973 | return err; | |
1974 | } | |
1975 | ||
1976 | ||
1977 | static void pch_gbe_set_multi(struct net_device *netdev); | |
1978 | /** | |
1979 | * pch_gbe_up - Up GbE network device | |
1980 | * @adapter: Board private structure | |
1981 | * Returns | |
1982 | * 0: Successfully | |
1983 | * Negative value: Failed | |
1984 | */ | |
1985 | int pch_gbe_up(struct pch_gbe_adapter *adapter) | |
1986 | { | |
1987 | struct net_device *netdev = adapter->netdev; | |
1988 | struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; | |
1989 | struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; | |
1990 | int err; | |
1991 | ||
2b53d078 DH |
1992 | /* Ensure we have a valid MAC */ |
1993 | if (!is_valid_ether_addr(adapter->hw.mac.addr)) { | |
1994 | pr_err("Error: Invalid MAC address\n"); | |
1995 | return -EINVAL; | |
1996 | } | |
1997 | ||
77555ee7 MO |
1998 | /* hardware has been reset, we need to reload some things */ |
1999 | pch_gbe_set_multi(netdev); | |
2000 | ||
2001 | pch_gbe_setup_tctl(adapter); | |
2002 | pch_gbe_configure_tx(adapter); | |
2003 | pch_gbe_setup_rctl(adapter); | |
2004 | pch_gbe_configure_rx(adapter); | |
2005 | ||
2006 | err = pch_gbe_request_irq(adapter); | |
2007 | if (err) { | |
2008 | pr_err("Error: can't bring device up\n"); | |
2009 | return err; | |
2010 | } | |
124d770a TO |
2011 | err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count); |
2012 | if (err) { | |
2013 | pr_err("Error: can't bring device up\n"); | |
2014 | return err; | |
2015 | } | |
77555ee7 MO |
2016 | pch_gbe_alloc_tx_buffers(adapter, tx_ring); |
2017 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); | |
2018 | adapter->tx_queue_len = netdev->tx_queue_len; | |
5229d87e | 2019 | pch_gbe_start_receive(&adapter->hw); |
77555ee7 MO |
2020 | |
2021 | mod_timer(&adapter->watchdog_timer, jiffies); | |
2022 | ||
2023 | napi_enable(&adapter->napi); | |
2024 | pch_gbe_irq_enable(adapter); | |
2025 | netif_start_queue(adapter->netdev); | |
2026 | ||
2027 | return 0; | |
2028 | } | |
2029 | ||
2030 | /** | |
2031 | * pch_gbe_down - Down GbE network device | |
2032 | * @adapter: Board private structure | |
2033 | */ | |
2034 | void pch_gbe_down(struct pch_gbe_adapter *adapter) | |
2035 | { | |
2036 | struct net_device *netdev = adapter->netdev; | |
124d770a | 2037 | struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; |
77555ee7 MO |
2038 | |
2039 | /* signal that we're down so the interrupt handler does not | |
2040 | * reschedule our watchdog timer */ | |
2041 | napi_disable(&adapter->napi); | |
2042 | atomic_set(&adapter->irq_sem, 0); | |
2043 | ||
2044 | pch_gbe_irq_disable(adapter); | |
2045 | pch_gbe_free_irq(adapter); | |
2046 | ||
2047 | del_timer_sync(&adapter->watchdog_timer); | |
2048 | ||
2049 | netdev->tx_queue_len = adapter->tx_queue_len; | |
2050 | netif_carrier_off(netdev); | |
2051 | netif_stop_queue(netdev); | |
2052 | ||
2053 | pch_gbe_reset(adapter); | |
2054 | pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); | |
2055 | pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); | |
124d770a TO |
2056 | |
2057 | pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size, | |
2058 | rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic); | |
2059 | rx_ring->rx_buff_pool_logic = 0; | |
2060 | rx_ring->rx_buff_pool_size = 0; | |
2061 | rx_ring->rx_buff_pool = NULL; | |
77555ee7 MO |
2062 | } |
2063 | ||
2064 | /** | |
2065 | * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter) | |
2066 | * @adapter: Board private structure to initialize | |
2067 | * Returns | |
2068 | * 0: Successfully | |
2069 | * Negative value: Failed | |
2070 | */ | |
2071 | static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter) | |
2072 | { | |
2073 | struct pch_gbe_hw *hw = &adapter->hw; | |
2074 | struct net_device *netdev = adapter->netdev; | |
2075 | ||
2076 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; | |
2077 | hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
2078 | hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
2079 | ||
2080 | /* Initialize the hardware-specific values */ | |
2081 | if (pch_gbe_hal_setup_init_funcs(hw)) { | |
2082 | pr_err("Hardware Initialization Failure\n"); | |
2083 | return -EIO; | |
2084 | } | |
2085 | if (pch_gbe_alloc_queues(adapter)) { | |
2086 | pr_err("Unable to allocate memory for queues\n"); | |
2087 | return -ENOMEM; | |
2088 | } | |
2089 | spin_lock_init(&adapter->hw.miim_lock); | |
2090 | spin_lock_init(&adapter->tx_queue_lock); | |
2091 | spin_lock_init(&adapter->stats_lock); | |
2092 | spin_lock_init(&adapter->ethtool_lock); | |
2093 | atomic_set(&adapter->irq_sem, 0); | |
2094 | pch_gbe_irq_disable(adapter); | |
2095 | ||
2096 | pch_gbe_init_stats(adapter); | |
2097 | ||
2098 | pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n", | |
2099 | (u32) adapter->rx_buffer_len, | |
2100 | hw->mac.min_frame_size, hw->mac.max_frame_size); | |
2101 | return 0; | |
2102 | } | |
2103 | ||
2104 | /** | |
2105 | * pch_gbe_open - Called when a network interface is made active | |
2106 | * @netdev: Network interface device structure | |
2107 | * Returns | |
2108 | * 0: Successfully | |
2109 | * Negative value: Failed | |
2110 | */ | |
2111 | static int pch_gbe_open(struct net_device *netdev) | |
2112 | { | |
2113 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2114 | struct pch_gbe_hw *hw = &adapter->hw; | |
2115 | int err; | |
2116 | ||
2117 | /* allocate transmit descriptors */ | |
2118 | err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring); | |
2119 | if (err) | |
2120 | goto err_setup_tx; | |
2121 | /* allocate receive descriptors */ | |
2122 | err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring); | |
2123 | if (err) | |
2124 | goto err_setup_rx; | |
2125 | pch_gbe_hal_power_up_phy(hw); | |
2126 | err = pch_gbe_up(adapter); | |
2127 | if (err) | |
2128 | goto err_up; | |
2129 | pr_debug("Success End\n"); | |
2130 | return 0; | |
2131 | ||
2132 | err_up: | |
2133 | if (!adapter->wake_up_evt) | |
2134 | pch_gbe_hal_power_down_phy(hw); | |
2135 | pch_gbe_free_rx_resources(adapter, adapter->rx_ring); | |
2136 | err_setup_rx: | |
2137 | pch_gbe_free_tx_resources(adapter, adapter->tx_ring); | |
2138 | err_setup_tx: | |
2139 | pch_gbe_reset(adapter); | |
2140 | pr_err("Error End\n"); | |
2141 | return err; | |
2142 | } | |
2143 | ||
2144 | /** | |
2145 | * pch_gbe_stop - Disables a network interface | |
2146 | * @netdev: Network interface device structure | |
2147 | * Returns | |
2148 | * 0: Successfully | |
2149 | */ | |
2150 | static int pch_gbe_stop(struct net_device *netdev) | |
2151 | { | |
2152 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2153 | struct pch_gbe_hw *hw = &adapter->hw; | |
2154 | ||
2155 | pch_gbe_down(adapter); | |
2156 | if (!adapter->wake_up_evt) | |
2157 | pch_gbe_hal_power_down_phy(hw); | |
2158 | pch_gbe_free_tx_resources(adapter, adapter->tx_ring); | |
2159 | pch_gbe_free_rx_resources(adapter, adapter->rx_ring); | |
2160 | return 0; | |
2161 | } | |
2162 | ||
2163 | /** | |
2164 | * pch_gbe_xmit_frame - Packet transmitting start | |
2165 | * @skb: Socket buffer structure | |
2166 | * @netdev: Network interface device structure | |
2167 | * Returns | |
2168 | * - NETDEV_TX_OK: Normal end | |
2169 | * - NETDEV_TX_BUSY: Error end | |
2170 | */ | |
2171 | static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2172 | { | |
2173 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2174 | struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; | |
2175 | unsigned long flags; | |
2176 | ||
2177 | if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) { | |
77555ee7 MO |
2178 | pr_err("Transfer length Error: skb len: %d > max: %d\n", |
2179 | skb->len, adapter->hw.mac.max_frame_size); | |
419c2046 | 2180 | dev_kfree_skb_any(skb); |
77555ee7 MO |
2181 | adapter->stats.tx_length_errors++; |
2182 | return NETDEV_TX_OK; | |
2183 | } | |
2184 | if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) { | |
2185 | /* Collision - tell upper layer to requeue */ | |
2186 | return NETDEV_TX_LOCKED; | |
2187 | } | |
2188 | if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) { | |
2189 | netif_stop_queue(netdev); | |
2190 | spin_unlock_irqrestore(&tx_ring->tx_lock, flags); | |
2191 | pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n", | |
2192 | tx_ring->next_to_use, tx_ring->next_to_clean); | |
2193 | return NETDEV_TX_BUSY; | |
2194 | } | |
2195 | spin_unlock_irqrestore(&tx_ring->tx_lock, flags); | |
2196 | ||
2197 | /* CRC,ITAG no support */ | |
2198 | pch_gbe_tx_queue(adapter, tx_ring, skb); | |
2199 | return NETDEV_TX_OK; | |
2200 | } | |
2201 | ||
2202 | /** | |
2203 | * pch_gbe_get_stats - Get System Network Statistics | |
2204 | * @netdev: Network interface device structure | |
2205 | * Returns: The current stats | |
2206 | */ | |
2207 | static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev) | |
2208 | { | |
2209 | /* only return the current stats */ | |
2210 | return &netdev->stats; | |
2211 | } | |
2212 | ||
2213 | /** | |
2214 | * pch_gbe_set_multi - Multicast and Promiscuous mode set | |
2215 | * @netdev: Network interface device structure | |
2216 | */ | |
2217 | static void pch_gbe_set_multi(struct net_device *netdev) | |
2218 | { | |
2219 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2220 | struct pch_gbe_hw *hw = &adapter->hw; | |
2221 | struct netdev_hw_addr *ha; | |
2222 | u8 *mta_list; | |
2223 | u32 rctl; | |
2224 | int i; | |
2225 | int mc_count; | |
2226 | ||
2227 | pr_debug("netdev->flags : 0x%08x\n", netdev->flags); | |
2228 | ||
2229 | /* Check for Promiscuous and All Multicast modes */ | |
2230 | rctl = ioread32(&hw->reg->RX_MODE); | |
2231 | mc_count = netdev_mc_count(netdev); | |
2232 | if ((netdev->flags & IFF_PROMISC)) { | |
2233 | rctl &= ~PCH_GBE_ADD_FIL_EN; | |
2234 | rctl &= ~PCH_GBE_MLT_FIL_EN; | |
2235 | } else if ((netdev->flags & IFF_ALLMULTI)) { | |
2236 | /* all the multicasting receive permissions */ | |
2237 | rctl |= PCH_GBE_ADD_FIL_EN; | |
2238 | rctl &= ~PCH_GBE_MLT_FIL_EN; | |
2239 | } else { | |
2240 | if (mc_count >= PCH_GBE_MAR_ENTRIES) { | |
2241 | /* all the multicasting receive permissions */ | |
2242 | rctl |= PCH_GBE_ADD_FIL_EN; | |
2243 | rctl &= ~PCH_GBE_MLT_FIL_EN; | |
2244 | } else { | |
2245 | rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN); | |
2246 | } | |
2247 | } | |
2248 | iowrite32(rctl, &hw->reg->RX_MODE); | |
2249 | ||
2250 | if (mc_count >= PCH_GBE_MAR_ENTRIES) | |
2251 | return; | |
2252 | mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC); | |
2253 | if (!mta_list) | |
2254 | return; | |
2255 | ||
2256 | /* The shared function expects a packed array of only addresses. */ | |
2257 | i = 0; | |
2258 | netdev_for_each_mc_addr(ha, netdev) { | |
2259 | if (i == mc_count) | |
2260 | break; | |
2261 | memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN); | |
2262 | } | |
2263 | pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1, | |
2264 | PCH_GBE_MAR_ENTRIES); | |
2265 | kfree(mta_list); | |
2266 | ||
2267 | pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n", | |
2268 | ioread32(&hw->reg->RX_MODE), mc_count); | |
2269 | } | |
2270 | ||
2271 | /** | |
2272 | * pch_gbe_set_mac - Change the Ethernet Address of the NIC | |
2273 | * @netdev: Network interface device structure | |
2274 | * @addr: Pointer to an address structure | |
2275 | * Returns | |
2276 | * 0: Successfully | |
2277 | * -EADDRNOTAVAIL: Failed | |
2278 | */ | |
2279 | static int pch_gbe_set_mac(struct net_device *netdev, void *addr) | |
2280 | { | |
2281 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2282 | struct sockaddr *skaddr = addr; | |
2283 | int ret_val; | |
2284 | ||
2285 | if (!is_valid_ether_addr(skaddr->sa_data)) { | |
2286 | ret_val = -EADDRNOTAVAIL; | |
2287 | } else { | |
2288 | memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len); | |
2289 | memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len); | |
2290 | pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0); | |
2291 | ret_val = 0; | |
2292 | } | |
2293 | pr_debug("ret_val : 0x%08x\n", ret_val); | |
2294 | pr_debug("dev_addr : %pM\n", netdev->dev_addr); | |
2295 | pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr); | |
2296 | pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n", | |
2297 | ioread32(&adapter->hw.reg->mac_adr[0].high), | |
2298 | ioread32(&adapter->hw.reg->mac_adr[0].low)); | |
2299 | return ret_val; | |
2300 | } | |
2301 | ||
2302 | /** | |
2303 | * pch_gbe_change_mtu - Change the Maximum Transfer Unit | |
2304 | * @netdev: Network interface device structure | |
2305 | * @new_mtu: New value for maximum frame size | |
2306 | * Returns | |
2307 | * 0: Successfully | |
2308 | * -EINVAL: Failed | |
2309 | */ | |
2310 | static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) | |
2311 | { | |
2312 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2313 | int max_frame; | |
124d770a TO |
2314 | unsigned long old_rx_buffer_len = adapter->rx_buffer_len; |
2315 | int err; | |
77555ee7 MO |
2316 | |
2317 | max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
2318 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | |
2319 | (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) { | |
2320 | pr_err("Invalid MTU setting\n"); | |
2321 | return -EINVAL; | |
2322 | } | |
2323 | if (max_frame <= PCH_GBE_FRAME_SIZE_2048) | |
2324 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; | |
2325 | else if (max_frame <= PCH_GBE_FRAME_SIZE_4096) | |
2326 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096; | |
2327 | else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) | |
2328 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; | |
2329 | else | |
124d770a | 2330 | adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE; |
77555ee7 | 2331 | |
124d770a TO |
2332 | if (netif_running(netdev)) { |
2333 | pch_gbe_down(adapter); | |
2334 | err = pch_gbe_up(adapter); | |
2335 | if (err) { | |
2336 | adapter->rx_buffer_len = old_rx_buffer_len; | |
2337 | pch_gbe_up(adapter); | |
2338 | return -ENOMEM; | |
2339 | } else { | |
2340 | netdev->mtu = new_mtu; | |
2341 | adapter->hw.mac.max_frame_size = max_frame; | |
2342 | } | |
2343 | } else { | |
77555ee7 | 2344 | pch_gbe_reset(adapter); |
124d770a TO |
2345 | netdev->mtu = new_mtu; |
2346 | adapter->hw.mac.max_frame_size = max_frame; | |
2347 | } | |
77555ee7 MO |
2348 | |
2349 | pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", | |
2350 | max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, | |
2351 | adapter->hw.mac.max_frame_size); | |
2352 | return 0; | |
2353 | } | |
2354 | ||
756a6b03 MM |
2355 | /** |
2356 | * pch_gbe_set_features - Reset device after features changed | |
2357 | * @netdev: Network interface device structure | |
2358 | * @features: New features | |
2359 | * Returns | |
2360 | * 0: HW state updated successfully | |
2361 | */ | |
c8f44aff MM |
2362 | static int pch_gbe_set_features(struct net_device *netdev, |
2363 | netdev_features_t features) | |
756a6b03 MM |
2364 | { |
2365 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
c8f44aff | 2366 | netdev_features_t changed = features ^ netdev->features; |
756a6b03 MM |
2367 | |
2368 | if (!(changed & NETIF_F_RXCSUM)) | |
2369 | return 0; | |
2370 | ||
2371 | if (netif_running(netdev)) | |
2372 | pch_gbe_reinit_locked(adapter); | |
2373 | else | |
2374 | pch_gbe_reset(adapter); | |
2375 | ||
2376 | return 0; | |
2377 | } | |
2378 | ||
77555ee7 MO |
2379 | /** |
2380 | * pch_gbe_ioctl - Controls register through a MII interface | |
2381 | * @netdev: Network interface device structure | |
2382 | * @ifr: Pointer to ifr structure | |
2383 | * @cmd: Control command | |
2384 | * Returns | |
2385 | * 0: Successfully | |
2386 | * Negative value: Failed | |
2387 | */ | |
2388 | static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
2389 | { | |
2390 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2391 | ||
2392 | pr_debug("cmd : 0x%04x\n", cmd); | |
2393 | ||
1a0bdadb TS |
2394 | #ifdef CONFIG_PCH_PTP |
2395 | if (cmd == SIOCSHWTSTAMP) | |
2396 | return hwtstamp_ioctl(netdev, ifr, cmd); | |
2397 | #endif | |
2398 | ||
77555ee7 MO |
2399 | return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); |
2400 | } | |
2401 | ||
2402 | /** | |
2403 | * pch_gbe_tx_timeout - Respond to a Tx Hang | |
2404 | * @netdev: Network interface device structure | |
2405 | */ | |
2406 | static void pch_gbe_tx_timeout(struct net_device *netdev) | |
2407 | { | |
2408 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2409 | ||
2410 | /* Do the reset outside of interrupt context */ | |
2411 | adapter->stats.tx_timeout_count++; | |
2412 | schedule_work(&adapter->reset_task); | |
2413 | } | |
2414 | ||
2415 | /** | |
2416 | * pch_gbe_napi_poll - NAPI receive and transfer polling callback | |
2417 | * @napi: Pointer of polling device struct | |
2418 | * @budget: The maximum number of a packet | |
2419 | * Returns | |
2420 | * false: Exit the polling mode | |
2421 | * true: Continue the polling mode | |
2422 | */ | |
2423 | static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) | |
2424 | { | |
2425 | struct pch_gbe_adapter *adapter = | |
2426 | container_of(napi, struct pch_gbe_adapter, napi); | |
77555ee7 MO |
2427 | int work_done = 0; |
2428 | bool poll_end_flag = false; | |
2429 | bool cleaned = false; | |
124d770a | 2430 | u32 int_en; |
77555ee7 MO |
2431 | |
2432 | pr_debug("budget : %d\n", budget); | |
2433 | ||
805e969f TO |
2434 | pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); |
2435 | cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); | |
2436 | ||
2437 | if (!cleaned) | |
2438 | work_done = budget; | |
2439 | /* If no Tx and not enough Rx work done, | |
2440 | * exit the polling mode | |
2441 | */ | |
2442 | if (work_done < budget) | |
77555ee7 | 2443 | poll_end_flag = true; |
805e969f TO |
2444 | |
2445 | if (poll_end_flag) { | |
2446 | napi_complete(napi); | |
2447 | if (adapter->rx_stop_flag) { | |
2448 | adapter->rx_stop_flag = false; | |
2449 | pch_gbe_start_receive(&adapter->hw); | |
2450 | } | |
2451 | pch_gbe_irq_enable(adapter); | |
2452 | } else | |
124d770a TO |
2453 | if (adapter->rx_stop_flag) { |
2454 | adapter->rx_stop_flag = false; | |
2455 | pch_gbe_start_receive(&adapter->hw); | |
2456 | int_en = ioread32(&adapter->hw.reg->INT_EN); | |
2457 | iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR), | |
805e969f | 2458 | &adapter->hw.reg->INT_EN); |
124d770a | 2459 | } |
77555ee7 MO |
2460 | |
2461 | pr_debug("poll_end_flag : %d work_done : %d budget : %d\n", | |
2462 | poll_end_flag, work_done, budget); | |
2463 | ||
2464 | return work_done; | |
2465 | } | |
2466 | ||
2467 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2468 | /** | |
2469 | * pch_gbe_netpoll - Used by things like netconsole to send skbs | |
2470 | * @netdev: Network interface device structure | |
2471 | */ | |
2472 | static void pch_gbe_netpoll(struct net_device *netdev) | |
2473 | { | |
2474 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2475 | ||
2476 | disable_irq(adapter->pdev->irq); | |
2477 | pch_gbe_intr(adapter->pdev->irq, netdev); | |
2478 | enable_irq(adapter->pdev->irq); | |
2479 | } | |
2480 | #endif | |
2481 | ||
2482 | static const struct net_device_ops pch_gbe_netdev_ops = { | |
2483 | .ndo_open = pch_gbe_open, | |
2484 | .ndo_stop = pch_gbe_stop, | |
2485 | .ndo_start_xmit = pch_gbe_xmit_frame, | |
2486 | .ndo_get_stats = pch_gbe_get_stats, | |
2487 | .ndo_set_mac_address = pch_gbe_set_mac, | |
2488 | .ndo_tx_timeout = pch_gbe_tx_timeout, | |
2489 | .ndo_change_mtu = pch_gbe_change_mtu, | |
756a6b03 | 2490 | .ndo_set_features = pch_gbe_set_features, |
77555ee7 | 2491 | .ndo_do_ioctl = pch_gbe_ioctl, |
afc4b13d | 2492 | .ndo_set_rx_mode = pch_gbe_set_multi, |
77555ee7 MO |
2493 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2494 | .ndo_poll_controller = pch_gbe_netpoll, | |
2495 | #endif | |
2496 | }; | |
2497 | ||
2498 | static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev, | |
2499 | pci_channel_state_t state) | |
2500 | { | |
2501 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2502 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2503 | ||
2504 | netif_device_detach(netdev); | |
2505 | if (netif_running(netdev)) | |
2506 | pch_gbe_down(adapter); | |
2507 | pci_disable_device(pdev); | |
2508 | /* Request a slot slot reset. */ | |
2509 | return PCI_ERS_RESULT_NEED_RESET; | |
2510 | } | |
2511 | ||
2512 | static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev) | |
2513 | { | |
2514 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2515 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2516 | struct pch_gbe_hw *hw = &adapter->hw; | |
2517 | ||
2518 | if (pci_enable_device(pdev)) { | |
2519 | pr_err("Cannot re-enable PCI device after reset\n"); | |
2520 | return PCI_ERS_RESULT_DISCONNECT; | |
2521 | } | |
2522 | pci_set_master(pdev); | |
2523 | pci_enable_wake(pdev, PCI_D0, 0); | |
2524 | pch_gbe_hal_power_up_phy(hw); | |
2525 | pch_gbe_reset(adapter); | |
2526 | /* Clear wake up status */ | |
2527 | pch_gbe_mac_set_wol_event(hw, 0); | |
2528 | ||
2529 | return PCI_ERS_RESULT_RECOVERED; | |
2530 | } | |
2531 | ||
2532 | static void pch_gbe_io_resume(struct pci_dev *pdev) | |
2533 | { | |
2534 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2535 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2536 | ||
2537 | if (netif_running(netdev)) { | |
2538 | if (pch_gbe_up(adapter)) { | |
2539 | pr_debug("can't bring device back up after reset\n"); | |
2540 | return; | |
2541 | } | |
2542 | } | |
2543 | netif_device_attach(netdev); | |
2544 | } | |
2545 | ||
2546 | static int __pch_gbe_suspend(struct pci_dev *pdev) | |
2547 | { | |
2548 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2549 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2550 | struct pch_gbe_hw *hw = &adapter->hw; | |
2551 | u32 wufc = adapter->wake_up_evt; | |
2552 | int retval = 0; | |
2553 | ||
2554 | netif_device_detach(netdev); | |
2555 | if (netif_running(netdev)) | |
2556 | pch_gbe_down(adapter); | |
2557 | if (wufc) { | |
2558 | pch_gbe_set_multi(netdev); | |
2559 | pch_gbe_setup_rctl(adapter); | |
2560 | pch_gbe_configure_rx(adapter); | |
2561 | pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, | |
2562 | hw->mac.link_duplex); | |
2563 | pch_gbe_set_mode(adapter, hw->mac.link_speed, | |
2564 | hw->mac.link_duplex); | |
2565 | pch_gbe_mac_set_wol_event(hw, wufc); | |
2566 | pci_disable_device(pdev); | |
2567 | } else { | |
2568 | pch_gbe_hal_power_down_phy(hw); | |
2569 | pch_gbe_mac_set_wol_event(hw, wufc); | |
2570 | pci_disable_device(pdev); | |
2571 | } | |
2572 | return retval; | |
2573 | } | |
2574 | ||
2575 | #ifdef CONFIG_PM | |
2576 | static int pch_gbe_suspend(struct device *device) | |
2577 | { | |
2578 | struct pci_dev *pdev = to_pci_dev(device); | |
2579 | ||
2580 | return __pch_gbe_suspend(pdev); | |
2581 | } | |
2582 | ||
2583 | static int pch_gbe_resume(struct device *device) | |
2584 | { | |
2585 | struct pci_dev *pdev = to_pci_dev(device); | |
2586 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2587 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2588 | struct pch_gbe_hw *hw = &adapter->hw; | |
2589 | u32 err; | |
2590 | ||
2591 | err = pci_enable_device(pdev); | |
2592 | if (err) { | |
2593 | pr_err("Cannot enable PCI device from suspend\n"); | |
2594 | return err; | |
2595 | } | |
2596 | pci_set_master(pdev); | |
2597 | pch_gbe_hal_power_up_phy(hw); | |
2598 | pch_gbe_reset(adapter); | |
2599 | /* Clear wake on lan control and status */ | |
2600 | pch_gbe_mac_set_wol_event(hw, 0); | |
2601 | ||
2602 | if (netif_running(netdev)) | |
2603 | pch_gbe_up(adapter); | |
2604 | netif_device_attach(netdev); | |
2605 | ||
2606 | return 0; | |
2607 | } | |
2608 | #endif /* CONFIG_PM */ | |
2609 | ||
2610 | static void pch_gbe_shutdown(struct pci_dev *pdev) | |
2611 | { | |
2612 | __pch_gbe_suspend(pdev); | |
2613 | if (system_state == SYSTEM_POWER_OFF) { | |
2614 | pci_wake_from_d3(pdev, true); | |
2615 | pci_set_power_state(pdev, PCI_D3hot); | |
2616 | } | |
2617 | } | |
2618 | ||
2619 | static void pch_gbe_remove(struct pci_dev *pdev) | |
2620 | { | |
2621 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2622 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | |
2623 | ||
2321f3b4 | 2624 | cancel_work_sync(&adapter->reset_task); |
77555ee7 MO |
2625 | unregister_netdev(netdev); |
2626 | ||
2627 | pch_gbe_hal_phy_hw_reset(&adapter->hw); | |
2628 | ||
2629 | kfree(adapter->tx_ring); | |
2630 | kfree(adapter->rx_ring); | |
2631 | ||
2632 | iounmap(adapter->hw.reg); | |
2633 | pci_release_regions(pdev); | |
2634 | free_netdev(netdev); | |
2635 | pci_disable_device(pdev); | |
2636 | } | |
2637 | ||
2638 | static int pch_gbe_probe(struct pci_dev *pdev, | |
2639 | const struct pci_device_id *pci_id) | |
2640 | { | |
2641 | struct net_device *netdev; | |
2642 | struct pch_gbe_adapter *adapter; | |
2643 | int ret; | |
2644 | ||
2645 | ret = pci_enable_device(pdev); | |
2646 | if (ret) | |
2647 | return ret; | |
2648 | ||
2649 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) | |
2650 | || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
2651 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2652 | if (ret) { | |
2653 | ret = pci_set_consistent_dma_mask(pdev, | |
2654 | DMA_BIT_MASK(32)); | |
2655 | if (ret) { | |
2656 | dev_err(&pdev->dev, "ERR: No usable DMA " | |
2657 | "configuration, aborting\n"); | |
2658 | goto err_disable_device; | |
2659 | } | |
2660 | } | |
2661 | } | |
2662 | ||
2663 | ret = pci_request_regions(pdev, KBUILD_MODNAME); | |
2664 | if (ret) { | |
2665 | dev_err(&pdev->dev, | |
2666 | "ERR: Can't reserve PCI I/O and memory resources\n"); | |
2667 | goto err_disable_device; | |
2668 | } | |
2669 | pci_set_master(pdev); | |
2670 | ||
2671 | netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter)); | |
2672 | if (!netdev) { | |
2673 | ret = -ENOMEM; | |
77555ee7 MO |
2674 | goto err_release_pci; |
2675 | } | |
2676 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
2677 | ||
2678 | pci_set_drvdata(pdev, netdev); | |
2679 | adapter = netdev_priv(netdev); | |
2680 | adapter->netdev = netdev; | |
2681 | adapter->pdev = pdev; | |
2682 | adapter->hw.back = adapter; | |
2683 | adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0); | |
2684 | if (!adapter->hw.reg) { | |
2685 | ret = -EIO; | |
2686 | dev_err(&pdev->dev, "Can't ioremap\n"); | |
2687 | goto err_free_netdev; | |
2688 | } | |
2689 | ||
1a0bdadb TS |
2690 | #ifdef CONFIG_PCH_PTP |
2691 | adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number, | |
2692 | PCI_DEVFN(12, 4)); | |
2693 | if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) { | |
2694 | pr_err("Bad ptp filter\n"); | |
2695 | return -EINVAL; | |
2696 | } | |
2697 | #endif | |
2698 | ||
77555ee7 MO |
2699 | netdev->netdev_ops = &pch_gbe_netdev_ops; |
2700 | netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD; | |
2701 | netif_napi_add(netdev, &adapter->napi, | |
2702 | pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT); | |
756a6b03 MM |
2703 | netdev->hw_features = NETIF_F_RXCSUM | |
2704 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | |
2705 | netdev->features = netdev->hw_features; | |
77555ee7 MO |
2706 | pch_gbe_set_ethtool_ops(netdev); |
2707 | ||
98200ec2 | 2708 | pch_gbe_mac_load_mac_addr(&adapter->hw); |
77555ee7 MO |
2709 | pch_gbe_mac_reset_hw(&adapter->hw); |
2710 | ||
2711 | /* setup the private structure */ | |
2712 | ret = pch_gbe_sw_init(adapter); | |
2713 | if (ret) | |
2714 | goto err_iounmap; | |
2715 | ||
2716 | /* Initialize PHY */ | |
2717 | ret = pch_gbe_init_phy(adapter); | |
2718 | if (ret) { | |
2719 | dev_err(&pdev->dev, "PHY initialize error\n"); | |
2720 | goto err_free_adapter; | |
2721 | } | |
2722 | pch_gbe_hal_get_bus_info(&adapter->hw); | |
2723 | ||
2724 | /* Read the MAC address. and store to the private data */ | |
2725 | ret = pch_gbe_hal_read_mac_addr(&adapter->hw); | |
2726 | if (ret) { | |
2727 | dev_err(&pdev->dev, "MAC address Read Error\n"); | |
2728 | goto err_free_adapter; | |
2729 | } | |
2730 | ||
2731 | memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); | |
2732 | if (!is_valid_ether_addr(netdev->dev_addr)) { | |
2b53d078 DH |
2733 | /* |
2734 | * If the MAC is invalid (or just missing), display a warning | |
2735 | * but do not abort setting up the device. pch_gbe_up will | |
2736 | * prevent the interface from being brought up until a valid MAC | |
2737 | * is set. | |
2738 | */ | |
2739 | dev_err(&pdev->dev, "Invalid MAC address, " | |
2740 | "interface disabled.\n"); | |
77555ee7 MO |
2741 | } |
2742 | setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog, | |
2743 | (unsigned long)adapter); | |
2744 | ||
2745 | INIT_WORK(&adapter->reset_task, pch_gbe_reset_task); | |
2746 | ||
2747 | pch_gbe_check_options(adapter); | |
2748 | ||
77555ee7 MO |
2749 | /* initialize the wol settings based on the eeprom settings */ |
2750 | adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING; | |
2751 | dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr); | |
2752 | ||
2753 | /* reset the hardware with the new settings */ | |
2754 | pch_gbe_reset(adapter); | |
2755 | ||
2756 | ret = register_netdev(netdev); | |
2757 | if (ret) | |
2758 | goto err_free_adapter; | |
2759 | /* tell the stack to leave us alone until pch_gbe_open() is called */ | |
2760 | netif_carrier_off(netdev); | |
2761 | netif_stop_queue(netdev); | |
2762 | ||
1a0bdadb | 2763 | dev_dbg(&pdev->dev, "PCH Network Connection\n"); |
77555ee7 MO |
2764 | |
2765 | device_set_wakeup_enable(&pdev->dev, 1); | |
2766 | return 0; | |
2767 | ||
2768 | err_free_adapter: | |
2769 | pch_gbe_hal_phy_hw_reset(&adapter->hw); | |
2770 | kfree(adapter->tx_ring); | |
2771 | kfree(adapter->rx_ring); | |
2772 | err_iounmap: | |
2773 | iounmap(adapter->hw.reg); | |
2774 | err_free_netdev: | |
2775 | free_netdev(netdev); | |
2776 | err_release_pci: | |
2777 | pci_release_regions(pdev); | |
2778 | err_disable_device: | |
2779 | pci_disable_device(pdev); | |
2780 | return ret; | |
2781 | } | |
2782 | ||
7fc44633 | 2783 | static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = { |
77555ee7 MO |
2784 | {.vendor = PCI_VENDOR_ID_INTEL, |
2785 | .device = PCI_DEVICE_ID_INTEL_IOH1_GBE, | |
2786 | .subvendor = PCI_ANY_ID, | |
2787 | .subdevice = PCI_ANY_ID, | |
2788 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), | |
2789 | .class_mask = (0xFFFF00) | |
2790 | }, | |
b0e6baf5 T |
2791 | {.vendor = PCI_VENDOR_ID_ROHM, |
2792 | .device = PCI_DEVICE_ID_ROHM_ML7223_GBE, | |
2793 | .subvendor = PCI_ANY_ID, | |
2794 | .subdevice = PCI_ANY_ID, | |
2795 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), | |
2796 | .class_mask = (0xFFFF00) | |
2797 | }, | |
7756332f TO |
2798 | {.vendor = PCI_VENDOR_ID_ROHM, |
2799 | .device = PCI_DEVICE_ID_ROHM_ML7831_GBE, | |
2800 | .subvendor = PCI_ANY_ID, | |
2801 | .subdevice = PCI_ANY_ID, | |
2802 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), | |
2803 | .class_mask = (0xFFFF00) | |
2804 | }, | |
77555ee7 MO |
2805 | /* required last entry */ |
2806 | {0} | |
2807 | }; | |
2808 | ||
2809 | #ifdef CONFIG_PM | |
2810 | static const struct dev_pm_ops pch_gbe_pm_ops = { | |
2811 | .suspend = pch_gbe_suspend, | |
2812 | .resume = pch_gbe_resume, | |
2813 | .freeze = pch_gbe_suspend, | |
2814 | .thaw = pch_gbe_resume, | |
2815 | .poweroff = pch_gbe_suspend, | |
2816 | .restore = pch_gbe_resume, | |
2817 | }; | |
2818 | #endif | |
2819 | ||
2820 | static struct pci_error_handlers pch_gbe_err_handler = { | |
2821 | .error_detected = pch_gbe_io_error_detected, | |
2822 | .slot_reset = pch_gbe_io_slot_reset, | |
2823 | .resume = pch_gbe_io_resume | |
2824 | }; | |
2825 | ||
f7594d42 | 2826 | static struct pci_driver pch_gbe_driver = { |
77555ee7 MO |
2827 | .name = KBUILD_MODNAME, |
2828 | .id_table = pch_gbe_pcidev_id, | |
2829 | .probe = pch_gbe_probe, | |
2830 | .remove = pch_gbe_remove, | |
aa338601 | 2831 | #ifdef CONFIG_PM |
77555ee7 MO |
2832 | .driver.pm = &pch_gbe_pm_ops, |
2833 | #endif | |
2834 | .shutdown = pch_gbe_shutdown, | |
2835 | .err_handler = &pch_gbe_err_handler | |
2836 | }; | |
2837 | ||
2838 | ||
2839 | static int __init pch_gbe_init_module(void) | |
2840 | { | |
2841 | int ret; | |
2842 | ||
f7594d42 | 2843 | ret = pci_register_driver(&pch_gbe_driver); |
77555ee7 MO |
2844 | if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) { |
2845 | if (copybreak == 0) { | |
2846 | pr_info("copybreak disabled\n"); | |
2847 | } else { | |
2848 | pr_info("copybreak enabled for packets <= %u bytes\n", | |
2849 | copybreak); | |
2850 | } | |
2851 | } | |
2852 | return ret; | |
2853 | } | |
2854 | ||
2855 | static void __exit pch_gbe_exit_module(void) | |
2856 | { | |
f7594d42 | 2857 | pci_unregister_driver(&pch_gbe_driver); |
77555ee7 MO |
2858 | } |
2859 | ||
2860 | module_init(pch_gbe_init_module); | |
2861 | module_exit(pch_gbe_exit_module); | |
2862 | ||
a1dcfcb7 | 2863 | MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver"); |
1a0bdadb | 2864 | MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>"); |
77555ee7 MO |
2865 | MODULE_LICENSE("GPL"); |
2866 | MODULE_VERSION(DRV_VERSION); | |
2867 | MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id); | |
2868 | ||
2869 | module_param(copybreak, uint, 0644); | |
2870 | MODULE_PARM_DESC(copybreak, | |
2871 | "Maximum size of packet that is copied to a new buffer on receive"); | |
2872 | ||
2873 | /* pch_gbe_main.c */ |