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drivers/net/ethernet: Fix (nearly-)kernel-doc comments for various functions
[deliverable/linux.git] / drivers / net / ethernet / oki-semi / pch_gbe / pch_gbe_main.c
CommitLineData
77555ee7
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
1a0bdadb 3 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
77555ee7
MO		 4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include "pch_gbe.h"
22#include "pch_gbe_api.h"
9d9779e7 23#include <linux/module.h>
1a0bdadb
TS		 24#ifdef CONFIG_PCH_PTP
25#include <linux/net_tstamp.h>
26#include <linux/ptp_classify.h>
27#endif
77555ee7
MO		 28
29#define DRV_VERSION "1.00"
30const char pch_driver_version[] = DRV_VERSION;
31
32#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
33#define PCH_GBE_MAR_ENTRIES 16
34#define PCH_GBE_SHORT_PKT 64
35#define DSC_INIT16 0xC000
36#define PCH_GBE_DMA_ALIGN 0
ac096642 37#define PCH_GBE_DMA_PADDING 2
77555ee7
MO		 38#define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
39#define PCH_GBE_COPYBREAK_DEFAULT 256
40#define PCH_GBE_PCI_BAR 1
124d770a 41#define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
77555ee7 42
b0e6baf5
T		 43/* Macros for ML7223 */
44#define PCI_VENDOR_ID_ROHM 0x10db
45#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
46
7756332f
TO		 47/* Macros for ML7831 */
48#define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
49
77555ee7
MO		 50#define PCH_GBE_TX_WEIGHT 64
51#define PCH_GBE_RX_WEIGHT 64
52#define PCH_GBE_RX_BUFFER_WRITE 16
53
54/* Initialize the wake-on-LAN settings */
55#define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
56
57#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
58 PCH_GBE_CHIP_TYPE_INTERNAL | \
ce3dad0f 59 PCH_GBE_RGMII_MODE_RGMII \
77555ee7
MO		 60 )
61
62/* Ethertype field values */
124d770a 63#define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
77555ee7
MO		 64#define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
65#define PCH_GBE_FRAME_SIZE_2048 2048
66#define PCH_GBE_FRAME_SIZE_4096 4096
67#define PCH_GBE_FRAME_SIZE_8192 8192
68
69#define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
70#define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
71#define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
72#define PCH_GBE_DESC_UNUSED(R) \
73 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
74 (R)->next_to_clean - (R)->next_to_use - 1)
75
76/* Pause packet value */
77#define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
78#define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
79#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
80#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
81
77555ee7
MO		 82
83/* This defines the bits that are set in the Interrupt Mask
84 * Set/Read Register. Each bit is documented below:
85 * o RXT0 = Receiver Timer Interrupt (ring 0)
86 * o TXDW = Transmit Descriptor Written Back
87 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
88 * o RXSEQ = Receive Sequence Error
89 * o LSC = Link Status Change
90 */
91#define PCH_GBE_INT_ENABLE_MASK ( \
92 PCH_GBE_INT_RX_DMA_CMPLT | \
93 PCH_GBE_INT_RX_DSC_EMP | \
124d770a 94 PCH_GBE_INT_RX_FIFO_ERR | \
77555ee7
MO		 95 PCH_GBE_INT_WOL_DET | \
96 PCH_GBE_INT_TX_CMPLT \
97 )
98
124d770a 99#define PCH_GBE_INT_DISABLE_ALL 0
77555ee7 100
1a0bdadb
TS		 101#ifdef CONFIG_PCH_PTP
102/* Macros for ieee1588 */
1a0bdadb
TS		 103/* 0x40 Time Synchronization Channel Control Register Bits */
104#define MASTER_MODE (1<<0)
93c8acb5 105#define SLAVE_MODE (0)
1a0bdadb 106#define V2_MODE (1<<31)
93c8acb5 107#define CAP_MODE0 (0)
1a0bdadb
TS		 108#define CAP_MODE2 (1<<17)
109
110/* 0x44 Time Synchronization Channel Event Register Bits */
111#define TX_SNAPSHOT_LOCKED (1<<0)
112#define RX_SNAPSHOT_LOCKED (1<<1)
358dfb6d
TS		 113
114#define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
115#define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
1a0bdadb
TS		 116#endif
117
77555ee7
MO		 118static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
119
191cc687 120static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
121static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
122 int data);
d344c4f3 123static void pch_gbe_set_multi(struct net_device *netdev);
98200ec2 124
1a0bdadb
TS		 125#ifdef CONFIG_PCH_PTP
126static struct sock_filter ptp_filter[] = {
127 PTP_FILTER
128};
129
130static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
131{
132 u8 *data = skb->data;
133 unsigned int offset;
134 u16 *hi, *id;
135 u32 lo;
136
32127a0a 137 if (sk_run_filter(skb, ptp_filter) == PTP_CLASS_NONE)
1a0bdadb 138 return 0;
1a0bdadb
TS		 139
140 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
141
142 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
143 return 0;
144
145 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
146 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
147
148 memcpy(&lo, &hi[1], sizeof(lo));
149
150 return (uid_hi == *hi &&
151 uid_lo == lo &&
152 seqid == *id);
153}
154
93c8acb5
TS		 155static void
156pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
1a0bdadb
TS		 157{
158 struct skb_shared_hwtstamps *shhwtstamps;
159 struct pci_dev *pdev;
160 u64 ns;
161 u32 hi, lo, val;
162 u16 uid, seq;
163
164 if (!adapter->hwts_rx_en)
165 return;
166
167 /* Get ieee1588's dev information */
168 pdev = adapter->ptp_pdev;
169
170 val = pch_ch_event_read(pdev);
171
172 if (!(val & RX_SNAPSHOT_LOCKED))
173 return;
174
175 lo = pch_src_uuid_lo_read(pdev);
176 hi = pch_src_uuid_hi_read(pdev);
177
178 uid = hi & 0xffff;
179 seq = (hi >> 16) & 0xffff;
180
181 if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
182 goto out;
183
184 ns = pch_rx_snap_read(pdev);
1a0bdadb
TS		 185
186 shhwtstamps = skb_hwtstamps(skb);
187 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
188 shhwtstamps->hwtstamp = ns_to_ktime(ns);
189out:
190 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
191}
192
93c8acb5
TS		 193static void
194pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
1a0bdadb
TS		 195{
196 struct skb_shared_hwtstamps shhwtstamps;
197 struct pci_dev *pdev;
198 struct skb_shared_info *shtx;
199 u64 ns;
200 u32 cnt, val;
201
202 shtx = skb_shinfo(skb);
5481c8cd 203 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
1a0bdadb
TS		 204 return;
205
5481c8cd
TS		 206 shtx->tx_flags |= SKBTX_IN_PROGRESS;
207
1a0bdadb
TS		 208 /* Get ieee1588's dev information */
209 pdev = adapter->ptp_pdev;
210
211 /*
212 * This really stinks, but we have to poll for the Tx time stamp.
1a0bdadb
TS		 213 */
214 for (cnt = 0; cnt < 100; cnt++) {
215 val = pch_ch_event_read(pdev);
216 if (val & TX_SNAPSHOT_LOCKED)
217 break;
218 udelay(1);
219 }
220 if (!(val & TX_SNAPSHOT_LOCKED)) {
221 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
222 return;
223 }
224
225 ns = pch_tx_snap_read(pdev);
1a0bdadb
TS		 226
227 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
228 shhwtstamps.hwtstamp = ns_to_ktime(ns);
229 skb_tstamp_tx(skb, &shhwtstamps);
230
231 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
232}
233
234static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
235{
236 struct hwtstamp_config cfg;
237 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
238 struct pci_dev *pdev;
358dfb6d 239 u8 station[20];
1a0bdadb
TS		 240
241 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
242 return -EFAULT;
243
244 if (cfg.flags) /* reserved for future extensions */
245 return -EINVAL;
246
247 /* Get ieee1588's dev information */
248 pdev = adapter->ptp_pdev;
249
250 switch (cfg.tx_type) {
251 case HWTSTAMP_TX_OFF:
252 adapter->hwts_tx_en = 0;
253 break;
254 case HWTSTAMP_TX_ON:
255 adapter->hwts_tx_en = 1;
256 break;
257 default:
258 return -ERANGE;
259 }
260
261 switch (cfg.rx_filter) {
262 case HWTSTAMP_FILTER_NONE:
263 adapter->hwts_rx_en = 0;
264 break;
265 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
266 adapter->hwts_rx_en = 0;
93c8acb5 267 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
1a0bdadb
TS		 268 break;
269 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
270 adapter->hwts_rx_en = 1;
93c8acb5 271 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
1a0bdadb 272 break;
358dfb6d
TS		 273 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
274 adapter->hwts_rx_en = 1;
275 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
276 strcpy(station, PTP_L4_MULTICAST_SA);
277 pch_set_station_address(station, pdev);
278 break;
279 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1a0bdadb 280 adapter->hwts_rx_en = 1;
93c8acb5 281 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
358dfb6d
TS		 282 strcpy(station, PTP_L2_MULTICAST_SA);
283 pch_set_station_address(station, pdev);
1a0bdadb
TS		 284 break;
285 default:
286 return -ERANGE;
287 }
288
289 /* Clear out any old time stamps. */
290 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
291
292 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
293}
294#endif
295
98200ec2
TO		 296inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
297{
298 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
299}
300
77555ee7
MO		 301/**
302 * pch_gbe_mac_read_mac_addr - Read MAC address
303 * @hw: Pointer to the HW structure
49ce9c2c 304 * Returns:
77555ee7
MO		 305 * 0: Successful.
306 */
307s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
308{
309 u32 adr1a, adr1b;
310
311 adr1a = ioread32(&hw->reg->mac_adr[0].high);
312 adr1b = ioread32(&hw->reg->mac_adr[0].low);
313
314 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
315 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
316 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
317 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
318 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
319 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
320
321 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
322 return 0;
323}
324
325/**
326 * pch_gbe_wait_clr_bit - Wait to clear a bit
327 * @reg: Pointer of register
328 * @busy: Busy bit
329 */
191cc687 330static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
77555ee7
MO		 331{
332 u32 tmp;
333 /* wait busy */
334 tmp = 1000;
335 while ((ioread32(reg) & bit) && --tmp)
336 cpu_relax();
337 if (!tmp)
338 pr_err("Error: busy bit is not cleared\n");
339}
124d770a
TO		 340
341/**
342 * pch_gbe_wait_clr_bit_irq - Wait to clear a bit for interrupt context
343 * @reg: Pointer of register
344 * @busy: Busy bit
345 */
346static int pch_gbe_wait_clr_bit_irq(void *reg, u32 bit)
347{
348 u32 tmp;
349 int ret = -1;
350 /* wait busy */
351 tmp = 20;
352 while ((ioread32(reg) & bit) && --tmp)
353 udelay(5);
354 if (!tmp)
355 pr_err("Error: busy bit is not cleared\n");
356 else
357 ret = 0;
358 return ret;
359}
360
77555ee7
MO		 361/**
362 * pch_gbe_mac_mar_set - Set MAC address register
363 * @hw: Pointer to the HW structure
364 * @addr: Pointer to the MAC address
365 * @index: MAC address array register
366 */
191cc687 367static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
77555ee7
MO		 368{
369 u32 mar_low, mar_high, adrmask;
370
371 pr_debug("index : 0x%x\n", index);
372
373 /*
374 * HW expects these in little endian so we reverse the byte order
375 * from network order (big endian) to little endian
376 */
377 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
378 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
379 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
380 /* Stop the MAC Address of index. */
381 adrmask = ioread32(&hw->reg->ADDR_MASK);
382 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
383 /* wait busy */
384 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
385 /* Set the MAC address to the MAC address 1A/1B register */
386 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
387 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
388 /* Start the MAC address of index */
389 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
390 /* wait busy */
391 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
392}
393
394/**
395 * pch_gbe_mac_reset_hw - Reset hardware
396 * @hw: Pointer to the HW structure
397 */
191cc687 398static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
77555ee7
MO		 399{
400 /* Read the MAC address. and store to the private data */
401 pch_gbe_mac_read_mac_addr(hw);
402 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
403#ifdef PCH_GBE_MAC_IFOP_RGMII
404 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
405#endif
406 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
eefc48b0 407 /* Setup the receive addresses */
77555ee7
MO		 408 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
409 return;
410}
411
124d770a
TO		 412static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw)
413{
eefc48b0 414 /* Read the MAC addresses. and store to the private data */
124d770a
TO		 415 pch_gbe_mac_read_mac_addr(hw);
416 iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET);
417 pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST);
eefc48b0 418 /* Setup the MAC addresses */
124d770a
TO		 419 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
420 return;
421}
422
77555ee7
MO		 423/**
424 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
425 * @hw: Pointer to the HW structure
426 * @mar_count: Receive address registers
427 */
191cc687 428static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
77555ee7
MO		 429{
430 u32 i;
431
432 /* Setup the receive address */
433 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
434
435 /* Zero out the other receive addresses */
436 for (i = 1; i < mar_count; i++) {
437 iowrite32(0, &hw->reg->mac_adr[i].high);
438 iowrite32(0, &hw->reg->mac_adr[i].low);
439 }
440 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
441 /* wait busy */
442 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
443}
444
445
446/**
447 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
448 * @hw: Pointer to the HW structure
449 * @mc_addr_list: Array of multicast addresses to program
450 * @mc_addr_count: Number of multicast addresses to program
451 * @mar_used_count: The first MAC Address register free to program
452 * @mar_total_num: Total number of supported MAC Address Registers
453 */
191cc687 454static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
455 u8 *mc_addr_list, u32 mc_addr_count,
456 u32 mar_used_count, u32 mar_total_num)
77555ee7
MO		 457{
458 u32 i, adrmask;
459
460 /* Load the first set of multicast addresses into the exact
461 * filters (RAR). If there are not enough to fill the RAR
462 * array, clear the filters.
463 */
464 for (i = mar_used_count; i < mar_total_num; i++) {
465 if (mc_addr_count) {
466 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
467 mc_addr_count--;
d89bdff1 468 mc_addr_list += ETH_ALEN;
77555ee7
MO		 469 } else {
470 /* Clear MAC address mask */
471 adrmask = ioread32(&hw->reg->ADDR_MASK);
472 iowrite32((adrmask | (0x0001 << i)),
473 &hw->reg->ADDR_MASK);
474 /* wait busy */
475 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
476 /* Clear MAC address */
477 iowrite32(0, &hw->reg->mac_adr[i].high);
478 iowrite32(0, &hw->reg->mac_adr[i].low);
479 }
480 }
481}
482
483/**
484 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
485 * @hw: Pointer to the HW structure
49ce9c2c 486 * Returns:
77555ee7
MO		 487 * 0: Successful.
488 * Negative value: Failed.
489 */
490s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
491{
492 struct pch_gbe_mac_info *mac = &hw->mac;
493 u32 rx_fctrl;
494
495 pr_debug("mac->fc = %u\n", mac->fc);
496
497 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
498
499 switch (mac->fc) {
500 case PCH_GBE_FC_NONE:
501 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
502 mac->tx_fc_enable = false;
503 break;
504 case PCH_GBE_FC_RX_PAUSE:
505 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
506 mac->tx_fc_enable = false;
507 break;
508 case PCH_GBE_FC_TX_PAUSE:
509 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
510 mac->tx_fc_enable = true;
511 break;
512 case PCH_GBE_FC_FULL:
513 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
514 mac->tx_fc_enable = true;
515 break;
516 default:
517 pr_err("Flow control param set incorrectly\n");
518 return -EINVAL;
519 }
520 if (mac->link_duplex == DUPLEX_HALF)
521 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
522 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
523 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
524 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
525 return 0;
526}
527
528/**
529 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
530 * @hw: Pointer to the HW structure
531 * @wu_evt: Wake up event
532 */
191cc687 533static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
77555ee7
MO		 534{
535 u32 addr_mask;
536
537 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
538 wu_evt, ioread32(&hw->reg->ADDR_MASK));
539
540 if (wu_evt) {
541 /* Set Wake-On-Lan address mask */
542 addr_mask = ioread32(&hw->reg->ADDR_MASK);
543 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
544 /* wait busy */
545 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
546 iowrite32(0, &hw->reg->WOL_ST);
547 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
548 iowrite32(0x02, &hw->reg->TCPIP_ACC);
549 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
550 } else {
551 iowrite32(0, &hw->reg->WOL_CTRL);
552 iowrite32(0, &hw->reg->WOL_ST);
553 }
554 return;
555}
556
557/**
558 * pch_gbe_mac_ctrl_miim - Control MIIM interface
559 * @hw: Pointer to the HW structure
560 * @addr: Address of PHY
561 * @dir: Operetion. (Write or Read)
562 * @reg: Access register of PHY
563 * @data: Write data.
564 *
565 * Returns: Read date.
566 */
567u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
568 u16 data)
569{
570 u32 data_out = 0;
571 unsigned int i;
572 unsigned long flags;
573
574 spin_lock_irqsave(&hw->miim_lock, flags);
575
576 for (i = 100; i; --i) {
577 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
578 break;
579 udelay(20);
580 }
581 if (i == 0) {
582 pr_err("pch-gbe.miim won't go Ready\n");
583 spin_unlock_irqrestore(&hw->miim_lock, flags);
584 return 0; /* No way to indicate timeout error */
585 }
586 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
587 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
588 dir | data), &hw->reg->MIIM);
589 for (i = 0; i < 100; i++) {
590 udelay(20);
591 data_out = ioread32(&hw->reg->MIIM);
592 if ((data_out & PCH_GBE_MIIM_OPER_READY))
593 break;
594 }
595 spin_unlock_irqrestore(&hw->miim_lock, flags);
596
597 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
598 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
599 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
600 return (u16) data_out;
601}
602
603/**
604 * pch_gbe_mac_set_pause_packet - Set pause packet
605 * @hw: Pointer to the HW structure
606 */
191cc687 607static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
77555ee7
MO		 608{
609 unsigned long tmp2, tmp3;
610
611 /* Set Pause packet */
612 tmp2 = hw->mac.addr[1];
613 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
614 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
615
616 tmp3 = hw->mac.addr[5];
617 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
618 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
619 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
620
621 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
622 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
623 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
624 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
625 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
626
627 /* Transmit Pause Packet */
628 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
629
630 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
631 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
632 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
633 ioread32(&hw->reg->PAUSE_PKT5));
634
635 return;
636}
637
638
639/**
640 * pch_gbe_alloc_queues - Allocate memory for all rings
641 * @adapter: Board private structure to initialize
49ce9c2c 642 * Returns:
77555ee7
MO		 643 * 0: Successfully
644 * Negative value: Failed
645 */
646static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
647{
3ab77bf2 648 adapter->tx_ring = kzalloc(sizeof(*adapter->tx_ring), GFP_KERNEL);
77555ee7
MO		 649 if (!adapter->tx_ring)
650 return -ENOMEM;
3ab77bf2
ED		 651
652 adapter->rx_ring = kzalloc(sizeof(*adapter->rx_ring), GFP_KERNEL);
77555ee7
MO		 653 if (!adapter->rx_ring) {
654 kfree(adapter->tx_ring);
655 return -ENOMEM;
656 }
657 return 0;
658}
659
660/**
661 * pch_gbe_init_stats - Initialize status
662 * @adapter: Board private structure to initialize
663 */
664static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
665{
666 memset(&adapter->stats, 0, sizeof(adapter->stats));
667 return;
668}
669
670/**
671 * pch_gbe_init_phy - Initialize PHY
672 * @adapter: Board private structure to initialize
49ce9c2c 673 * Returns:
77555ee7
MO		 674 * 0: Successfully
675 * Negative value: Failed
676 */
677static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
678{
679 struct net_device *netdev = adapter->netdev;
680 u32 addr;
681 u16 bmcr, stat;
682
683 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
684 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
685 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
686 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
687 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
688 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
689 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
690 break;
691 }
692 adapter->hw.phy.addr = adapter->mii.phy_id;
693 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
694 if (addr == 32)
695 return -EAGAIN;
696 /* Selected the phy and isolate the rest */
697 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
698 if (addr != adapter->mii.phy_id) {
699 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
700 BMCR_ISOLATE);
701 } else {
702 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
703 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
704 bmcr & ~BMCR_ISOLATE);
705 }
706 }
707
708 /* MII setup */
709 adapter->mii.phy_id_mask = 0x1F;
710 adapter->mii.reg_num_mask = 0x1F;
711 adapter->mii.dev = adapter->netdev;
712 adapter->mii.mdio_read = pch_gbe_mdio_read;
713 adapter->mii.mdio_write = pch_gbe_mdio_write;
714 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
715 return 0;
716}
717
718/**
719 * pch_gbe_mdio_read - The read function for mii
720 * @netdev: Network interface device structure
721 * @addr: Phy ID
722 * @reg: Access location
49ce9c2c 723 * Returns:
77555ee7
MO		 724 * 0: Successfully
725 * Negative value: Failed
726 */
191cc687 727static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
77555ee7
MO		 728{
729 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
730 struct pch_gbe_hw *hw = &adapter->hw;
731
732 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
733 (u16) 0);
734}
735
736/**
737 * pch_gbe_mdio_write - The write function for mii
738 * @netdev: Network interface device structure
739 * @addr: Phy ID (not used)
740 * @reg: Access location
741 * @data: Write data
742 */
191cc687 743static void pch_gbe_mdio_write(struct net_device *netdev,
744 int addr, int reg, int data)
77555ee7
MO		 745{
746 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
747 struct pch_gbe_hw *hw = &adapter->hw;
748
749 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
750}
751
752/**
753 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
754 * @work: Pointer of board private structure
755 */
756static void pch_gbe_reset_task(struct work_struct *work)
757{
758 struct pch_gbe_adapter *adapter;
759 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
760
75d1a752 761 rtnl_lock();
77555ee7 762 pch_gbe_reinit_locked(adapter);
75d1a752 763 rtnl_unlock();
77555ee7
MO		 764}
765
766/**
767 * pch_gbe_reinit_locked- Re-initialization
768 * @adapter: Board private structure
769 */
770void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
771{
75d1a752
TO		 772 pch_gbe_down(adapter);
773 pch_gbe_up(adapter);
77555ee7
MO		 774}
775
776/**
777 * pch_gbe_reset - Reset GbE
778 * @adapter: Board private structure
779 */
780void pch_gbe_reset(struct pch_gbe_adapter *adapter)
781{
782 pch_gbe_mac_reset_hw(&adapter->hw);
d344c4f3
RL		 783 /* reprogram multicast address register after reset */
784 pch_gbe_set_multi(adapter->netdev);
77555ee7
MO		 785 /* Setup the receive address. */
786 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
787 if (pch_gbe_hal_init_hw(&adapter->hw))
788 pr_err("Hardware Error\n");
789}
790
791/**
792 * pch_gbe_free_irq - Free an interrupt
793 * @adapter: Board private structure
794 */
795static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
796{
797 struct net_device *netdev = adapter->netdev;
798
799 free_irq(adapter->pdev->irq, netdev);
800 if (adapter->have_msi) {
801 pci_disable_msi(adapter->pdev);
802 pr_debug("call pci_disable_msi\n");
803 }
804}
805
806/**
807 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
808 * @adapter: Board private structure
809 */
810static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
811{
812 struct pch_gbe_hw *hw = &adapter->hw;
813
814 atomic_inc(&adapter->irq_sem);
815 iowrite32(0, &hw->reg->INT_EN);
816 ioread32(&hw->reg->INT_ST);
817 synchronize_irq(adapter->pdev->irq);
818
819 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
820}
821
822/**
823 * pch_gbe_irq_enable - Enable default interrupt generation settings
824 * @adapter: Board private structure
825 */
826static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
827{
828 struct pch_gbe_hw *hw = &adapter->hw;
829
830 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
831 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
832 ioread32(&hw->reg->INT_ST);
833 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
834}
835
836
837
838/**
839 * pch_gbe_setup_tctl - configure the Transmit control registers
840 * @adapter: Board private structure
841 */
842static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
843{
844 struct pch_gbe_hw *hw = &adapter->hw;
845 u32 tx_mode, tcpip;
846
847 tx_mode = PCH_GBE_TM_LONG_PKT |
848 PCH_GBE_TM_ST_AND_FD |
849 PCH_GBE_TM_SHORT_PKT |
850 PCH_GBE_TM_TH_TX_STRT_8 |
851 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
852
853 iowrite32(tx_mode, &hw->reg->TX_MODE);
854
855 tcpip = ioread32(&hw->reg->TCPIP_ACC);
856 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
857 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
858 return;
859}
860
861/**
862 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
863 * @adapter: Board private structure
864 */
865static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
866{
867 struct pch_gbe_hw *hw = &adapter->hw;
868 u32 tdba, tdlen, dctrl;
869
870 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
871 (unsigned long long)adapter->tx_ring->dma,
872 adapter->tx_ring->size);
873
874 /* Setup the HW Tx Head and Tail descriptor pointers */
875 tdba = adapter->tx_ring->dma;
876 tdlen = adapter->tx_ring->size - 0x10;
877 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
878 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
879 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
880
881 /* Enables Transmission DMA */
882 dctrl = ioread32(&hw->reg->DMA_CTRL);
883 dctrl |= PCH_GBE_TX_DMA_EN;
884 iowrite32(dctrl, &hw->reg->DMA_CTRL);
885}
886
887/**
888 * pch_gbe_setup_rctl - Configure the receive control registers
889 * @adapter: Board private structure
890 */
891static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
892{
893 struct pch_gbe_hw *hw = &adapter->hw;
894 u32 rx_mode, tcpip;
895
896 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
897 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
898
899 iowrite32(rx_mode, &hw->reg->RX_MODE);
900
901 tcpip = ioread32(&hw->reg->TCPIP_ACC);
902
124d770a
TO		 903 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
904 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
77555ee7
MO		 905 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
906 return;
907}
908
909/**
910 * pch_gbe_configure_rx - Configure Receive Unit after Reset
911 * @adapter: Board private structure
912 */
913static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
914{
915 struct pch_gbe_hw *hw = &adapter->hw;
916 u32 rdba, rdlen, rctl, rxdma;
917
918 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
919 (unsigned long long)adapter->rx_ring->dma,
920 adapter->rx_ring->size);
921
922 pch_gbe_mac_force_mac_fc(hw);
923
924 /* Disables Receive MAC */
925 rctl = ioread32(&hw->reg->MAC_RX_EN);
926 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
927
928 /* Disables Receive DMA */
929 rxdma = ioread32(&hw->reg->DMA_CTRL);
930 rxdma &= ~PCH_GBE_RX_DMA_EN;
931 iowrite32(rxdma, &hw->reg->DMA_CTRL);
932
933 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
934 ioread32(&hw->reg->MAC_RX_EN),
935 ioread32(&hw->reg->DMA_CTRL));
936
937 /* Setup the HW Rx Head and Tail Descriptor Pointers and
938 * the Base and Length of the Rx Descriptor Ring */
939 rdba = adapter->rx_ring->dma;
940 rdlen = adapter->rx_ring->size - 0x10;
941 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
942 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
943 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
77555ee7
MO		 944}
945
946/**
947 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
948 * @adapter: Board private structure
949 * @buffer_info: Buffer information structure
950 */
951static void pch_gbe_unmap_and_free_tx_resource(
952 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
953{
954 if (buffer_info->mapped) {
955 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
956 buffer_info->length, DMA_TO_DEVICE);
957 buffer_info->mapped = false;
958 }
959 if (buffer_info->skb) {
960 dev_kfree_skb_any(buffer_info->skb);
961 buffer_info->skb = NULL;
962 }
963}
964
965/**
966 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
967 * @adapter: Board private structure
968 * @buffer_info: Buffer information structure
969 */
970static void pch_gbe_unmap_and_free_rx_resource(
971 struct pch_gbe_adapter *adapter,
972 struct pch_gbe_buffer *buffer_info)
973{
974 if (buffer_info->mapped) {
975 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
976 buffer_info->length, DMA_FROM_DEVICE);
977 buffer_info->mapped = false;
978 }
979 if (buffer_info->skb) {
980 dev_kfree_skb_any(buffer_info->skb);
981 buffer_info->skb = NULL;
982 }
983}
984
985/**
986 * pch_gbe_clean_tx_ring - Free Tx Buffers
987 * @adapter: Board private structure
988 * @tx_ring: Ring to be cleaned
989 */
990static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
991 struct pch_gbe_tx_ring *tx_ring)
992{
993 struct pch_gbe_hw *hw = &adapter->hw;
994 struct pch_gbe_buffer *buffer_info;
995 unsigned long size;
996 unsigned int i;
997
998 /* Free all the Tx ring sk_buffs */
999 for (i = 0; i < tx_ring->count; i++) {
1000 buffer_info = &tx_ring->buffer_info[i];
1001 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
1002 }
1003 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
1004
1005 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1006 memset(tx_ring->buffer_info, 0, size);
1007
1008 /* Zero out the descriptor ring */
1009 memset(tx_ring->desc, 0, tx_ring->size);
1010 tx_ring->next_to_use = 0;
1011 tx_ring->next_to_clean = 0;
1012 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
1013 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
1014}
1015
1016/**
1017 * pch_gbe_clean_rx_ring - Free Rx Buffers
1018 * @adapter: Board private structure
1019 * @rx_ring: Ring to free buffers from
1020 */
1021static void
1022pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1023 struct pch_gbe_rx_ring *rx_ring)
1024{
1025 struct pch_gbe_hw *hw = &adapter->hw;
1026 struct pch_gbe_buffer *buffer_info;
1027 unsigned long size;
1028 unsigned int i;
1029
1030 /* Free all the Rx ring sk_buffs */
1031 for (i = 0; i < rx_ring->count; i++) {
1032 buffer_info = &rx_ring->buffer_info[i];
1033 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1034 }
1035 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1036 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1037 memset(rx_ring->buffer_info, 0, size);
1038
1039 /* Zero out the descriptor ring */
1040 memset(rx_ring->desc, 0, rx_ring->size);
1041 rx_ring->next_to_clean = 0;
1042 rx_ring->next_to_use = 0;
1043 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1044 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1045}
1046
1047static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1048 u16 duplex)
1049{
1050 struct pch_gbe_hw *hw = &adapter->hw;
1051 unsigned long rgmii = 0;
1052
1053 /* Set the RGMII control. */
1054#ifdef PCH_GBE_MAC_IFOP_RGMII
1055 switch (speed) {
1056 case SPEED_10:
1057 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1058 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1059 break;
1060 case SPEED_100:
1061 rgmii = (PCH_GBE_RGMII_RATE_25M |
1062 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1063 break;
1064 case SPEED_1000:
1065 rgmii = (PCH_GBE_RGMII_RATE_125M |
1066 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1067 break;
1068 }
1069 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1070#else /* GMII */
1071 rgmii = 0;
1072 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1073#endif
1074}
1075static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1076 u16 duplex)
1077{
1078 struct net_device *netdev = adapter->netdev;
1079 struct pch_gbe_hw *hw = &adapter->hw;
1080 unsigned long mode = 0;
1081
1082 /* Set the communication mode */
1083 switch (speed) {
1084 case SPEED_10:
1085 mode = PCH_GBE_MODE_MII_ETHER;
1086 netdev->tx_queue_len = 10;
1087 break;
1088 case SPEED_100:
1089 mode = PCH_GBE_MODE_MII_ETHER;
1090 netdev->tx_queue_len = 100;
1091 break;
1092 case SPEED_1000:
1093 mode = PCH_GBE_MODE_GMII_ETHER;
1094 break;
1095 }
1096 if (duplex == DUPLEX_FULL)
1097 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1098 else
1099 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1100 iowrite32(mode, &hw->reg->MODE);
1101}
1102
1103/**
1104 * pch_gbe_watchdog - Watchdog process
1105 * @data: Board private structure
1106 */
1107static void pch_gbe_watchdog(unsigned long data)
1108{
1109 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1110 struct net_device *netdev = adapter->netdev;
1111 struct pch_gbe_hw *hw = &adapter->hw;
77555ee7
MO		 1112
1113 pr_debug("right now = %ld\n", jiffies);
1114
1115 pch_gbe_update_stats(adapter);
1116 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
8ae6daca 1117 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
77555ee7
MO		 1118 netdev->tx_queue_len = adapter->tx_queue_len;
1119 /* mii library handles link maintenance tasks */
1120 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1121 pr_err("ethtool get setting Error\n");
1122 mod_timer(&adapter->watchdog_timer,
1123 round_jiffies(jiffies +
1124 PCH_GBE_WATCHDOG_PERIOD));
1125 return;
1126 }
8ae6daca 1127 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
77555ee7
MO		 1128 hw->mac.link_duplex = cmd.duplex;
1129 /* Set the RGMII control. */
1130 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1131 hw->mac.link_duplex);
1132 /* Set the communication mode */
1133 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1134 hw->mac.link_duplex);
1135 netdev_dbg(netdev,
1136 "Link is Up %d Mbps %s-Duplex\n",
8ae6daca 1137 hw->mac.link_speed,
77555ee7
MO		 1138 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1139 netif_carrier_on(netdev);
1140 netif_wake_queue(netdev);
1141 } else if ((!mii_link_ok(&adapter->mii)) &&
1142 (netif_carrier_ok(netdev))) {
1143 netdev_dbg(netdev, "NIC Link is Down\n");
1144 hw->mac.link_speed = SPEED_10;
1145 hw->mac.link_duplex = DUPLEX_HALF;
1146 netif_carrier_off(netdev);
1147 netif_stop_queue(netdev);
1148 }
1149 mod_timer(&adapter->watchdog_timer,
1150 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1151}
1152
1153/**
1154 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1155 * @adapter: Board private structure
1156 * @tx_ring: Tx descriptor ring structure
1157 * @skb: Sockt buffer structure
1158 */
1159static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1160 struct pch_gbe_tx_ring *tx_ring,
1161 struct sk_buff *skb)
1162{
1163 struct pch_gbe_hw *hw = &adapter->hw;
1164 struct pch_gbe_tx_desc *tx_desc;
1165 struct pch_gbe_buffer *buffer_info;
1166 struct sk_buff *tmp_skb;
1167 unsigned int frame_ctrl;
1168 unsigned int ring_num;
77555ee7
MO		 1169
1170 /*-- Set frame control --*/
1171 frame_ctrl = 0;
1172 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1173 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
756a6b03 1174 if (skb->ip_summed == CHECKSUM_NONE)
77555ee7
MO		 1175 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1176
1177 /* Performs checksum processing */
1178 /*
1179 * It is because the hardware accelerator does not support a checksum,
1180 * when the received data size is less than 64 bytes.
1181 */
756a6b03 1182 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
77555ee7
MO		 1183 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1184 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1185 if (skb->protocol == htons(ETH_P_IP)) {
1186 struct iphdr *iph = ip_hdr(skb);
1187 unsigned int offset;
77555ee7
MO		 1188 offset = skb_transport_offset(skb);
1189 if (iph->protocol == IPPROTO_TCP) {
1190 skb->csum = 0;
1191 tcp_hdr(skb)->check = 0;
1192 skb->csum = skb_checksum(skb, offset,
1193 skb->len - offset, 0);
1194 tcp_hdr(skb)->check =
1195 csum_tcpudp_magic(iph->saddr,
1196 iph->daddr,
1197 skb->len - offset,
1198 IPPROTO_TCP,
1199 skb->csum);
1200 } else if (iph->protocol == IPPROTO_UDP) {
1201 skb->csum = 0;
1202 udp_hdr(skb)->check = 0;
1203 skb->csum =
1204 skb_checksum(skb, offset,
1205 skb->len - offset, 0);
1206 udp_hdr(skb)->check =
1207 csum_tcpudp_magic(iph->saddr,
1208 iph->daddr,
1209 skb->len - offset,
1210 IPPROTO_UDP,
1211 skb->csum);
1212 }
1213 }
1214 }
3ab77bf2 1215
77555ee7
MO		 1216 ring_num = tx_ring->next_to_use;
1217 if (unlikely((ring_num + 1) == tx_ring->count))
1218 tx_ring->next_to_use = 0;
1219 else
1220 tx_ring->next_to_use = ring_num + 1;
1221
3ab77bf2 1222
77555ee7
MO		 1223 buffer_info = &tx_ring->buffer_info[ring_num];
1224 tmp_skb = buffer_info->skb;
1225
1226 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1227 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1228 tmp_skb->data[ETH_HLEN] = 0x00;
1229 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1230 tmp_skb->len = skb->len;
1231 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1232 (skb->len - ETH_HLEN));
25985edc 1233 /*-- Set Buffer information --*/
77555ee7
MO		 1234 buffer_info->length = tmp_skb->len;
1235 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1236 buffer_info->length,
1237 DMA_TO_DEVICE);
1238 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1239 pr_err("TX DMA map failed\n");
1240 buffer_info->dma = 0;
1241 buffer_info->time_stamp = 0;
1242 tx_ring->next_to_use = ring_num;
1243 return;
1244 }
1245 buffer_info->mapped = true;
1246 buffer_info->time_stamp = jiffies;
1247
1248 /*-- Set Tx descriptor --*/
1249 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1250 tx_desc->buffer_addr = (buffer_info->dma);
1251 tx_desc->length = (tmp_skb->len);
1252 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1253 tx_desc->tx_frame_ctrl = (frame_ctrl);
1254 tx_desc->gbec_status = (DSC_INIT16);
1255
1256 if (unlikely(++ring_num == tx_ring->count))
1257 ring_num = 0;
1258
1259 /* Update software pointer of TX descriptor */
1260 iowrite32(tx_ring->dma +
1261 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1262 &hw->reg->TX_DSC_SW_P);
1a0bdadb
TS		 1263
1264#ifdef CONFIG_PCH_PTP
1265 pch_tx_timestamp(adapter, skb);
1266#endif
1267
77555ee7
MO		 1268 dev_kfree_skb_any(skb);
1269}
1270
1271/**
1272 * pch_gbe_update_stats - Update the board statistics counters
1273 * @adapter: Board private structure
1274 */
1275void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1276{
1277 struct net_device *netdev = adapter->netdev;
1278 struct pci_dev *pdev = adapter->pdev;
1279 struct pch_gbe_hw_stats *stats = &adapter->stats;
1280 unsigned long flags;
1281
1282 /*
1283 * Prevent stats update while adapter is being reset, or if the pci
1284 * connection is down.
1285 */
1286 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1287 return;
1288
1289 spin_lock_irqsave(&adapter->stats_lock, flags);
1290
1291 /* Update device status "adapter->stats" */
1292 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1293 stats->tx_errors = stats->tx_length_errors +
1294 stats->tx_aborted_errors +
1295 stats->tx_carrier_errors + stats->tx_timeout_count;
1296
1297 /* Update network device status "adapter->net_stats" */
1298 netdev->stats.rx_packets = stats->rx_packets;
1299 netdev->stats.rx_bytes = stats->rx_bytes;
1300 netdev->stats.rx_dropped = stats->rx_dropped;
1301 netdev->stats.tx_packets = stats->tx_packets;
1302 netdev->stats.tx_bytes = stats->tx_bytes;
1303 netdev->stats.tx_dropped = stats->tx_dropped;
1304 /* Fill out the OS statistics structure */
1305 netdev->stats.multicast = stats->multicast;
1306 netdev->stats.collisions = stats->collisions;
1307 /* Rx Errors */
1308 netdev->stats.rx_errors = stats->rx_errors;
1309 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1310 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1311 /* Tx Errors */
1312 netdev->stats.tx_errors = stats->tx_errors;
1313 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1314 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1315
1316 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1317}
1318
124d770a
TO		 1319static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter)
1320{
1321 struct pch_gbe_hw *hw = &adapter->hw;
1322 u32 rxdma;
1323 u16 value;
1324 int ret;
1325
1326 /* Disable Receive DMA */
1327 rxdma = ioread32(&hw->reg->DMA_CTRL);
1328 rxdma &= ~PCH_GBE_RX_DMA_EN;
1329 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1330 /* Wait Rx DMA BUS is IDLE */
1331 ret = pch_gbe_wait_clr_bit_irq(&hw->reg->RX_DMA_ST, PCH_GBE_IDLE_CHECK);
1332 if (ret) {
1333 /* Disable Bus master */
1334 pci_read_config_word(adapter->pdev, PCI_COMMAND, &value);
1335 value &= ~PCI_COMMAND_MASTER;
1336 pci_write_config_word(adapter->pdev, PCI_COMMAND, value);
1337 /* Stop Receive */
1338 pch_gbe_mac_reset_rx(hw);
1339 /* Enable Bus master */
1340 value |= PCI_COMMAND_MASTER;
1341 pci_write_config_word(adapter->pdev, PCI_COMMAND, value);
1342 } else {
1343 /* Stop Receive */
1344 pch_gbe_mac_reset_rx(hw);
1345 }
d344c4f3
RL		 1346 /* reprogram multicast address register after reset */
1347 pch_gbe_set_multi(adapter->netdev);
124d770a
TO		 1348}
1349
5229d87e
TO		 1350static void pch_gbe_start_receive(struct pch_gbe_hw *hw)
1351{
1352 u32 rxdma;
1353
1354 /* Enables Receive DMA */
1355 rxdma = ioread32(&hw->reg->DMA_CTRL);
1356 rxdma |= PCH_GBE_RX_DMA_EN;
1357 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1358 /* Enables Receive */
1359 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
1360 return;
1361}
1362
77555ee7
MO		 1363/**
1364 * pch_gbe_intr - Interrupt Handler
1365 * @irq: Interrupt number
1366 * @data: Pointer to a network interface device structure
49ce9c2c 1367 * Returns:
77555ee7
MO		 1368 * - IRQ_HANDLED: Our interrupt
1369 * - IRQ_NONE: Not our interrupt
1370 */
1371static irqreturn_t pch_gbe_intr(int irq, void *data)
1372{
1373 struct net_device *netdev = data;
1374 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1375 struct pch_gbe_hw *hw = &adapter->hw;
1376 u32 int_st;
1377 u32 int_en;
1378
1379 /* Check request status */
1380 int_st = ioread32(&hw->reg->INT_ST);
1381 int_st = int_st & ioread32(&hw->reg->INT_EN);
1382 /* When request status is no interruption factor */
1383 if (unlikely(!int_st))
1384 return IRQ_NONE; /* Not our interrupt. End processing. */
1385 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1386 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1387 adapter->stats.intr_rx_frame_err_count++;
1388 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
124d770a
TO		 1389 if (!adapter->rx_stop_flag) {
1390 adapter->stats.intr_rx_fifo_err_count++;
1391 pr_debug("Rx fifo over run\n");
1392 adapter->rx_stop_flag = true;
1393 int_en = ioread32(&hw->reg->INT_EN);
1394 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1395 &hw->reg->INT_EN);
1396 pch_gbe_stop_receive(adapter);
805e969f
TO		 1397 int_st |= ioread32(&hw->reg->INT_ST);
1398 int_st = int_st & ioread32(&hw->reg->INT_EN);
124d770a 1399 }
77555ee7
MO		 1400 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1401 adapter->stats.intr_rx_dma_err_count++;
1402 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1403 adapter->stats.intr_tx_fifo_err_count++;
1404 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1405 adapter->stats.intr_tx_dma_err_count++;
1406 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1407 adapter->stats.intr_tcpip_err_count++;
1408 /* When Rx descriptor is empty */
1409 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1410 adapter->stats.intr_rx_dsc_empty_count++;
124d770a 1411 pr_debug("Rx descriptor is empty\n");
77555ee7
MO		 1412 int_en = ioread32(&hw->reg->INT_EN);
1413 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1414 if (hw->mac.tx_fc_enable) {
1415 /* Set Pause packet */
1416 pch_gbe_mac_set_pause_packet(hw);
1417 }
77555ee7
MO		 1418 }
1419
1420 /* When request status is Receive interruption */
805e969f 1421 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
23677ce3 1422 (adapter->rx_stop_flag)) {
77555ee7
MO		 1423 if (likely(napi_schedule_prep(&adapter->napi))) {
1424 /* Enable only Rx Descriptor empty */
1425 atomic_inc(&adapter->irq_sem);
1426 int_en = ioread32(&hw->reg->INT_EN);
1427 int_en &=
1428 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1429 iowrite32(int_en, &hw->reg->INT_EN);
1430 /* Start polling for NAPI */
1431 __napi_schedule(&adapter->napi);
1432 }
1433 }
1434 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1435 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1436 return IRQ_HANDLED;
1437}
1438
1439/**
1440 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1441 * @adapter: Board private structure
1442 * @rx_ring: Rx descriptor ring
1443 * @cleaned_count: Cleaned count
1444 */
1445static void
1446pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1447 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1448{
1449 struct net_device *netdev = adapter->netdev;
1450 struct pci_dev *pdev = adapter->pdev;
1451 struct pch_gbe_hw *hw = &adapter->hw;
1452 struct pch_gbe_rx_desc *rx_desc;
1453 struct pch_gbe_buffer *buffer_info;
1454 struct sk_buff *skb;
1455 unsigned int i;
1456 unsigned int bufsz;
1457
124d770a 1458 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
77555ee7
MO		 1459 i = rx_ring->next_to_use;
1460
1461 while ((cleaned_count--)) {
1462 buffer_info = &rx_ring->buffer_info[i];
124d770a
TO		 1463 skb = netdev_alloc_skb(netdev, bufsz);
1464 if (unlikely(!skb)) {
1465 /* Better luck next round */
1466 adapter->stats.rx_alloc_buff_failed++;
1467 break;
77555ee7 1468 }
124d770a
TO		 1469 /* align */
1470 skb_reserve(skb, NET_IP_ALIGN);
1471 buffer_info->skb = skb;
1472
77555ee7 1473 buffer_info->dma = dma_map_single(&pdev->dev,
124d770a 1474 buffer_info->rx_buffer,
77555ee7
MO		 1475 buffer_info->length,
1476 DMA_FROM_DEVICE);
1477 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1478 dev_kfree_skb(skb);
1479 buffer_info->skb = NULL;
1480 buffer_info->dma = 0;
1481 adapter->stats.rx_alloc_buff_failed++;
1482 break; /* while !buffer_info->skb */
1483 }
1484 buffer_info->mapped = true;
1485 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1486 rx_desc->buffer_addr = (buffer_info->dma);
1487 rx_desc->gbec_status = DSC_INIT16;
1488
1489 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1490 i, (unsigned long long)buffer_info->dma,
1491 buffer_info->length);
1492
1493 if (unlikely(++i == rx_ring->count))
1494 i = 0;
1495 }
1496 if (likely(rx_ring->next_to_use != i)) {
1497 rx_ring->next_to_use = i;
1498 if (unlikely(i-- == 0))
1499 i = (rx_ring->count - 1);
1500 iowrite32(rx_ring->dma +
1501 (int)sizeof(struct pch_gbe_rx_desc) * i,
1502 &hw->reg->RX_DSC_SW_P);
1503 }
1504 return;
1505}
1506
124d770a
TO		 1507static int
1508pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1509 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1510{
1511 struct pci_dev *pdev = adapter->pdev;
1512 struct pch_gbe_buffer *buffer_info;
1513 unsigned int i;
1514 unsigned int bufsz;
1515 unsigned int size;
1516
1517 bufsz = adapter->rx_buffer_len;
1518
1519 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1520 rx_ring->rx_buff_pool = dma_alloc_coherent(&pdev->dev, size,
1521 &rx_ring->rx_buff_pool_logic,
1522 GFP_KERNEL);
1523 if (!rx_ring->rx_buff_pool) {
3ab77bf2 1524 pr_err("Unable to allocate memory for the receive pool buffer\n");
124d770a
TO		 1525 return -ENOMEM;
1526 }
1527 memset(rx_ring->rx_buff_pool, 0, size);
1528 rx_ring->rx_buff_pool_size = size;
1529 for (i = 0; i < rx_ring->count; i++) {
1530 buffer_info = &rx_ring->buffer_info[i];
1531 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1532 buffer_info->length = bufsz;
1533 }
1534 return 0;
1535}
1536
77555ee7
MO		 1537/**
1538 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1539 * @adapter: Board private structure
1540 * @tx_ring: Tx descriptor ring
1541 */
1542static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1543 struct pch_gbe_tx_ring *tx_ring)
1544{
1545 struct pch_gbe_buffer *buffer_info;
1546 struct sk_buff *skb;
1547 unsigned int i;
1548 unsigned int bufsz;
1549 struct pch_gbe_tx_desc *tx_desc;
1550
1551 bufsz =
1552 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1553
1554 for (i = 0; i < tx_ring->count; i++) {
1555 buffer_info = &tx_ring->buffer_info[i];
1556 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1557 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1558 buffer_info->skb = skb;
1559 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1560 tx_desc->gbec_status = (DSC_INIT16);
1561 }
1562 return;
1563}
1564
1565/**
1566 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1567 * @adapter: Board private structure
1568 * @tx_ring: Tx descriptor ring
49ce9c2c 1569 * Returns:
77555ee7
MO		 1570 * true: Cleaned the descriptor
1571 * false: Not cleaned the descriptor
1572 */
1573static bool
1574pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1575 struct pch_gbe_tx_ring *tx_ring)
1576{
1577 struct pch_gbe_tx_desc *tx_desc;
1578 struct pch_gbe_buffer *buffer_info;
1579 struct sk_buff *skb;
1580 unsigned int i;
1581 unsigned int cleaned_count = 0;
805e969f 1582 bool cleaned = true;
77555ee7
MO		 1583
1584 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1585
1586 i = tx_ring->next_to_clean;
1587 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1588 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1589 tx_desc->gbec_status, tx_desc->dma_status);
1590
1591 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1592 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
77555ee7
MO		 1593 buffer_info = &tx_ring->buffer_info[i];
1594 skb = buffer_info->skb;
1595
1596 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1597 adapter->stats.tx_aborted_errors++;
1598 pr_err("Transfer Abort Error\n");
1599 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1600 ) {
1601 adapter->stats.tx_carrier_errors++;
1602 pr_err("Transfer Carrier Sense Error\n");
1603 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1604 ) {
1605 adapter->stats.tx_aborted_errors++;
1606 pr_err("Transfer Collision Abort Error\n");
1607 } else if ((tx_desc->gbec_status &
1608 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1609 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1610 adapter->stats.collisions++;
1611 adapter->stats.tx_packets++;
1612 adapter->stats.tx_bytes += skb->len;
1613 pr_debug("Transfer Collision\n");
1614 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1615 ) {
1616 adapter->stats.tx_packets++;
1617 adapter->stats.tx_bytes += skb->len;
1618 }
1619 if (buffer_info->mapped) {
1620 pr_debug("unmap buffer_info->dma : %d\n", i);
1621 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1622 buffer_info->length, DMA_TO_DEVICE);
1623 buffer_info->mapped = false;
1624 }
1625 if (buffer_info->skb) {
1626 pr_debug("trim buffer_info->skb : %d\n", i);
1627 skb_trim(buffer_info->skb, 0);
1628 }
1629 tx_desc->gbec_status = DSC_INIT16;
1630 if (unlikely(++i == tx_ring->count))
1631 i = 0;
1632 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1633
1634 /* weight of a sort for tx, to avoid endless transmit cleanup */
805e969f
TO		 1635 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1636 cleaned = false;
77555ee7 1637 break;
805e969f 1638 }
77555ee7
MO		 1639 }
1640 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1641 cleaned_count);
1642 /* Recover from running out of Tx resources in xmit_frame */
3ab77bf2 1643 spin_lock(&tx_ring->tx_lock);
77555ee7
MO		 1644 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1645 netif_wake_queue(adapter->netdev);
1646 adapter->stats.tx_restart_count++;
1647 pr_debug("Tx wake queue\n");
1648 }
3ab77bf2 1649
77555ee7 1650 tx_ring->next_to_clean = i;
3ab77bf2 1651
77555ee7 1652 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
3ab77bf2 1653 spin_unlock(&tx_ring->tx_lock);
77555ee7
MO		 1654 return cleaned;
1655}
1656
1657/**
1658 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1659 * @adapter: Board private structure
1660 * @rx_ring: Rx descriptor ring
1661 * @work_done: Completed count
1662 * @work_to_do: Request count
49ce9c2c 1663 * Returns:
77555ee7
MO		 1664 * true: Cleaned the descriptor
1665 * false: Not cleaned the descriptor
1666 */
1667static bool
1668pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1669 struct pch_gbe_rx_ring *rx_ring,
1670 int *work_done, int work_to_do)
1671{
1672 struct net_device *netdev = adapter->netdev;
1673 struct pci_dev *pdev = adapter->pdev;
1674 struct pch_gbe_buffer *buffer_info;
1675 struct pch_gbe_rx_desc *rx_desc;
1676 u32 length;
77555ee7
MO		 1677 unsigned int i;
1678 unsigned int cleaned_count = 0;
1679 bool cleaned = false;
124d770a 1680 struct sk_buff *skb;
77555ee7
MO		 1681 u8 dma_status;
1682 u16 gbec_status;
1683 u32 tcp_ip_status;
77555ee7
MO		 1684
1685 i = rx_ring->next_to_clean;
1686
1687 while (*work_done < work_to_do) {
1688 /* Check Rx descriptor status */
1689 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1690 if (rx_desc->gbec_status == DSC_INIT16)
1691 break;
1692 cleaned = true;
1693 cleaned_count++;
1694
1695 dma_status = rx_desc->dma_status;
1696 gbec_status = rx_desc->gbec_status;
1697 tcp_ip_status = rx_desc->tcp_ip_status;
1698 rx_desc->gbec_status = DSC_INIT16;
1699 buffer_info = &rx_ring->buffer_info[i];
1700 skb = buffer_info->skb;
124d770a 1701 buffer_info->skb = NULL;
77555ee7
MO		 1702
1703 /* unmap dma */
1704 dma_unmap_single(&pdev->dev, buffer_info->dma,
1705 buffer_info->length, DMA_FROM_DEVICE);
1706 buffer_info->mapped = false;
77555ee7
MO		 1707
1708 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1709 "TCP:0x%08x] BufInf = 0x%p\n",
1710 i, dma_status, gbec_status, tcp_ip_status,
1711 buffer_info);
1712 /* Error check */
1713 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1714 adapter->stats.rx_frame_errors++;
1715 pr_err("Receive Not Octal Error\n");
1716 } else if (unlikely(gbec_status &
1717 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1718 adapter->stats.rx_frame_errors++;
1719 pr_err("Receive Nibble Error\n");
1720 } else if (unlikely(gbec_status &
1721 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1722 adapter->stats.rx_crc_errors++;
1723 pr_err("Receive CRC Error\n");
1724 } else {
1725 /* get receive length */
124d770a
TO		 1726 /* length convert[-3], length includes FCS length */
1727 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1728 if (rx_desc->rx_words_eob & 0x02)
1729 length = length - 4;
1730 /*
1731 * buffer_info->rx_buffer: [Header:14][payload]
1732 * skb->data: [Reserve:2][Header:14][payload]
1733 */
1734 memcpy(skb->data, buffer_info->rx_buffer, length);
1735
77555ee7
MO		 1736 /* update status of driver */
1737 adapter->stats.rx_bytes += length;
1738 adapter->stats.rx_packets++;
1739 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1740 adapter->stats.multicast++;
1741 /* Write meta date of skb */
1742 skb_put(skb, length);
1a0bdadb
TS		 1743
1744#ifdef CONFIG_PCH_PTP
1745 pch_rx_timestamp(adapter, skb);
1746#endif
1747
77555ee7 1748 skb->protocol = eth_type_trans(skb, netdev);
5d05a04d 1749 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
77555ee7 1750 skb->ip_summed = CHECKSUM_NONE;
5d05a04d
TO		 1751 else
1752 skb->ip_summed = CHECKSUM_UNNECESSARY;
1753
77555ee7
MO		 1754 napi_gro_receive(&adapter->napi, skb);
1755 (*work_done)++;
1756 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1757 skb->ip_summed, length);
1758 }
77555ee7
MO		 1759 /* return some buffers to hardware, one at a time is too slow */
1760 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1761 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1762 cleaned_count);
1763 cleaned_count = 0;
1764 }
1765 if (++i == rx_ring->count)
1766 i = 0;
1767 }
1768 rx_ring->next_to_clean = i;
1769 if (cleaned_count)
1770 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1771 return cleaned;
1772}
1773
1774/**
1775 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1776 * @adapter: Board private structure
1777 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
49ce9c2c 1778 * Returns:
77555ee7
MO		 1779 * 0: Successfully
1780 * Negative value: Failed
1781 */
1782int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1783 struct pch_gbe_tx_ring *tx_ring)
1784{
1785 struct pci_dev *pdev = adapter->pdev;
1786 struct pch_gbe_tx_desc *tx_desc;
1787 int size;
1788 int desNo;
1789
1790 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
89bf67f1 1791 tx_ring->buffer_info = vzalloc(size);
e404decb 1792 if (!tx_ring->buffer_info)
77555ee7 1793 return -ENOMEM;
77555ee7
MO		 1794
1795 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1796
1797 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1798 &tx_ring->dma, GFP_KERNEL);
1799 if (!tx_ring->desc) {
1800 vfree(tx_ring->buffer_info);
1801 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1802 return -ENOMEM;
1803 }
1804 memset(tx_ring->desc, 0, tx_ring->size);
1805
1806 tx_ring->next_to_use = 0;
1807 tx_ring->next_to_clean = 0;
1808 spin_lock_init(&tx_ring->tx_lock);
1809
1810 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1811 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1812 tx_desc->gbec_status = DSC_INIT16;
1813 }
1814 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1815 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1816 tx_ring->desc, (unsigned long long)tx_ring->dma,
1817 tx_ring->next_to_clean, tx_ring->next_to_use);
1818 return 0;
1819}
1820
1821/**
1822 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1823 * @adapter: Board private structure
1824 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
49ce9c2c 1825 * Returns:
77555ee7
MO		 1826 * 0: Successfully
1827 * Negative value: Failed
1828 */
1829int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1830 struct pch_gbe_rx_ring *rx_ring)
1831{
1832 struct pci_dev *pdev = adapter->pdev;
1833 struct pch_gbe_rx_desc *rx_desc;
1834 int size;
1835 int desNo;
1836
1837 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
89bf67f1 1838 rx_ring->buffer_info = vzalloc(size);
e404decb 1839 if (!rx_ring->buffer_info)
77555ee7 1840 return -ENOMEM;
e404decb 1841
77555ee7
MO		 1842 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1843 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1844 &rx_ring->dma, GFP_KERNEL);
1845
1846 if (!rx_ring->desc) {
1847 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1848 vfree(rx_ring->buffer_info);
1849 return -ENOMEM;
1850 }
1851 memset(rx_ring->desc, 0, rx_ring->size);
1852 rx_ring->next_to_clean = 0;
1853 rx_ring->next_to_use = 0;
1854 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1855 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1856 rx_desc->gbec_status = DSC_INIT16;
1857 }
1858 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1859 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1860 rx_ring->desc, (unsigned long long)rx_ring->dma,
1861 rx_ring->next_to_clean, rx_ring->next_to_use);
1862 return 0;
1863}
1864
1865/**
1866 * pch_gbe_free_tx_resources - Free Tx Resources
1867 * @adapter: Board private structure
1868 * @tx_ring: Tx descriptor ring for a specific queue
1869 */
1870void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1871 struct pch_gbe_tx_ring *tx_ring)
1872{
1873 struct pci_dev *pdev = adapter->pdev;
1874
1875 pch_gbe_clean_tx_ring(adapter, tx_ring);
1876 vfree(tx_ring->buffer_info);
1877 tx_ring->buffer_info = NULL;
1878 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1879 tx_ring->desc = NULL;
1880}
1881
1882/**
1883 * pch_gbe_free_rx_resources - Free Rx Resources
1884 * @adapter: Board private structure
1885 * @rx_ring: Ring to clean the resources from
1886 */
1887void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1888 struct pch_gbe_rx_ring *rx_ring)
1889{
1890 struct pci_dev *pdev = adapter->pdev;
1891
1892 pch_gbe_clean_rx_ring(adapter, rx_ring);
1893 vfree(rx_ring->buffer_info);
1894 rx_ring->buffer_info = NULL;
1895 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1896 rx_ring->desc = NULL;
1897}
1898
1899/**
1900 * pch_gbe_request_irq - Allocate an interrupt line
1901 * @adapter: Board private structure
49ce9c2c 1902 * Returns:
77555ee7
MO		 1903 * 0: Successfully
1904 * Negative value: Failed
1905 */
1906static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1907{
1908 struct net_device *netdev = adapter->netdev;
1909 int err;
1910 int flags;
1911
1912 flags = IRQF_SHARED;
1913 adapter->have_msi = false;
1914 err = pci_enable_msi(adapter->pdev);
1915 pr_debug("call pci_enable_msi\n");
1916 if (err) {
1917 pr_debug("call pci_enable_msi - Error: %d\n", err);
1918 } else {
1919 flags = 0;
1920 adapter->have_msi = true;
1921 }
1922 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1923 flags, netdev->name, netdev);
1924 if (err)
1925 pr_err("Unable to allocate interrupt Error: %d\n", err);
1926 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1927 adapter->have_msi, flags, err);
1928 return err;
1929}
1930
1931
77555ee7
MO		 1932/**
1933 * pch_gbe_up - Up GbE network device
1934 * @adapter: Board private structure
49ce9c2c 1935 * Returns:
77555ee7
MO		 1936 * 0: Successfully
1937 * Negative value: Failed
1938 */
1939int pch_gbe_up(struct pch_gbe_adapter *adapter)
1940{
1941 struct net_device *netdev = adapter->netdev;
1942 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1943 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1944 int err;
1945
2b53d078
DH		 1946 /* Ensure we have a valid MAC */
1947 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1948 pr_err("Error: Invalid MAC address\n");
1949 return -EINVAL;
1950 }
1951
77555ee7
MO		 1952 /* hardware has been reset, we need to reload some things */
1953 pch_gbe_set_multi(netdev);
1954
1955 pch_gbe_setup_tctl(adapter);
1956 pch_gbe_configure_tx(adapter);
1957 pch_gbe_setup_rctl(adapter);
1958 pch_gbe_configure_rx(adapter);
1959
1960 err = pch_gbe_request_irq(adapter);
1961 if (err) {
1962 pr_err("Error: can't bring device up\n");
1963 return err;
1964 }
124d770a
TO		 1965 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1966 if (err) {
1967 pr_err("Error: can't bring device up\n");
1968 return err;
1969 }
77555ee7
MO		 1970 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1971 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1972 adapter->tx_queue_len = netdev->tx_queue_len;
5229d87e 1973 pch_gbe_start_receive(&adapter->hw);
77555ee7
MO		 1974
1975 mod_timer(&adapter->watchdog_timer, jiffies);
1976
1977 napi_enable(&adapter->napi);
1978 pch_gbe_irq_enable(adapter);
1979 netif_start_queue(adapter->netdev);
1980
1981 return 0;
1982}
1983
1984/**
1985 * pch_gbe_down - Down GbE network device
1986 * @adapter: Board private structure
1987 */
1988void pch_gbe_down(struct pch_gbe_adapter *adapter)
1989{
1990 struct net_device *netdev = adapter->netdev;
124d770a 1991 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
77555ee7
MO		 1992
1993 /* signal that we're down so the interrupt handler does not
1994 * reschedule our watchdog timer */
1995 napi_disable(&adapter->napi);
1996 atomic_set(&adapter->irq_sem, 0);
1997
1998 pch_gbe_irq_disable(adapter);
1999 pch_gbe_free_irq(adapter);
2000
2001 del_timer_sync(&adapter->watchdog_timer);
2002
2003 netdev->tx_queue_len = adapter->tx_queue_len;
2004 netif_carrier_off(netdev);
2005 netif_stop_queue(netdev);
2006
2007 pch_gbe_reset(adapter);
2008 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2009 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
124d770a
TO		 2010
2011 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2012 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2013 rx_ring->rx_buff_pool_logic = 0;
2014 rx_ring->rx_buff_pool_size = 0;
2015 rx_ring->rx_buff_pool = NULL;
77555ee7
MO		 2016}
2017
2018/**
2019 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2020 * @adapter: Board private structure to initialize
49ce9c2c 2021 * Returns:
77555ee7
MO		 2022 * 0: Successfully
2023 * Negative value: Failed
2024 */
2025static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2026{
2027 struct pch_gbe_hw *hw = &adapter->hw;
2028 struct net_device *netdev = adapter->netdev;
2029
2030 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2031 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2032 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2033
2034 /* Initialize the hardware-specific values */
2035 if (pch_gbe_hal_setup_init_funcs(hw)) {
2036 pr_err("Hardware Initialization Failure\n");
2037 return -EIO;
2038 }
2039 if (pch_gbe_alloc_queues(adapter)) {
2040 pr_err("Unable to allocate memory for queues\n");
2041 return -ENOMEM;
2042 }
2043 spin_lock_init(&adapter->hw.miim_lock);
77555ee7
MO		 2044 spin_lock_init(&adapter->stats_lock);
2045 spin_lock_init(&adapter->ethtool_lock);
2046 atomic_set(&adapter->irq_sem, 0);
2047 pch_gbe_irq_disable(adapter);
2048
2049 pch_gbe_init_stats(adapter);
2050
2051 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
2052 (u32) adapter->rx_buffer_len,
2053 hw->mac.min_frame_size, hw->mac.max_frame_size);
2054 return 0;
2055}
2056
2057/**
2058 * pch_gbe_open - Called when a network interface is made active
2059 * @netdev: Network interface device structure
49ce9c2c 2060 * Returns:
77555ee7
MO		 2061 * 0: Successfully
2062 * Negative value: Failed
2063 */
2064static int pch_gbe_open(struct net_device *netdev)
2065{
2066 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2067 struct pch_gbe_hw *hw = &adapter->hw;
2068 int err;
2069
2070 /* allocate transmit descriptors */
2071 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2072 if (err)
2073 goto err_setup_tx;
2074 /* allocate receive descriptors */
2075 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2076 if (err)
2077 goto err_setup_rx;
2078 pch_gbe_hal_power_up_phy(hw);
2079 err = pch_gbe_up(adapter);
2080 if (err)
2081 goto err_up;
2082 pr_debug("Success End\n");
2083 return 0;
2084
2085err_up:
2086 if (!adapter->wake_up_evt)
2087 pch_gbe_hal_power_down_phy(hw);
2088 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2089err_setup_rx:
2090 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2091err_setup_tx:
2092 pch_gbe_reset(adapter);
2093 pr_err("Error End\n");
2094 return err;
2095}
2096
2097/**
2098 * pch_gbe_stop - Disables a network interface
2099 * @netdev: Network interface device structure
49ce9c2c 2100 * Returns:
77555ee7
MO		 2101 * 0: Successfully
2102 */
2103static int pch_gbe_stop(struct net_device *netdev)
2104{
2105 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2106 struct pch_gbe_hw *hw = &adapter->hw;
2107
2108 pch_gbe_down(adapter);
2109 if (!adapter->wake_up_evt)
2110 pch_gbe_hal_power_down_phy(hw);
2111 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2112 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2113 return 0;
2114}
2115
2116/**
2117 * pch_gbe_xmit_frame - Packet transmitting start
2118 * @skb: Socket buffer structure
2119 * @netdev: Network interface device structure
49ce9c2c 2120 * Returns:
77555ee7
MO		 2121 * - NETDEV_TX_OK: Normal end
2122 * - NETDEV_TX_BUSY: Error end
2123 */
2124static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2125{
2126 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2127 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2128 unsigned long flags;
2129
2130 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
77555ee7
MO		 2131 pr_err("Transfer length Error: skb len: %d > max: %d\n",
2132 skb->len, adapter->hw.mac.max_frame_size);
419c2046 2133 dev_kfree_skb_any(skb);
77555ee7
MO		 2134 adapter->stats.tx_length_errors++;
2135 return NETDEV_TX_OK;
2136 }
2137 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
2138 /* Collision - tell upper layer to requeue */
2139 return NETDEV_TX_LOCKED;
2140 }
2141 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2142 netif_stop_queue(netdev);
2143 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2144 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2145 tx_ring->next_to_use, tx_ring->next_to_clean);
2146 return NETDEV_TX_BUSY;
2147 }
77555ee7
MO		 2148
2149 /* CRC,ITAG no support */
2150 pch_gbe_tx_queue(adapter, tx_ring, skb);
3ab77bf2 2151 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
77555ee7
MO		 2152 return NETDEV_TX_OK;
2153}
2154
2155/**
2156 * pch_gbe_get_stats - Get System Network Statistics
2157 * @netdev: Network interface device structure
2158 * Returns: The current stats
2159 */
2160static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
2161{
2162 /* only return the current stats */
2163 return &netdev->stats;
2164}
2165
2166/**
2167 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2168 * @netdev: Network interface device structure
2169 */
2170static void pch_gbe_set_multi(struct net_device *netdev)
2171{
2172 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2173 struct pch_gbe_hw *hw = &adapter->hw;
2174 struct netdev_hw_addr *ha;
2175 u8 *mta_list;
2176 u32 rctl;
2177 int i;
2178 int mc_count;
2179
2180 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
2181
2182 /* Check for Promiscuous and All Multicast modes */
2183 rctl = ioread32(&hw->reg->RX_MODE);
2184 mc_count = netdev_mc_count(netdev);
2185 if ((netdev->flags & IFF_PROMISC)) {
2186 rctl &= ~PCH_GBE_ADD_FIL_EN;
2187 rctl &= ~PCH_GBE_MLT_FIL_EN;
2188 } else if ((netdev->flags & IFF_ALLMULTI)) {
2189 /* all the multicasting receive permissions */
2190 rctl |= PCH_GBE_ADD_FIL_EN;
2191 rctl &= ~PCH_GBE_MLT_FIL_EN;
2192 } else {
2193 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2194 /* all the multicasting receive permissions */
2195 rctl |= PCH_GBE_ADD_FIL_EN;
2196 rctl &= ~PCH_GBE_MLT_FIL_EN;
2197 } else {
2198 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2199 }
2200 }
2201 iowrite32(rctl, &hw->reg->RX_MODE);
2202
2203 if (mc_count >= PCH_GBE_MAR_ENTRIES)
2204 return;
2205 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2206 if (!mta_list)
2207 return;
2208
2209 /* The shared function expects a packed array of only addresses. */
2210 i = 0;
2211 netdev_for_each_mc_addr(ha, netdev) {
2212 if (i == mc_count)
2213 break;
2214 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2215 }
2216 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2217 PCH_GBE_MAR_ENTRIES);
2218 kfree(mta_list);
2219
2220 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2221 ioread32(&hw->reg->RX_MODE), mc_count);
2222}
2223
2224/**
2225 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2226 * @netdev: Network interface device structure
2227 * @addr: Pointer to an address structure
49ce9c2c 2228 * Returns:
77555ee7
MO		 2229 * 0: Successfully
2230 * -EADDRNOTAVAIL: Failed
2231 */
2232static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2233{
2234 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2235 struct sockaddr *skaddr = addr;
2236 int ret_val;
2237
2238 if (!is_valid_ether_addr(skaddr->sa_data)) {
2239 ret_val = -EADDRNOTAVAIL;
2240 } else {
2241 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2242 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2243 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2244 ret_val = 0;
2245 }
2246 pr_debug("ret_val : 0x%08x\n", ret_val);
2247 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
2248 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
2249 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2250 ioread32(&adapter->hw.reg->mac_adr[0].high),
2251 ioread32(&adapter->hw.reg->mac_adr[0].low));
2252 return ret_val;
2253}
2254
2255/**
2256 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2257 * @netdev: Network interface device structure
2258 * @new_mtu: New value for maximum frame size
49ce9c2c 2259 * Returns:
77555ee7
MO		 2260 * 0: Successfully
2261 * -EINVAL: Failed
2262 */
2263static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2264{
2265 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2266 int max_frame;
124d770a
TO		 2267 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2268 int err;
77555ee7
MO		 2269
2270 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2271 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2272 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2273 pr_err("Invalid MTU setting\n");
2274 return -EINVAL;
2275 }
2276 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2277 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2278 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2279 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2280 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2281 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2282 else
124d770a 2283 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
77555ee7 2284
124d770a
TO		 2285 if (netif_running(netdev)) {
2286 pch_gbe_down(adapter);
2287 err = pch_gbe_up(adapter);
2288 if (err) {
2289 adapter->rx_buffer_len = old_rx_buffer_len;
2290 pch_gbe_up(adapter);
2291 return -ENOMEM;
2292 } else {
2293 netdev->mtu = new_mtu;
2294 adapter->hw.mac.max_frame_size = max_frame;
2295 }
2296 } else {
77555ee7 2297 pch_gbe_reset(adapter);
124d770a
TO		 2298 netdev->mtu = new_mtu;
2299 adapter->hw.mac.max_frame_size = max_frame;
2300 }
77555ee7
MO		 2301
2302 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2303 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2304 adapter->hw.mac.max_frame_size);
2305 return 0;
2306}
2307
756a6b03
MM		 2308/**
2309 * pch_gbe_set_features - Reset device after features changed
2310 * @netdev: Network interface device structure
2311 * @features: New features
49ce9c2c 2312 * Returns:
756a6b03
MM		 2313 * 0: HW state updated successfully
2314 */
c8f44aff
MM		 2315static int pch_gbe_set_features(struct net_device *netdev,
2316 netdev_features_t features)
756a6b03
MM		 2317{
2318 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
c8f44aff 2319 netdev_features_t changed = features ^ netdev->features;
756a6b03
MM		 2320
2321 if (!(changed & NETIF_F_RXCSUM))
2322 return 0;
2323
2324 if (netif_running(netdev))
2325 pch_gbe_reinit_locked(adapter);
2326 else
2327 pch_gbe_reset(adapter);
2328
2329 return 0;
2330}
2331
77555ee7
MO		 2332/**
2333 * pch_gbe_ioctl - Controls register through a MII interface
2334 * @netdev: Network interface device structure
2335 * @ifr: Pointer to ifr structure
2336 * @cmd: Control command
49ce9c2c 2337 * Returns:
77555ee7
MO		 2338 * 0: Successfully
2339 * Negative value: Failed
2340 */
2341static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2342{
2343 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2344
2345 pr_debug("cmd : 0x%04x\n", cmd);
2346
1a0bdadb
TS		 2347#ifdef CONFIG_PCH_PTP
2348 if (cmd == SIOCSHWTSTAMP)
2349 return hwtstamp_ioctl(netdev, ifr, cmd);
2350#endif
2351
77555ee7
MO		 2352 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2353}
2354
2355/**
2356 * pch_gbe_tx_timeout - Respond to a Tx Hang
2357 * @netdev: Network interface device structure
2358 */
2359static void pch_gbe_tx_timeout(struct net_device *netdev)
2360{
2361 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2362
2363 /* Do the reset outside of interrupt context */
2364 adapter->stats.tx_timeout_count++;
2365 schedule_work(&adapter->reset_task);
2366}
2367
2368/**
2369 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2370 * @napi: Pointer of polling device struct
2371 * @budget: The maximum number of a packet
49ce9c2c 2372 * Returns:
77555ee7
MO		 2373 * false: Exit the polling mode
2374 * true: Continue the polling mode
2375 */
2376static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2377{
2378 struct pch_gbe_adapter *adapter =
2379 container_of(napi, struct pch_gbe_adapter, napi);
77555ee7
MO		 2380 int work_done = 0;
2381 bool poll_end_flag = false;
2382 bool cleaned = false;
124d770a 2383 u32 int_en;
77555ee7
MO		 2384
2385 pr_debug("budget : %d\n", budget);
2386
805e969f
TO		 2387 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2388 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2389
2390 if (!cleaned)
2391 work_done = budget;
2392 /* If no Tx and not enough Rx work done,
2393 * exit the polling mode
2394 */
2395 if (work_done < budget)
77555ee7 2396 poll_end_flag = true;
805e969f
TO		 2397
2398 if (poll_end_flag) {
2399 napi_complete(napi);
2400 if (adapter->rx_stop_flag) {
2401 adapter->rx_stop_flag = false;
2402 pch_gbe_start_receive(&adapter->hw);
2403 }
2404 pch_gbe_irq_enable(adapter);
2405 } else
124d770a
TO		 2406 if (adapter->rx_stop_flag) {
2407 adapter->rx_stop_flag = false;
2408 pch_gbe_start_receive(&adapter->hw);
2409 int_en = ioread32(&adapter->hw.reg->INT_EN);
2410 iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR),
805e969f 2411 &adapter->hw.reg->INT_EN);
124d770a 2412 }
77555ee7
MO		 2413
2414 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2415 poll_end_flag, work_done, budget);
2416
2417 return work_done;
2418}
2419
2420#ifdef CONFIG_NET_POLL_CONTROLLER
2421/**
2422 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2423 * @netdev: Network interface device structure
2424 */
2425static void pch_gbe_netpoll(struct net_device *netdev)
2426{
2427 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2428
2429 disable_irq(adapter->pdev->irq);
2430 pch_gbe_intr(adapter->pdev->irq, netdev);
2431 enable_irq(adapter->pdev->irq);
2432}
2433#endif
2434
2435static const struct net_device_ops pch_gbe_netdev_ops = {
2436 .ndo_open = pch_gbe_open,
2437 .ndo_stop = pch_gbe_stop,
2438 .ndo_start_xmit = pch_gbe_xmit_frame,
2439 .ndo_get_stats = pch_gbe_get_stats,
2440 .ndo_set_mac_address = pch_gbe_set_mac,
2441 .ndo_tx_timeout = pch_gbe_tx_timeout,
2442 .ndo_change_mtu = pch_gbe_change_mtu,
756a6b03 2443 .ndo_set_features = pch_gbe_set_features,
77555ee7 2444 .ndo_do_ioctl = pch_gbe_ioctl,
afc4b13d 2445 .ndo_set_rx_mode = pch_gbe_set_multi,
77555ee7
MO		 2446#ifdef CONFIG_NET_POLL_CONTROLLER
2447 .ndo_poll_controller = pch_gbe_netpoll,
2448#endif
2449};
2450
2451static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2452 pci_channel_state_t state)
2453{
2454 struct net_device *netdev = pci_get_drvdata(pdev);
2455 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2456
2457 netif_device_detach(netdev);
2458 if (netif_running(netdev))
2459 pch_gbe_down(adapter);
2460 pci_disable_device(pdev);
2461 /* Request a slot slot reset. */
2462 return PCI_ERS_RESULT_NEED_RESET;
2463}
2464
2465static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2466{
2467 struct net_device *netdev = pci_get_drvdata(pdev);
2468 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2469 struct pch_gbe_hw *hw = &adapter->hw;
2470
2471 if (pci_enable_device(pdev)) {
2472 pr_err("Cannot re-enable PCI device after reset\n");
2473 return PCI_ERS_RESULT_DISCONNECT;
2474 }
2475 pci_set_master(pdev);
2476 pci_enable_wake(pdev, PCI_D0, 0);
2477 pch_gbe_hal_power_up_phy(hw);
2478 pch_gbe_reset(adapter);
2479 /* Clear wake up status */
2480 pch_gbe_mac_set_wol_event(hw, 0);
2481
2482 return PCI_ERS_RESULT_RECOVERED;
2483}
2484
2485static void pch_gbe_io_resume(struct pci_dev *pdev)
2486{
2487 struct net_device *netdev = pci_get_drvdata(pdev);
2488 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2489
2490 if (netif_running(netdev)) {
2491 if (pch_gbe_up(adapter)) {
2492 pr_debug("can't bring device back up after reset\n");
2493 return;
2494 }
2495 }
2496 netif_device_attach(netdev);
2497}
2498
2499static int __pch_gbe_suspend(struct pci_dev *pdev)
2500{
2501 struct net_device *netdev = pci_get_drvdata(pdev);
2502 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2503 struct pch_gbe_hw *hw = &adapter->hw;
2504 u32 wufc = adapter->wake_up_evt;
2505 int retval = 0;
2506
2507 netif_device_detach(netdev);
2508 if (netif_running(netdev))
2509 pch_gbe_down(adapter);
2510 if (wufc) {
2511 pch_gbe_set_multi(netdev);
2512 pch_gbe_setup_rctl(adapter);
2513 pch_gbe_configure_rx(adapter);
2514 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2515 hw->mac.link_duplex);
2516 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2517 hw->mac.link_duplex);
2518 pch_gbe_mac_set_wol_event(hw, wufc);
2519 pci_disable_device(pdev);
2520 } else {
2521 pch_gbe_hal_power_down_phy(hw);
2522 pch_gbe_mac_set_wol_event(hw, wufc);
2523 pci_disable_device(pdev);
2524 }
2525 return retval;
2526}
2527
2528#ifdef CONFIG_PM
2529static int pch_gbe_suspend(struct device *device)
2530{
2531 struct pci_dev *pdev = to_pci_dev(device);
2532
2533 return __pch_gbe_suspend(pdev);
2534}
2535
2536static int pch_gbe_resume(struct device *device)
2537{
2538 struct pci_dev *pdev = to_pci_dev(device);
2539 struct net_device *netdev = pci_get_drvdata(pdev);
2540 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2541 struct pch_gbe_hw *hw = &adapter->hw;
2542 u32 err;
2543
2544 err = pci_enable_device(pdev);
2545 if (err) {
2546 pr_err("Cannot enable PCI device from suspend\n");
2547 return err;
2548 }
2549 pci_set_master(pdev);
2550 pch_gbe_hal_power_up_phy(hw);
2551 pch_gbe_reset(adapter);
2552 /* Clear wake on lan control and status */
2553 pch_gbe_mac_set_wol_event(hw, 0);
2554
2555 if (netif_running(netdev))
2556 pch_gbe_up(adapter);
2557 netif_device_attach(netdev);
2558
2559 return 0;
2560}
2561#endif /* CONFIG_PM */
2562
2563static void pch_gbe_shutdown(struct pci_dev *pdev)
2564{
2565 __pch_gbe_suspend(pdev);
2566 if (system_state == SYSTEM_POWER_OFF) {
2567 pci_wake_from_d3(pdev, true);
2568 pci_set_power_state(pdev, PCI_D3hot);
2569 }
2570}
2571
2572static void pch_gbe_remove(struct pci_dev *pdev)
2573{
2574 struct net_device *netdev = pci_get_drvdata(pdev);
2575 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2576
2321f3b4 2577 cancel_work_sync(&adapter->reset_task);
77555ee7
MO		 2578 unregister_netdev(netdev);
2579
2580 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2581
2582 kfree(adapter->tx_ring);
2583 kfree(adapter->rx_ring);
2584
2585 iounmap(adapter->hw.reg);
2586 pci_release_regions(pdev);
2587 free_netdev(netdev);
2588 pci_disable_device(pdev);
2589}
2590
2591static int pch_gbe_probe(struct pci_dev *pdev,
2592 const struct pci_device_id *pci_id)
2593{
2594 struct net_device *netdev;
2595 struct pch_gbe_adapter *adapter;
2596 int ret;
2597
2598 ret = pci_enable_device(pdev);
2599 if (ret)
2600 return ret;
2601
2602 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2603 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2604 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2605 if (ret) {
2606 ret = pci_set_consistent_dma_mask(pdev,
2607 DMA_BIT_MASK(32));
2608 if (ret) {
2609 dev_err(&pdev->dev, "ERR: No usable DMA "
2610 "configuration, aborting\n");
2611 goto err_disable_device;
2612 }
2613 }
2614 }
2615
2616 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2617 if (ret) {
2618 dev_err(&pdev->dev,
2619 "ERR: Can't reserve PCI I/O and memory resources\n");
2620 goto err_disable_device;
2621 }
2622 pci_set_master(pdev);
2623
2624 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2625 if (!netdev) {
2626 ret = -ENOMEM;
77555ee7
MO		 2627 goto err_release_pci;
2628 }
2629 SET_NETDEV_DEV(netdev, &pdev->dev);
2630
2631 pci_set_drvdata(pdev, netdev);
2632 adapter = netdev_priv(netdev);
2633 adapter->netdev = netdev;
2634 adapter->pdev = pdev;
2635 adapter->hw.back = adapter;
2636 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2637 if (!adapter->hw.reg) {
2638 ret = -EIO;
2639 dev_err(&pdev->dev, "Can't ioremap\n");
2640 goto err_free_netdev;
2641 }
2642
1a0bdadb
TS		 2643#ifdef CONFIG_PCH_PTP
2644 adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2645 PCI_DEVFN(12, 4));
2646 if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
2647 pr_err("Bad ptp filter\n");
2648 return -EINVAL;
2649 }
2650#endif
2651
77555ee7
MO		 2652 netdev->netdev_ops = &pch_gbe_netdev_ops;
2653 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2654 netif_napi_add(netdev, &adapter->napi,
2655 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
756a6b03
MM		 2656 netdev->hw_features = NETIF_F_RXCSUM |
2657 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2658 netdev->features = netdev->hw_features;
77555ee7
MO		 2659 pch_gbe_set_ethtool_ops(netdev);
2660
98200ec2 2661 pch_gbe_mac_load_mac_addr(&adapter->hw);
77555ee7
MO		 2662 pch_gbe_mac_reset_hw(&adapter->hw);
2663
2664 /* setup the private structure */
2665 ret = pch_gbe_sw_init(adapter);
2666 if (ret)
2667 goto err_iounmap;
2668
2669 /* Initialize PHY */
2670 ret = pch_gbe_init_phy(adapter);
2671 if (ret) {
2672 dev_err(&pdev->dev, "PHY initialize error\n");
2673 goto err_free_adapter;
2674 }
2675 pch_gbe_hal_get_bus_info(&adapter->hw);
2676
2677 /* Read the MAC address. and store to the private data */
2678 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2679 if (ret) {
2680 dev_err(&pdev->dev, "MAC address Read Error\n");
2681 goto err_free_adapter;
2682 }
2683
2684 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2685 if (!is_valid_ether_addr(netdev->dev_addr)) {
2b53d078
DH		 2686 /*
2687 * If the MAC is invalid (or just missing), display a warning
2688 * but do not abort setting up the device. pch_gbe_up will
2689 * prevent the interface from being brought up until a valid MAC
2690 * is set.
2691 */
2692 dev_err(&pdev->dev, "Invalid MAC address, "
2693 "interface disabled.\n");
77555ee7
MO		 2694 }
2695 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2696 (unsigned long)adapter);
2697
2698 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2699
2700 pch_gbe_check_options(adapter);
2701
77555ee7
MO		 2702 /* initialize the wol settings based on the eeprom settings */
2703 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2704 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2705
2706 /* reset the hardware with the new settings */
2707 pch_gbe_reset(adapter);
2708
2709 ret = register_netdev(netdev);
2710 if (ret)
2711 goto err_free_adapter;
2712 /* tell the stack to leave us alone until pch_gbe_open() is called */
2713 netif_carrier_off(netdev);
2714 netif_stop_queue(netdev);
2715
1a0bdadb 2716 dev_dbg(&pdev->dev, "PCH Network Connection\n");
77555ee7
MO		 2717
2718 device_set_wakeup_enable(&pdev->dev, 1);
2719 return 0;
2720
2721err_free_adapter:
2722 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2723 kfree(adapter->tx_ring);
2724 kfree(adapter->rx_ring);
2725err_iounmap:
2726 iounmap(adapter->hw.reg);
2727err_free_netdev:
2728 free_netdev(netdev);
2729err_release_pci:
2730 pci_release_regions(pdev);
2731err_disable_device:
2732 pci_disable_device(pdev);
2733 return ret;
2734}
2735
7fc44633 2736static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
77555ee7
MO		 2737 {.vendor = PCI_VENDOR_ID_INTEL,
2738 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2739 .subvendor = PCI_ANY_ID,
2740 .subdevice = PCI_ANY_ID,
2741 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2742 .class_mask = (0xFFFF00)
2743 },
b0e6baf5
T		 2744 {.vendor = PCI_VENDOR_ID_ROHM,
2745 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2746 .subvendor = PCI_ANY_ID,
2747 .subdevice = PCI_ANY_ID,
2748 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2749 .class_mask = (0xFFFF00)
2750 },
7756332f
TO		 2751 {.vendor = PCI_VENDOR_ID_ROHM,
2752 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2753 .subvendor = PCI_ANY_ID,
2754 .subdevice = PCI_ANY_ID,
2755 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2756 .class_mask = (0xFFFF00)
2757 },
77555ee7
MO		 2758 /* required last entry */
2759 {0}
2760};
2761
2762#ifdef CONFIG_PM
2763static const struct dev_pm_ops pch_gbe_pm_ops = {
2764 .suspend = pch_gbe_suspend,
2765 .resume = pch_gbe_resume,
2766 .freeze = pch_gbe_suspend,
2767 .thaw = pch_gbe_resume,
2768 .poweroff = pch_gbe_suspend,
2769 .restore = pch_gbe_resume,
2770};
2771#endif
2772
2773static struct pci_error_handlers pch_gbe_err_handler = {
2774 .error_detected = pch_gbe_io_error_detected,
2775 .slot_reset = pch_gbe_io_slot_reset,
2776 .resume = pch_gbe_io_resume
2777};
2778
f7594d42 2779static struct pci_driver pch_gbe_driver = {
77555ee7
MO		 2780 .name = KBUILD_MODNAME,
2781 .id_table = pch_gbe_pcidev_id,
2782 .probe = pch_gbe_probe,
2783 .remove = pch_gbe_remove,
aa338601 2784#ifdef CONFIG_PM
77555ee7
MO		 2785 .driver.pm = &pch_gbe_pm_ops,
2786#endif
2787 .shutdown = pch_gbe_shutdown,
2788 .err_handler = &pch_gbe_err_handler
2789};
2790
2791
2792static int __init pch_gbe_init_module(void)
2793{
2794 int ret;
2795
f7594d42 2796 ret = pci_register_driver(&pch_gbe_driver);
77555ee7
MO		 2797 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2798 if (copybreak == 0) {
2799 pr_info("copybreak disabled\n");
2800 } else {
2801 pr_info("copybreak enabled for packets <= %u bytes\n",
2802 copybreak);
2803 }
2804 }
2805 return ret;
2806}
2807
2808static void __exit pch_gbe_exit_module(void)
2809{
f7594d42 2810 pci_unregister_driver(&pch_gbe_driver);
77555ee7
MO		 2811}
2812
2813module_init(pch_gbe_init_module);
2814module_exit(pch_gbe_exit_module);
2815
a1dcfcb7 2816MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
1a0bdadb 2817MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
77555ee7
MO		 2818MODULE_LICENSE("GPL");
2819MODULE_VERSION(DRV_VERSION);
2820MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2821
2822module_param(copybreak, uint, 0644);
2823MODULE_PARM_DESC(copybreak,
2824 "Maximum size of packet that is copied to a new buffer on receive");
2825
2826/* pch_gbe_main.c */
Linux kernel - Deliverables
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