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qed: Support B0 instead of A0
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
CommitLineData
fe56b9e6
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <linux/mutex.h>
17#include <linux/pci.h>
18#include <linux/slab.h>
19#include <linux/string.h>
20#include <linux/etherdevice.h>
21#include <linux/qed/qed_chain.h>
22#include <linux/qed/qed_if.h>
23#include "qed.h"
24#include "qed_cxt.h"
25#include "qed_dev_api.h"
26#include "qed_hsi.h"
27#include "qed_hw.h"
28#include "qed_init_ops.h"
29#include "qed_int.h"
30#include "qed_mcp.h"
31#include "qed_reg_addr.h"
32#include "qed_sp.h"
33
34/* API common to all protocols */
c2035eea
RA		 35enum BAR_ID {
36 BAR_ID_0, /* used for GRC */
37 BAR_ID_1 /* Used for doorbells */
38};
39
40static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
41 enum BAR_ID bar_id)
42{
43 u32 bar_reg = (bar_id == BAR_ID_0 ?
44 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
45 u32 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
46
47 if (val)
48 return 1 << (val + 15);
49
50 /* Old MFW initialized above registered only conditionally */
51 if (p_hwfn->cdev->num_hwfns > 1) {
52 DP_INFO(p_hwfn,
53 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
54 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
55 } else {
56 DP_INFO(p_hwfn,
57 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
58 return 512 * 1024;
59 }
60}
61
fe56b9e6
YM		 62void qed_init_dp(struct qed_dev *cdev,
63 u32 dp_module, u8 dp_level)
64{
65 u32 i;
66
67 cdev->dp_level = dp_level;
68 cdev->dp_module = dp_module;
69 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
70 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
71
72 p_hwfn->dp_level = dp_level;
73 p_hwfn->dp_module = dp_module;
74 }
75}
76
77void qed_init_struct(struct qed_dev *cdev)
78{
79 u8 i;
80
81 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
82 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
83
84 p_hwfn->cdev = cdev;
85 p_hwfn->my_id = i;
86 p_hwfn->b_active = false;
87
88 mutex_init(&p_hwfn->dmae_info.mutex);
89 }
90
91 /* hwfn 0 is always active */
92 cdev->hwfns[0].b_active = true;
93
94 /* set the default cache alignment to 128 */
95 cdev->cache_shift = 7;
96}
97
98static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
99{
100 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
101
102 kfree(qm_info->qm_pq_params);
103 qm_info->qm_pq_params = NULL;
104 kfree(qm_info->qm_vport_params);
105 qm_info->qm_vport_params = NULL;
106 kfree(qm_info->qm_port_params);
107 qm_info->qm_port_params = NULL;
108}
109
110void qed_resc_free(struct qed_dev *cdev)
111{
112 int i;
113
114 kfree(cdev->fw_data);
115 cdev->fw_data = NULL;
116
117 kfree(cdev->reset_stats);
118
25c089d7
YM		 119 for_each_hwfn(cdev, i) {
120 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
121
122 kfree(p_hwfn->p_tx_cids);
123 p_hwfn->p_tx_cids = NULL;
124 kfree(p_hwfn->p_rx_cids);
125 p_hwfn->p_rx_cids = NULL;
126 }
127
fe56b9e6
YM		 128 for_each_hwfn(cdev, i) {
129 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
130
131 qed_cxt_mngr_free(p_hwfn);
132 qed_qm_info_free(p_hwfn);
133 qed_spq_free(p_hwfn);
134 qed_eq_free(p_hwfn, p_hwfn->p_eq);
135 qed_consq_free(p_hwfn, p_hwfn->p_consq);
136 qed_int_free(p_hwfn);
137 qed_dmae_info_free(p_hwfn);
138 }
139}
140
141static int qed_init_qm_info(struct qed_hwfn *p_hwfn)
142{
143 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
144 struct init_qm_port_params *p_qm_port;
145 u8 num_vports, i, vport_id, num_ports;
146 u16 num_pqs, multi_cos_tcs = 1;
147
148 memset(qm_info, 0, sizeof(*qm_info));
149
150 num_pqs = multi_cos_tcs + 1; /* The '1' is for pure-LB */
151 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
152
153 /* Sanity checking that setup requires legal number of resources */
154 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
155 DP_ERR(p_hwfn,
156 "Need too many Physical queues - 0x%04x when only %04x are available\n",
157 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
158 return -EINVAL;
159 }
160
161 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
162 */
163 qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
60fffb3b 164 num_pqs, GFP_KERNEL);
fe56b9e6
YM		 165 if (!qm_info->qm_pq_params)
166 goto alloc_err;
167
168 qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
60fffb3b 169 num_vports, GFP_KERNEL);
fe56b9e6
YM		 170 if (!qm_info->qm_vport_params)
171 goto alloc_err;
172
173 qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
60fffb3b 174 MAX_NUM_PORTS, GFP_KERNEL);
fe56b9e6
YM		 175 if (!qm_info->qm_port_params)
176 goto alloc_err;
177
178 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
179
180 /* First init per-TC PQs */
181 for (i = 0; i < multi_cos_tcs; i++) {
182 struct init_qm_pq_params *params = &qm_info->qm_pq_params[i];
183
184 params->vport_id = vport_id;
185 params->tc_id = p_hwfn->hw_info.non_offload_tc;
186 params->wrr_group = 1;
187 }
188
189 /* Then init pure-LB PQ */
190 qm_info->pure_lb_pq = i;
191 qm_info->qm_pq_params[i].vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
192 qm_info->qm_pq_params[i].tc_id = PURE_LB_TC;
193 qm_info->qm_pq_params[i].wrr_group = 1;
194 i++;
195
196 qm_info->offload_pq = 0;
197 qm_info->num_pqs = num_pqs;
198 qm_info->num_vports = num_vports;
199
200 /* Initialize qm port parameters */
201 num_ports = p_hwfn->cdev->num_ports_in_engines;
202 for (i = 0; i < num_ports; i++) {
203 p_qm_port = &qm_info->qm_port_params[i];
204 p_qm_port->active = 1;
205 p_qm_port->num_active_phys_tcs = 4;
206 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
207 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
208 }
209
210 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
211
212 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
213
214 qm_info->start_vport = (u8)RESC_START(p_hwfn, QED_VPORT);
215
216 qm_info->pf_wfq = 0;
217 qm_info->pf_rl = 0;
218 qm_info->vport_rl_en = 1;
219
220 return 0;
221
222alloc_err:
223 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
224 kfree(qm_info->qm_pq_params);
225 kfree(qm_info->qm_vport_params);
226 kfree(qm_info->qm_port_params);
227
228 return -ENOMEM;
229}
230
231int qed_resc_alloc(struct qed_dev *cdev)
232{
233 struct qed_consq *p_consq;
234 struct qed_eq *p_eq;
235 int i, rc = 0;
236
237 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
238 if (!cdev->fw_data)
239 return -ENOMEM;
240
25c089d7
YM		 241 /* Allocate Memory for the Queue->CID mapping */
242 for_each_hwfn(cdev, i) {
243 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
244 int tx_size = sizeof(struct qed_hw_cid_data) *
245 RESC_NUM(p_hwfn, QED_L2_QUEUE);
246 int rx_size = sizeof(struct qed_hw_cid_data) *
247 RESC_NUM(p_hwfn, QED_L2_QUEUE);
248
249 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
250 if (!p_hwfn->p_tx_cids) {
251 DP_NOTICE(p_hwfn,
252 "Failed to allocate memory for Tx Cids\n");
9b15acbf 253 rc = -ENOMEM;
25c089d7
YM		 254 goto alloc_err;
255 }
256
257 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
258 if (!p_hwfn->p_rx_cids) {
259 DP_NOTICE(p_hwfn,
260 "Failed to allocate memory for Rx Cids\n");
9b15acbf 261 rc = -ENOMEM;
25c089d7
YM		 262 goto alloc_err;
263 }
264 }
265
fe56b9e6
YM		 266 for_each_hwfn(cdev, i) {
267 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
268
269 /* First allocate the context manager structure */
270 rc = qed_cxt_mngr_alloc(p_hwfn);
271 if (rc)
272 goto alloc_err;
273
274 /* Set the HW cid/tid numbers (in the contest manager)
275 * Must be done prior to any further computations.
276 */
277 rc = qed_cxt_set_pf_params(p_hwfn);
278 if (rc)
279 goto alloc_err;
280
281 /* Prepare and process QM requirements */
282 rc = qed_init_qm_info(p_hwfn);
283 if (rc)
284 goto alloc_err;
285
286 /* Compute the ILT client partition */
287 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
288 if (rc)
289 goto alloc_err;
290
291 /* CID map / ILT shadow table / T2
292 * The talbes sizes are determined by the computations above
293 */
294 rc = qed_cxt_tables_alloc(p_hwfn);
295 if (rc)
296 goto alloc_err;
297
298 /* SPQ, must follow ILT because initializes SPQ context */
299 rc = qed_spq_alloc(p_hwfn);
300 if (rc)
301 goto alloc_err;
302
303 /* SP status block allocation */
304 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
305 RESERVED_PTT_DPC);
306
307 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
308 if (rc)
309 goto alloc_err;
310
311 /* EQ */
312 p_eq = qed_eq_alloc(p_hwfn, 256);
9b15acbf
DC		 313 if (!p_eq) {
314 rc = -ENOMEM;
fe56b9e6 315 goto alloc_err;
9b15acbf 316 }
fe56b9e6
YM		 317 p_hwfn->p_eq = p_eq;
318
319 p_consq = qed_consq_alloc(p_hwfn);
9b15acbf
DC		 320 if (!p_consq) {
321 rc = -ENOMEM;
fe56b9e6 322 goto alloc_err;
9b15acbf 323 }
fe56b9e6
YM		 324 p_hwfn->p_consq = p_consq;
325
326 /* DMA info initialization */
327 rc = qed_dmae_info_alloc(p_hwfn);
328 if (rc) {
329 DP_NOTICE(p_hwfn,
330 "Failed to allocate memory for dmae_info structure\n");
331 goto alloc_err;
332 }
333 }
334
335 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
336 if (!cdev->reset_stats) {
337 DP_NOTICE(cdev, "Failed to allocate reset statistics\n");
9b15acbf 338 rc = -ENOMEM;
fe56b9e6
YM		 339 goto alloc_err;
340 }
341
342 return 0;
343
344alloc_err:
345 qed_resc_free(cdev);
346 return rc;
347}
348
349void qed_resc_setup(struct qed_dev *cdev)
350{
351 int i;
352
353 for_each_hwfn(cdev, i) {
354 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
355
356 qed_cxt_mngr_setup(p_hwfn);
357 qed_spq_setup(p_hwfn);
358 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
359 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
360
361 /* Read shadow of current MFW mailbox */
362 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
363 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
364 p_hwfn->mcp_info->mfw_mb_cur,
365 p_hwfn->mcp_info->mfw_mb_length);
366
367 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
368 }
369}
370
fe56b9e6
YM		 371#define FINAL_CLEANUP_POLL_CNT (100)
372#define FINAL_CLEANUP_POLL_TIME (10)
373int qed_final_cleanup(struct qed_hwfn *p_hwfn,
374 struct qed_ptt *p_ptt,
375 u16 id)
376{
377 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
378 int rc = -EBUSY;
379
fc48b7a6
YM		 380 addr = GTT_BAR0_MAP_REG_USDM_RAM +
381 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
fe56b9e6 382
fc48b7a6
YM		 383 command |= X_FINAL_CLEANUP_AGG_INT <<
384 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
385 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
386 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
387 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
fe56b9e6
YM		 388
389 /* Make sure notification is not set before initiating final cleanup */
390 if (REG_RD(p_hwfn, addr)) {
391 DP_NOTICE(
392 p_hwfn,
393 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
394 REG_WR(p_hwfn, addr, 0);
395 }
396
397 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
398 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
399 id, command);
400
401 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
402
403 /* Poll until completion */
404 while (!REG_RD(p_hwfn, addr) && count--)
405 msleep(FINAL_CLEANUP_POLL_TIME);
406
407 if (REG_RD(p_hwfn, addr))
408 rc = 0;
409 else
410 DP_NOTICE(p_hwfn,
411 "Failed to receive FW final cleanup notification\n");
412
413 /* Cleanup afterwards */
414 REG_WR(p_hwfn, addr, 0);
415
416 return rc;
417}
418
419static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
420{
421 int hw_mode = 0;
422
12e09c69 423 hw_mode = (1 << MODE_BB_B0);
fe56b9e6
YM		 424
425 switch (p_hwfn->cdev->num_ports_in_engines) {
426 case 1:
427 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
428 break;
429 case 2:
430 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
431 break;
432 case 4:
433 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
434 break;
435 default:
436 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
437 p_hwfn->cdev->num_ports_in_engines);
438 return;
439 }
440
441 switch (p_hwfn->cdev->mf_mode) {
fc48b7a6
YM		 442 case QED_MF_DEFAULT:
443 case QED_MF_NPAR:
444 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6 445 break;
fc48b7a6 446 case QED_MF_OVLAN:
fe56b9e6
YM		 447 hw_mode |= 1 << MODE_MF_SD;
448 break;
fe56b9e6 449 default:
fc48b7a6
YM		 450 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
451 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6
YM		 452 }
453
454 hw_mode |= 1 << MODE_ASIC;
455
456 p_hwfn->hw_info.hw_mode = hw_mode;
457}
458
459/* Init run time data for all PFs on an engine. */
460static void qed_init_cau_rt_data(struct qed_dev *cdev)
461{
462 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
463 int i, sb_id;
464
465 for_each_hwfn(cdev, i) {
466 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
467 struct qed_igu_info *p_igu_info;
468 struct qed_igu_block *p_block;
469 struct cau_sb_entry sb_entry;
470
471 p_igu_info = p_hwfn->hw_info.p_igu_info;
472
473 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
474 sb_id++) {
475 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
476 if (!p_block->is_pf)
477 continue;
478
479 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
480 p_block->function_id,
481 0, 0);
482 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2,
483 sb_entry);
484 }
485 }
486}
487
488static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
489 struct qed_ptt *p_ptt,
490 int hw_mode)
491{
492 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
493 struct qed_qm_common_rt_init_params params;
494 struct qed_dev *cdev = p_hwfn->cdev;
495 int rc = 0;
496
497 qed_init_cau_rt_data(cdev);
498
499 /* Program GTT windows */
500 qed_gtt_init(p_hwfn);
501
502 if (p_hwfn->mcp_info) {
503 if (p_hwfn->mcp_info->func_info.bandwidth_max)
504 qm_info->pf_rl_en = 1;
505 if (p_hwfn->mcp_info->func_info.bandwidth_min)
506 qm_info->pf_wfq_en = 1;
507 }
508
509 memset(&params, 0, sizeof(params));
510 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
511 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
512 params.pf_rl_en = qm_info->pf_rl_en;
513 params.pf_wfq_en = qm_info->pf_wfq_en;
514 params.vport_rl_en = qm_info->vport_rl_en;
515 params.vport_wfq_en = qm_info->vport_wfq_en;
516 params.port_params = qm_info->qm_port_params;
517
518 qed_qm_common_rt_init(p_hwfn, &params);
519
520 qed_cxt_hw_init_common(p_hwfn);
521
522 /* Close gate from NIG to BRB/Storm; By default they are open, but
523 * we close them to prevent NIG from passing data to reset blocks.
524 * Should have been done in the ENGINE phase, but init-tool lacks
525 * proper port-pretend capabilities.
526 */
527 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
528 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
529 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
530 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
531 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
532 qed_port_unpretend(p_hwfn, p_ptt);
533
534 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
535 if (rc != 0)
536 return rc;
537
538 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
539 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
540
541 /* Disable relaxed ordering in the PCI config space */
542 qed_wr(p_hwfn, p_ptt, 0x20b4,
543 qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
544
545 return rc;
546}
547
548static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
549 struct qed_ptt *p_ptt,
550 int hw_mode)
551{
552 int rc = 0;
553
554 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
555 hw_mode);
556 return rc;
557}
558
559static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
560 struct qed_ptt *p_ptt,
561 int hw_mode,
562 bool b_hw_start,
563 enum qed_int_mode int_mode,
564 bool allow_npar_tx_switch)
565{
566 u8 rel_pf_id = p_hwfn->rel_pf_id;
567 int rc = 0;
568
569 if (p_hwfn->mcp_info) {
570 struct qed_mcp_function_info *p_info;
571
572 p_info = &p_hwfn->mcp_info->func_info;
573 if (p_info->bandwidth_min)
574 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
575
576 /* Update rate limit once we'll actually have a link */
577 p_hwfn->qm_info.pf_rl = 100;
578 }
579
580 qed_cxt_hw_init_pf(p_hwfn);
581
582 qed_int_igu_init_rt(p_hwfn);
583
584 /* Set VLAN in NIG if needed */
585 if (hw_mode & (1 << MODE_MF_SD)) {
586 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
587 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
588 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
589 p_hwfn->hw_info.ovlan);
590 }
591
592 /* Enable classification by MAC if needed */
87aec47d 593 if (hw_mode & (1 << MODE_MF_SI)) {
fe56b9e6
YM		 594 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
595 "Configuring TAGMAC_CLS_TYPE\n");
596 STORE_RT_REG(p_hwfn,
597 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
598 }
599
600 /* Protocl Configuration */
601 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
602 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
603 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
604
605 /* Cleanup chip from previous driver if such remains exist */
606 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id);
607 if (rc != 0)
608 return rc;
609
610 /* PF Init sequence */
611 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
612 if (rc)
613 return rc;
614
615 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
616 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
617 if (rc)
618 return rc;
619
620 /* Pure runtime initializations - directly to the HW */
621 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
622
623 if (b_hw_start) {
624 /* enable interrupts */
625 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
626
627 /* send function start command */
628 rc = qed_sp_pf_start(p_hwfn, p_hwfn->cdev->mf_mode);
629 if (rc)
630 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
631 }
632 return rc;
633}
634
635static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
636 struct qed_ptt *p_ptt,
637 u8 enable)
638{
639 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
640
641 /* Change PF in PXP */
642 qed_wr(p_hwfn, p_ptt,
643 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
644
645 /* wait until value is set - try for 1 second every 50us */
646 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
647 val = qed_rd(p_hwfn, p_ptt,
648 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
649 if (val == set_val)
650 break;
651
652 usleep_range(50, 60);
653 }
654
655 if (val != set_val) {
656 DP_NOTICE(p_hwfn,
657 "PFID_ENABLE_MASTER wasn't changed after a second\n");
658 return -EAGAIN;
659 }
660
661 return 0;
662}
663
664static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
665 struct qed_ptt *p_main_ptt)
666{
667 /* Read shadow of current MFW mailbox */
668 qed_mcp_read_mb(p_hwfn, p_main_ptt);
669 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
670 p_hwfn->mcp_info->mfw_mb_cur,
671 p_hwfn->mcp_info->mfw_mb_length);
672}
673
674int qed_hw_init(struct qed_dev *cdev,
675 bool b_hw_start,
676 enum qed_int_mode int_mode,
677 bool allow_npar_tx_switch,
678 const u8 *bin_fw_data)
679{
9df2ed04
MC		 680 struct qed_storm_stats *p_stat;
681 u32 load_code, param, *p_address;
fe56b9e6 682 int rc, mfw_rc, i;
9df2ed04 683 u8 fw_vport = 0;
fe56b9e6
YM		 684
685 rc = qed_init_fw_data(cdev, bin_fw_data);
686 if (rc != 0)
687 return rc;
688
689 for_each_hwfn(cdev, i) {
690 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
691
9df2ed04
MC		 692 rc = qed_fw_vport(p_hwfn, 0, &fw_vport);
693 if (rc != 0)
694 return rc;
695
fe56b9e6
YM		 696 /* Enable DMAE in PXP */
697 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
698
699 qed_calc_hw_mode(p_hwfn);
700
701 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
702 &load_code);
703 if (rc) {
704 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
705 return rc;
706 }
707
708 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
709
710 DP_VERBOSE(p_hwfn, QED_MSG_SP,
711 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
712 rc, load_code);
713
714 p_hwfn->first_on_engine = (load_code ==
715 FW_MSG_CODE_DRV_LOAD_ENGINE);
716
717 switch (load_code) {
718 case FW_MSG_CODE_DRV_LOAD_ENGINE:
719 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
720 p_hwfn->hw_info.hw_mode);
721 if (rc)
722 break;
723 /* Fall into */
724 case FW_MSG_CODE_DRV_LOAD_PORT:
725 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
726 p_hwfn->hw_info.hw_mode);
727 if (rc)
728 break;
729
730 /* Fall into */
731 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
732 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
733 p_hwfn->hw_info.hw_mode,
734 b_hw_start, int_mode,
735 allow_npar_tx_switch);
736 break;
737 default:
738 rc = -EINVAL;
739 break;
740 }
741
742 if (rc)
743 DP_NOTICE(p_hwfn,
744 "init phase failed for loadcode 0x%x (rc %d)\n",
745 load_code, rc);
746
747 /* ACK mfw regardless of success or failure of initialization */
748 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
749 DRV_MSG_CODE_LOAD_DONE,
750 0, &load_code, &param);
751 if (rc)
752 return rc;
753 if (mfw_rc) {
754 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
755 return mfw_rc;
756 }
757
758 p_hwfn->hw_init_done = true;
9df2ed04
MC		 759
760 /* init PF stats */
761 p_stat = &p_hwfn->storm_stats;
762 p_stat->mstats.address = BAR0_MAP_REG_MSDM_RAM +
763 MSTORM_QUEUE_STAT_OFFSET(fw_vport);
764 p_stat->mstats.len = sizeof(struct eth_mstorm_per_queue_stat);
765
766 p_stat->ustats.address = BAR0_MAP_REG_USDM_RAM +
767 USTORM_QUEUE_STAT_OFFSET(fw_vport);
768 p_stat->ustats.len = sizeof(struct eth_ustorm_per_queue_stat);
769
770 p_stat->pstats.address = BAR0_MAP_REG_PSDM_RAM +
771 PSTORM_QUEUE_STAT_OFFSET(fw_vport);
772 p_stat->pstats.len = sizeof(struct eth_pstorm_per_queue_stat);
773
774 p_address = &p_stat->tstats.address;
775 *p_address = BAR0_MAP_REG_TSDM_RAM +
776 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
777 p_stat->tstats.len = sizeof(struct tstorm_per_port_stat);
fe56b9e6
YM		 778 }
779
780 return 0;
781}
782
783#define QED_HW_STOP_RETRY_LIMIT (10)
784int qed_hw_stop(struct qed_dev *cdev)
785{
786 int rc = 0, t_rc;
787 int i, j;
788
789 for_each_hwfn(cdev, j) {
790 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
791 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
792
793 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
794
795 /* mark the hw as uninitialized... */
796 p_hwfn->hw_init_done = false;
797
798 rc = qed_sp_pf_stop(p_hwfn);
799 if (rc)
800 return rc;
801
802 qed_wr(p_hwfn, p_ptt,
803 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
804
805 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
806 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
807 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
808 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
809 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
810
811 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
812 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
813 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
814 if ((!qed_rd(p_hwfn, p_ptt,
815 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
816 (!qed_rd(p_hwfn, p_ptt,
817 TM_REG_PF_SCAN_ACTIVE_TASK)))
818 break;
819
820 usleep_range(1000, 2000);
821 }
822 if (i == QED_HW_STOP_RETRY_LIMIT)
823 DP_NOTICE(p_hwfn,
824 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
825 (u8)qed_rd(p_hwfn, p_ptt,
826 TM_REG_PF_SCAN_ACTIVE_CONN),
827 (u8)qed_rd(p_hwfn, p_ptt,
828 TM_REG_PF_SCAN_ACTIVE_TASK));
829
830 /* Disable Attention Generation */
831 qed_int_igu_disable_int(p_hwfn, p_ptt);
832
833 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
834 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
835
836 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
837
838 /* Need to wait 1ms to guarantee SBs are cleared */
839 usleep_range(1000, 2000);
840 }
841
842 /* Disable DMAE in PXP - in CMT, this should only be done for
843 * first hw-function, and only after all transactions have
844 * stopped for all active hw-functions.
845 */
846 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
847 cdev->hwfns[0].p_main_ptt,
848 false);
849 if (t_rc != 0)
850 rc = t_rc;
851
852 return rc;
853}
854
cee4d264
MC		 855void qed_hw_stop_fastpath(struct qed_dev *cdev)
856{
857 int i, j;
858
859 for_each_hwfn(cdev, j) {
860 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
861 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
862
863 DP_VERBOSE(p_hwfn,
864 NETIF_MSG_IFDOWN,
865 "Shutting down the fastpath\n");
866
867 qed_wr(p_hwfn, p_ptt,
868 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
869
870 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
871 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
872 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
873 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
874 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
875
876 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
877 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
878 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
879 if ((!qed_rd(p_hwfn, p_ptt,
880 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
881 (!qed_rd(p_hwfn, p_ptt,
882 TM_REG_PF_SCAN_ACTIVE_TASK)))
883 break;
884
885 usleep_range(1000, 2000);
886 }
887 if (i == QED_HW_STOP_RETRY_LIMIT)
888 DP_NOTICE(p_hwfn,
889 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
890 (u8)qed_rd(p_hwfn, p_ptt,
891 TM_REG_PF_SCAN_ACTIVE_CONN),
892 (u8)qed_rd(p_hwfn, p_ptt,
893 TM_REG_PF_SCAN_ACTIVE_TASK));
894
895 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
896
897 /* Need to wait 1ms to guarantee SBs are cleared */
898 usleep_range(1000, 2000);
899 }
900}
901
902void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
903{
904 /* Re-open incoming traffic */
905 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
906 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
907}
908
fe56b9e6
YM		 909static int qed_reg_assert(struct qed_hwfn *hwfn,
910 struct qed_ptt *ptt, u32 reg,
911 bool expected)
912{
913 u32 assert_val = qed_rd(hwfn, ptt, reg);
914
915 if (assert_val != expected) {
916 DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n",
917 reg, expected);
918 return -EINVAL;
919 }
920
921 return 0;
922}
923
924int qed_hw_reset(struct qed_dev *cdev)
925{
926 int rc = 0;
927 u32 unload_resp, unload_param;
928 int i;
929
930 for_each_hwfn(cdev, i) {
931 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
932
933 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
934
935 /* Check for incorrect states */
936 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
937 QM_REG_USG_CNT_PF_TX, 0);
938 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
939 QM_REG_USG_CNT_PF_OTHER, 0);
940
941 /* Disable PF in HW blocks */
942 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
943 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
944 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
945 TCFC_REG_STRONG_ENABLE_PF, 0);
946 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
947 CCFC_REG_STRONG_ENABLE_PF, 0);
948
949 /* Send unload command to MCP */
950 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
951 DRV_MSG_CODE_UNLOAD_REQ,
952 DRV_MB_PARAM_UNLOAD_WOL_MCP,
953 &unload_resp, &unload_param);
954 if (rc) {
955 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
956 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
957 }
958
959 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
960 DRV_MSG_CODE_UNLOAD_DONE,
961 0, &unload_resp, &unload_param);
962 if (rc) {
963 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
964 return rc;
965 }
966 }
967
968 return rc;
969}
970
971/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
972static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
973{
974 qed_ptt_pool_free(p_hwfn);
975 kfree(p_hwfn->hw_info.p_igu_info);
976}
977
978/* Setup bar access */
12e09c69 979static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
fe56b9e6 980{
fe56b9e6
YM		 981 /* clear indirect access */
982 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
983 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
984 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
985 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
986
987 /* Clean Previous errors if such exist */
988 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
989 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
990 1 << p_hwfn->abs_pf_id);
991
992 /* enable internal target-read */
993 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
994 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
fe56b9e6
YM		 995}
996
997static void get_function_id(struct qed_hwfn *p_hwfn)
998{
999 /* ME Register */
1000 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR);
1001
1002 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1003
1004 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1005 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1006 PXP_CONCRETE_FID_PFID);
1007 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1008 PXP_CONCRETE_FID_PORT);
1009}
1010
25c089d7
YM		 1011static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1012{
1013 u32 *feat_num = p_hwfn->hw_info.feat_num;
1014 int num_features = 1;
1015
1016 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1017 num_features,
1018 RESC_NUM(p_hwfn, QED_L2_QUEUE));
1019 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1020 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1021 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1022 num_features);
1023}
1024
fe56b9e6
YM		 1025static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1026{
1027 u32 *resc_start = p_hwfn->hw_info.resc_start;
1028 u32 *resc_num = p_hwfn->hw_info.resc_num;
4ac801b7 1029 struct qed_sb_cnt_info sb_cnt_info;
fe56b9e6
YM		 1030 int num_funcs, i;
1031
fc48b7a6 1032 num_funcs = MAX_NUM_PFS_BB;
fe56b9e6 1033
4ac801b7
YM		 1034 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1035 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1036
fe56b9e6
YM		 1037 resc_num[QED_SB] = min_t(u32,
1038 (MAX_SB_PER_PATH_BB / num_funcs),
4ac801b7 1039 sb_cnt_info.sb_cnt);
25c089d7 1040 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
fe56b9e6 1041 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
25c089d7 1042 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
fe56b9e6
YM		 1043 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1044 resc_num[QED_RL] = 8;
25c089d7
YM		 1045 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1046 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1047 num_funcs;
fe56b9e6
YM		 1048 resc_num[QED_ILT] = 950;
1049
1050 for (i = 0; i < QED_MAX_RESC; i++)
1051 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1052
25c089d7
YM		 1053 qed_hw_set_feat(p_hwfn);
1054
fe56b9e6
YM		 1055 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1056 "The numbers for each resource are:\n"
1057 "SB = %d start = %d\n"
25c089d7 1058 "L2_QUEUE = %d start = %d\n"
fe56b9e6
YM		 1059 "VPORT = %d start = %d\n"
1060 "PQ = %d start = %d\n"
1061 "RL = %d start = %d\n"
25c089d7
YM		 1062 "MAC = %d start = %d\n"
1063 "VLAN = %d start = %d\n"
fe56b9e6
YM		 1064 "ILT = %d start = %d\n",
1065 p_hwfn->hw_info.resc_num[QED_SB],
1066 p_hwfn->hw_info.resc_start[QED_SB],
25c089d7
YM		 1067 p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1068 p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
fe56b9e6
YM		 1069 p_hwfn->hw_info.resc_num[QED_VPORT],
1070 p_hwfn->hw_info.resc_start[QED_VPORT],
1071 p_hwfn->hw_info.resc_num[QED_PQ],
1072 p_hwfn->hw_info.resc_start[QED_PQ],
1073 p_hwfn->hw_info.resc_num[QED_RL],
1074 p_hwfn->hw_info.resc_start[QED_RL],
25c089d7
YM		 1075 p_hwfn->hw_info.resc_num[QED_MAC],
1076 p_hwfn->hw_info.resc_start[QED_MAC],
1077 p_hwfn->hw_info.resc_num[QED_VLAN],
1078 p_hwfn->hw_info.resc_start[QED_VLAN],
fe56b9e6
YM		 1079 p_hwfn->hw_info.resc_num[QED_ILT],
1080 p_hwfn->hw_info.resc_start[QED_ILT]);
1081}
1082
1083static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
1084 struct qed_ptt *p_ptt)
1085{
cc875c2e 1086 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
fc48b7a6 1087 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
cc875c2e 1088 struct qed_mcp_link_params *link;
fe56b9e6
YM		 1089
1090 /* Read global nvm_cfg address */
1091 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1092
1093 /* Verify MCP has initialized it */
1094 if (!nvm_cfg_addr) {
1095 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1096 return -EINVAL;
1097 }
1098
1099 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1100 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1101
1102 /* Read Vendor Id / Device Id */
1103 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1104 offsetof(struct nvm_cfg1, glob) +
1105 offsetof(struct nvm_cfg1_glob, pci_id);
1106 p_hwfn->hw_info.vendor_id = qed_rd(p_hwfn, p_ptt, addr) &
1107 NVM_CFG1_GLOB_VENDOR_ID_MASK;
cc875c2e
YM		 1108
1109 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1110 offsetof(struct nvm_cfg1, glob) +
1111 offsetof(struct nvm_cfg1_glob, core_cfg);
1112
1113 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1114
1115 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1116 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1117 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1118 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1119 break;
1120 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1121 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1122 break;
1123 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1124 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1125 break;
1126 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1127 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1128 break;
1129 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1130 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1131 break;
1132 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1133 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1134 break;
1135 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1136 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1137 break;
1138 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1139 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1140 break;
1141 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1142 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1143 break;
1144 default:
1145 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n",
1146 core_cfg);
1147 break;
1148 }
1149
cc875c2e
YM		 1150 /* Read default link configuration */
1151 link = &p_hwfn->mcp_info->link_input;
1152 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1153 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1154 link_temp = qed_rd(p_hwfn, p_ptt,
1155 port_cfg_addr +
1156 offsetof(struct nvm_cfg1_port, speed_cap_mask));
1157 link->speed.advertised_speeds =
1158 link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1159
1160 p_hwfn->mcp_info->link_capabilities.speed_capabilities =
1161 link->speed.advertised_speeds;
1162
1163 link_temp = qed_rd(p_hwfn, p_ptt,
1164 port_cfg_addr +
1165 offsetof(struct nvm_cfg1_port, link_settings));
1166 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1167 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1168 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1169 link->speed.autoneg = true;
1170 break;
1171 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1172 link->speed.forced_speed = 1000;
1173 break;
1174 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1175 link->speed.forced_speed = 10000;
1176 break;
1177 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1178 link->speed.forced_speed = 25000;
1179 break;
1180 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1181 link->speed.forced_speed = 40000;
1182 break;
1183 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1184 link->speed.forced_speed = 50000;
1185 break;
1186 case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1187 link->speed.forced_speed = 100000;
1188 break;
1189 default:
1190 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n",
1191 link_temp);
1192 }
1193
1194 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1195 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1196 link->pause.autoneg = !!(link_temp &
1197 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1198 link->pause.forced_rx = !!(link_temp &
1199 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1200 link->pause.forced_tx = !!(link_temp &
1201 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1202 link->loopback_mode = 0;
1203
1204 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1205 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1206 link->speed.forced_speed, link->speed.advertised_speeds,
1207 link->speed.autoneg, link->pause.autoneg);
1208
fe56b9e6
YM		 1209 /* Read Multi-function information from shmem */
1210 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1211 offsetof(struct nvm_cfg1, glob) +
1212 offsetof(struct nvm_cfg1_glob, generic_cont0);
1213
1214 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1215
1216 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1217 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1218
1219 switch (mf_mode) {
1220 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
fc48b7a6 1221 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
fe56b9e6
YM		 1222 break;
1223 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
fc48b7a6 1224 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
fe56b9e6 1225 break;
fc48b7a6
YM		 1226 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1227 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
fe56b9e6
YM		 1228 break;
1229 }
1230 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1231 p_hwfn->cdev->mf_mode);
1232
fc48b7a6
YM		 1233 /* Read Multi-function information from shmem */
1234 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1235 offsetof(struct nvm_cfg1, glob) +
1236 offsetof(struct nvm_cfg1_glob, device_capabilities);
1237
1238 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1239 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1240 __set_bit(QED_DEV_CAP_ETH,
1241 &p_hwfn->hw_info.device_capabilities);
1242
fe56b9e6
YM		 1243 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1244}
1245
1246static int
1247qed_get_hw_info(struct qed_hwfn *p_hwfn,
1248 struct qed_ptt *p_ptt,
1249 enum qed_pci_personality personality)
1250{
1251 u32 port_mode;
1252 int rc;
1253
1254 /* Read the port mode */
1255 port_mode = qed_rd(p_hwfn, p_ptt,
1256 CNIG_REG_NW_PORT_MODE_BB_B0);
1257
1258 if (port_mode < 3) {
1259 p_hwfn->cdev->num_ports_in_engines = 1;
1260 } else if (port_mode <= 5) {
1261 p_hwfn->cdev->num_ports_in_engines = 2;
1262 } else {
1263 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1264 p_hwfn->cdev->num_ports_in_engines);
1265
1266 /* Default num_ports_in_engines to something */
1267 p_hwfn->cdev->num_ports_in_engines = 1;
1268 }
1269
1270 qed_hw_get_nvm_info(p_hwfn, p_ptt);
1271
1272 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1273 if (rc)
1274 return rc;
1275
1276 if (qed_mcp_is_init(p_hwfn))
1277 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1278 p_hwfn->mcp_info->func_info.mac);
1279 else
1280 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1281
1282 if (qed_mcp_is_init(p_hwfn)) {
1283 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1284 p_hwfn->hw_info.ovlan =
1285 p_hwfn->mcp_info->func_info.ovlan;
1286
1287 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1288 }
1289
1290 if (qed_mcp_is_init(p_hwfn)) {
1291 enum qed_pci_personality protocol;
1292
1293 protocol = p_hwfn->mcp_info->func_info.protocol;
1294 p_hwfn->hw_info.personality = protocol;
1295 }
1296
1297 qed_hw_get_resc(p_hwfn);
1298
1299 return rc;
1300}
1301
12e09c69 1302static int qed_get_dev_info(struct qed_dev *cdev)
fe56b9e6 1303{
fc48b7a6 1304 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 1305 u32 tmp;
1306
fc48b7a6
YM		 1307 /* Read Vendor Id / Device Id */
1308 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID,
1309 &cdev->vendor_id);
1310 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID,
1311 &cdev->device_id);
1312 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6 1313 MISCS_REG_CHIP_NUM);
fc48b7a6 1314 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1315 MISCS_REG_CHIP_REV);
1316 MASK_FIELD(CHIP_REV, cdev->chip_rev);
1317
fc48b7a6 1318 cdev->type = QED_DEV_TYPE_BB;
fe56b9e6 1319 /* Learn number of HW-functions */
fc48b7a6 1320 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1321 MISCS_REG_CMT_ENABLED_FOR_PAIR);
1322
fc48b7a6 1323 if (tmp & (1 << p_hwfn->rel_pf_id)) {
fe56b9e6
YM		 1324 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1325 cdev->num_hwfns = 2;
1326 } else {
1327 cdev->num_hwfns = 1;
1328 }
1329
fc48b7a6 1330 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1331 MISCS_REG_CHIP_TEST_REG) >> 4;
1332 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
fc48b7a6 1333 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1334 MISCS_REG_CHIP_METAL);
1335 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1336
1337 DP_INFO(cdev->hwfns,
1338 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1339 cdev->chip_num, cdev->chip_rev,
1340 cdev->chip_bond_id, cdev->chip_metal);
12e09c69
YM		 1341
1342 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1343 DP_NOTICE(cdev->hwfns,
1344 "The chip type/rev (BB A0) is not supported!\n");
1345 return -EINVAL;
1346 }
1347
1348 return 0;
fe56b9e6
YM		 1349}
1350
1351static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1352 void __iomem *p_regview,
1353 void __iomem *p_doorbells,
1354 enum qed_pci_personality personality)
1355{
1356 int rc = 0;
1357
1358 /* Split PCI bars evenly between hwfns */
1359 p_hwfn->regview = p_regview;
1360 p_hwfn->doorbells = p_doorbells;
1361
1362 /* Validate that chip access is feasible */
1363 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1364 DP_ERR(p_hwfn,
1365 "Reading the ME register returns all Fs; Preventing further chip access\n");
1366 return -EINVAL;
1367 }
1368
1369 get_function_id(p_hwfn);
1370
12e09c69
YM		 1371 /* Allocate PTT pool */
1372 rc = qed_ptt_pool_alloc(p_hwfn);
fe56b9e6
YM		 1373 if (rc) {
1374 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n");
1375 goto err0;
1376 }
1377
12e09c69
YM		 1378 /* Allocate the main PTT */
1379 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1380
fe56b9e6 1381 /* First hwfn learns basic information, e.g., number of hwfns */
12e09c69
YM		 1382 if (!p_hwfn->my_id) {
1383 rc = qed_get_dev_info(p_hwfn->cdev);
1384 if (rc != 0)
1385 goto err1;
1386 }
1387
1388 qed_hw_hwfn_prepare(p_hwfn);
fe56b9e6
YM		 1389
1390 /* Initialize MCP structure */
1391 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1392 if (rc) {
1393 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1394 goto err1;
1395 }
1396
1397 /* Read the device configuration information from the HW and SHMEM */
1398 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1399 if (rc) {
1400 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1401 goto err2;
1402 }
1403
1404 /* Allocate the init RT array and initialize the init-ops engine */
1405 rc = qed_init_alloc(p_hwfn);
1406 if (rc) {
1407 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n");
1408 goto err2;
1409 }
1410
1411 return rc;
1412err2:
1413 qed_mcp_free(p_hwfn);
1414err1:
1415 qed_hw_hwfn_free(p_hwfn);
1416err0:
1417 return rc;
1418}
1419
fe56b9e6
YM		 1420int qed_hw_prepare(struct qed_dev *cdev,
1421 int personality)
1422{
c78df14e
AE		 1423 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1424 int rc;
fe56b9e6
YM		 1425
1426 /* Store the precompiled init data ptrs */
1427 qed_init_iro_array(cdev);
1428
1429 /* Initialize the first hwfn - will learn number of hwfns */
c78df14e
AE		 1430 rc = qed_hw_prepare_single(p_hwfn,
1431 cdev->regview,
fe56b9e6
YM		 1432 cdev->doorbells, personality);
1433 if (rc)
1434 return rc;
1435
c78df14e 1436 personality = p_hwfn->hw_info.personality;
fe56b9e6
YM		 1437
1438 /* Initialize the rest of the hwfns */
c78df14e 1439 if (cdev->num_hwfns > 1) {
fe56b9e6 1440 void __iomem *p_regview, *p_doorbell;
c78df14e
AE		 1441 u8 __iomem *addr;
1442
1443 /* adjust bar offset for second engine */
c2035eea 1444 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
c78df14e 1445 p_regview = addr;
fe56b9e6 1446
c78df14e 1447 /* adjust doorbell bar offset for second engine */
c2035eea 1448 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
c78df14e
AE		 1449 p_doorbell = addr;
1450
1451 /* prepare second hw function */
1452 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
fe56b9e6 1453 p_doorbell, personality);
c78df14e
AE		 1454
1455 /* in case of error, need to free the previously
1456 * initiliazed hwfn 0.
1457 */
fe56b9e6 1458 if (rc) {
c78df14e
AE		 1459 qed_init_free(p_hwfn);
1460 qed_mcp_free(p_hwfn);
1461 qed_hw_hwfn_free(p_hwfn);
fe56b9e6
YM		 1462 }
1463 }
1464
c78df14e 1465 return rc;
fe56b9e6
YM		 1466}
1467
1468void qed_hw_remove(struct qed_dev *cdev)
1469{
1470 int i;
1471
1472 for_each_hwfn(cdev, i) {
1473 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1474
1475 qed_init_free(p_hwfn);
1476 qed_hw_hwfn_free(p_hwfn);
1477 qed_mcp_free(p_hwfn);
1478 }
1479}
1480
1481int qed_chain_alloc(struct qed_dev *cdev,
1482 enum qed_chain_use_mode intended_use,
1483 enum qed_chain_mode mode,
1484 u16 num_elems,
1485 size_t elem_size,
1486 struct qed_chain *p_chain)
1487{
1488 dma_addr_t p_pbl_phys = 0;
1489 void *p_pbl_virt = NULL;
1490 dma_addr_t p_phys = 0;
1491 void *p_virt = NULL;
1492 u16 page_cnt = 0;
1493 size_t size;
1494
1495 if (mode == QED_CHAIN_MODE_SINGLE)
1496 page_cnt = 1;
1497 else
1498 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
1499
1500 size = page_cnt * QED_CHAIN_PAGE_SIZE;
1501 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1502 size, &p_phys, GFP_KERNEL);
1503 if (!p_virt) {
1504 DP_NOTICE(cdev, "Failed to allocate chain mem\n");
1505 goto nomem;
1506 }
1507
1508 if (mode == QED_CHAIN_MODE_PBL) {
1509 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1510 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
1511 size, &p_pbl_phys,
1512 GFP_KERNEL);
1513 if (!p_pbl_virt) {
1514 DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n");
1515 goto nomem;
1516 }
1517
1518 qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt,
1519 (u8)elem_size, intended_use,
1520 p_pbl_phys, p_pbl_virt);
1521 } else {
1522 qed_chain_init(p_chain, p_virt, p_phys, page_cnt,
1523 (u8)elem_size, intended_use, mode);
1524 }
1525
1526 return 0;
1527
1528nomem:
1529 dma_free_coherent(&cdev->pdev->dev,
1530 page_cnt * QED_CHAIN_PAGE_SIZE,
1531 p_virt, p_phys);
1532 dma_free_coherent(&cdev->pdev->dev,
1533 page_cnt * QED_CHAIN_PBL_ENTRY_SIZE,
1534 p_pbl_virt, p_pbl_phys);
1535
1536 return -ENOMEM;
1537}
1538
1539void qed_chain_free(struct qed_dev *cdev,
1540 struct qed_chain *p_chain)
1541{
1542 size_t size;
1543
1544 if (!p_chain->p_virt_addr)
1545 return;
1546
1547 if (p_chain->mode == QED_CHAIN_MODE_PBL) {
1548 size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1549 dma_free_coherent(&cdev->pdev->dev, size,
1550 p_chain->pbl.p_virt_table,
1551 p_chain->pbl.p_phys_table);
1552 }
1553
1554 size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE;
1555 dma_free_coherent(&cdev->pdev->dev, size,
1556 p_chain->p_virt_addr,
1557 p_chain->p_phys_addr);
1558}
cee4d264 1559
9df2ed04
MC		 1560static void __qed_get_vport_stats(struct qed_dev *cdev,
1561 struct qed_eth_stats *stats)
1562{
1563 int i, j;
1564
1565 memset(stats, 0, sizeof(*stats));
1566
1567 for_each_hwfn(cdev, i) {
1568 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1569 struct eth_mstorm_per_queue_stat mstats;
1570 struct eth_ustorm_per_queue_stat ustats;
1571 struct eth_pstorm_per_queue_stat pstats;
1572 struct tstorm_per_port_stat tstats;
1573 struct port_stats port_stats;
1574 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1575
1576 if (!p_ptt) {
1577 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1578 continue;
1579 }
1580
1581 memset(&mstats, 0, sizeof(mstats));
1582 qed_memcpy_from(p_hwfn, p_ptt, &mstats,
1583 p_hwfn->storm_stats.mstats.address,
1584 p_hwfn->storm_stats.mstats.len);
1585
1586 memset(&ustats, 0, sizeof(ustats));
1587 qed_memcpy_from(p_hwfn, p_ptt, &ustats,
1588 p_hwfn->storm_stats.ustats.address,
1589 p_hwfn->storm_stats.ustats.len);
1590
1591 memset(&pstats, 0, sizeof(pstats));
1592 qed_memcpy_from(p_hwfn, p_ptt, &pstats,
1593 p_hwfn->storm_stats.pstats.address,
1594 p_hwfn->storm_stats.pstats.len);
1595
1596 memset(&tstats, 0, sizeof(tstats));
1597 qed_memcpy_from(p_hwfn, p_ptt, &tstats,
1598 p_hwfn->storm_stats.tstats.address,
1599 p_hwfn->storm_stats.tstats.len);
1600
1601 memset(&port_stats, 0, sizeof(port_stats));
1602
1603 if (p_hwfn->mcp_info)
1604 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1605 p_hwfn->mcp_info->port_addr +
1606 offsetof(struct public_port, stats),
1607 sizeof(port_stats));
1608 qed_ptt_release(p_hwfn, p_ptt);
1609
1610 stats->no_buff_discards +=
1611 HILO_64_REGPAIR(mstats.no_buff_discard);
1612 stats->packet_too_big_discard +=
1613 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1614 stats->ttl0_discard +=
1615 HILO_64_REGPAIR(mstats.ttl0_discard);
1616 stats->tpa_coalesced_pkts +=
1617 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1618 stats->tpa_coalesced_events +=
1619 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1620 stats->tpa_aborts_num +=
1621 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1622 stats->tpa_coalesced_bytes +=
1623 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1624
1625 stats->rx_ucast_bytes +=
1626 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1627 stats->rx_mcast_bytes +=
1628 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1629 stats->rx_bcast_bytes +=
1630 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1631 stats->rx_ucast_pkts +=
1632 HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1633 stats->rx_mcast_pkts +=
1634 HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1635 stats->rx_bcast_pkts +=
1636 HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1637
1638 stats->mftag_filter_discards +=
1639 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1640 stats->mac_filter_discards +=
1641 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1642
1643 stats->tx_ucast_bytes +=
1644 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1645 stats->tx_mcast_bytes +=
1646 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1647 stats->tx_bcast_bytes +=
1648 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1649 stats->tx_ucast_pkts +=
1650 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1651 stats->tx_mcast_pkts +=
1652 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1653 stats->tx_bcast_pkts +=
1654 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1655 stats->tx_err_drop_pkts +=
1656 HILO_64_REGPAIR(pstats.error_drop_pkts);
1657 stats->rx_64_byte_packets += port_stats.pmm.r64;
1658 stats->rx_127_byte_packets += port_stats.pmm.r127;
1659 stats->rx_255_byte_packets += port_stats.pmm.r255;
1660 stats->rx_511_byte_packets += port_stats.pmm.r511;
1661 stats->rx_1023_byte_packets += port_stats.pmm.r1023;
1662 stats->rx_1518_byte_packets += port_stats.pmm.r1518;
1663 stats->rx_1522_byte_packets += port_stats.pmm.r1522;
1664 stats->rx_2047_byte_packets += port_stats.pmm.r2047;
1665 stats->rx_4095_byte_packets += port_stats.pmm.r4095;
1666 stats->rx_9216_byte_packets += port_stats.pmm.r9216;
1667 stats->rx_16383_byte_packets += port_stats.pmm.r16383;
1668 stats->rx_crc_errors += port_stats.pmm.rfcs;
1669 stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
1670 stats->rx_pause_frames += port_stats.pmm.rxpf;
1671 stats->rx_pfc_frames += port_stats.pmm.rxpp;
1672 stats->rx_align_errors += port_stats.pmm.raln;
1673 stats->rx_carrier_errors += port_stats.pmm.rfcr;
1674 stats->rx_oversize_packets += port_stats.pmm.rovr;
1675 stats->rx_jabbers += port_stats.pmm.rjbr;
1676 stats->rx_undersize_packets += port_stats.pmm.rund;
1677 stats->rx_fragments += port_stats.pmm.rfrg;
1678 stats->tx_64_byte_packets += port_stats.pmm.t64;
1679 stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
1680 stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
1681 stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
1682 stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
1683 stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
1684 stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
1685 stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
1686 stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
1687 stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
1688 stats->tx_pause_frames += port_stats.pmm.txpf;
1689 stats->tx_pfc_frames += port_stats.pmm.txpp;
1690 stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
1691 stats->tx_total_collisions += port_stats.pmm.tncl;
1692 stats->rx_mac_bytes += port_stats.pmm.rbyte;
1693 stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
1694 stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
1695 stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
1696 stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
1697 stats->tx_mac_bytes += port_stats.pmm.tbyte;
1698 stats->tx_mac_uc_packets += port_stats.pmm.txuca;
1699 stats->tx_mac_mc_packets += port_stats.pmm.txmca;
1700 stats->tx_mac_bc_packets += port_stats.pmm.txbca;
1701 stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
1702
1703 for (j = 0; j < 8; j++) {
1704 stats->brb_truncates += port_stats.brb.brb_truncate[j];
1705 stats->brb_discards += port_stats.brb.brb_discard[j];
1706 }
1707 }
1708}
1709
1710void qed_get_vport_stats(struct qed_dev *cdev,
1711 struct qed_eth_stats *stats)
1712{
1713 u32 i;
1714
1715 if (!cdev) {
1716 memset(stats, 0, sizeof(*stats));
1717 return;
1718 }
1719
1720 __qed_get_vport_stats(cdev, stats);
1721
1722 if (!cdev->reset_stats)
1723 return;
1724
1725 /* Reduce the statistics baseline */
1726 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1727 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1728}
1729
1730/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1731void qed_reset_vport_stats(struct qed_dev *cdev)
1732{
1733 int i;
1734
1735 for_each_hwfn(cdev, i) {
1736 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1737 struct eth_mstorm_per_queue_stat mstats;
1738 struct eth_ustorm_per_queue_stat ustats;
1739 struct eth_pstorm_per_queue_stat pstats;
1740 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1741
1742 if (!p_ptt) {
1743 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1744 continue;
1745 }
1746
1747 memset(&mstats, 0, sizeof(mstats));
1748 qed_memcpy_to(p_hwfn, p_ptt,
1749 p_hwfn->storm_stats.mstats.address,
1750 &mstats,
1751 p_hwfn->storm_stats.mstats.len);
1752
1753 memset(&ustats, 0, sizeof(ustats));
1754 qed_memcpy_to(p_hwfn, p_ptt,
1755 p_hwfn->storm_stats.ustats.address,
1756 &ustats,
1757 p_hwfn->storm_stats.ustats.len);
1758
1759 memset(&pstats, 0, sizeof(pstats));
1760 qed_memcpy_to(p_hwfn, p_ptt,
1761 p_hwfn->storm_stats.pstats.address,
1762 &pstats,
1763 p_hwfn->storm_stats.pstats.len);
1764
1765 qed_ptt_release(p_hwfn, p_ptt);
1766 }
1767
1768 /* PORT statistics are not necessarily reset, so we need to
1769 * read and create a baseline for future statistics.
1770 */
1771 if (!cdev->reset_stats)
1772 DP_INFO(cdev, "Reset stats not allocated\n");
1773 else
1774 __qed_get_vport_stats(cdev, cdev->reset_stats);
1775}
1776
cee4d264
MC		 1777int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
1778 u16 src_id, u16 *dst_id)
1779{
1780 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
1781 u16 min, max;
1782
1783 min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
1784 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
1785 DP_NOTICE(p_hwfn,
1786 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
1787 src_id, min, max);
1788
1789 return -EINVAL;
1790 }
1791
1792 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
1793
1794 return 0;
1795}
1796
1797int qed_fw_vport(struct qed_hwfn *p_hwfn,
1798 u8 src_id, u8 *dst_id)
1799{
1800 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
1801 u8 min, max;
1802
1803 min = (u8)RESC_START(p_hwfn, QED_VPORT);
1804 max = min + RESC_NUM(p_hwfn, QED_VPORT);
1805 DP_NOTICE(p_hwfn,
1806 "vport id [%d] is not valid, available indices [%d - %d]\n",
1807 src_id, min, max);
1808
1809 return -EINVAL;
1810 }
1811
1812 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
1813
1814 return 0;
1815}
1816
1817int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
1818 u8 src_id, u8 *dst_id)
1819{
1820 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
1821 u8 min, max;
1822
1823 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
1824 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
1825 DP_NOTICE(p_hwfn,
1826 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
1827 src_id, min, max);
1828
1829 return -EINVAL;
1830 }
1831
1832 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
1833
1834 return 0;
1835}
Linux kernel - Deliverables
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