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fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <asm/byteorder.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/mutex.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/qed/qed_chain.h> | |
22 | #include <linux/qed/qed_if.h> | |
23 | #include "qed.h" | |
24 | #include "qed_cxt.h" | |
25 | #include "qed_dev_api.h" | |
26 | #include "qed_hsi.h" | |
27 | #include "qed_hw.h" | |
28 | #include "qed_init_ops.h" | |
29 | #include "qed_int.h" | |
30 | #include "qed_mcp.h" | |
31 | #include "qed_reg_addr.h" | |
32 | #include "qed_sp.h" | |
33 | ||
34 | /* API common to all protocols */ | |
c2035eea RA |
35 | enum BAR_ID { |
36 | BAR_ID_0, /* used for GRC */ | |
37 | BAR_ID_1 /* Used for doorbells */ | |
38 | }; | |
39 | ||
40 | static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, | |
41 | enum BAR_ID bar_id) | |
42 | { | |
43 | u32 bar_reg = (bar_id == BAR_ID_0 ? | |
44 | PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); | |
45 | u32 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); | |
46 | ||
47 | if (val) | |
48 | return 1 << (val + 15); | |
49 | ||
50 | /* Old MFW initialized above registered only conditionally */ | |
51 | if (p_hwfn->cdev->num_hwfns > 1) { | |
52 | DP_INFO(p_hwfn, | |
53 | "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); | |
54 | return BAR_ID_0 ? 256 * 1024 : 512 * 1024; | |
55 | } else { | |
56 | DP_INFO(p_hwfn, | |
57 | "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); | |
58 | return 512 * 1024; | |
59 | } | |
60 | } | |
61 | ||
fe56b9e6 YM |
62 | void qed_init_dp(struct qed_dev *cdev, |
63 | u32 dp_module, u8 dp_level) | |
64 | { | |
65 | u32 i; | |
66 | ||
67 | cdev->dp_level = dp_level; | |
68 | cdev->dp_module = dp_module; | |
69 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { | |
70 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
71 | ||
72 | p_hwfn->dp_level = dp_level; | |
73 | p_hwfn->dp_module = dp_module; | |
74 | } | |
75 | } | |
76 | ||
77 | void qed_init_struct(struct qed_dev *cdev) | |
78 | { | |
79 | u8 i; | |
80 | ||
81 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { | |
82 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
83 | ||
84 | p_hwfn->cdev = cdev; | |
85 | p_hwfn->my_id = i; | |
86 | p_hwfn->b_active = false; | |
87 | ||
88 | mutex_init(&p_hwfn->dmae_info.mutex); | |
89 | } | |
90 | ||
91 | /* hwfn 0 is always active */ | |
92 | cdev->hwfns[0].b_active = true; | |
93 | ||
94 | /* set the default cache alignment to 128 */ | |
95 | cdev->cache_shift = 7; | |
96 | } | |
97 | ||
98 | static void qed_qm_info_free(struct qed_hwfn *p_hwfn) | |
99 | { | |
100 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
101 | ||
102 | kfree(qm_info->qm_pq_params); | |
103 | qm_info->qm_pq_params = NULL; | |
104 | kfree(qm_info->qm_vport_params); | |
105 | qm_info->qm_vport_params = NULL; | |
106 | kfree(qm_info->qm_port_params); | |
107 | qm_info->qm_port_params = NULL; | |
bcd197c8 MC |
108 | kfree(qm_info->wfq_data); |
109 | qm_info->wfq_data = NULL; | |
fe56b9e6 YM |
110 | } |
111 | ||
112 | void qed_resc_free(struct qed_dev *cdev) | |
113 | { | |
114 | int i; | |
115 | ||
116 | kfree(cdev->fw_data); | |
117 | cdev->fw_data = NULL; | |
118 | ||
119 | kfree(cdev->reset_stats); | |
120 | ||
25c089d7 YM |
121 | for_each_hwfn(cdev, i) { |
122 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
123 | ||
124 | kfree(p_hwfn->p_tx_cids); | |
125 | p_hwfn->p_tx_cids = NULL; | |
126 | kfree(p_hwfn->p_rx_cids); | |
127 | p_hwfn->p_rx_cids = NULL; | |
128 | } | |
129 | ||
fe56b9e6 YM |
130 | for_each_hwfn(cdev, i) { |
131 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
132 | ||
133 | qed_cxt_mngr_free(p_hwfn); | |
134 | qed_qm_info_free(p_hwfn); | |
135 | qed_spq_free(p_hwfn); | |
136 | qed_eq_free(p_hwfn, p_hwfn->p_eq); | |
137 | qed_consq_free(p_hwfn, p_hwfn->p_consq); | |
138 | qed_int_free(p_hwfn); | |
139 | qed_dmae_info_free(p_hwfn); | |
140 | } | |
141 | } | |
142 | ||
143 | static int qed_init_qm_info(struct qed_hwfn *p_hwfn) | |
144 | { | |
145 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
146 | struct init_qm_port_params *p_qm_port; | |
147 | u8 num_vports, i, vport_id, num_ports; | |
148 | u16 num_pqs, multi_cos_tcs = 1; | |
149 | ||
150 | memset(qm_info, 0, sizeof(*qm_info)); | |
151 | ||
152 | num_pqs = multi_cos_tcs + 1; /* The '1' is for pure-LB */ | |
153 | num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); | |
154 | ||
155 | /* Sanity checking that setup requires legal number of resources */ | |
156 | if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { | |
157 | DP_ERR(p_hwfn, | |
158 | "Need too many Physical queues - 0x%04x when only %04x are available\n", | |
159 | num_pqs, RESC_NUM(p_hwfn, QED_PQ)); | |
160 | return -EINVAL; | |
161 | } | |
162 | ||
163 | /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. | |
164 | */ | |
165 | qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) * | |
60fffb3b | 166 | num_pqs, GFP_KERNEL); |
fe56b9e6 YM |
167 | if (!qm_info->qm_pq_params) |
168 | goto alloc_err; | |
169 | ||
170 | qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) * | |
60fffb3b | 171 | num_vports, GFP_KERNEL); |
fe56b9e6 YM |
172 | if (!qm_info->qm_vport_params) |
173 | goto alloc_err; | |
174 | ||
175 | qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) * | |
60fffb3b | 176 | MAX_NUM_PORTS, GFP_KERNEL); |
fe56b9e6 YM |
177 | if (!qm_info->qm_port_params) |
178 | goto alloc_err; | |
179 | ||
bcd197c8 MC |
180 | qm_info->wfq_data = kcalloc(num_vports, sizeof(*qm_info->wfq_data), |
181 | GFP_KERNEL); | |
182 | if (!qm_info->wfq_data) | |
183 | goto alloc_err; | |
184 | ||
fe56b9e6 YM |
185 | vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); |
186 | ||
187 | /* First init per-TC PQs */ | |
188 | for (i = 0; i < multi_cos_tcs; i++) { | |
189 | struct init_qm_pq_params *params = &qm_info->qm_pq_params[i]; | |
190 | ||
191 | params->vport_id = vport_id; | |
192 | params->tc_id = p_hwfn->hw_info.non_offload_tc; | |
193 | params->wrr_group = 1; | |
194 | } | |
195 | ||
196 | /* Then init pure-LB PQ */ | |
197 | qm_info->pure_lb_pq = i; | |
198 | qm_info->qm_pq_params[i].vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); | |
199 | qm_info->qm_pq_params[i].tc_id = PURE_LB_TC; | |
200 | qm_info->qm_pq_params[i].wrr_group = 1; | |
201 | i++; | |
202 | ||
203 | qm_info->offload_pq = 0; | |
204 | qm_info->num_pqs = num_pqs; | |
205 | qm_info->num_vports = num_vports; | |
206 | ||
207 | /* Initialize qm port parameters */ | |
208 | num_ports = p_hwfn->cdev->num_ports_in_engines; | |
209 | for (i = 0; i < num_ports; i++) { | |
210 | p_qm_port = &qm_info->qm_port_params[i]; | |
211 | p_qm_port->active = 1; | |
212 | p_qm_port->num_active_phys_tcs = 4; | |
213 | p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; | |
214 | p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; | |
215 | } | |
216 | ||
217 | qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; | |
218 | ||
219 | qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); | |
220 | ||
221 | qm_info->start_vport = (u8)RESC_START(p_hwfn, QED_VPORT); | |
222 | ||
223 | qm_info->pf_wfq = 0; | |
224 | qm_info->pf_rl = 0; | |
225 | qm_info->vport_rl_en = 1; | |
226 | ||
227 | return 0; | |
228 | ||
229 | alloc_err: | |
230 | DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); | |
bcd197c8 | 231 | qed_qm_info_free(p_hwfn); |
fe56b9e6 YM |
232 | return -ENOMEM; |
233 | } | |
234 | ||
235 | int qed_resc_alloc(struct qed_dev *cdev) | |
236 | { | |
237 | struct qed_consq *p_consq; | |
238 | struct qed_eq *p_eq; | |
239 | int i, rc = 0; | |
240 | ||
241 | cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); | |
242 | if (!cdev->fw_data) | |
243 | return -ENOMEM; | |
244 | ||
25c089d7 YM |
245 | /* Allocate Memory for the Queue->CID mapping */ |
246 | for_each_hwfn(cdev, i) { | |
247 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
248 | int tx_size = sizeof(struct qed_hw_cid_data) * | |
249 | RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
250 | int rx_size = sizeof(struct qed_hw_cid_data) * | |
251 | RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
252 | ||
253 | p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); | |
254 | if (!p_hwfn->p_tx_cids) { | |
255 | DP_NOTICE(p_hwfn, | |
256 | "Failed to allocate memory for Tx Cids\n"); | |
9b15acbf | 257 | rc = -ENOMEM; |
25c089d7 YM |
258 | goto alloc_err; |
259 | } | |
260 | ||
261 | p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); | |
262 | if (!p_hwfn->p_rx_cids) { | |
263 | DP_NOTICE(p_hwfn, | |
264 | "Failed to allocate memory for Rx Cids\n"); | |
9b15acbf | 265 | rc = -ENOMEM; |
25c089d7 YM |
266 | goto alloc_err; |
267 | } | |
268 | } | |
269 | ||
fe56b9e6 YM |
270 | for_each_hwfn(cdev, i) { |
271 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
272 | ||
273 | /* First allocate the context manager structure */ | |
274 | rc = qed_cxt_mngr_alloc(p_hwfn); | |
275 | if (rc) | |
276 | goto alloc_err; | |
277 | ||
278 | /* Set the HW cid/tid numbers (in the contest manager) | |
279 | * Must be done prior to any further computations. | |
280 | */ | |
281 | rc = qed_cxt_set_pf_params(p_hwfn); | |
282 | if (rc) | |
283 | goto alloc_err; | |
284 | ||
285 | /* Prepare and process QM requirements */ | |
286 | rc = qed_init_qm_info(p_hwfn); | |
287 | if (rc) | |
288 | goto alloc_err; | |
289 | ||
290 | /* Compute the ILT client partition */ | |
291 | rc = qed_cxt_cfg_ilt_compute(p_hwfn); | |
292 | if (rc) | |
293 | goto alloc_err; | |
294 | ||
295 | /* CID map / ILT shadow table / T2 | |
296 | * The talbes sizes are determined by the computations above | |
297 | */ | |
298 | rc = qed_cxt_tables_alloc(p_hwfn); | |
299 | if (rc) | |
300 | goto alloc_err; | |
301 | ||
302 | /* SPQ, must follow ILT because initializes SPQ context */ | |
303 | rc = qed_spq_alloc(p_hwfn); | |
304 | if (rc) | |
305 | goto alloc_err; | |
306 | ||
307 | /* SP status block allocation */ | |
308 | p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, | |
309 | RESERVED_PTT_DPC); | |
310 | ||
311 | rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); | |
312 | if (rc) | |
313 | goto alloc_err; | |
314 | ||
315 | /* EQ */ | |
316 | p_eq = qed_eq_alloc(p_hwfn, 256); | |
9b15acbf DC |
317 | if (!p_eq) { |
318 | rc = -ENOMEM; | |
fe56b9e6 | 319 | goto alloc_err; |
9b15acbf | 320 | } |
fe56b9e6 YM |
321 | p_hwfn->p_eq = p_eq; |
322 | ||
323 | p_consq = qed_consq_alloc(p_hwfn); | |
9b15acbf DC |
324 | if (!p_consq) { |
325 | rc = -ENOMEM; | |
fe56b9e6 | 326 | goto alloc_err; |
9b15acbf | 327 | } |
fe56b9e6 YM |
328 | p_hwfn->p_consq = p_consq; |
329 | ||
330 | /* DMA info initialization */ | |
331 | rc = qed_dmae_info_alloc(p_hwfn); | |
332 | if (rc) { | |
333 | DP_NOTICE(p_hwfn, | |
334 | "Failed to allocate memory for dmae_info structure\n"); | |
335 | goto alloc_err; | |
336 | } | |
337 | } | |
338 | ||
339 | cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); | |
340 | if (!cdev->reset_stats) { | |
341 | DP_NOTICE(cdev, "Failed to allocate reset statistics\n"); | |
9b15acbf | 342 | rc = -ENOMEM; |
fe56b9e6 YM |
343 | goto alloc_err; |
344 | } | |
345 | ||
346 | return 0; | |
347 | ||
348 | alloc_err: | |
349 | qed_resc_free(cdev); | |
350 | return rc; | |
351 | } | |
352 | ||
353 | void qed_resc_setup(struct qed_dev *cdev) | |
354 | { | |
355 | int i; | |
356 | ||
357 | for_each_hwfn(cdev, i) { | |
358 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
359 | ||
360 | qed_cxt_mngr_setup(p_hwfn); | |
361 | qed_spq_setup(p_hwfn); | |
362 | qed_eq_setup(p_hwfn, p_hwfn->p_eq); | |
363 | qed_consq_setup(p_hwfn, p_hwfn->p_consq); | |
364 | ||
365 | /* Read shadow of current MFW mailbox */ | |
366 | qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); | |
367 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, | |
368 | p_hwfn->mcp_info->mfw_mb_cur, | |
369 | p_hwfn->mcp_info->mfw_mb_length); | |
370 | ||
371 | qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); | |
372 | } | |
373 | } | |
374 | ||
fe56b9e6 YM |
375 | #define FINAL_CLEANUP_POLL_CNT (100) |
376 | #define FINAL_CLEANUP_POLL_TIME (10) | |
377 | int qed_final_cleanup(struct qed_hwfn *p_hwfn, | |
378 | struct qed_ptt *p_ptt, | |
379 | u16 id) | |
380 | { | |
381 | u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; | |
382 | int rc = -EBUSY; | |
383 | ||
fc48b7a6 YM |
384 | addr = GTT_BAR0_MAP_REG_USDM_RAM + |
385 | USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); | |
fe56b9e6 | 386 | |
fc48b7a6 YM |
387 | command |= X_FINAL_CLEANUP_AGG_INT << |
388 | SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; | |
389 | command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; | |
390 | command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; | |
391 | command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; | |
fe56b9e6 YM |
392 | |
393 | /* Make sure notification is not set before initiating final cleanup */ | |
394 | if (REG_RD(p_hwfn, addr)) { | |
395 | DP_NOTICE( | |
396 | p_hwfn, | |
397 | "Unexpected; Found final cleanup notification before initiating final cleanup\n"); | |
398 | REG_WR(p_hwfn, addr, 0); | |
399 | } | |
400 | ||
401 | DP_VERBOSE(p_hwfn, QED_MSG_IOV, | |
402 | "Sending final cleanup for PFVF[%d] [Command %08x\n]", | |
403 | id, command); | |
404 | ||
405 | qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); | |
406 | ||
407 | /* Poll until completion */ | |
408 | while (!REG_RD(p_hwfn, addr) && count--) | |
409 | msleep(FINAL_CLEANUP_POLL_TIME); | |
410 | ||
411 | if (REG_RD(p_hwfn, addr)) | |
412 | rc = 0; | |
413 | else | |
414 | DP_NOTICE(p_hwfn, | |
415 | "Failed to receive FW final cleanup notification\n"); | |
416 | ||
417 | /* Cleanup afterwards */ | |
418 | REG_WR(p_hwfn, addr, 0); | |
419 | ||
420 | return rc; | |
421 | } | |
422 | ||
423 | static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) | |
424 | { | |
425 | int hw_mode = 0; | |
426 | ||
12e09c69 | 427 | hw_mode = (1 << MODE_BB_B0); |
fe56b9e6 YM |
428 | |
429 | switch (p_hwfn->cdev->num_ports_in_engines) { | |
430 | case 1: | |
431 | hw_mode |= 1 << MODE_PORTS_PER_ENG_1; | |
432 | break; | |
433 | case 2: | |
434 | hw_mode |= 1 << MODE_PORTS_PER_ENG_2; | |
435 | break; | |
436 | case 4: | |
437 | hw_mode |= 1 << MODE_PORTS_PER_ENG_4; | |
438 | break; | |
439 | default: | |
440 | DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", | |
441 | p_hwfn->cdev->num_ports_in_engines); | |
442 | return; | |
443 | } | |
444 | ||
445 | switch (p_hwfn->cdev->mf_mode) { | |
fc48b7a6 YM |
446 | case QED_MF_DEFAULT: |
447 | case QED_MF_NPAR: | |
448 | hw_mode |= 1 << MODE_MF_SI; | |
fe56b9e6 | 449 | break; |
fc48b7a6 | 450 | case QED_MF_OVLAN: |
fe56b9e6 YM |
451 | hw_mode |= 1 << MODE_MF_SD; |
452 | break; | |
fe56b9e6 | 453 | default: |
fc48b7a6 YM |
454 | DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); |
455 | hw_mode |= 1 << MODE_MF_SI; | |
fe56b9e6 YM |
456 | } |
457 | ||
458 | hw_mode |= 1 << MODE_ASIC; | |
459 | ||
460 | p_hwfn->hw_info.hw_mode = hw_mode; | |
461 | } | |
462 | ||
463 | /* Init run time data for all PFs on an engine. */ | |
464 | static void qed_init_cau_rt_data(struct qed_dev *cdev) | |
465 | { | |
466 | u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; | |
467 | int i, sb_id; | |
468 | ||
469 | for_each_hwfn(cdev, i) { | |
470 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
471 | struct qed_igu_info *p_igu_info; | |
472 | struct qed_igu_block *p_block; | |
473 | struct cau_sb_entry sb_entry; | |
474 | ||
475 | p_igu_info = p_hwfn->hw_info.p_igu_info; | |
476 | ||
477 | for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); | |
478 | sb_id++) { | |
479 | p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; | |
480 | if (!p_block->is_pf) | |
481 | continue; | |
482 | ||
483 | qed_init_cau_sb_entry(p_hwfn, &sb_entry, | |
484 | p_block->function_id, | |
485 | 0, 0); | |
486 | STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, | |
487 | sb_entry); | |
488 | } | |
489 | } | |
490 | } | |
491 | ||
492 | static int qed_hw_init_common(struct qed_hwfn *p_hwfn, | |
493 | struct qed_ptt *p_ptt, | |
494 | int hw_mode) | |
495 | { | |
496 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
497 | struct qed_qm_common_rt_init_params params; | |
498 | struct qed_dev *cdev = p_hwfn->cdev; | |
499 | int rc = 0; | |
500 | ||
501 | qed_init_cau_rt_data(cdev); | |
502 | ||
503 | /* Program GTT windows */ | |
504 | qed_gtt_init(p_hwfn); | |
505 | ||
506 | if (p_hwfn->mcp_info) { | |
507 | if (p_hwfn->mcp_info->func_info.bandwidth_max) | |
508 | qm_info->pf_rl_en = 1; | |
509 | if (p_hwfn->mcp_info->func_info.bandwidth_min) | |
510 | qm_info->pf_wfq_en = 1; | |
511 | } | |
512 | ||
513 | memset(¶ms, 0, sizeof(params)); | |
514 | params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; | |
515 | params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; | |
516 | params.pf_rl_en = qm_info->pf_rl_en; | |
517 | params.pf_wfq_en = qm_info->pf_wfq_en; | |
518 | params.vport_rl_en = qm_info->vport_rl_en; | |
519 | params.vport_wfq_en = qm_info->vport_wfq_en; | |
520 | params.port_params = qm_info->qm_port_params; | |
521 | ||
522 | qed_qm_common_rt_init(p_hwfn, ¶ms); | |
523 | ||
524 | qed_cxt_hw_init_common(p_hwfn); | |
525 | ||
526 | /* Close gate from NIG to BRB/Storm; By default they are open, but | |
527 | * we close them to prevent NIG from passing data to reset blocks. | |
528 | * Should have been done in the ENGINE phase, but init-tool lacks | |
529 | * proper port-pretend capabilities. | |
530 | */ | |
531 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); | |
532 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); | |
533 | qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); | |
534 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); | |
535 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); | |
536 | qed_port_unpretend(p_hwfn, p_ptt); | |
537 | ||
538 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); | |
539 | if (rc != 0) | |
540 | return rc; | |
541 | ||
542 | qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); | |
543 | qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); | |
544 | ||
545 | /* Disable relaxed ordering in the PCI config space */ | |
546 | qed_wr(p_hwfn, p_ptt, 0x20b4, | |
547 | qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10); | |
548 | ||
549 | return rc; | |
550 | } | |
551 | ||
552 | static int qed_hw_init_port(struct qed_hwfn *p_hwfn, | |
553 | struct qed_ptt *p_ptt, | |
554 | int hw_mode) | |
555 | { | |
556 | int rc = 0; | |
557 | ||
558 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, | |
559 | hw_mode); | |
560 | return rc; | |
561 | } | |
562 | ||
563 | static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, | |
564 | struct qed_ptt *p_ptt, | |
464f6645 | 565 | struct qed_tunn_start_params *p_tunn, |
fe56b9e6 YM |
566 | int hw_mode, |
567 | bool b_hw_start, | |
568 | enum qed_int_mode int_mode, | |
569 | bool allow_npar_tx_switch) | |
570 | { | |
571 | u8 rel_pf_id = p_hwfn->rel_pf_id; | |
572 | int rc = 0; | |
573 | ||
574 | if (p_hwfn->mcp_info) { | |
575 | struct qed_mcp_function_info *p_info; | |
576 | ||
577 | p_info = &p_hwfn->mcp_info->func_info; | |
578 | if (p_info->bandwidth_min) | |
579 | p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; | |
580 | ||
581 | /* Update rate limit once we'll actually have a link */ | |
4b01e519 | 582 | p_hwfn->qm_info.pf_rl = 100000; |
fe56b9e6 YM |
583 | } |
584 | ||
585 | qed_cxt_hw_init_pf(p_hwfn); | |
586 | ||
587 | qed_int_igu_init_rt(p_hwfn); | |
588 | ||
589 | /* Set VLAN in NIG if needed */ | |
590 | if (hw_mode & (1 << MODE_MF_SD)) { | |
591 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); | |
592 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); | |
593 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, | |
594 | p_hwfn->hw_info.ovlan); | |
595 | } | |
596 | ||
597 | /* Enable classification by MAC if needed */ | |
87aec47d | 598 | if (hw_mode & (1 << MODE_MF_SI)) { |
fe56b9e6 YM |
599 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, |
600 | "Configuring TAGMAC_CLS_TYPE\n"); | |
601 | STORE_RT_REG(p_hwfn, | |
602 | NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); | |
603 | } | |
604 | ||
605 | /* Protocl Configuration */ | |
606 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0); | |
607 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); | |
608 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); | |
609 | ||
610 | /* Cleanup chip from previous driver if such remains exist */ | |
611 | rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id); | |
612 | if (rc != 0) | |
613 | return rc; | |
614 | ||
615 | /* PF Init sequence */ | |
616 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); | |
617 | if (rc) | |
618 | return rc; | |
619 | ||
620 | /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ | |
621 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); | |
622 | if (rc) | |
623 | return rc; | |
624 | ||
625 | /* Pure runtime initializations - directly to the HW */ | |
626 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); | |
627 | ||
628 | if (b_hw_start) { | |
629 | /* enable interrupts */ | |
630 | qed_int_igu_enable(p_hwfn, p_ptt, int_mode); | |
631 | ||
632 | /* send function start command */ | |
464f6645 | 633 | rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode); |
fe56b9e6 YM |
634 | if (rc) |
635 | DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); | |
636 | } | |
637 | return rc; | |
638 | } | |
639 | ||
640 | static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, | |
641 | struct qed_ptt *p_ptt, | |
642 | u8 enable) | |
643 | { | |
644 | u32 delay_idx = 0, val, set_val = enable ? 1 : 0; | |
645 | ||
646 | /* Change PF in PXP */ | |
647 | qed_wr(p_hwfn, p_ptt, | |
648 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); | |
649 | ||
650 | /* wait until value is set - try for 1 second every 50us */ | |
651 | for (delay_idx = 0; delay_idx < 20000; delay_idx++) { | |
652 | val = qed_rd(p_hwfn, p_ptt, | |
653 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
654 | if (val == set_val) | |
655 | break; | |
656 | ||
657 | usleep_range(50, 60); | |
658 | } | |
659 | ||
660 | if (val != set_val) { | |
661 | DP_NOTICE(p_hwfn, | |
662 | "PFID_ENABLE_MASTER wasn't changed after a second\n"); | |
663 | return -EAGAIN; | |
664 | } | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, | |
670 | struct qed_ptt *p_main_ptt) | |
671 | { | |
672 | /* Read shadow of current MFW mailbox */ | |
673 | qed_mcp_read_mb(p_hwfn, p_main_ptt); | |
674 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, | |
675 | p_hwfn->mcp_info->mfw_mb_cur, | |
676 | p_hwfn->mcp_info->mfw_mb_length); | |
677 | } | |
678 | ||
679 | int qed_hw_init(struct qed_dev *cdev, | |
464f6645 | 680 | struct qed_tunn_start_params *p_tunn, |
fe56b9e6 YM |
681 | bool b_hw_start, |
682 | enum qed_int_mode int_mode, | |
683 | bool allow_npar_tx_switch, | |
684 | const u8 *bin_fw_data) | |
685 | { | |
86622ee7 | 686 | u32 load_code, param; |
fe56b9e6 YM |
687 | int rc, mfw_rc, i; |
688 | ||
689 | rc = qed_init_fw_data(cdev, bin_fw_data); | |
690 | if (rc != 0) | |
691 | return rc; | |
692 | ||
693 | for_each_hwfn(cdev, i) { | |
694 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
695 | ||
696 | /* Enable DMAE in PXP */ | |
697 | rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); | |
698 | ||
699 | qed_calc_hw_mode(p_hwfn); | |
700 | ||
701 | rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, | |
702 | &load_code); | |
703 | if (rc) { | |
704 | DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); | |
705 | return rc; | |
706 | } | |
707 | ||
708 | qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); | |
709 | ||
710 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
711 | "Load request was sent. Resp:0x%x, Load code: 0x%x\n", | |
712 | rc, load_code); | |
713 | ||
714 | p_hwfn->first_on_engine = (load_code == | |
715 | FW_MSG_CODE_DRV_LOAD_ENGINE); | |
716 | ||
717 | switch (load_code) { | |
718 | case FW_MSG_CODE_DRV_LOAD_ENGINE: | |
719 | rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, | |
720 | p_hwfn->hw_info.hw_mode); | |
721 | if (rc) | |
722 | break; | |
723 | /* Fall into */ | |
724 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
725 | rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, | |
726 | p_hwfn->hw_info.hw_mode); | |
727 | if (rc) | |
728 | break; | |
729 | ||
730 | /* Fall into */ | |
731 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
732 | rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, | |
464f6645 | 733 | p_tunn, p_hwfn->hw_info.hw_mode, |
fe56b9e6 YM |
734 | b_hw_start, int_mode, |
735 | allow_npar_tx_switch); | |
736 | break; | |
737 | default: | |
738 | rc = -EINVAL; | |
739 | break; | |
740 | } | |
741 | ||
742 | if (rc) | |
743 | DP_NOTICE(p_hwfn, | |
744 | "init phase failed for loadcode 0x%x (rc %d)\n", | |
745 | load_code, rc); | |
746 | ||
747 | /* ACK mfw regardless of success or failure of initialization */ | |
748 | mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
749 | DRV_MSG_CODE_LOAD_DONE, | |
750 | 0, &load_code, ¶m); | |
751 | if (rc) | |
752 | return rc; | |
753 | if (mfw_rc) { | |
754 | DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); | |
755 | return mfw_rc; | |
756 | } | |
757 | ||
758 | p_hwfn->hw_init_done = true; | |
759 | } | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | #define QED_HW_STOP_RETRY_LIMIT (10) | |
8c925c44 YM |
765 | static inline void qed_hw_timers_stop(struct qed_dev *cdev, |
766 | struct qed_hwfn *p_hwfn, | |
767 | struct qed_ptt *p_ptt) | |
768 | { | |
769 | int i; | |
770 | ||
771 | /* close timers */ | |
772 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); | |
773 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); | |
774 | ||
775 | for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { | |
776 | if ((!qed_rd(p_hwfn, p_ptt, | |
777 | TM_REG_PF_SCAN_ACTIVE_CONN)) && | |
778 | (!qed_rd(p_hwfn, p_ptt, | |
779 | TM_REG_PF_SCAN_ACTIVE_TASK))) | |
780 | break; | |
781 | ||
782 | /* Dependent on number of connection/tasks, possibly | |
783 | * 1ms sleep is required between polls | |
784 | */ | |
785 | usleep_range(1000, 2000); | |
786 | } | |
787 | ||
788 | if (i < QED_HW_STOP_RETRY_LIMIT) | |
789 | return; | |
790 | ||
791 | DP_NOTICE(p_hwfn, | |
792 | "Timers linear scans are not over [Connection %02x Tasks %02x]\n", | |
793 | (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), | |
794 | (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); | |
795 | } | |
796 | ||
797 | void qed_hw_timers_stop_all(struct qed_dev *cdev) | |
798 | { | |
799 | int j; | |
800 | ||
801 | for_each_hwfn(cdev, j) { | |
802 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
803 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
804 | ||
805 | qed_hw_timers_stop(cdev, p_hwfn, p_ptt); | |
806 | } | |
807 | } | |
808 | ||
fe56b9e6 YM |
809 | int qed_hw_stop(struct qed_dev *cdev) |
810 | { | |
811 | int rc = 0, t_rc; | |
8c925c44 | 812 | int j; |
fe56b9e6 YM |
813 | |
814 | for_each_hwfn(cdev, j) { | |
815 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
816 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
817 | ||
818 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); | |
819 | ||
820 | /* mark the hw as uninitialized... */ | |
821 | p_hwfn->hw_init_done = false; | |
822 | ||
823 | rc = qed_sp_pf_stop(p_hwfn); | |
824 | if (rc) | |
8c925c44 YM |
825 | DP_NOTICE(p_hwfn, |
826 | "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); | |
fe56b9e6 YM |
827 | |
828 | qed_wr(p_hwfn, p_ptt, | |
829 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); | |
830 | ||
831 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); | |
832 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); | |
833 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); | |
834 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); | |
835 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); | |
836 | ||
8c925c44 | 837 | qed_hw_timers_stop(cdev, p_hwfn, p_ptt); |
fe56b9e6 YM |
838 | |
839 | /* Disable Attention Generation */ | |
840 | qed_int_igu_disable_int(p_hwfn, p_ptt); | |
841 | ||
842 | qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); | |
843 | qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
844 | ||
845 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); | |
846 | ||
847 | /* Need to wait 1ms to guarantee SBs are cleared */ | |
848 | usleep_range(1000, 2000); | |
849 | } | |
850 | ||
851 | /* Disable DMAE in PXP - in CMT, this should only be done for | |
852 | * first hw-function, and only after all transactions have | |
853 | * stopped for all active hw-functions. | |
854 | */ | |
855 | t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], | |
856 | cdev->hwfns[0].p_main_ptt, | |
857 | false); | |
858 | if (t_rc != 0) | |
859 | rc = t_rc; | |
860 | ||
861 | return rc; | |
862 | } | |
863 | ||
cee4d264 MC |
864 | void qed_hw_stop_fastpath(struct qed_dev *cdev) |
865 | { | |
8c925c44 | 866 | int j; |
cee4d264 MC |
867 | |
868 | for_each_hwfn(cdev, j) { | |
869 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
870 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
871 | ||
872 | DP_VERBOSE(p_hwfn, | |
873 | NETIF_MSG_IFDOWN, | |
874 | "Shutting down the fastpath\n"); | |
875 | ||
876 | qed_wr(p_hwfn, p_ptt, | |
877 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); | |
878 | ||
879 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); | |
880 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); | |
881 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); | |
882 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); | |
883 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); | |
884 | ||
cee4d264 MC |
885 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); |
886 | ||
887 | /* Need to wait 1ms to guarantee SBs are cleared */ | |
888 | usleep_range(1000, 2000); | |
889 | } | |
890 | } | |
891 | ||
892 | void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) | |
893 | { | |
894 | /* Re-open incoming traffic */ | |
895 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
896 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); | |
897 | } | |
898 | ||
fe56b9e6 YM |
899 | static int qed_reg_assert(struct qed_hwfn *hwfn, |
900 | struct qed_ptt *ptt, u32 reg, | |
901 | bool expected) | |
902 | { | |
903 | u32 assert_val = qed_rd(hwfn, ptt, reg); | |
904 | ||
905 | if (assert_val != expected) { | |
906 | DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n", | |
907 | reg, expected); | |
908 | return -EINVAL; | |
909 | } | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | int qed_hw_reset(struct qed_dev *cdev) | |
915 | { | |
916 | int rc = 0; | |
917 | u32 unload_resp, unload_param; | |
918 | int i; | |
919 | ||
920 | for_each_hwfn(cdev, i) { | |
921 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
922 | ||
923 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); | |
924 | ||
925 | /* Check for incorrect states */ | |
926 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, | |
927 | QM_REG_USG_CNT_PF_TX, 0); | |
928 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, | |
929 | QM_REG_USG_CNT_PF_OTHER, 0); | |
930 | ||
931 | /* Disable PF in HW blocks */ | |
932 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); | |
933 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); | |
934 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
935 | TCFC_REG_STRONG_ENABLE_PF, 0); | |
936 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
937 | CCFC_REG_STRONG_ENABLE_PF, 0); | |
938 | ||
939 | /* Send unload command to MCP */ | |
940 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
941 | DRV_MSG_CODE_UNLOAD_REQ, | |
942 | DRV_MB_PARAM_UNLOAD_WOL_MCP, | |
943 | &unload_resp, &unload_param); | |
944 | if (rc) { | |
945 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); | |
946 | unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; | |
947 | } | |
948 | ||
949 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
950 | DRV_MSG_CODE_UNLOAD_DONE, | |
951 | 0, &unload_resp, &unload_param); | |
952 | if (rc) { | |
953 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); | |
954 | return rc; | |
955 | } | |
956 | } | |
957 | ||
958 | return rc; | |
959 | } | |
960 | ||
961 | /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ | |
962 | static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) | |
963 | { | |
964 | qed_ptt_pool_free(p_hwfn); | |
965 | kfree(p_hwfn->hw_info.p_igu_info); | |
966 | } | |
967 | ||
968 | /* Setup bar access */ | |
12e09c69 | 969 | static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) |
fe56b9e6 | 970 | { |
fe56b9e6 YM |
971 | /* clear indirect access */ |
972 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); | |
973 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); | |
974 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); | |
975 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); | |
976 | ||
977 | /* Clean Previous errors if such exist */ | |
978 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
979 | PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, | |
980 | 1 << p_hwfn->abs_pf_id); | |
981 | ||
982 | /* enable internal target-read */ | |
983 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
984 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
fe56b9e6 YM |
985 | } |
986 | ||
987 | static void get_function_id(struct qed_hwfn *p_hwfn) | |
988 | { | |
989 | /* ME Register */ | |
990 | p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR); | |
991 | ||
992 | p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); | |
993 | ||
994 | p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; | |
995 | p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, | |
996 | PXP_CONCRETE_FID_PFID); | |
997 | p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, | |
998 | PXP_CONCRETE_FID_PORT); | |
999 | } | |
1000 | ||
25c089d7 YM |
1001 | static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) |
1002 | { | |
1003 | u32 *feat_num = p_hwfn->hw_info.feat_num; | |
1004 | int num_features = 1; | |
1005 | ||
1006 | feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / | |
1007 | num_features, | |
1008 | RESC_NUM(p_hwfn, QED_L2_QUEUE)); | |
1009 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, | |
1010 | "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", | |
1011 | feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), | |
1012 | num_features); | |
1013 | } | |
1014 | ||
fe56b9e6 YM |
1015 | static void qed_hw_get_resc(struct qed_hwfn *p_hwfn) |
1016 | { | |
1017 | u32 *resc_start = p_hwfn->hw_info.resc_start; | |
1018 | u32 *resc_num = p_hwfn->hw_info.resc_num; | |
4ac801b7 | 1019 | struct qed_sb_cnt_info sb_cnt_info; |
fe56b9e6 YM |
1020 | int num_funcs, i; |
1021 | ||
fc48b7a6 | 1022 | num_funcs = MAX_NUM_PFS_BB; |
fe56b9e6 | 1023 | |
4ac801b7 YM |
1024 | memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); |
1025 | qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); | |
1026 | ||
fe56b9e6 YM |
1027 | resc_num[QED_SB] = min_t(u32, |
1028 | (MAX_SB_PER_PATH_BB / num_funcs), | |
4ac801b7 | 1029 | sb_cnt_info.sb_cnt); |
25c089d7 | 1030 | resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; |
fe56b9e6 | 1031 | resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; |
25c089d7 | 1032 | resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; |
fe56b9e6 YM |
1033 | resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; |
1034 | resc_num[QED_RL] = 8; | |
25c089d7 YM |
1035 | resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; |
1036 | resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / | |
1037 | num_funcs; | |
fe56b9e6 YM |
1038 | resc_num[QED_ILT] = 950; |
1039 | ||
1040 | for (i = 0; i < QED_MAX_RESC; i++) | |
1041 | resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id; | |
1042 | ||
25c089d7 YM |
1043 | qed_hw_set_feat(p_hwfn); |
1044 | ||
fe56b9e6 YM |
1045 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, |
1046 | "The numbers for each resource are:\n" | |
1047 | "SB = %d start = %d\n" | |
25c089d7 | 1048 | "L2_QUEUE = %d start = %d\n" |
fe56b9e6 YM |
1049 | "VPORT = %d start = %d\n" |
1050 | "PQ = %d start = %d\n" | |
1051 | "RL = %d start = %d\n" | |
25c089d7 YM |
1052 | "MAC = %d start = %d\n" |
1053 | "VLAN = %d start = %d\n" | |
fe56b9e6 YM |
1054 | "ILT = %d start = %d\n", |
1055 | p_hwfn->hw_info.resc_num[QED_SB], | |
1056 | p_hwfn->hw_info.resc_start[QED_SB], | |
25c089d7 YM |
1057 | p_hwfn->hw_info.resc_num[QED_L2_QUEUE], |
1058 | p_hwfn->hw_info.resc_start[QED_L2_QUEUE], | |
fe56b9e6 YM |
1059 | p_hwfn->hw_info.resc_num[QED_VPORT], |
1060 | p_hwfn->hw_info.resc_start[QED_VPORT], | |
1061 | p_hwfn->hw_info.resc_num[QED_PQ], | |
1062 | p_hwfn->hw_info.resc_start[QED_PQ], | |
1063 | p_hwfn->hw_info.resc_num[QED_RL], | |
1064 | p_hwfn->hw_info.resc_start[QED_RL], | |
25c089d7 YM |
1065 | p_hwfn->hw_info.resc_num[QED_MAC], |
1066 | p_hwfn->hw_info.resc_start[QED_MAC], | |
1067 | p_hwfn->hw_info.resc_num[QED_VLAN], | |
1068 | p_hwfn->hw_info.resc_start[QED_VLAN], | |
fe56b9e6 YM |
1069 | p_hwfn->hw_info.resc_num[QED_ILT], |
1070 | p_hwfn->hw_info.resc_start[QED_ILT]); | |
1071 | } | |
1072 | ||
1073 | static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, | |
1074 | struct qed_ptt *p_ptt) | |
1075 | { | |
cc875c2e | 1076 | u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; |
fc48b7a6 | 1077 | u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; |
cc875c2e | 1078 | struct qed_mcp_link_params *link; |
fe56b9e6 YM |
1079 | |
1080 | /* Read global nvm_cfg address */ | |
1081 | nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); | |
1082 | ||
1083 | /* Verify MCP has initialized it */ | |
1084 | if (!nvm_cfg_addr) { | |
1085 | DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); | |
1086 | return -EINVAL; | |
1087 | } | |
1088 | ||
1089 | /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ | |
1090 | nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); | |
1091 | ||
cc875c2e YM |
1092 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + |
1093 | offsetof(struct nvm_cfg1, glob) + | |
1094 | offsetof(struct nvm_cfg1_glob, core_cfg); | |
1095 | ||
1096 | core_cfg = qed_rd(p_hwfn, p_ptt, addr); | |
1097 | ||
1098 | switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> | |
1099 | NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { | |
1100 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G: | |
1101 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; | |
1102 | break; | |
1103 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G: | |
1104 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; | |
1105 | break; | |
1106 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G: | |
1107 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; | |
1108 | break; | |
1109 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F: | |
1110 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; | |
1111 | break; | |
1112 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E: | |
1113 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; | |
1114 | break; | |
1115 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G: | |
1116 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; | |
1117 | break; | |
1118 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G: | |
1119 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; | |
1120 | break; | |
1121 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G: | |
1122 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; | |
1123 | break; | |
1124 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G: | |
1125 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; | |
1126 | break; | |
1127 | default: | |
1128 | DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", | |
1129 | core_cfg); | |
1130 | break; | |
1131 | } | |
1132 | ||
cc875c2e YM |
1133 | /* Read default link configuration */ |
1134 | link = &p_hwfn->mcp_info->link_input; | |
1135 | port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1136 | offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); | |
1137 | link_temp = qed_rd(p_hwfn, p_ptt, | |
1138 | port_cfg_addr + | |
1139 | offsetof(struct nvm_cfg1_port, speed_cap_mask)); | |
1140 | link->speed.advertised_speeds = | |
1141 | link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; | |
1142 | ||
1143 | p_hwfn->mcp_info->link_capabilities.speed_capabilities = | |
1144 | link->speed.advertised_speeds; | |
1145 | ||
1146 | link_temp = qed_rd(p_hwfn, p_ptt, | |
1147 | port_cfg_addr + | |
1148 | offsetof(struct nvm_cfg1_port, link_settings)); | |
1149 | switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> | |
1150 | NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { | |
1151 | case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: | |
1152 | link->speed.autoneg = true; | |
1153 | break; | |
1154 | case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: | |
1155 | link->speed.forced_speed = 1000; | |
1156 | break; | |
1157 | case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: | |
1158 | link->speed.forced_speed = 10000; | |
1159 | break; | |
1160 | case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: | |
1161 | link->speed.forced_speed = 25000; | |
1162 | break; | |
1163 | case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: | |
1164 | link->speed.forced_speed = 40000; | |
1165 | break; | |
1166 | case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: | |
1167 | link->speed.forced_speed = 50000; | |
1168 | break; | |
1169 | case NVM_CFG1_PORT_DRV_LINK_SPEED_100G: | |
1170 | link->speed.forced_speed = 100000; | |
1171 | break; | |
1172 | default: | |
1173 | DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", | |
1174 | link_temp); | |
1175 | } | |
1176 | ||
1177 | link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; | |
1178 | link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; | |
1179 | link->pause.autoneg = !!(link_temp & | |
1180 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); | |
1181 | link->pause.forced_rx = !!(link_temp & | |
1182 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); | |
1183 | link->pause.forced_tx = !!(link_temp & | |
1184 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); | |
1185 | link->loopback_mode = 0; | |
1186 | ||
1187 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1188 | "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", | |
1189 | link->speed.forced_speed, link->speed.advertised_speeds, | |
1190 | link->speed.autoneg, link->pause.autoneg); | |
1191 | ||
fe56b9e6 YM |
1192 | /* Read Multi-function information from shmem */ |
1193 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1194 | offsetof(struct nvm_cfg1, glob) + | |
1195 | offsetof(struct nvm_cfg1_glob, generic_cont0); | |
1196 | ||
1197 | generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); | |
1198 | ||
1199 | mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> | |
1200 | NVM_CFG1_GLOB_MF_MODE_OFFSET; | |
1201 | ||
1202 | switch (mf_mode) { | |
1203 | case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: | |
fc48b7a6 | 1204 | p_hwfn->cdev->mf_mode = QED_MF_OVLAN; |
fe56b9e6 YM |
1205 | break; |
1206 | case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: | |
fc48b7a6 | 1207 | p_hwfn->cdev->mf_mode = QED_MF_NPAR; |
fe56b9e6 | 1208 | break; |
fc48b7a6 YM |
1209 | case NVM_CFG1_GLOB_MF_MODE_DEFAULT: |
1210 | p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; | |
fe56b9e6 YM |
1211 | break; |
1212 | } | |
1213 | DP_INFO(p_hwfn, "Multi function mode is %08x\n", | |
1214 | p_hwfn->cdev->mf_mode); | |
1215 | ||
fc48b7a6 YM |
1216 | /* Read Multi-function information from shmem */ |
1217 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1218 | offsetof(struct nvm_cfg1, glob) + | |
1219 | offsetof(struct nvm_cfg1_glob, device_capabilities); | |
1220 | ||
1221 | device_capabilities = qed_rd(p_hwfn, p_ptt, addr); | |
1222 | if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) | |
1223 | __set_bit(QED_DEV_CAP_ETH, | |
1224 | &p_hwfn->hw_info.device_capabilities); | |
1225 | ||
fe56b9e6 YM |
1226 | return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); |
1227 | } | |
1228 | ||
1229 | static int | |
1230 | qed_get_hw_info(struct qed_hwfn *p_hwfn, | |
1231 | struct qed_ptt *p_ptt, | |
1232 | enum qed_pci_personality personality) | |
1233 | { | |
1234 | u32 port_mode; | |
1235 | int rc; | |
1236 | ||
1237 | /* Read the port mode */ | |
1238 | port_mode = qed_rd(p_hwfn, p_ptt, | |
1239 | CNIG_REG_NW_PORT_MODE_BB_B0); | |
1240 | ||
1241 | if (port_mode < 3) { | |
1242 | p_hwfn->cdev->num_ports_in_engines = 1; | |
1243 | } else if (port_mode <= 5) { | |
1244 | p_hwfn->cdev->num_ports_in_engines = 2; | |
1245 | } else { | |
1246 | DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", | |
1247 | p_hwfn->cdev->num_ports_in_engines); | |
1248 | ||
1249 | /* Default num_ports_in_engines to something */ | |
1250 | p_hwfn->cdev->num_ports_in_engines = 1; | |
1251 | } | |
1252 | ||
1253 | qed_hw_get_nvm_info(p_hwfn, p_ptt); | |
1254 | ||
1255 | rc = qed_int_igu_read_cam(p_hwfn, p_ptt); | |
1256 | if (rc) | |
1257 | return rc; | |
1258 | ||
1259 | if (qed_mcp_is_init(p_hwfn)) | |
1260 | ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, | |
1261 | p_hwfn->mcp_info->func_info.mac); | |
1262 | else | |
1263 | eth_random_addr(p_hwfn->hw_info.hw_mac_addr); | |
1264 | ||
1265 | if (qed_mcp_is_init(p_hwfn)) { | |
1266 | if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) | |
1267 | p_hwfn->hw_info.ovlan = | |
1268 | p_hwfn->mcp_info->func_info.ovlan; | |
1269 | ||
1270 | qed_mcp_cmd_port_init(p_hwfn, p_ptt); | |
1271 | } | |
1272 | ||
1273 | if (qed_mcp_is_init(p_hwfn)) { | |
1274 | enum qed_pci_personality protocol; | |
1275 | ||
1276 | protocol = p_hwfn->mcp_info->func_info.protocol; | |
1277 | p_hwfn->hw_info.personality = protocol; | |
1278 | } | |
1279 | ||
1280 | qed_hw_get_resc(p_hwfn); | |
1281 | ||
1282 | return rc; | |
1283 | } | |
1284 | ||
12e09c69 | 1285 | static int qed_get_dev_info(struct qed_dev *cdev) |
fe56b9e6 | 1286 | { |
fc48b7a6 | 1287 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
fe56b9e6 YM |
1288 | u32 tmp; |
1289 | ||
fc48b7a6 YM |
1290 | /* Read Vendor Id / Device Id */ |
1291 | pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, | |
1292 | &cdev->vendor_id); | |
1293 | pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, | |
1294 | &cdev->device_id); | |
1295 | cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, | |
fe56b9e6 | 1296 | MISCS_REG_CHIP_NUM); |
fc48b7a6 | 1297 | cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1298 | MISCS_REG_CHIP_REV); |
1299 | MASK_FIELD(CHIP_REV, cdev->chip_rev); | |
1300 | ||
fc48b7a6 | 1301 | cdev->type = QED_DEV_TYPE_BB; |
fe56b9e6 | 1302 | /* Learn number of HW-functions */ |
fc48b7a6 | 1303 | tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1304 | MISCS_REG_CMT_ENABLED_FOR_PAIR); |
1305 | ||
fc48b7a6 | 1306 | if (tmp & (1 << p_hwfn->rel_pf_id)) { |
fe56b9e6 YM |
1307 | DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); |
1308 | cdev->num_hwfns = 2; | |
1309 | } else { | |
1310 | cdev->num_hwfns = 1; | |
1311 | } | |
1312 | ||
fc48b7a6 | 1313 | cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1314 | MISCS_REG_CHIP_TEST_REG) >> 4; |
1315 | MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); | |
fc48b7a6 | 1316 | cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1317 | MISCS_REG_CHIP_METAL); |
1318 | MASK_FIELD(CHIP_METAL, cdev->chip_metal); | |
1319 | ||
1320 | DP_INFO(cdev->hwfns, | |
1321 | "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", | |
1322 | cdev->chip_num, cdev->chip_rev, | |
1323 | cdev->chip_bond_id, cdev->chip_metal); | |
12e09c69 YM |
1324 | |
1325 | if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { | |
1326 | DP_NOTICE(cdev->hwfns, | |
1327 | "The chip type/rev (BB A0) is not supported!\n"); | |
1328 | return -EINVAL; | |
1329 | } | |
1330 | ||
1331 | return 0; | |
fe56b9e6 YM |
1332 | } |
1333 | ||
1334 | static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, | |
1335 | void __iomem *p_regview, | |
1336 | void __iomem *p_doorbells, | |
1337 | enum qed_pci_personality personality) | |
1338 | { | |
1339 | int rc = 0; | |
1340 | ||
1341 | /* Split PCI bars evenly between hwfns */ | |
1342 | p_hwfn->regview = p_regview; | |
1343 | p_hwfn->doorbells = p_doorbells; | |
1344 | ||
1345 | /* Validate that chip access is feasible */ | |
1346 | if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { | |
1347 | DP_ERR(p_hwfn, | |
1348 | "Reading the ME register returns all Fs; Preventing further chip access\n"); | |
1349 | return -EINVAL; | |
1350 | } | |
1351 | ||
1352 | get_function_id(p_hwfn); | |
1353 | ||
12e09c69 YM |
1354 | /* Allocate PTT pool */ |
1355 | rc = qed_ptt_pool_alloc(p_hwfn); | |
fe56b9e6 YM |
1356 | if (rc) { |
1357 | DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n"); | |
1358 | goto err0; | |
1359 | } | |
1360 | ||
12e09c69 YM |
1361 | /* Allocate the main PTT */ |
1362 | p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); | |
1363 | ||
fe56b9e6 | 1364 | /* First hwfn learns basic information, e.g., number of hwfns */ |
12e09c69 YM |
1365 | if (!p_hwfn->my_id) { |
1366 | rc = qed_get_dev_info(p_hwfn->cdev); | |
1367 | if (rc != 0) | |
1368 | goto err1; | |
1369 | } | |
1370 | ||
1371 | qed_hw_hwfn_prepare(p_hwfn); | |
fe56b9e6 YM |
1372 | |
1373 | /* Initialize MCP structure */ | |
1374 | rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); | |
1375 | if (rc) { | |
1376 | DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); | |
1377 | goto err1; | |
1378 | } | |
1379 | ||
1380 | /* Read the device configuration information from the HW and SHMEM */ | |
1381 | rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); | |
1382 | if (rc) { | |
1383 | DP_NOTICE(p_hwfn, "Failed to get HW information\n"); | |
1384 | goto err2; | |
1385 | } | |
1386 | ||
1387 | /* Allocate the init RT array and initialize the init-ops engine */ | |
1388 | rc = qed_init_alloc(p_hwfn); | |
1389 | if (rc) { | |
1390 | DP_NOTICE(p_hwfn, "Failed to allocate the init array\n"); | |
1391 | goto err2; | |
1392 | } | |
1393 | ||
1394 | return rc; | |
1395 | err2: | |
1396 | qed_mcp_free(p_hwfn); | |
1397 | err1: | |
1398 | qed_hw_hwfn_free(p_hwfn); | |
1399 | err0: | |
1400 | return rc; | |
1401 | } | |
1402 | ||
fe56b9e6 YM |
1403 | int qed_hw_prepare(struct qed_dev *cdev, |
1404 | int personality) | |
1405 | { | |
c78df14e AE |
1406 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
1407 | int rc; | |
fe56b9e6 YM |
1408 | |
1409 | /* Store the precompiled init data ptrs */ | |
1410 | qed_init_iro_array(cdev); | |
1411 | ||
1412 | /* Initialize the first hwfn - will learn number of hwfns */ | |
c78df14e AE |
1413 | rc = qed_hw_prepare_single(p_hwfn, |
1414 | cdev->regview, | |
fe56b9e6 YM |
1415 | cdev->doorbells, personality); |
1416 | if (rc) | |
1417 | return rc; | |
1418 | ||
c78df14e | 1419 | personality = p_hwfn->hw_info.personality; |
fe56b9e6 YM |
1420 | |
1421 | /* Initialize the rest of the hwfns */ | |
c78df14e | 1422 | if (cdev->num_hwfns > 1) { |
fe56b9e6 | 1423 | void __iomem *p_regview, *p_doorbell; |
c78df14e AE |
1424 | u8 __iomem *addr; |
1425 | ||
1426 | /* adjust bar offset for second engine */ | |
c2035eea | 1427 | addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; |
c78df14e | 1428 | p_regview = addr; |
fe56b9e6 | 1429 | |
c78df14e | 1430 | /* adjust doorbell bar offset for second engine */ |
c2035eea | 1431 | addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; |
c78df14e AE |
1432 | p_doorbell = addr; |
1433 | ||
1434 | /* prepare second hw function */ | |
1435 | rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, | |
fe56b9e6 | 1436 | p_doorbell, personality); |
c78df14e AE |
1437 | |
1438 | /* in case of error, need to free the previously | |
1439 | * initiliazed hwfn 0. | |
1440 | */ | |
fe56b9e6 | 1441 | if (rc) { |
c78df14e AE |
1442 | qed_init_free(p_hwfn); |
1443 | qed_mcp_free(p_hwfn); | |
1444 | qed_hw_hwfn_free(p_hwfn); | |
fe56b9e6 YM |
1445 | } |
1446 | } | |
1447 | ||
c78df14e | 1448 | return rc; |
fe56b9e6 YM |
1449 | } |
1450 | ||
1451 | void qed_hw_remove(struct qed_dev *cdev) | |
1452 | { | |
1453 | int i; | |
1454 | ||
1455 | for_each_hwfn(cdev, i) { | |
1456 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1457 | ||
1458 | qed_init_free(p_hwfn); | |
1459 | qed_hw_hwfn_free(p_hwfn); | |
1460 | qed_mcp_free(p_hwfn); | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | int qed_chain_alloc(struct qed_dev *cdev, | |
1465 | enum qed_chain_use_mode intended_use, | |
1466 | enum qed_chain_mode mode, | |
1467 | u16 num_elems, | |
1468 | size_t elem_size, | |
1469 | struct qed_chain *p_chain) | |
1470 | { | |
1471 | dma_addr_t p_pbl_phys = 0; | |
1472 | void *p_pbl_virt = NULL; | |
1473 | dma_addr_t p_phys = 0; | |
1474 | void *p_virt = NULL; | |
1475 | u16 page_cnt = 0; | |
1476 | size_t size; | |
1477 | ||
1478 | if (mode == QED_CHAIN_MODE_SINGLE) | |
1479 | page_cnt = 1; | |
1480 | else | |
1481 | page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); | |
1482 | ||
1483 | size = page_cnt * QED_CHAIN_PAGE_SIZE; | |
1484 | p_virt = dma_alloc_coherent(&cdev->pdev->dev, | |
1485 | size, &p_phys, GFP_KERNEL); | |
1486 | if (!p_virt) { | |
1487 | DP_NOTICE(cdev, "Failed to allocate chain mem\n"); | |
1488 | goto nomem; | |
1489 | } | |
1490 | ||
1491 | if (mode == QED_CHAIN_MODE_PBL) { | |
1492 | size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; | |
1493 | p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, | |
1494 | size, &p_pbl_phys, | |
1495 | GFP_KERNEL); | |
1496 | if (!p_pbl_virt) { | |
1497 | DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n"); | |
1498 | goto nomem; | |
1499 | } | |
1500 | ||
1501 | qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt, | |
1502 | (u8)elem_size, intended_use, | |
1503 | p_pbl_phys, p_pbl_virt); | |
1504 | } else { | |
1505 | qed_chain_init(p_chain, p_virt, p_phys, page_cnt, | |
1506 | (u8)elem_size, intended_use, mode); | |
1507 | } | |
1508 | ||
1509 | return 0; | |
1510 | ||
1511 | nomem: | |
1512 | dma_free_coherent(&cdev->pdev->dev, | |
1513 | page_cnt * QED_CHAIN_PAGE_SIZE, | |
1514 | p_virt, p_phys); | |
1515 | dma_free_coherent(&cdev->pdev->dev, | |
1516 | page_cnt * QED_CHAIN_PBL_ENTRY_SIZE, | |
1517 | p_pbl_virt, p_pbl_phys); | |
1518 | ||
1519 | return -ENOMEM; | |
1520 | } | |
1521 | ||
1522 | void qed_chain_free(struct qed_dev *cdev, | |
1523 | struct qed_chain *p_chain) | |
1524 | { | |
1525 | size_t size; | |
1526 | ||
1527 | if (!p_chain->p_virt_addr) | |
1528 | return; | |
1529 | ||
1530 | if (p_chain->mode == QED_CHAIN_MODE_PBL) { | |
1531 | size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; | |
1532 | dma_free_coherent(&cdev->pdev->dev, size, | |
1533 | p_chain->pbl.p_virt_table, | |
1534 | p_chain->pbl.p_phys_table); | |
1535 | } | |
1536 | ||
1537 | size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE; | |
1538 | dma_free_coherent(&cdev->pdev->dev, size, | |
1539 | p_chain->p_virt_addr, | |
1540 | p_chain->p_phys_addr); | |
1541 | } | |
cee4d264 MC |
1542 | |
1543 | int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, | |
1544 | u16 src_id, u16 *dst_id) | |
1545 | { | |
1546 | if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { | |
1547 | u16 min, max; | |
1548 | ||
1549 | min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); | |
1550 | max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
1551 | DP_NOTICE(p_hwfn, | |
1552 | "l2_queue id [%d] is not valid, available indices [%d - %d]\n", | |
1553 | src_id, min, max); | |
1554 | ||
1555 | return -EINVAL; | |
1556 | } | |
1557 | ||
1558 | *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; | |
1559 | ||
1560 | return 0; | |
1561 | } | |
1562 | ||
1563 | int qed_fw_vport(struct qed_hwfn *p_hwfn, | |
1564 | u8 src_id, u8 *dst_id) | |
1565 | { | |
1566 | if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { | |
1567 | u8 min, max; | |
1568 | ||
1569 | min = (u8)RESC_START(p_hwfn, QED_VPORT); | |
1570 | max = min + RESC_NUM(p_hwfn, QED_VPORT); | |
1571 | DP_NOTICE(p_hwfn, | |
1572 | "vport id [%d] is not valid, available indices [%d - %d]\n", | |
1573 | src_id, min, max); | |
1574 | ||
1575 | return -EINVAL; | |
1576 | } | |
1577 | ||
1578 | *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
1583 | int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, | |
1584 | u8 src_id, u8 *dst_id) | |
1585 | { | |
1586 | if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { | |
1587 | u8 min, max; | |
1588 | ||
1589 | min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); | |
1590 | max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); | |
1591 | DP_NOTICE(p_hwfn, | |
1592 | "rss_eng id [%d] is not valid, available indices [%d - %d]\n", | |
1593 | src_id, min, max); | |
1594 | ||
1595 | return -EINVAL; | |
1596 | } | |
1597 | ||
1598 | *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; | |
1599 | ||
1600 | return 0; | |
1601 | } | |
bcd197c8 MC |
1602 | |
1603 | /* Calculate final WFQ values for all vports and configure them. | |
1604 | * After this configuration each vport will have | |
1605 | * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) | |
1606 | */ | |
1607 | static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, | |
1608 | struct qed_ptt *p_ptt, | |
1609 | u32 min_pf_rate) | |
1610 | { | |
1611 | struct init_qm_vport_params *vport_params; | |
1612 | int i; | |
1613 | ||
1614 | vport_params = p_hwfn->qm_info.qm_vport_params; | |
1615 | ||
1616 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { | |
1617 | u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; | |
1618 | ||
1619 | vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / | |
1620 | min_pf_rate; | |
1621 | qed_init_vport_wfq(p_hwfn, p_ptt, | |
1622 | vport_params[i].first_tx_pq_id, | |
1623 | vport_params[i].vport_wfq); | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, | |
1628 | u32 min_pf_rate) | |
1629 | ||
1630 | { | |
1631 | int i; | |
1632 | ||
1633 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) | |
1634 | p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; | |
1635 | } | |
1636 | ||
1637 | static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, | |
1638 | struct qed_ptt *p_ptt, | |
1639 | u32 min_pf_rate) | |
1640 | { | |
1641 | struct init_qm_vport_params *vport_params; | |
1642 | int i; | |
1643 | ||
1644 | vport_params = p_hwfn->qm_info.qm_vport_params; | |
1645 | ||
1646 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { | |
1647 | qed_init_wfq_default_param(p_hwfn, min_pf_rate); | |
1648 | qed_init_vport_wfq(p_hwfn, p_ptt, | |
1649 | vport_params[i].first_tx_pq_id, | |
1650 | vport_params[i].vport_wfq); | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | /* This function performs several validations for WFQ | |
1655 | * configuration and required min rate for a given vport | |
1656 | * 1. req_rate must be greater than one percent of min_pf_rate. | |
1657 | * 2. req_rate should not cause other vports [not configured for WFQ explicitly] | |
1658 | * rates to get less than one percent of min_pf_rate. | |
1659 | * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. | |
1660 | */ | |
1661 | static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, | |
1662 | u16 vport_id, u32 req_rate, | |
1663 | u32 min_pf_rate) | |
1664 | { | |
1665 | u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; | |
1666 | int non_requested_count = 0, req_count = 0, i, num_vports; | |
1667 | ||
1668 | num_vports = p_hwfn->qm_info.num_vports; | |
1669 | ||
1670 | /* Accounting for the vports which are configured for WFQ explicitly */ | |
1671 | for (i = 0; i < num_vports; i++) { | |
1672 | u32 tmp_speed; | |
1673 | ||
1674 | if ((i != vport_id) && | |
1675 | p_hwfn->qm_info.wfq_data[i].configured) { | |
1676 | req_count++; | |
1677 | tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; | |
1678 | total_req_min_rate += tmp_speed; | |
1679 | } | |
1680 | } | |
1681 | ||
1682 | /* Include current vport data as well */ | |
1683 | req_count++; | |
1684 | total_req_min_rate += req_rate; | |
1685 | non_requested_count = num_vports - req_count; | |
1686 | ||
1687 | if (req_rate < min_pf_rate / QED_WFQ_UNIT) { | |
1688 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1689 | "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", | |
1690 | vport_id, req_rate, min_pf_rate); | |
1691 | return -EINVAL; | |
1692 | } | |
1693 | ||
1694 | if (num_vports > QED_WFQ_UNIT) { | |
1695 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1696 | "Number of vports is greater than %d\n", | |
1697 | QED_WFQ_UNIT); | |
1698 | return -EINVAL; | |
1699 | } | |
1700 | ||
1701 | if (total_req_min_rate > min_pf_rate) { | |
1702 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1703 | "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", | |
1704 | total_req_min_rate, min_pf_rate); | |
1705 | return -EINVAL; | |
1706 | } | |
1707 | ||
1708 | total_left_rate = min_pf_rate - total_req_min_rate; | |
1709 | ||
1710 | left_rate_per_vp = total_left_rate / non_requested_count; | |
1711 | if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { | |
1712 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1713 | "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", | |
1714 | left_rate_per_vp, min_pf_rate); | |
1715 | return -EINVAL; | |
1716 | } | |
1717 | ||
1718 | p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; | |
1719 | p_hwfn->qm_info.wfq_data[vport_id].configured = true; | |
1720 | ||
1721 | for (i = 0; i < num_vports; i++) { | |
1722 | if (p_hwfn->qm_info.wfq_data[i].configured) | |
1723 | continue; | |
1724 | ||
1725 | p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; | |
1726 | } | |
1727 | ||
1728 | return 0; | |
1729 | } | |
1730 | ||
1731 | static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, | |
1732 | struct qed_ptt *p_ptt, | |
1733 | u32 min_pf_rate) | |
1734 | { | |
1735 | bool use_wfq = false; | |
1736 | int rc = 0; | |
1737 | u16 i; | |
1738 | ||
1739 | /* Validate all pre configured vports for wfq */ | |
1740 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { | |
1741 | u32 rate; | |
1742 | ||
1743 | if (!p_hwfn->qm_info.wfq_data[i].configured) | |
1744 | continue; | |
1745 | ||
1746 | rate = p_hwfn->qm_info.wfq_data[i].min_speed; | |
1747 | use_wfq = true; | |
1748 | ||
1749 | rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); | |
1750 | if (rc) { | |
1751 | DP_NOTICE(p_hwfn, | |
1752 | "WFQ validation failed while configuring min rate\n"); | |
1753 | break; | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | if (!rc && use_wfq) | |
1758 | qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); | |
1759 | else | |
1760 | qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); | |
1761 | ||
1762 | return rc; | |
1763 | } | |
1764 | ||
1765 | /* API to configure WFQ from mcp link change */ | |
1766 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) | |
1767 | { | |
1768 | int i; | |
1769 | ||
1770 | for_each_hwfn(cdev, i) { | |
1771 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1772 | ||
1773 | __qed_configure_vp_wfq_on_link_change(p_hwfn, | |
1774 | p_hwfn->p_dpc_ptt, | |
1775 | min_pf_rate); | |
1776 | } | |
1777 | } | |
4b01e519 MC |
1778 | |
1779 | int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, | |
1780 | struct qed_ptt *p_ptt, | |
1781 | struct qed_mcp_link_state *p_link, | |
1782 | u8 max_bw) | |
1783 | { | |
1784 | int rc = 0; | |
1785 | ||
1786 | p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; | |
1787 | ||
1788 | if (!p_link->line_speed && (max_bw != 100)) | |
1789 | return rc; | |
1790 | ||
1791 | p_link->speed = (p_link->line_speed * max_bw) / 100; | |
1792 | p_hwfn->qm_info.pf_rl = p_link->speed; | |
1793 | ||
1794 | /* Since the limiter also affects Tx-switched traffic, we don't want it | |
1795 | * to limit such traffic in case there's no actual limit. | |
1796 | * In that case, set limit to imaginary high boundary. | |
1797 | */ | |
1798 | if (max_bw == 100) | |
1799 | p_hwfn->qm_info.pf_rl = 100000; | |
1800 | ||
1801 | rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, | |
1802 | p_hwfn->qm_info.pf_rl); | |
1803 | ||
1804 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1805 | "Configured MAX bandwidth to be %08x Mb/sec\n", | |
1806 | p_link->speed); | |
1807 | ||
1808 | return rc; | |
1809 | } | |
1810 | ||
1811 | /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ | |
1812 | int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) | |
1813 | { | |
1814 | int i, rc = -EINVAL; | |
1815 | ||
1816 | if (max_bw < 1 || max_bw > 100) { | |
1817 | DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); | |
1818 | return rc; | |
1819 | } | |
1820 | ||
1821 | for_each_hwfn(cdev, i) { | |
1822 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1823 | struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); | |
1824 | struct qed_mcp_link_state *p_link; | |
1825 | struct qed_ptt *p_ptt; | |
1826 | ||
1827 | p_link = &p_lead->mcp_info->link_output; | |
1828 | ||
1829 | p_ptt = qed_ptt_acquire(p_hwfn); | |
1830 | if (!p_ptt) | |
1831 | return -EBUSY; | |
1832 | ||
1833 | rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, | |
1834 | p_link, max_bw); | |
1835 | ||
1836 | qed_ptt_release(p_hwfn, p_ptt); | |
1837 | ||
1838 | if (rc) | |
1839 | break; | |
1840 | } | |
1841 | ||
1842 | return rc; | |
1843 | } |