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fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <asm/byteorder.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/mutex.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/qed/qed_chain.h> | |
22 | #include <linux/qed/qed_if.h> | |
23 | #include "qed.h" | |
24 | #include "qed_cxt.h" | |
25 | #include "qed_dev_api.h" | |
26 | #include "qed_hsi.h" | |
27 | #include "qed_hw.h" | |
28 | #include "qed_init_ops.h" | |
29 | #include "qed_int.h" | |
30 | #include "qed_mcp.h" | |
31 | #include "qed_reg_addr.h" | |
32 | #include "qed_sp.h" | |
33 | ||
34 | /* API common to all protocols */ | |
c2035eea RA |
35 | enum BAR_ID { |
36 | BAR_ID_0, /* used for GRC */ | |
37 | BAR_ID_1 /* Used for doorbells */ | |
38 | }; | |
39 | ||
40 | static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, | |
41 | enum BAR_ID bar_id) | |
42 | { | |
43 | u32 bar_reg = (bar_id == BAR_ID_0 ? | |
44 | PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); | |
45 | u32 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); | |
46 | ||
47 | if (val) | |
48 | return 1 << (val + 15); | |
49 | ||
50 | /* Old MFW initialized above registered only conditionally */ | |
51 | if (p_hwfn->cdev->num_hwfns > 1) { | |
52 | DP_INFO(p_hwfn, | |
53 | "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); | |
54 | return BAR_ID_0 ? 256 * 1024 : 512 * 1024; | |
55 | } else { | |
56 | DP_INFO(p_hwfn, | |
57 | "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); | |
58 | return 512 * 1024; | |
59 | } | |
60 | } | |
61 | ||
fe56b9e6 YM |
62 | void qed_init_dp(struct qed_dev *cdev, |
63 | u32 dp_module, u8 dp_level) | |
64 | { | |
65 | u32 i; | |
66 | ||
67 | cdev->dp_level = dp_level; | |
68 | cdev->dp_module = dp_module; | |
69 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { | |
70 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
71 | ||
72 | p_hwfn->dp_level = dp_level; | |
73 | p_hwfn->dp_module = dp_module; | |
74 | } | |
75 | } | |
76 | ||
77 | void qed_init_struct(struct qed_dev *cdev) | |
78 | { | |
79 | u8 i; | |
80 | ||
81 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { | |
82 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
83 | ||
84 | p_hwfn->cdev = cdev; | |
85 | p_hwfn->my_id = i; | |
86 | p_hwfn->b_active = false; | |
87 | ||
88 | mutex_init(&p_hwfn->dmae_info.mutex); | |
89 | } | |
90 | ||
91 | /* hwfn 0 is always active */ | |
92 | cdev->hwfns[0].b_active = true; | |
93 | ||
94 | /* set the default cache alignment to 128 */ | |
95 | cdev->cache_shift = 7; | |
96 | } | |
97 | ||
98 | static void qed_qm_info_free(struct qed_hwfn *p_hwfn) | |
99 | { | |
100 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
101 | ||
102 | kfree(qm_info->qm_pq_params); | |
103 | qm_info->qm_pq_params = NULL; | |
104 | kfree(qm_info->qm_vport_params); | |
105 | qm_info->qm_vport_params = NULL; | |
106 | kfree(qm_info->qm_port_params); | |
107 | qm_info->qm_port_params = NULL; | |
108 | } | |
109 | ||
110 | void qed_resc_free(struct qed_dev *cdev) | |
111 | { | |
112 | int i; | |
113 | ||
114 | kfree(cdev->fw_data); | |
115 | cdev->fw_data = NULL; | |
116 | ||
117 | kfree(cdev->reset_stats); | |
118 | ||
25c089d7 YM |
119 | for_each_hwfn(cdev, i) { |
120 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
121 | ||
122 | kfree(p_hwfn->p_tx_cids); | |
123 | p_hwfn->p_tx_cids = NULL; | |
124 | kfree(p_hwfn->p_rx_cids); | |
125 | p_hwfn->p_rx_cids = NULL; | |
126 | } | |
127 | ||
fe56b9e6 YM |
128 | for_each_hwfn(cdev, i) { |
129 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
130 | ||
131 | qed_cxt_mngr_free(p_hwfn); | |
132 | qed_qm_info_free(p_hwfn); | |
133 | qed_spq_free(p_hwfn); | |
134 | qed_eq_free(p_hwfn, p_hwfn->p_eq); | |
135 | qed_consq_free(p_hwfn, p_hwfn->p_consq); | |
136 | qed_int_free(p_hwfn); | |
137 | qed_dmae_info_free(p_hwfn); | |
138 | } | |
139 | } | |
140 | ||
141 | static int qed_init_qm_info(struct qed_hwfn *p_hwfn) | |
142 | { | |
143 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
144 | struct init_qm_port_params *p_qm_port; | |
145 | u8 num_vports, i, vport_id, num_ports; | |
146 | u16 num_pqs, multi_cos_tcs = 1; | |
147 | ||
148 | memset(qm_info, 0, sizeof(*qm_info)); | |
149 | ||
150 | num_pqs = multi_cos_tcs + 1; /* The '1' is for pure-LB */ | |
151 | num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); | |
152 | ||
153 | /* Sanity checking that setup requires legal number of resources */ | |
154 | if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { | |
155 | DP_ERR(p_hwfn, | |
156 | "Need too many Physical queues - 0x%04x when only %04x are available\n", | |
157 | num_pqs, RESC_NUM(p_hwfn, QED_PQ)); | |
158 | return -EINVAL; | |
159 | } | |
160 | ||
161 | /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. | |
162 | */ | |
163 | qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) * | |
60fffb3b | 164 | num_pqs, GFP_KERNEL); |
fe56b9e6 YM |
165 | if (!qm_info->qm_pq_params) |
166 | goto alloc_err; | |
167 | ||
168 | qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) * | |
60fffb3b | 169 | num_vports, GFP_KERNEL); |
fe56b9e6 YM |
170 | if (!qm_info->qm_vport_params) |
171 | goto alloc_err; | |
172 | ||
173 | qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) * | |
60fffb3b | 174 | MAX_NUM_PORTS, GFP_KERNEL); |
fe56b9e6 YM |
175 | if (!qm_info->qm_port_params) |
176 | goto alloc_err; | |
177 | ||
178 | vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); | |
179 | ||
180 | /* First init per-TC PQs */ | |
181 | for (i = 0; i < multi_cos_tcs; i++) { | |
182 | struct init_qm_pq_params *params = &qm_info->qm_pq_params[i]; | |
183 | ||
184 | params->vport_id = vport_id; | |
185 | params->tc_id = p_hwfn->hw_info.non_offload_tc; | |
186 | params->wrr_group = 1; | |
187 | } | |
188 | ||
189 | /* Then init pure-LB PQ */ | |
190 | qm_info->pure_lb_pq = i; | |
191 | qm_info->qm_pq_params[i].vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); | |
192 | qm_info->qm_pq_params[i].tc_id = PURE_LB_TC; | |
193 | qm_info->qm_pq_params[i].wrr_group = 1; | |
194 | i++; | |
195 | ||
196 | qm_info->offload_pq = 0; | |
197 | qm_info->num_pqs = num_pqs; | |
198 | qm_info->num_vports = num_vports; | |
199 | ||
200 | /* Initialize qm port parameters */ | |
201 | num_ports = p_hwfn->cdev->num_ports_in_engines; | |
202 | for (i = 0; i < num_ports; i++) { | |
203 | p_qm_port = &qm_info->qm_port_params[i]; | |
204 | p_qm_port->active = 1; | |
205 | p_qm_port->num_active_phys_tcs = 4; | |
206 | p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; | |
207 | p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; | |
208 | } | |
209 | ||
210 | qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; | |
211 | ||
212 | qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); | |
213 | ||
214 | qm_info->start_vport = (u8)RESC_START(p_hwfn, QED_VPORT); | |
215 | ||
216 | qm_info->pf_wfq = 0; | |
217 | qm_info->pf_rl = 0; | |
218 | qm_info->vport_rl_en = 1; | |
219 | ||
220 | return 0; | |
221 | ||
222 | alloc_err: | |
223 | DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); | |
224 | kfree(qm_info->qm_pq_params); | |
225 | kfree(qm_info->qm_vport_params); | |
226 | kfree(qm_info->qm_port_params); | |
227 | ||
228 | return -ENOMEM; | |
229 | } | |
230 | ||
231 | int qed_resc_alloc(struct qed_dev *cdev) | |
232 | { | |
233 | struct qed_consq *p_consq; | |
234 | struct qed_eq *p_eq; | |
235 | int i, rc = 0; | |
236 | ||
237 | cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); | |
238 | if (!cdev->fw_data) | |
239 | return -ENOMEM; | |
240 | ||
25c089d7 YM |
241 | /* Allocate Memory for the Queue->CID mapping */ |
242 | for_each_hwfn(cdev, i) { | |
243 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
244 | int tx_size = sizeof(struct qed_hw_cid_data) * | |
245 | RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
246 | int rx_size = sizeof(struct qed_hw_cid_data) * | |
247 | RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
248 | ||
249 | p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); | |
250 | if (!p_hwfn->p_tx_cids) { | |
251 | DP_NOTICE(p_hwfn, | |
252 | "Failed to allocate memory for Tx Cids\n"); | |
9b15acbf | 253 | rc = -ENOMEM; |
25c089d7 YM |
254 | goto alloc_err; |
255 | } | |
256 | ||
257 | p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); | |
258 | if (!p_hwfn->p_rx_cids) { | |
259 | DP_NOTICE(p_hwfn, | |
260 | "Failed to allocate memory for Rx Cids\n"); | |
9b15acbf | 261 | rc = -ENOMEM; |
25c089d7 YM |
262 | goto alloc_err; |
263 | } | |
264 | } | |
265 | ||
fe56b9e6 YM |
266 | for_each_hwfn(cdev, i) { |
267 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
268 | ||
269 | /* First allocate the context manager structure */ | |
270 | rc = qed_cxt_mngr_alloc(p_hwfn); | |
271 | if (rc) | |
272 | goto alloc_err; | |
273 | ||
274 | /* Set the HW cid/tid numbers (in the contest manager) | |
275 | * Must be done prior to any further computations. | |
276 | */ | |
277 | rc = qed_cxt_set_pf_params(p_hwfn); | |
278 | if (rc) | |
279 | goto alloc_err; | |
280 | ||
281 | /* Prepare and process QM requirements */ | |
282 | rc = qed_init_qm_info(p_hwfn); | |
283 | if (rc) | |
284 | goto alloc_err; | |
285 | ||
286 | /* Compute the ILT client partition */ | |
287 | rc = qed_cxt_cfg_ilt_compute(p_hwfn); | |
288 | if (rc) | |
289 | goto alloc_err; | |
290 | ||
291 | /* CID map / ILT shadow table / T2 | |
292 | * The talbes sizes are determined by the computations above | |
293 | */ | |
294 | rc = qed_cxt_tables_alloc(p_hwfn); | |
295 | if (rc) | |
296 | goto alloc_err; | |
297 | ||
298 | /* SPQ, must follow ILT because initializes SPQ context */ | |
299 | rc = qed_spq_alloc(p_hwfn); | |
300 | if (rc) | |
301 | goto alloc_err; | |
302 | ||
303 | /* SP status block allocation */ | |
304 | p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, | |
305 | RESERVED_PTT_DPC); | |
306 | ||
307 | rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); | |
308 | if (rc) | |
309 | goto alloc_err; | |
310 | ||
311 | /* EQ */ | |
312 | p_eq = qed_eq_alloc(p_hwfn, 256); | |
9b15acbf DC |
313 | if (!p_eq) { |
314 | rc = -ENOMEM; | |
fe56b9e6 | 315 | goto alloc_err; |
9b15acbf | 316 | } |
fe56b9e6 YM |
317 | p_hwfn->p_eq = p_eq; |
318 | ||
319 | p_consq = qed_consq_alloc(p_hwfn); | |
9b15acbf DC |
320 | if (!p_consq) { |
321 | rc = -ENOMEM; | |
fe56b9e6 | 322 | goto alloc_err; |
9b15acbf | 323 | } |
fe56b9e6 YM |
324 | p_hwfn->p_consq = p_consq; |
325 | ||
326 | /* DMA info initialization */ | |
327 | rc = qed_dmae_info_alloc(p_hwfn); | |
328 | if (rc) { | |
329 | DP_NOTICE(p_hwfn, | |
330 | "Failed to allocate memory for dmae_info structure\n"); | |
331 | goto alloc_err; | |
332 | } | |
333 | } | |
334 | ||
335 | cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); | |
336 | if (!cdev->reset_stats) { | |
337 | DP_NOTICE(cdev, "Failed to allocate reset statistics\n"); | |
9b15acbf | 338 | rc = -ENOMEM; |
fe56b9e6 YM |
339 | goto alloc_err; |
340 | } | |
341 | ||
342 | return 0; | |
343 | ||
344 | alloc_err: | |
345 | qed_resc_free(cdev); | |
346 | return rc; | |
347 | } | |
348 | ||
349 | void qed_resc_setup(struct qed_dev *cdev) | |
350 | { | |
351 | int i; | |
352 | ||
353 | for_each_hwfn(cdev, i) { | |
354 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
355 | ||
356 | qed_cxt_mngr_setup(p_hwfn); | |
357 | qed_spq_setup(p_hwfn); | |
358 | qed_eq_setup(p_hwfn, p_hwfn->p_eq); | |
359 | qed_consq_setup(p_hwfn, p_hwfn->p_consq); | |
360 | ||
361 | /* Read shadow of current MFW mailbox */ | |
362 | qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); | |
363 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, | |
364 | p_hwfn->mcp_info->mfw_mb_cur, | |
365 | p_hwfn->mcp_info->mfw_mb_length); | |
366 | ||
367 | qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); | |
368 | } | |
369 | } | |
370 | ||
fe56b9e6 YM |
371 | #define FINAL_CLEANUP_POLL_CNT (100) |
372 | #define FINAL_CLEANUP_POLL_TIME (10) | |
373 | int qed_final_cleanup(struct qed_hwfn *p_hwfn, | |
374 | struct qed_ptt *p_ptt, | |
375 | u16 id) | |
376 | { | |
377 | u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; | |
378 | int rc = -EBUSY; | |
379 | ||
fc48b7a6 YM |
380 | addr = GTT_BAR0_MAP_REG_USDM_RAM + |
381 | USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); | |
fe56b9e6 | 382 | |
fc48b7a6 YM |
383 | command |= X_FINAL_CLEANUP_AGG_INT << |
384 | SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; | |
385 | command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; | |
386 | command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; | |
387 | command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; | |
fe56b9e6 YM |
388 | |
389 | /* Make sure notification is not set before initiating final cleanup */ | |
390 | if (REG_RD(p_hwfn, addr)) { | |
391 | DP_NOTICE( | |
392 | p_hwfn, | |
393 | "Unexpected; Found final cleanup notification before initiating final cleanup\n"); | |
394 | REG_WR(p_hwfn, addr, 0); | |
395 | } | |
396 | ||
397 | DP_VERBOSE(p_hwfn, QED_MSG_IOV, | |
398 | "Sending final cleanup for PFVF[%d] [Command %08x\n]", | |
399 | id, command); | |
400 | ||
401 | qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); | |
402 | ||
403 | /* Poll until completion */ | |
404 | while (!REG_RD(p_hwfn, addr) && count--) | |
405 | msleep(FINAL_CLEANUP_POLL_TIME); | |
406 | ||
407 | if (REG_RD(p_hwfn, addr)) | |
408 | rc = 0; | |
409 | else | |
410 | DP_NOTICE(p_hwfn, | |
411 | "Failed to receive FW final cleanup notification\n"); | |
412 | ||
413 | /* Cleanup afterwards */ | |
414 | REG_WR(p_hwfn, addr, 0); | |
415 | ||
416 | return rc; | |
417 | } | |
418 | ||
419 | static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) | |
420 | { | |
421 | int hw_mode = 0; | |
422 | ||
12e09c69 | 423 | hw_mode = (1 << MODE_BB_B0); |
fe56b9e6 YM |
424 | |
425 | switch (p_hwfn->cdev->num_ports_in_engines) { | |
426 | case 1: | |
427 | hw_mode |= 1 << MODE_PORTS_PER_ENG_1; | |
428 | break; | |
429 | case 2: | |
430 | hw_mode |= 1 << MODE_PORTS_PER_ENG_2; | |
431 | break; | |
432 | case 4: | |
433 | hw_mode |= 1 << MODE_PORTS_PER_ENG_4; | |
434 | break; | |
435 | default: | |
436 | DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", | |
437 | p_hwfn->cdev->num_ports_in_engines); | |
438 | return; | |
439 | } | |
440 | ||
441 | switch (p_hwfn->cdev->mf_mode) { | |
fc48b7a6 YM |
442 | case QED_MF_DEFAULT: |
443 | case QED_MF_NPAR: | |
444 | hw_mode |= 1 << MODE_MF_SI; | |
fe56b9e6 | 445 | break; |
fc48b7a6 | 446 | case QED_MF_OVLAN: |
fe56b9e6 YM |
447 | hw_mode |= 1 << MODE_MF_SD; |
448 | break; | |
fe56b9e6 | 449 | default: |
fc48b7a6 YM |
450 | DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); |
451 | hw_mode |= 1 << MODE_MF_SI; | |
fe56b9e6 YM |
452 | } |
453 | ||
454 | hw_mode |= 1 << MODE_ASIC; | |
455 | ||
456 | p_hwfn->hw_info.hw_mode = hw_mode; | |
457 | } | |
458 | ||
459 | /* Init run time data for all PFs on an engine. */ | |
460 | static void qed_init_cau_rt_data(struct qed_dev *cdev) | |
461 | { | |
462 | u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; | |
463 | int i, sb_id; | |
464 | ||
465 | for_each_hwfn(cdev, i) { | |
466 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
467 | struct qed_igu_info *p_igu_info; | |
468 | struct qed_igu_block *p_block; | |
469 | struct cau_sb_entry sb_entry; | |
470 | ||
471 | p_igu_info = p_hwfn->hw_info.p_igu_info; | |
472 | ||
473 | for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); | |
474 | sb_id++) { | |
475 | p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; | |
476 | if (!p_block->is_pf) | |
477 | continue; | |
478 | ||
479 | qed_init_cau_sb_entry(p_hwfn, &sb_entry, | |
480 | p_block->function_id, | |
481 | 0, 0); | |
482 | STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, | |
483 | sb_entry); | |
484 | } | |
485 | } | |
486 | } | |
487 | ||
488 | static int qed_hw_init_common(struct qed_hwfn *p_hwfn, | |
489 | struct qed_ptt *p_ptt, | |
490 | int hw_mode) | |
491 | { | |
492 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
493 | struct qed_qm_common_rt_init_params params; | |
494 | struct qed_dev *cdev = p_hwfn->cdev; | |
495 | int rc = 0; | |
496 | ||
497 | qed_init_cau_rt_data(cdev); | |
498 | ||
499 | /* Program GTT windows */ | |
500 | qed_gtt_init(p_hwfn); | |
501 | ||
502 | if (p_hwfn->mcp_info) { | |
503 | if (p_hwfn->mcp_info->func_info.bandwidth_max) | |
504 | qm_info->pf_rl_en = 1; | |
505 | if (p_hwfn->mcp_info->func_info.bandwidth_min) | |
506 | qm_info->pf_wfq_en = 1; | |
507 | } | |
508 | ||
509 | memset(¶ms, 0, sizeof(params)); | |
510 | params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; | |
511 | params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; | |
512 | params.pf_rl_en = qm_info->pf_rl_en; | |
513 | params.pf_wfq_en = qm_info->pf_wfq_en; | |
514 | params.vport_rl_en = qm_info->vport_rl_en; | |
515 | params.vport_wfq_en = qm_info->vport_wfq_en; | |
516 | params.port_params = qm_info->qm_port_params; | |
517 | ||
518 | qed_qm_common_rt_init(p_hwfn, ¶ms); | |
519 | ||
520 | qed_cxt_hw_init_common(p_hwfn); | |
521 | ||
522 | /* Close gate from NIG to BRB/Storm; By default they are open, but | |
523 | * we close them to prevent NIG from passing data to reset blocks. | |
524 | * Should have been done in the ENGINE phase, but init-tool lacks | |
525 | * proper port-pretend capabilities. | |
526 | */ | |
527 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); | |
528 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); | |
529 | qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); | |
530 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); | |
531 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); | |
532 | qed_port_unpretend(p_hwfn, p_ptt); | |
533 | ||
534 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); | |
535 | if (rc != 0) | |
536 | return rc; | |
537 | ||
538 | qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); | |
539 | qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); | |
540 | ||
541 | /* Disable relaxed ordering in the PCI config space */ | |
542 | qed_wr(p_hwfn, p_ptt, 0x20b4, | |
543 | qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10); | |
544 | ||
545 | return rc; | |
546 | } | |
547 | ||
548 | static int qed_hw_init_port(struct qed_hwfn *p_hwfn, | |
549 | struct qed_ptt *p_ptt, | |
550 | int hw_mode) | |
551 | { | |
552 | int rc = 0; | |
553 | ||
554 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, | |
555 | hw_mode); | |
556 | return rc; | |
557 | } | |
558 | ||
559 | static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, | |
560 | struct qed_ptt *p_ptt, | |
561 | int hw_mode, | |
562 | bool b_hw_start, | |
563 | enum qed_int_mode int_mode, | |
564 | bool allow_npar_tx_switch) | |
565 | { | |
566 | u8 rel_pf_id = p_hwfn->rel_pf_id; | |
567 | int rc = 0; | |
568 | ||
569 | if (p_hwfn->mcp_info) { | |
570 | struct qed_mcp_function_info *p_info; | |
571 | ||
572 | p_info = &p_hwfn->mcp_info->func_info; | |
573 | if (p_info->bandwidth_min) | |
574 | p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; | |
575 | ||
576 | /* Update rate limit once we'll actually have a link */ | |
577 | p_hwfn->qm_info.pf_rl = 100; | |
578 | } | |
579 | ||
580 | qed_cxt_hw_init_pf(p_hwfn); | |
581 | ||
582 | qed_int_igu_init_rt(p_hwfn); | |
583 | ||
584 | /* Set VLAN in NIG if needed */ | |
585 | if (hw_mode & (1 << MODE_MF_SD)) { | |
586 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); | |
587 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); | |
588 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, | |
589 | p_hwfn->hw_info.ovlan); | |
590 | } | |
591 | ||
592 | /* Enable classification by MAC if needed */ | |
87aec47d | 593 | if (hw_mode & (1 << MODE_MF_SI)) { |
fe56b9e6 YM |
594 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, |
595 | "Configuring TAGMAC_CLS_TYPE\n"); | |
596 | STORE_RT_REG(p_hwfn, | |
597 | NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); | |
598 | } | |
599 | ||
600 | /* Protocl Configuration */ | |
601 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0); | |
602 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); | |
603 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); | |
604 | ||
605 | /* Cleanup chip from previous driver if such remains exist */ | |
606 | rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id); | |
607 | if (rc != 0) | |
608 | return rc; | |
609 | ||
610 | /* PF Init sequence */ | |
611 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); | |
612 | if (rc) | |
613 | return rc; | |
614 | ||
615 | /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ | |
616 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); | |
617 | if (rc) | |
618 | return rc; | |
619 | ||
620 | /* Pure runtime initializations - directly to the HW */ | |
621 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); | |
622 | ||
623 | if (b_hw_start) { | |
624 | /* enable interrupts */ | |
625 | qed_int_igu_enable(p_hwfn, p_ptt, int_mode); | |
626 | ||
627 | /* send function start command */ | |
628 | rc = qed_sp_pf_start(p_hwfn, p_hwfn->cdev->mf_mode); | |
629 | if (rc) | |
630 | DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); | |
631 | } | |
632 | return rc; | |
633 | } | |
634 | ||
635 | static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, | |
636 | struct qed_ptt *p_ptt, | |
637 | u8 enable) | |
638 | { | |
639 | u32 delay_idx = 0, val, set_val = enable ? 1 : 0; | |
640 | ||
641 | /* Change PF in PXP */ | |
642 | qed_wr(p_hwfn, p_ptt, | |
643 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); | |
644 | ||
645 | /* wait until value is set - try for 1 second every 50us */ | |
646 | for (delay_idx = 0; delay_idx < 20000; delay_idx++) { | |
647 | val = qed_rd(p_hwfn, p_ptt, | |
648 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
649 | if (val == set_val) | |
650 | break; | |
651 | ||
652 | usleep_range(50, 60); | |
653 | } | |
654 | ||
655 | if (val != set_val) { | |
656 | DP_NOTICE(p_hwfn, | |
657 | "PFID_ENABLE_MASTER wasn't changed after a second\n"); | |
658 | return -EAGAIN; | |
659 | } | |
660 | ||
661 | return 0; | |
662 | } | |
663 | ||
664 | static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, | |
665 | struct qed_ptt *p_main_ptt) | |
666 | { | |
667 | /* Read shadow of current MFW mailbox */ | |
668 | qed_mcp_read_mb(p_hwfn, p_main_ptt); | |
669 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, | |
670 | p_hwfn->mcp_info->mfw_mb_cur, | |
671 | p_hwfn->mcp_info->mfw_mb_length); | |
672 | } | |
673 | ||
674 | int qed_hw_init(struct qed_dev *cdev, | |
675 | bool b_hw_start, | |
676 | enum qed_int_mode int_mode, | |
677 | bool allow_npar_tx_switch, | |
678 | const u8 *bin_fw_data) | |
679 | { | |
86622ee7 | 680 | u32 load_code, param; |
fe56b9e6 YM |
681 | int rc, mfw_rc, i; |
682 | ||
683 | rc = qed_init_fw_data(cdev, bin_fw_data); | |
684 | if (rc != 0) | |
685 | return rc; | |
686 | ||
687 | for_each_hwfn(cdev, i) { | |
688 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
689 | ||
690 | /* Enable DMAE in PXP */ | |
691 | rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); | |
692 | ||
693 | qed_calc_hw_mode(p_hwfn); | |
694 | ||
695 | rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, | |
696 | &load_code); | |
697 | if (rc) { | |
698 | DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); | |
699 | return rc; | |
700 | } | |
701 | ||
702 | qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); | |
703 | ||
704 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
705 | "Load request was sent. Resp:0x%x, Load code: 0x%x\n", | |
706 | rc, load_code); | |
707 | ||
708 | p_hwfn->first_on_engine = (load_code == | |
709 | FW_MSG_CODE_DRV_LOAD_ENGINE); | |
710 | ||
711 | switch (load_code) { | |
712 | case FW_MSG_CODE_DRV_LOAD_ENGINE: | |
713 | rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, | |
714 | p_hwfn->hw_info.hw_mode); | |
715 | if (rc) | |
716 | break; | |
717 | /* Fall into */ | |
718 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
719 | rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, | |
720 | p_hwfn->hw_info.hw_mode); | |
721 | if (rc) | |
722 | break; | |
723 | ||
724 | /* Fall into */ | |
725 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
726 | rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, | |
727 | p_hwfn->hw_info.hw_mode, | |
728 | b_hw_start, int_mode, | |
729 | allow_npar_tx_switch); | |
730 | break; | |
731 | default: | |
732 | rc = -EINVAL; | |
733 | break; | |
734 | } | |
735 | ||
736 | if (rc) | |
737 | DP_NOTICE(p_hwfn, | |
738 | "init phase failed for loadcode 0x%x (rc %d)\n", | |
739 | load_code, rc); | |
740 | ||
741 | /* ACK mfw regardless of success or failure of initialization */ | |
742 | mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
743 | DRV_MSG_CODE_LOAD_DONE, | |
744 | 0, &load_code, ¶m); | |
745 | if (rc) | |
746 | return rc; | |
747 | if (mfw_rc) { | |
748 | DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); | |
749 | return mfw_rc; | |
750 | } | |
751 | ||
752 | p_hwfn->hw_init_done = true; | |
753 | } | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
758 | #define QED_HW_STOP_RETRY_LIMIT (10) | |
759 | int qed_hw_stop(struct qed_dev *cdev) | |
760 | { | |
761 | int rc = 0, t_rc; | |
762 | int i, j; | |
763 | ||
764 | for_each_hwfn(cdev, j) { | |
765 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
766 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
767 | ||
768 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); | |
769 | ||
770 | /* mark the hw as uninitialized... */ | |
771 | p_hwfn->hw_init_done = false; | |
772 | ||
773 | rc = qed_sp_pf_stop(p_hwfn); | |
774 | if (rc) | |
775 | return rc; | |
776 | ||
777 | qed_wr(p_hwfn, p_ptt, | |
778 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); | |
779 | ||
780 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); | |
781 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); | |
782 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); | |
783 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); | |
784 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); | |
785 | ||
786 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); | |
787 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); | |
788 | for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { | |
789 | if ((!qed_rd(p_hwfn, p_ptt, | |
790 | TM_REG_PF_SCAN_ACTIVE_CONN)) && | |
791 | (!qed_rd(p_hwfn, p_ptt, | |
792 | TM_REG_PF_SCAN_ACTIVE_TASK))) | |
793 | break; | |
794 | ||
795 | usleep_range(1000, 2000); | |
796 | } | |
797 | if (i == QED_HW_STOP_RETRY_LIMIT) | |
798 | DP_NOTICE(p_hwfn, | |
799 | "Timers linear scans are not over [Connection %02x Tasks %02x]\n", | |
800 | (u8)qed_rd(p_hwfn, p_ptt, | |
801 | TM_REG_PF_SCAN_ACTIVE_CONN), | |
802 | (u8)qed_rd(p_hwfn, p_ptt, | |
803 | TM_REG_PF_SCAN_ACTIVE_TASK)); | |
804 | ||
805 | /* Disable Attention Generation */ | |
806 | qed_int_igu_disable_int(p_hwfn, p_ptt); | |
807 | ||
808 | qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); | |
809 | qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
810 | ||
811 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); | |
812 | ||
813 | /* Need to wait 1ms to guarantee SBs are cleared */ | |
814 | usleep_range(1000, 2000); | |
815 | } | |
816 | ||
817 | /* Disable DMAE in PXP - in CMT, this should only be done for | |
818 | * first hw-function, and only after all transactions have | |
819 | * stopped for all active hw-functions. | |
820 | */ | |
821 | t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], | |
822 | cdev->hwfns[0].p_main_ptt, | |
823 | false); | |
824 | if (t_rc != 0) | |
825 | rc = t_rc; | |
826 | ||
827 | return rc; | |
828 | } | |
829 | ||
cee4d264 MC |
830 | void qed_hw_stop_fastpath(struct qed_dev *cdev) |
831 | { | |
832 | int i, j; | |
833 | ||
834 | for_each_hwfn(cdev, j) { | |
835 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
836 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
837 | ||
838 | DP_VERBOSE(p_hwfn, | |
839 | NETIF_MSG_IFDOWN, | |
840 | "Shutting down the fastpath\n"); | |
841 | ||
842 | qed_wr(p_hwfn, p_ptt, | |
843 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); | |
844 | ||
845 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); | |
846 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); | |
847 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); | |
848 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); | |
849 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); | |
850 | ||
851 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); | |
852 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); | |
853 | for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { | |
854 | if ((!qed_rd(p_hwfn, p_ptt, | |
855 | TM_REG_PF_SCAN_ACTIVE_CONN)) && | |
856 | (!qed_rd(p_hwfn, p_ptt, | |
857 | TM_REG_PF_SCAN_ACTIVE_TASK))) | |
858 | break; | |
859 | ||
860 | usleep_range(1000, 2000); | |
861 | } | |
862 | if (i == QED_HW_STOP_RETRY_LIMIT) | |
863 | DP_NOTICE(p_hwfn, | |
864 | "Timers linear scans are not over [Connection %02x Tasks %02x]\n", | |
865 | (u8)qed_rd(p_hwfn, p_ptt, | |
866 | TM_REG_PF_SCAN_ACTIVE_CONN), | |
867 | (u8)qed_rd(p_hwfn, p_ptt, | |
868 | TM_REG_PF_SCAN_ACTIVE_TASK)); | |
869 | ||
870 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); | |
871 | ||
872 | /* Need to wait 1ms to guarantee SBs are cleared */ | |
873 | usleep_range(1000, 2000); | |
874 | } | |
875 | } | |
876 | ||
877 | void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) | |
878 | { | |
879 | /* Re-open incoming traffic */ | |
880 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
881 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); | |
882 | } | |
883 | ||
fe56b9e6 YM |
884 | static int qed_reg_assert(struct qed_hwfn *hwfn, |
885 | struct qed_ptt *ptt, u32 reg, | |
886 | bool expected) | |
887 | { | |
888 | u32 assert_val = qed_rd(hwfn, ptt, reg); | |
889 | ||
890 | if (assert_val != expected) { | |
891 | DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n", | |
892 | reg, expected); | |
893 | return -EINVAL; | |
894 | } | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | int qed_hw_reset(struct qed_dev *cdev) | |
900 | { | |
901 | int rc = 0; | |
902 | u32 unload_resp, unload_param; | |
903 | int i; | |
904 | ||
905 | for_each_hwfn(cdev, i) { | |
906 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
907 | ||
908 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); | |
909 | ||
910 | /* Check for incorrect states */ | |
911 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, | |
912 | QM_REG_USG_CNT_PF_TX, 0); | |
913 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, | |
914 | QM_REG_USG_CNT_PF_OTHER, 0); | |
915 | ||
916 | /* Disable PF in HW blocks */ | |
917 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); | |
918 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); | |
919 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
920 | TCFC_REG_STRONG_ENABLE_PF, 0); | |
921 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
922 | CCFC_REG_STRONG_ENABLE_PF, 0); | |
923 | ||
924 | /* Send unload command to MCP */ | |
925 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
926 | DRV_MSG_CODE_UNLOAD_REQ, | |
927 | DRV_MB_PARAM_UNLOAD_WOL_MCP, | |
928 | &unload_resp, &unload_param); | |
929 | if (rc) { | |
930 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); | |
931 | unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; | |
932 | } | |
933 | ||
934 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
935 | DRV_MSG_CODE_UNLOAD_DONE, | |
936 | 0, &unload_resp, &unload_param); | |
937 | if (rc) { | |
938 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); | |
939 | return rc; | |
940 | } | |
941 | } | |
942 | ||
943 | return rc; | |
944 | } | |
945 | ||
946 | /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ | |
947 | static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) | |
948 | { | |
949 | qed_ptt_pool_free(p_hwfn); | |
950 | kfree(p_hwfn->hw_info.p_igu_info); | |
951 | } | |
952 | ||
953 | /* Setup bar access */ | |
12e09c69 | 954 | static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) |
fe56b9e6 | 955 | { |
fe56b9e6 YM |
956 | /* clear indirect access */ |
957 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); | |
958 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); | |
959 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); | |
960 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); | |
961 | ||
962 | /* Clean Previous errors if such exist */ | |
963 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
964 | PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, | |
965 | 1 << p_hwfn->abs_pf_id); | |
966 | ||
967 | /* enable internal target-read */ | |
968 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
969 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
fe56b9e6 YM |
970 | } |
971 | ||
972 | static void get_function_id(struct qed_hwfn *p_hwfn) | |
973 | { | |
974 | /* ME Register */ | |
975 | p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR); | |
976 | ||
977 | p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); | |
978 | ||
979 | p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; | |
980 | p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, | |
981 | PXP_CONCRETE_FID_PFID); | |
982 | p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, | |
983 | PXP_CONCRETE_FID_PORT); | |
984 | } | |
985 | ||
25c089d7 YM |
986 | static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) |
987 | { | |
988 | u32 *feat_num = p_hwfn->hw_info.feat_num; | |
989 | int num_features = 1; | |
990 | ||
991 | feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / | |
992 | num_features, | |
993 | RESC_NUM(p_hwfn, QED_L2_QUEUE)); | |
994 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, | |
995 | "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", | |
996 | feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), | |
997 | num_features); | |
998 | } | |
999 | ||
fe56b9e6 YM |
1000 | static void qed_hw_get_resc(struct qed_hwfn *p_hwfn) |
1001 | { | |
1002 | u32 *resc_start = p_hwfn->hw_info.resc_start; | |
1003 | u32 *resc_num = p_hwfn->hw_info.resc_num; | |
4ac801b7 | 1004 | struct qed_sb_cnt_info sb_cnt_info; |
fe56b9e6 YM |
1005 | int num_funcs, i; |
1006 | ||
fc48b7a6 | 1007 | num_funcs = MAX_NUM_PFS_BB; |
fe56b9e6 | 1008 | |
4ac801b7 YM |
1009 | memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); |
1010 | qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); | |
1011 | ||
fe56b9e6 YM |
1012 | resc_num[QED_SB] = min_t(u32, |
1013 | (MAX_SB_PER_PATH_BB / num_funcs), | |
4ac801b7 | 1014 | sb_cnt_info.sb_cnt); |
25c089d7 | 1015 | resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; |
fe56b9e6 | 1016 | resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; |
25c089d7 | 1017 | resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; |
fe56b9e6 YM |
1018 | resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; |
1019 | resc_num[QED_RL] = 8; | |
25c089d7 YM |
1020 | resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; |
1021 | resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / | |
1022 | num_funcs; | |
fe56b9e6 YM |
1023 | resc_num[QED_ILT] = 950; |
1024 | ||
1025 | for (i = 0; i < QED_MAX_RESC; i++) | |
1026 | resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id; | |
1027 | ||
25c089d7 YM |
1028 | qed_hw_set_feat(p_hwfn); |
1029 | ||
fe56b9e6 YM |
1030 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, |
1031 | "The numbers for each resource are:\n" | |
1032 | "SB = %d start = %d\n" | |
25c089d7 | 1033 | "L2_QUEUE = %d start = %d\n" |
fe56b9e6 YM |
1034 | "VPORT = %d start = %d\n" |
1035 | "PQ = %d start = %d\n" | |
1036 | "RL = %d start = %d\n" | |
25c089d7 YM |
1037 | "MAC = %d start = %d\n" |
1038 | "VLAN = %d start = %d\n" | |
fe56b9e6 YM |
1039 | "ILT = %d start = %d\n", |
1040 | p_hwfn->hw_info.resc_num[QED_SB], | |
1041 | p_hwfn->hw_info.resc_start[QED_SB], | |
25c089d7 YM |
1042 | p_hwfn->hw_info.resc_num[QED_L2_QUEUE], |
1043 | p_hwfn->hw_info.resc_start[QED_L2_QUEUE], | |
fe56b9e6 YM |
1044 | p_hwfn->hw_info.resc_num[QED_VPORT], |
1045 | p_hwfn->hw_info.resc_start[QED_VPORT], | |
1046 | p_hwfn->hw_info.resc_num[QED_PQ], | |
1047 | p_hwfn->hw_info.resc_start[QED_PQ], | |
1048 | p_hwfn->hw_info.resc_num[QED_RL], | |
1049 | p_hwfn->hw_info.resc_start[QED_RL], | |
25c089d7 YM |
1050 | p_hwfn->hw_info.resc_num[QED_MAC], |
1051 | p_hwfn->hw_info.resc_start[QED_MAC], | |
1052 | p_hwfn->hw_info.resc_num[QED_VLAN], | |
1053 | p_hwfn->hw_info.resc_start[QED_VLAN], | |
fe56b9e6 YM |
1054 | p_hwfn->hw_info.resc_num[QED_ILT], |
1055 | p_hwfn->hw_info.resc_start[QED_ILT]); | |
1056 | } | |
1057 | ||
1058 | static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, | |
1059 | struct qed_ptt *p_ptt) | |
1060 | { | |
cc875c2e | 1061 | u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; |
fc48b7a6 | 1062 | u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; |
cc875c2e | 1063 | struct qed_mcp_link_params *link; |
fe56b9e6 YM |
1064 | |
1065 | /* Read global nvm_cfg address */ | |
1066 | nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); | |
1067 | ||
1068 | /* Verify MCP has initialized it */ | |
1069 | if (!nvm_cfg_addr) { | |
1070 | DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); | |
1071 | return -EINVAL; | |
1072 | } | |
1073 | ||
1074 | /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ | |
1075 | nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); | |
1076 | ||
1077 | /* Read Vendor Id / Device Id */ | |
1078 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1079 | offsetof(struct nvm_cfg1, glob) + | |
1080 | offsetof(struct nvm_cfg1_glob, pci_id); | |
1081 | p_hwfn->hw_info.vendor_id = qed_rd(p_hwfn, p_ptt, addr) & | |
1082 | NVM_CFG1_GLOB_VENDOR_ID_MASK; | |
cc875c2e YM |
1083 | |
1084 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1085 | offsetof(struct nvm_cfg1, glob) + | |
1086 | offsetof(struct nvm_cfg1_glob, core_cfg); | |
1087 | ||
1088 | core_cfg = qed_rd(p_hwfn, p_ptt, addr); | |
1089 | ||
1090 | switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> | |
1091 | NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { | |
1092 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G: | |
1093 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; | |
1094 | break; | |
1095 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G: | |
1096 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; | |
1097 | break; | |
1098 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G: | |
1099 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; | |
1100 | break; | |
1101 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F: | |
1102 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; | |
1103 | break; | |
1104 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E: | |
1105 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; | |
1106 | break; | |
1107 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G: | |
1108 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; | |
1109 | break; | |
1110 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G: | |
1111 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; | |
1112 | break; | |
1113 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G: | |
1114 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; | |
1115 | break; | |
1116 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G: | |
1117 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; | |
1118 | break; | |
1119 | default: | |
1120 | DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", | |
1121 | core_cfg); | |
1122 | break; | |
1123 | } | |
1124 | ||
cc875c2e YM |
1125 | /* Read default link configuration */ |
1126 | link = &p_hwfn->mcp_info->link_input; | |
1127 | port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1128 | offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); | |
1129 | link_temp = qed_rd(p_hwfn, p_ptt, | |
1130 | port_cfg_addr + | |
1131 | offsetof(struct nvm_cfg1_port, speed_cap_mask)); | |
1132 | link->speed.advertised_speeds = | |
1133 | link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; | |
1134 | ||
1135 | p_hwfn->mcp_info->link_capabilities.speed_capabilities = | |
1136 | link->speed.advertised_speeds; | |
1137 | ||
1138 | link_temp = qed_rd(p_hwfn, p_ptt, | |
1139 | port_cfg_addr + | |
1140 | offsetof(struct nvm_cfg1_port, link_settings)); | |
1141 | switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> | |
1142 | NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { | |
1143 | case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: | |
1144 | link->speed.autoneg = true; | |
1145 | break; | |
1146 | case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: | |
1147 | link->speed.forced_speed = 1000; | |
1148 | break; | |
1149 | case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: | |
1150 | link->speed.forced_speed = 10000; | |
1151 | break; | |
1152 | case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: | |
1153 | link->speed.forced_speed = 25000; | |
1154 | break; | |
1155 | case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: | |
1156 | link->speed.forced_speed = 40000; | |
1157 | break; | |
1158 | case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: | |
1159 | link->speed.forced_speed = 50000; | |
1160 | break; | |
1161 | case NVM_CFG1_PORT_DRV_LINK_SPEED_100G: | |
1162 | link->speed.forced_speed = 100000; | |
1163 | break; | |
1164 | default: | |
1165 | DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", | |
1166 | link_temp); | |
1167 | } | |
1168 | ||
1169 | link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; | |
1170 | link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; | |
1171 | link->pause.autoneg = !!(link_temp & | |
1172 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); | |
1173 | link->pause.forced_rx = !!(link_temp & | |
1174 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); | |
1175 | link->pause.forced_tx = !!(link_temp & | |
1176 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); | |
1177 | link->loopback_mode = 0; | |
1178 | ||
1179 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1180 | "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", | |
1181 | link->speed.forced_speed, link->speed.advertised_speeds, | |
1182 | link->speed.autoneg, link->pause.autoneg); | |
1183 | ||
fe56b9e6 YM |
1184 | /* Read Multi-function information from shmem */ |
1185 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1186 | offsetof(struct nvm_cfg1, glob) + | |
1187 | offsetof(struct nvm_cfg1_glob, generic_cont0); | |
1188 | ||
1189 | generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); | |
1190 | ||
1191 | mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> | |
1192 | NVM_CFG1_GLOB_MF_MODE_OFFSET; | |
1193 | ||
1194 | switch (mf_mode) { | |
1195 | case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: | |
fc48b7a6 | 1196 | p_hwfn->cdev->mf_mode = QED_MF_OVLAN; |
fe56b9e6 YM |
1197 | break; |
1198 | case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: | |
fc48b7a6 | 1199 | p_hwfn->cdev->mf_mode = QED_MF_NPAR; |
fe56b9e6 | 1200 | break; |
fc48b7a6 YM |
1201 | case NVM_CFG1_GLOB_MF_MODE_DEFAULT: |
1202 | p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; | |
fe56b9e6 YM |
1203 | break; |
1204 | } | |
1205 | DP_INFO(p_hwfn, "Multi function mode is %08x\n", | |
1206 | p_hwfn->cdev->mf_mode); | |
1207 | ||
fc48b7a6 YM |
1208 | /* Read Multi-function information from shmem */ |
1209 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1210 | offsetof(struct nvm_cfg1, glob) + | |
1211 | offsetof(struct nvm_cfg1_glob, device_capabilities); | |
1212 | ||
1213 | device_capabilities = qed_rd(p_hwfn, p_ptt, addr); | |
1214 | if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) | |
1215 | __set_bit(QED_DEV_CAP_ETH, | |
1216 | &p_hwfn->hw_info.device_capabilities); | |
1217 | ||
fe56b9e6 YM |
1218 | return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); |
1219 | } | |
1220 | ||
1221 | static int | |
1222 | qed_get_hw_info(struct qed_hwfn *p_hwfn, | |
1223 | struct qed_ptt *p_ptt, | |
1224 | enum qed_pci_personality personality) | |
1225 | { | |
1226 | u32 port_mode; | |
1227 | int rc; | |
1228 | ||
1229 | /* Read the port mode */ | |
1230 | port_mode = qed_rd(p_hwfn, p_ptt, | |
1231 | CNIG_REG_NW_PORT_MODE_BB_B0); | |
1232 | ||
1233 | if (port_mode < 3) { | |
1234 | p_hwfn->cdev->num_ports_in_engines = 1; | |
1235 | } else if (port_mode <= 5) { | |
1236 | p_hwfn->cdev->num_ports_in_engines = 2; | |
1237 | } else { | |
1238 | DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", | |
1239 | p_hwfn->cdev->num_ports_in_engines); | |
1240 | ||
1241 | /* Default num_ports_in_engines to something */ | |
1242 | p_hwfn->cdev->num_ports_in_engines = 1; | |
1243 | } | |
1244 | ||
1245 | qed_hw_get_nvm_info(p_hwfn, p_ptt); | |
1246 | ||
1247 | rc = qed_int_igu_read_cam(p_hwfn, p_ptt); | |
1248 | if (rc) | |
1249 | return rc; | |
1250 | ||
1251 | if (qed_mcp_is_init(p_hwfn)) | |
1252 | ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, | |
1253 | p_hwfn->mcp_info->func_info.mac); | |
1254 | else | |
1255 | eth_random_addr(p_hwfn->hw_info.hw_mac_addr); | |
1256 | ||
1257 | if (qed_mcp_is_init(p_hwfn)) { | |
1258 | if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) | |
1259 | p_hwfn->hw_info.ovlan = | |
1260 | p_hwfn->mcp_info->func_info.ovlan; | |
1261 | ||
1262 | qed_mcp_cmd_port_init(p_hwfn, p_ptt); | |
1263 | } | |
1264 | ||
1265 | if (qed_mcp_is_init(p_hwfn)) { | |
1266 | enum qed_pci_personality protocol; | |
1267 | ||
1268 | protocol = p_hwfn->mcp_info->func_info.protocol; | |
1269 | p_hwfn->hw_info.personality = protocol; | |
1270 | } | |
1271 | ||
1272 | qed_hw_get_resc(p_hwfn); | |
1273 | ||
1274 | return rc; | |
1275 | } | |
1276 | ||
12e09c69 | 1277 | static int qed_get_dev_info(struct qed_dev *cdev) |
fe56b9e6 | 1278 | { |
fc48b7a6 | 1279 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
fe56b9e6 YM |
1280 | u32 tmp; |
1281 | ||
fc48b7a6 YM |
1282 | /* Read Vendor Id / Device Id */ |
1283 | pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, | |
1284 | &cdev->vendor_id); | |
1285 | pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, | |
1286 | &cdev->device_id); | |
1287 | cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, | |
fe56b9e6 | 1288 | MISCS_REG_CHIP_NUM); |
fc48b7a6 | 1289 | cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1290 | MISCS_REG_CHIP_REV); |
1291 | MASK_FIELD(CHIP_REV, cdev->chip_rev); | |
1292 | ||
fc48b7a6 | 1293 | cdev->type = QED_DEV_TYPE_BB; |
fe56b9e6 | 1294 | /* Learn number of HW-functions */ |
fc48b7a6 | 1295 | tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1296 | MISCS_REG_CMT_ENABLED_FOR_PAIR); |
1297 | ||
fc48b7a6 | 1298 | if (tmp & (1 << p_hwfn->rel_pf_id)) { |
fe56b9e6 YM |
1299 | DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); |
1300 | cdev->num_hwfns = 2; | |
1301 | } else { | |
1302 | cdev->num_hwfns = 1; | |
1303 | } | |
1304 | ||
fc48b7a6 | 1305 | cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1306 | MISCS_REG_CHIP_TEST_REG) >> 4; |
1307 | MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); | |
fc48b7a6 | 1308 | cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1309 | MISCS_REG_CHIP_METAL); |
1310 | MASK_FIELD(CHIP_METAL, cdev->chip_metal); | |
1311 | ||
1312 | DP_INFO(cdev->hwfns, | |
1313 | "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", | |
1314 | cdev->chip_num, cdev->chip_rev, | |
1315 | cdev->chip_bond_id, cdev->chip_metal); | |
12e09c69 YM |
1316 | |
1317 | if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { | |
1318 | DP_NOTICE(cdev->hwfns, | |
1319 | "The chip type/rev (BB A0) is not supported!\n"); | |
1320 | return -EINVAL; | |
1321 | } | |
1322 | ||
1323 | return 0; | |
fe56b9e6 YM |
1324 | } |
1325 | ||
1326 | static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, | |
1327 | void __iomem *p_regview, | |
1328 | void __iomem *p_doorbells, | |
1329 | enum qed_pci_personality personality) | |
1330 | { | |
1331 | int rc = 0; | |
1332 | ||
1333 | /* Split PCI bars evenly between hwfns */ | |
1334 | p_hwfn->regview = p_regview; | |
1335 | p_hwfn->doorbells = p_doorbells; | |
1336 | ||
1337 | /* Validate that chip access is feasible */ | |
1338 | if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { | |
1339 | DP_ERR(p_hwfn, | |
1340 | "Reading the ME register returns all Fs; Preventing further chip access\n"); | |
1341 | return -EINVAL; | |
1342 | } | |
1343 | ||
1344 | get_function_id(p_hwfn); | |
1345 | ||
12e09c69 YM |
1346 | /* Allocate PTT pool */ |
1347 | rc = qed_ptt_pool_alloc(p_hwfn); | |
fe56b9e6 YM |
1348 | if (rc) { |
1349 | DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n"); | |
1350 | goto err0; | |
1351 | } | |
1352 | ||
12e09c69 YM |
1353 | /* Allocate the main PTT */ |
1354 | p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); | |
1355 | ||
fe56b9e6 | 1356 | /* First hwfn learns basic information, e.g., number of hwfns */ |
12e09c69 YM |
1357 | if (!p_hwfn->my_id) { |
1358 | rc = qed_get_dev_info(p_hwfn->cdev); | |
1359 | if (rc != 0) | |
1360 | goto err1; | |
1361 | } | |
1362 | ||
1363 | qed_hw_hwfn_prepare(p_hwfn); | |
fe56b9e6 YM |
1364 | |
1365 | /* Initialize MCP structure */ | |
1366 | rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); | |
1367 | if (rc) { | |
1368 | DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); | |
1369 | goto err1; | |
1370 | } | |
1371 | ||
1372 | /* Read the device configuration information from the HW and SHMEM */ | |
1373 | rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); | |
1374 | if (rc) { | |
1375 | DP_NOTICE(p_hwfn, "Failed to get HW information\n"); | |
1376 | goto err2; | |
1377 | } | |
1378 | ||
1379 | /* Allocate the init RT array and initialize the init-ops engine */ | |
1380 | rc = qed_init_alloc(p_hwfn); | |
1381 | if (rc) { | |
1382 | DP_NOTICE(p_hwfn, "Failed to allocate the init array\n"); | |
1383 | goto err2; | |
1384 | } | |
1385 | ||
1386 | return rc; | |
1387 | err2: | |
1388 | qed_mcp_free(p_hwfn); | |
1389 | err1: | |
1390 | qed_hw_hwfn_free(p_hwfn); | |
1391 | err0: | |
1392 | return rc; | |
1393 | } | |
1394 | ||
fe56b9e6 YM |
1395 | int qed_hw_prepare(struct qed_dev *cdev, |
1396 | int personality) | |
1397 | { | |
c78df14e AE |
1398 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
1399 | int rc; | |
fe56b9e6 YM |
1400 | |
1401 | /* Store the precompiled init data ptrs */ | |
1402 | qed_init_iro_array(cdev); | |
1403 | ||
1404 | /* Initialize the first hwfn - will learn number of hwfns */ | |
c78df14e AE |
1405 | rc = qed_hw_prepare_single(p_hwfn, |
1406 | cdev->regview, | |
fe56b9e6 YM |
1407 | cdev->doorbells, personality); |
1408 | if (rc) | |
1409 | return rc; | |
1410 | ||
c78df14e | 1411 | personality = p_hwfn->hw_info.personality; |
fe56b9e6 YM |
1412 | |
1413 | /* Initialize the rest of the hwfns */ | |
c78df14e | 1414 | if (cdev->num_hwfns > 1) { |
fe56b9e6 | 1415 | void __iomem *p_regview, *p_doorbell; |
c78df14e AE |
1416 | u8 __iomem *addr; |
1417 | ||
1418 | /* adjust bar offset for second engine */ | |
c2035eea | 1419 | addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; |
c78df14e | 1420 | p_regview = addr; |
fe56b9e6 | 1421 | |
c78df14e | 1422 | /* adjust doorbell bar offset for second engine */ |
c2035eea | 1423 | addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; |
c78df14e AE |
1424 | p_doorbell = addr; |
1425 | ||
1426 | /* prepare second hw function */ | |
1427 | rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, | |
fe56b9e6 | 1428 | p_doorbell, personality); |
c78df14e AE |
1429 | |
1430 | /* in case of error, need to free the previously | |
1431 | * initiliazed hwfn 0. | |
1432 | */ | |
fe56b9e6 | 1433 | if (rc) { |
c78df14e AE |
1434 | qed_init_free(p_hwfn); |
1435 | qed_mcp_free(p_hwfn); | |
1436 | qed_hw_hwfn_free(p_hwfn); | |
fe56b9e6 YM |
1437 | } |
1438 | } | |
1439 | ||
c78df14e | 1440 | return rc; |
fe56b9e6 YM |
1441 | } |
1442 | ||
1443 | void qed_hw_remove(struct qed_dev *cdev) | |
1444 | { | |
1445 | int i; | |
1446 | ||
1447 | for_each_hwfn(cdev, i) { | |
1448 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1449 | ||
1450 | qed_init_free(p_hwfn); | |
1451 | qed_hw_hwfn_free(p_hwfn); | |
1452 | qed_mcp_free(p_hwfn); | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | int qed_chain_alloc(struct qed_dev *cdev, | |
1457 | enum qed_chain_use_mode intended_use, | |
1458 | enum qed_chain_mode mode, | |
1459 | u16 num_elems, | |
1460 | size_t elem_size, | |
1461 | struct qed_chain *p_chain) | |
1462 | { | |
1463 | dma_addr_t p_pbl_phys = 0; | |
1464 | void *p_pbl_virt = NULL; | |
1465 | dma_addr_t p_phys = 0; | |
1466 | void *p_virt = NULL; | |
1467 | u16 page_cnt = 0; | |
1468 | size_t size; | |
1469 | ||
1470 | if (mode == QED_CHAIN_MODE_SINGLE) | |
1471 | page_cnt = 1; | |
1472 | else | |
1473 | page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); | |
1474 | ||
1475 | size = page_cnt * QED_CHAIN_PAGE_SIZE; | |
1476 | p_virt = dma_alloc_coherent(&cdev->pdev->dev, | |
1477 | size, &p_phys, GFP_KERNEL); | |
1478 | if (!p_virt) { | |
1479 | DP_NOTICE(cdev, "Failed to allocate chain mem\n"); | |
1480 | goto nomem; | |
1481 | } | |
1482 | ||
1483 | if (mode == QED_CHAIN_MODE_PBL) { | |
1484 | size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; | |
1485 | p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, | |
1486 | size, &p_pbl_phys, | |
1487 | GFP_KERNEL); | |
1488 | if (!p_pbl_virt) { | |
1489 | DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n"); | |
1490 | goto nomem; | |
1491 | } | |
1492 | ||
1493 | qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt, | |
1494 | (u8)elem_size, intended_use, | |
1495 | p_pbl_phys, p_pbl_virt); | |
1496 | } else { | |
1497 | qed_chain_init(p_chain, p_virt, p_phys, page_cnt, | |
1498 | (u8)elem_size, intended_use, mode); | |
1499 | } | |
1500 | ||
1501 | return 0; | |
1502 | ||
1503 | nomem: | |
1504 | dma_free_coherent(&cdev->pdev->dev, | |
1505 | page_cnt * QED_CHAIN_PAGE_SIZE, | |
1506 | p_virt, p_phys); | |
1507 | dma_free_coherent(&cdev->pdev->dev, | |
1508 | page_cnt * QED_CHAIN_PBL_ENTRY_SIZE, | |
1509 | p_pbl_virt, p_pbl_phys); | |
1510 | ||
1511 | return -ENOMEM; | |
1512 | } | |
1513 | ||
1514 | void qed_chain_free(struct qed_dev *cdev, | |
1515 | struct qed_chain *p_chain) | |
1516 | { | |
1517 | size_t size; | |
1518 | ||
1519 | if (!p_chain->p_virt_addr) | |
1520 | return; | |
1521 | ||
1522 | if (p_chain->mode == QED_CHAIN_MODE_PBL) { | |
1523 | size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; | |
1524 | dma_free_coherent(&cdev->pdev->dev, size, | |
1525 | p_chain->pbl.p_virt_table, | |
1526 | p_chain->pbl.p_phys_table); | |
1527 | } | |
1528 | ||
1529 | size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE; | |
1530 | dma_free_coherent(&cdev->pdev->dev, size, | |
1531 | p_chain->p_virt_addr, | |
1532 | p_chain->p_phys_addr); | |
1533 | } | |
cee4d264 MC |
1534 | |
1535 | int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, | |
1536 | u16 src_id, u16 *dst_id) | |
1537 | { | |
1538 | if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { | |
1539 | u16 min, max; | |
1540 | ||
1541 | min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); | |
1542 | max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
1543 | DP_NOTICE(p_hwfn, | |
1544 | "l2_queue id [%d] is not valid, available indices [%d - %d]\n", | |
1545 | src_id, min, max); | |
1546 | ||
1547 | return -EINVAL; | |
1548 | } | |
1549 | ||
1550 | *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; | |
1551 | ||
1552 | return 0; | |
1553 | } | |
1554 | ||
1555 | int qed_fw_vport(struct qed_hwfn *p_hwfn, | |
1556 | u8 src_id, u8 *dst_id) | |
1557 | { | |
1558 | if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { | |
1559 | u8 min, max; | |
1560 | ||
1561 | min = (u8)RESC_START(p_hwfn, QED_VPORT); | |
1562 | max = min + RESC_NUM(p_hwfn, QED_VPORT); | |
1563 | DP_NOTICE(p_hwfn, | |
1564 | "vport id [%d] is not valid, available indices [%d - %d]\n", | |
1565 | src_id, min, max); | |
1566 | ||
1567 | return -EINVAL; | |
1568 | } | |
1569 | ||
1570 | *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; | |
1571 | ||
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, | |
1576 | u8 src_id, u8 *dst_id) | |
1577 | { | |
1578 | if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { | |
1579 | u8 min, max; | |
1580 | ||
1581 | min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); | |
1582 | max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); | |
1583 | DP_NOTICE(p_hwfn, | |
1584 | "rss_eng id [%d] is not valid, available indices [%d - %d]\n", | |
1585 | src_id, min, max); | |
1586 | ||
1587 | return -EINVAL; | |
1588 | } | |
1589 | ||
1590 | *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; | |
1591 | ||
1592 | return 0; | |
1593 | } |