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qede: Add VF support
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
CommitLineData
fe56b9e6
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <linux/mutex.h>
17#include <linux/pci.h>
18#include <linux/slab.h>
19#include <linux/string.h>
20#include <linux/etherdevice.h>
21#include <linux/qed/qed_chain.h>
22#include <linux/qed/qed_if.h>
23#include "qed.h"
24#include "qed_cxt.h"
25#include "qed_dev_api.h"
26#include "qed_hsi.h"
27#include "qed_hw.h"
28#include "qed_init_ops.h"
29#include "qed_int.h"
30#include "qed_mcp.h"
31#include "qed_reg_addr.h"
32#include "qed_sp.h"
32a47e72 33#include "qed_sriov.h"
0b55e27d 34#include "qed_vf.h"
fe56b9e6
YM		 35
36/* API common to all protocols */
c2035eea
RA		 37enum BAR_ID {
38 BAR_ID_0, /* used for GRC */
39 BAR_ID_1 /* Used for doorbells */
40};
41
42static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
43 enum BAR_ID bar_id)
44{
1408cc1f
YM		 45 u32 bar_reg = (bar_id == BAR_ID_0 ?
46 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
47 u32 val;
c2035eea 48
1408cc1f
YM		 49 if (IS_VF(p_hwfn->cdev))
50 return 1 << 17;
51
52 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
c2035eea
RA		 53 if (val)
54 return 1 << (val + 15);
55
56 /* Old MFW initialized above registered only conditionally */
57 if (p_hwfn->cdev->num_hwfns > 1) {
58 DP_INFO(p_hwfn,
59 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
60 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
61 } else {
62 DP_INFO(p_hwfn,
63 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
64 return 512 * 1024;
65 }
66}
67
fe56b9e6
YM		 68void qed_init_dp(struct qed_dev *cdev,
69 u32 dp_module, u8 dp_level)
70{
71 u32 i;
72
73 cdev->dp_level = dp_level;
74 cdev->dp_module = dp_module;
75 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
76 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
77
78 p_hwfn->dp_level = dp_level;
79 p_hwfn->dp_module = dp_module;
80 }
81}
82
83void qed_init_struct(struct qed_dev *cdev)
84{
85 u8 i;
86
87 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
88 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
89
90 p_hwfn->cdev = cdev;
91 p_hwfn->my_id = i;
92 p_hwfn->b_active = false;
93
94 mutex_init(&p_hwfn->dmae_info.mutex);
95 }
96
97 /* hwfn 0 is always active */
98 cdev->hwfns[0].b_active = true;
99
100 /* set the default cache alignment to 128 */
101 cdev->cache_shift = 7;
102}
103
104static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
105{
106 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
107
108 kfree(qm_info->qm_pq_params);
109 qm_info->qm_pq_params = NULL;
110 kfree(qm_info->qm_vport_params);
111 qm_info->qm_vport_params = NULL;
112 kfree(qm_info->qm_port_params);
113 qm_info->qm_port_params = NULL;
bcd197c8
MC		 114 kfree(qm_info->wfq_data);
115 qm_info->wfq_data = NULL;
fe56b9e6
YM		 116}
117
118void qed_resc_free(struct qed_dev *cdev)
119{
120 int i;
121
1408cc1f
YM		 122 if (IS_VF(cdev))
123 return;
124
fe56b9e6
YM		 125 kfree(cdev->fw_data);
126 cdev->fw_data = NULL;
127
128 kfree(cdev->reset_stats);
129
25c089d7
YM		 130 for_each_hwfn(cdev, i) {
131 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
132
133 kfree(p_hwfn->p_tx_cids);
134 p_hwfn->p_tx_cids = NULL;
135 kfree(p_hwfn->p_rx_cids);
136 p_hwfn->p_rx_cids = NULL;
137 }
138
fe56b9e6
YM		 139 for_each_hwfn(cdev, i) {
140 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
141
142 qed_cxt_mngr_free(p_hwfn);
143 qed_qm_info_free(p_hwfn);
144 qed_spq_free(p_hwfn);
145 qed_eq_free(p_hwfn, p_hwfn->p_eq);
146 qed_consq_free(p_hwfn, p_hwfn->p_consq);
147 qed_int_free(p_hwfn);
32a47e72 148 qed_iov_free(p_hwfn);
fe56b9e6
YM		 149 qed_dmae_info_free(p_hwfn);
150 }
151}
152
153static int qed_init_qm_info(struct qed_hwfn *p_hwfn)
154{
1408cc1f 155 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
fe56b9e6
YM		 156 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
157 struct init_qm_port_params *p_qm_port;
fe56b9e6 158 u16 num_pqs, multi_cos_tcs = 1;
1408cc1f 159 u16 num_vfs = 0;
fe56b9e6 160
1408cc1f
YM		 161#ifdef CONFIG_QED_SRIOV
162 if (p_hwfn->cdev->p_iov_info)
163 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
164#endif
fe56b9e6
YM		 165 memset(qm_info, 0, sizeof(*qm_info));
166
1408cc1f 167 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
fe56b9e6
YM		 168 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
169
170 /* Sanity checking that setup requires legal number of resources */
171 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
172 DP_ERR(p_hwfn,
173 "Need too many Physical queues - 0x%04x when only %04x are available\n",
174 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
175 return -EINVAL;
176 }
177
178 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
179 */
180 qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
60fffb3b 181 num_pqs, GFP_KERNEL);
fe56b9e6
YM		 182 if (!qm_info->qm_pq_params)
183 goto alloc_err;
184
185 qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
60fffb3b 186 num_vports, GFP_KERNEL);
fe56b9e6
YM		 187 if (!qm_info->qm_vport_params)
188 goto alloc_err;
189
190 qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
60fffb3b 191 MAX_NUM_PORTS, GFP_KERNEL);
fe56b9e6
YM		 192 if (!qm_info->qm_port_params)
193 goto alloc_err;
194
bcd197c8
MC		 195 qm_info->wfq_data = kcalloc(num_vports, sizeof(*qm_info->wfq_data),
196 GFP_KERNEL);
197 if (!qm_info->wfq_data)
198 goto alloc_err;
199
fe56b9e6
YM		 200 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
201
202 /* First init per-TC PQs */
1408cc1f
YM		 203 for (i = 0; i < multi_cos_tcs; i++, curr_queue++) {
204 struct init_qm_pq_params *params =
205 &qm_info->qm_pq_params[curr_queue];
fe56b9e6
YM		 206
207 params->vport_id = vport_id;
208 params->tc_id = p_hwfn->hw_info.non_offload_tc;
209 params->wrr_group = 1;
210 }
211
212 /* Then init pure-LB PQ */
1408cc1f
YM		 213 qm_info->pure_lb_pq = curr_queue;
214 qm_info->qm_pq_params[curr_queue].vport_id =
215 (u8) RESC_START(p_hwfn, QED_VPORT);
216 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
217 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
218 curr_queue++;
fe56b9e6
YM		 219
220 qm_info->offload_pq = 0;
1408cc1f
YM		 221 /* Then init per-VF PQs */
222 vf_offset = curr_queue;
223 for (i = 0; i < num_vfs; i++) {
224 /* First vport is used by the PF */
225 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
226 qm_info->qm_pq_params[curr_queue].tc_id =
227 p_hwfn->hw_info.non_offload_tc;
228 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
229 curr_queue++;
230 }
231
232 qm_info->vf_queues_offset = vf_offset;
fe56b9e6
YM		 233 qm_info->num_pqs = num_pqs;
234 qm_info->num_vports = num_vports;
235
236 /* Initialize qm port parameters */
237 num_ports = p_hwfn->cdev->num_ports_in_engines;
238 for (i = 0; i < num_ports; i++) {
239 p_qm_port = &qm_info->qm_port_params[i];
240 p_qm_port->active = 1;
241 p_qm_port->num_active_phys_tcs = 4;
242 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
243 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
244 }
245
246 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
247
248 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
249
1408cc1f
YM		 250 qm_info->num_vf_pqs = num_vfs;
251 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
fe56b9e6 252
a64b02d5
MC		 253 for (i = 0; i < qm_info->num_vports; i++)
254 qm_info->qm_vport_params[i].vport_wfq = 1;
255
fe56b9e6
YM		 256 qm_info->pf_wfq = 0;
257 qm_info->pf_rl = 0;
258 qm_info->vport_rl_en = 1;
a64b02d5 259 qm_info->vport_wfq_en = 1;
fe56b9e6
YM		 260
261 return 0;
262
263alloc_err:
264 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
bcd197c8 265 qed_qm_info_free(p_hwfn);
fe56b9e6
YM		 266 return -ENOMEM;
267}
268
269int qed_resc_alloc(struct qed_dev *cdev)
270{
271 struct qed_consq *p_consq;
272 struct qed_eq *p_eq;
273 int i, rc = 0;
274
1408cc1f
YM		 275 if (IS_VF(cdev))
276 return rc;
277
fe56b9e6
YM		 278 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
279 if (!cdev->fw_data)
280 return -ENOMEM;
281
25c089d7
YM		 282 /* Allocate Memory for the Queue->CID mapping */
283 for_each_hwfn(cdev, i) {
284 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
285 int tx_size = sizeof(struct qed_hw_cid_data) *
286 RESC_NUM(p_hwfn, QED_L2_QUEUE);
287 int rx_size = sizeof(struct qed_hw_cid_data) *
288 RESC_NUM(p_hwfn, QED_L2_QUEUE);
289
290 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
291 if (!p_hwfn->p_tx_cids) {
292 DP_NOTICE(p_hwfn,
293 "Failed to allocate memory for Tx Cids\n");
9b15acbf 294 rc = -ENOMEM;
25c089d7
YM		 295 goto alloc_err;
296 }
297
298 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
299 if (!p_hwfn->p_rx_cids) {
300 DP_NOTICE(p_hwfn,
301 "Failed to allocate memory for Rx Cids\n");
9b15acbf 302 rc = -ENOMEM;
25c089d7
YM		 303 goto alloc_err;
304 }
305 }
306
fe56b9e6
YM		 307 for_each_hwfn(cdev, i) {
308 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
309
310 /* First allocate the context manager structure */
311 rc = qed_cxt_mngr_alloc(p_hwfn);
312 if (rc)
313 goto alloc_err;
314
315 /* Set the HW cid/tid numbers (in the contest manager)
316 * Must be done prior to any further computations.
317 */
318 rc = qed_cxt_set_pf_params(p_hwfn);
319 if (rc)
320 goto alloc_err;
321
322 /* Prepare and process QM requirements */
323 rc = qed_init_qm_info(p_hwfn);
324 if (rc)
325 goto alloc_err;
326
327 /* Compute the ILT client partition */
328 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
329 if (rc)
330 goto alloc_err;
331
332 /* CID map / ILT shadow table / T2
333 * The talbes sizes are determined by the computations above
334 */
335 rc = qed_cxt_tables_alloc(p_hwfn);
336 if (rc)
337 goto alloc_err;
338
339 /* SPQ, must follow ILT because initializes SPQ context */
340 rc = qed_spq_alloc(p_hwfn);
341 if (rc)
342 goto alloc_err;
343
344 /* SP status block allocation */
345 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
346 RESERVED_PTT_DPC);
347
348 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
349 if (rc)
350 goto alloc_err;
351
32a47e72
YM		 352 rc = qed_iov_alloc(p_hwfn);
353 if (rc)
354 goto alloc_err;
355
fe56b9e6
YM		 356 /* EQ */
357 p_eq = qed_eq_alloc(p_hwfn, 256);
9b15acbf
DC		 358 if (!p_eq) {
359 rc = -ENOMEM;
fe56b9e6 360 goto alloc_err;
9b15acbf 361 }
fe56b9e6
YM		 362 p_hwfn->p_eq = p_eq;
363
364 p_consq = qed_consq_alloc(p_hwfn);
9b15acbf
DC		 365 if (!p_consq) {
366 rc = -ENOMEM;
fe56b9e6 367 goto alloc_err;
9b15acbf 368 }
fe56b9e6
YM		 369 p_hwfn->p_consq = p_consq;
370
371 /* DMA info initialization */
372 rc = qed_dmae_info_alloc(p_hwfn);
373 if (rc) {
374 DP_NOTICE(p_hwfn,
375 "Failed to allocate memory for dmae_info structure\n");
376 goto alloc_err;
377 }
378 }
379
380 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
381 if (!cdev->reset_stats) {
382 DP_NOTICE(cdev, "Failed to allocate reset statistics\n");
9b15acbf 383 rc = -ENOMEM;
fe56b9e6
YM		 384 goto alloc_err;
385 }
386
387 return 0;
388
389alloc_err:
390 qed_resc_free(cdev);
391 return rc;
392}
393
394void qed_resc_setup(struct qed_dev *cdev)
395{
396 int i;
397
1408cc1f
YM		 398 if (IS_VF(cdev))
399 return;
400
fe56b9e6
YM		 401 for_each_hwfn(cdev, i) {
402 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
403
404 qed_cxt_mngr_setup(p_hwfn);
405 qed_spq_setup(p_hwfn);
406 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
407 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
408
409 /* Read shadow of current MFW mailbox */
410 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
411 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
412 p_hwfn->mcp_info->mfw_mb_cur,
413 p_hwfn->mcp_info->mfw_mb_length);
414
415 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
32a47e72
YM		 416
417 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
fe56b9e6
YM		 418 }
419}
420
fe56b9e6
YM		 421#define FINAL_CLEANUP_POLL_CNT (100)
422#define FINAL_CLEANUP_POLL_TIME (10)
423int qed_final_cleanup(struct qed_hwfn *p_hwfn,
0b55e27d 424 struct qed_ptt *p_ptt, u16 id, bool is_vf)
fe56b9e6
YM		 425{
426 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
427 int rc = -EBUSY;
428
fc48b7a6
YM		 429 addr = GTT_BAR0_MAP_REG_USDM_RAM +
430 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
fe56b9e6 431
0b55e27d
YM		 432 if (is_vf)
433 id += 0x10;
434
fc48b7a6
YM		 435 command |= X_FINAL_CLEANUP_AGG_INT <<
436 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
437 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
438 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
439 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
fe56b9e6
YM		 440
441 /* Make sure notification is not set before initiating final cleanup */
442 if (REG_RD(p_hwfn, addr)) {
443 DP_NOTICE(
444 p_hwfn,
445 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
446 REG_WR(p_hwfn, addr, 0);
447 }
448
449 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
450 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
451 id, command);
452
453 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
454
455 /* Poll until completion */
456 while (!REG_RD(p_hwfn, addr) && count--)
457 msleep(FINAL_CLEANUP_POLL_TIME);
458
459 if (REG_RD(p_hwfn, addr))
460 rc = 0;
461 else
462 DP_NOTICE(p_hwfn,
463 "Failed to receive FW final cleanup notification\n");
464
465 /* Cleanup afterwards */
466 REG_WR(p_hwfn, addr, 0);
467
468 return rc;
469}
470
471static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
472{
473 int hw_mode = 0;
474
12e09c69 475 hw_mode = (1 << MODE_BB_B0);
fe56b9e6
YM		 476
477 switch (p_hwfn->cdev->num_ports_in_engines) {
478 case 1:
479 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
480 break;
481 case 2:
482 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
483 break;
484 case 4:
485 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
486 break;
487 default:
488 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
489 p_hwfn->cdev->num_ports_in_engines);
490 return;
491 }
492
493 switch (p_hwfn->cdev->mf_mode) {
fc48b7a6
YM		 494 case QED_MF_DEFAULT:
495 case QED_MF_NPAR:
496 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6 497 break;
fc48b7a6 498 case QED_MF_OVLAN:
fe56b9e6
YM		 499 hw_mode |= 1 << MODE_MF_SD;
500 break;
fe56b9e6 501 default:
fc48b7a6
YM		 502 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
503 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6
YM		 504 }
505
506 hw_mode |= 1 << MODE_ASIC;
507
508 p_hwfn->hw_info.hw_mode = hw_mode;
509}
510
511/* Init run time data for all PFs on an engine. */
512static void qed_init_cau_rt_data(struct qed_dev *cdev)
513{
514 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
515 int i, sb_id;
516
517 for_each_hwfn(cdev, i) {
518 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
519 struct qed_igu_info *p_igu_info;
520 struct qed_igu_block *p_block;
521 struct cau_sb_entry sb_entry;
522
523 p_igu_info = p_hwfn->hw_info.p_igu_info;
524
525 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
526 sb_id++) {
527 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
528 if (!p_block->is_pf)
529 continue;
530
531 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
532 p_block->function_id,
533 0, 0);
534 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2,
535 sb_entry);
536 }
537 }
538}
539
540static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
541 struct qed_ptt *p_ptt,
542 int hw_mode)
543{
544 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
545 struct qed_qm_common_rt_init_params params;
546 struct qed_dev *cdev = p_hwfn->cdev;
1408cc1f 547 u32 concrete_fid;
fe56b9e6 548 int rc = 0;
1408cc1f 549 u8 vf_id;
fe56b9e6
YM		 550
551 qed_init_cau_rt_data(cdev);
552
553 /* Program GTT windows */
554 qed_gtt_init(p_hwfn);
555
556 if (p_hwfn->mcp_info) {
557 if (p_hwfn->mcp_info->func_info.bandwidth_max)
558 qm_info->pf_rl_en = 1;
559 if (p_hwfn->mcp_info->func_info.bandwidth_min)
560 qm_info->pf_wfq_en = 1;
561 }
562
563 memset(&params, 0, sizeof(params));
564 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
565 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
566 params.pf_rl_en = qm_info->pf_rl_en;
567 params.pf_wfq_en = qm_info->pf_wfq_en;
568 params.vport_rl_en = qm_info->vport_rl_en;
569 params.vport_wfq_en = qm_info->vport_wfq_en;
570 params.port_params = qm_info->qm_port_params;
571
572 qed_qm_common_rt_init(p_hwfn, &params);
573
574 qed_cxt_hw_init_common(p_hwfn);
575
576 /* Close gate from NIG to BRB/Storm; By default they are open, but
577 * we close them to prevent NIG from passing data to reset blocks.
578 * Should have been done in the ENGINE phase, but init-tool lacks
579 * proper port-pretend capabilities.
580 */
581 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
582 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
583 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
584 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
585 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
586 qed_port_unpretend(p_hwfn, p_ptt);
587
588 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
589 if (rc != 0)
590 return rc;
591
592 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
593 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
594
595 /* Disable relaxed ordering in the PCI config space */
596 qed_wr(p_hwfn, p_ptt, 0x20b4,
597 qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
598
1408cc1f
YM		 599 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
600 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
601 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
602 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
603 }
604 /* pretend to original PF */
605 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
606
fe56b9e6
YM		 607 return rc;
608}
609
610static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
611 struct qed_ptt *p_ptt,
612 int hw_mode)
613{
614 int rc = 0;
615
616 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
617 hw_mode);
618 return rc;
619}
620
621static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
622 struct qed_ptt *p_ptt,
464f6645 623 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 624 int hw_mode,
625 bool b_hw_start,
626 enum qed_int_mode int_mode,
627 bool allow_npar_tx_switch)
628{
629 u8 rel_pf_id = p_hwfn->rel_pf_id;
630 int rc = 0;
631
632 if (p_hwfn->mcp_info) {
633 struct qed_mcp_function_info *p_info;
634
635 p_info = &p_hwfn->mcp_info->func_info;
636 if (p_info->bandwidth_min)
637 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
638
639 /* Update rate limit once we'll actually have a link */
4b01e519 640 p_hwfn->qm_info.pf_rl = 100000;
fe56b9e6
YM		 641 }
642
643 qed_cxt_hw_init_pf(p_hwfn);
644
645 qed_int_igu_init_rt(p_hwfn);
646
647 /* Set VLAN in NIG if needed */
648 if (hw_mode & (1 << MODE_MF_SD)) {
649 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
650 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
651 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
652 p_hwfn->hw_info.ovlan);
653 }
654
655 /* Enable classification by MAC if needed */
87aec47d 656 if (hw_mode & (1 << MODE_MF_SI)) {
fe56b9e6
YM		 657 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
658 "Configuring TAGMAC_CLS_TYPE\n");
659 STORE_RT_REG(p_hwfn,
660 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
661 }
662
663 /* Protocl Configuration */
664 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
665 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
666 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
667
668 /* Cleanup chip from previous driver if such remains exist */
0b55e27d 669 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
fe56b9e6
YM		 670 if (rc != 0)
671 return rc;
672
673 /* PF Init sequence */
674 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
675 if (rc)
676 return rc;
677
678 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
679 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
680 if (rc)
681 return rc;
682
683 /* Pure runtime initializations - directly to the HW */
684 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
685
686 if (b_hw_start) {
687 /* enable interrupts */
688 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
689
690 /* send function start command */
464f6645 691 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode);
fe56b9e6
YM		 692 if (rc)
693 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
694 }
695 return rc;
696}
697
698static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
699 struct qed_ptt *p_ptt,
700 u8 enable)
701{
702 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
703
704 /* Change PF in PXP */
705 qed_wr(p_hwfn, p_ptt,
706 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
707
708 /* wait until value is set - try for 1 second every 50us */
709 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
710 val = qed_rd(p_hwfn, p_ptt,
711 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
712 if (val == set_val)
713 break;
714
715 usleep_range(50, 60);
716 }
717
718 if (val != set_val) {
719 DP_NOTICE(p_hwfn,
720 "PFID_ENABLE_MASTER wasn't changed after a second\n");
721 return -EAGAIN;
722 }
723
724 return 0;
725}
726
727static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
728 struct qed_ptt *p_main_ptt)
729{
730 /* Read shadow of current MFW mailbox */
731 qed_mcp_read_mb(p_hwfn, p_main_ptt);
732 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
733 p_hwfn->mcp_info->mfw_mb_cur,
734 p_hwfn->mcp_info->mfw_mb_length);
735}
736
737int qed_hw_init(struct qed_dev *cdev,
464f6645 738 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 739 bool b_hw_start,
740 enum qed_int_mode int_mode,
741 bool allow_npar_tx_switch,
742 const u8 *bin_fw_data)
743{
86622ee7 744 u32 load_code, param;
fe56b9e6
YM		 745 int rc, mfw_rc, i;
746
1408cc1f
YM		 747 if (IS_PF(cdev)) {
748 rc = qed_init_fw_data(cdev, bin_fw_data);
749 if (rc != 0)
750 return rc;
751 }
fe56b9e6
YM		 752
753 for_each_hwfn(cdev, i) {
754 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
755
1408cc1f
YM		 756 if (IS_VF(cdev)) {
757 p_hwfn->b_int_enabled = 1;
758 continue;
759 }
760
fe56b9e6
YM		 761 /* Enable DMAE in PXP */
762 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
763
764 qed_calc_hw_mode(p_hwfn);
765
766 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
767 &load_code);
768 if (rc) {
769 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
770 return rc;
771 }
772
773 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
774
775 DP_VERBOSE(p_hwfn, QED_MSG_SP,
776 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
777 rc, load_code);
778
779 p_hwfn->first_on_engine = (load_code ==
780 FW_MSG_CODE_DRV_LOAD_ENGINE);
781
782 switch (load_code) {
783 case FW_MSG_CODE_DRV_LOAD_ENGINE:
784 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
785 p_hwfn->hw_info.hw_mode);
786 if (rc)
787 break;
788 /* Fall into */
789 case FW_MSG_CODE_DRV_LOAD_PORT:
790 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
791 p_hwfn->hw_info.hw_mode);
792 if (rc)
793 break;
794
795 /* Fall into */
796 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
797 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
464f6645 798 p_tunn, p_hwfn->hw_info.hw_mode,
fe56b9e6
YM		 799 b_hw_start, int_mode,
800 allow_npar_tx_switch);
801 break;
802 default:
803 rc = -EINVAL;
804 break;
805 }
806
807 if (rc)
808 DP_NOTICE(p_hwfn,
809 "init phase failed for loadcode 0x%x (rc %d)\n",
810 load_code, rc);
811
812 /* ACK mfw regardless of success or failure of initialization */
813 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
814 DRV_MSG_CODE_LOAD_DONE,
815 0, &load_code, &param);
816 if (rc)
817 return rc;
818 if (mfw_rc) {
819 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
820 return mfw_rc;
821 }
822
823 p_hwfn->hw_init_done = true;
824 }
825
826 return 0;
827}
828
829#define QED_HW_STOP_RETRY_LIMIT (10)
8c925c44
YM		 830static inline void qed_hw_timers_stop(struct qed_dev *cdev,
831 struct qed_hwfn *p_hwfn,
832 struct qed_ptt *p_ptt)
833{
834 int i;
835
836 /* close timers */
837 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
838 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
839
840 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
841 if ((!qed_rd(p_hwfn, p_ptt,
842 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
843 (!qed_rd(p_hwfn, p_ptt,
844 TM_REG_PF_SCAN_ACTIVE_TASK)))
845 break;
846
847 /* Dependent on number of connection/tasks, possibly
848 * 1ms sleep is required between polls
849 */
850 usleep_range(1000, 2000);
851 }
852
853 if (i < QED_HW_STOP_RETRY_LIMIT)
854 return;
855
856 DP_NOTICE(p_hwfn,
857 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
858 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
859 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
860}
861
862void qed_hw_timers_stop_all(struct qed_dev *cdev)
863{
864 int j;
865
866 for_each_hwfn(cdev, j) {
867 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
868 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
869
870 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
871 }
872}
873
fe56b9e6
YM		 874int qed_hw_stop(struct qed_dev *cdev)
875{
876 int rc = 0, t_rc;
8c925c44 877 int j;
fe56b9e6
YM		 878
879 for_each_hwfn(cdev, j) {
880 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
881 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
882
883 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
884
1408cc1f 885 if (IS_VF(cdev)) {
0b55e27d 886 qed_vf_pf_int_cleanup(p_hwfn);
1408cc1f
YM		 887 continue;
888 }
889
fe56b9e6
YM		 890 /* mark the hw as uninitialized... */
891 p_hwfn->hw_init_done = false;
892
893 rc = qed_sp_pf_stop(p_hwfn);
894 if (rc)
8c925c44
YM		 895 DP_NOTICE(p_hwfn,
896 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
fe56b9e6
YM		 897
898 qed_wr(p_hwfn, p_ptt,
899 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
900
901 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
902 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
903 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
904 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
905 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
906
8c925c44 907 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
fe56b9e6
YM		 908
909 /* Disable Attention Generation */
910 qed_int_igu_disable_int(p_hwfn, p_ptt);
911
912 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
913 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
914
915 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
916
917 /* Need to wait 1ms to guarantee SBs are cleared */
918 usleep_range(1000, 2000);
919 }
920
1408cc1f
YM		 921 if (IS_PF(cdev)) {
922 /* Disable DMAE in PXP - in CMT, this should only be done for
923 * first hw-function, and only after all transactions have
924 * stopped for all active hw-functions.
925 */
926 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
927 cdev->hwfns[0].p_main_ptt, false);
928 if (t_rc != 0)
929 rc = t_rc;
930 }
fe56b9e6
YM		 931
932 return rc;
933}
934
cee4d264
MC		 935void qed_hw_stop_fastpath(struct qed_dev *cdev)
936{
8c925c44 937 int j;
cee4d264
MC		 938
939 for_each_hwfn(cdev, j) {
940 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
dacd88d6
YM		 941 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
942
943 if (IS_VF(cdev)) {
944 qed_vf_pf_int_cleanup(p_hwfn);
945 continue;
946 }
cee4d264
MC		 947
948 DP_VERBOSE(p_hwfn,
949 NETIF_MSG_IFDOWN,
950 "Shutting down the fastpath\n");
951
952 qed_wr(p_hwfn, p_ptt,
953 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
954
955 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
956 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
957 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
958 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
959 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
960
cee4d264
MC		 961 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
962
963 /* Need to wait 1ms to guarantee SBs are cleared */
964 usleep_range(1000, 2000);
965 }
966}
967
968void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
969{
dacd88d6
YM		 970 if (IS_VF(p_hwfn->cdev))
971 return;
972
cee4d264
MC		 973 /* Re-open incoming traffic */
974 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
975 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
976}
977
fe56b9e6
YM		 978static int qed_reg_assert(struct qed_hwfn *hwfn,
979 struct qed_ptt *ptt, u32 reg,
980 bool expected)
981{
982 u32 assert_val = qed_rd(hwfn, ptt, reg);
983
984 if (assert_val != expected) {
985 DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n",
986 reg, expected);
987 return -EINVAL;
988 }
989
990 return 0;
991}
992
993int qed_hw_reset(struct qed_dev *cdev)
994{
995 int rc = 0;
996 u32 unload_resp, unload_param;
997 int i;
998
999 for_each_hwfn(cdev, i) {
1000 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1001
1408cc1f 1002 if (IS_VF(cdev)) {
0b55e27d
YM		 1003 rc = qed_vf_pf_reset(p_hwfn);
1004 if (rc)
1005 return rc;
1408cc1f
YM		 1006 continue;
1007 }
1008
fe56b9e6
YM		 1009 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1010
1011 /* Check for incorrect states */
1012 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1013 QM_REG_USG_CNT_PF_TX, 0);
1014 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1015 QM_REG_USG_CNT_PF_OTHER, 0);
1016
1017 /* Disable PF in HW blocks */
1018 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1019 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1020 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1021 TCFC_REG_STRONG_ENABLE_PF, 0);
1022 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1023 CCFC_REG_STRONG_ENABLE_PF, 0);
1024
1025 /* Send unload command to MCP */
1026 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1027 DRV_MSG_CODE_UNLOAD_REQ,
1028 DRV_MB_PARAM_UNLOAD_WOL_MCP,
1029 &unload_resp, &unload_param);
1030 if (rc) {
1031 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1032 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1033 }
1034
1035 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1036 DRV_MSG_CODE_UNLOAD_DONE,
1037 0, &unload_resp, &unload_param);
1038 if (rc) {
1039 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1040 return rc;
1041 }
1042 }
1043
1044 return rc;
1045}
1046
1047/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1048static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1049{
1050 qed_ptt_pool_free(p_hwfn);
1051 kfree(p_hwfn->hw_info.p_igu_info);
1052}
1053
1054/* Setup bar access */
12e09c69 1055static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
fe56b9e6 1056{
fe56b9e6
YM		 1057 /* clear indirect access */
1058 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1059 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1060 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1061 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1062
1063 /* Clean Previous errors if such exist */
1064 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1065 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1066 1 << p_hwfn->abs_pf_id);
1067
1068 /* enable internal target-read */
1069 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1070 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
fe56b9e6
YM		 1071}
1072
1073static void get_function_id(struct qed_hwfn *p_hwfn)
1074{
1075 /* ME Register */
1076 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR);
1077
1078 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1079
1080 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1081 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1082 PXP_CONCRETE_FID_PFID);
1083 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1084 PXP_CONCRETE_FID_PORT);
1085}
1086
25c089d7
YM		 1087static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1088{
1089 u32 *feat_num = p_hwfn->hw_info.feat_num;
1090 int num_features = 1;
1091
1092 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1093 num_features,
1094 RESC_NUM(p_hwfn, QED_L2_QUEUE));
1095 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1096 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1097 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1098 num_features);
1099}
1100
fe56b9e6
YM		 1101static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1102{
1103 u32 *resc_start = p_hwfn->hw_info.resc_start;
1408cc1f 1104 u8 num_funcs = p_hwfn->num_funcs_on_engine;
fe56b9e6 1105 u32 *resc_num = p_hwfn->hw_info.resc_num;
4ac801b7 1106 struct qed_sb_cnt_info sb_cnt_info;
1408cc1f 1107 int i;
fe56b9e6 1108
4ac801b7
YM		 1109 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1110 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1111
fe56b9e6
YM		 1112 resc_num[QED_SB] = min_t(u32,
1113 (MAX_SB_PER_PATH_BB / num_funcs),
4ac801b7 1114 sb_cnt_info.sb_cnt);
25c089d7 1115 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
fe56b9e6 1116 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
25c089d7 1117 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
fe56b9e6
YM		 1118 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1119 resc_num[QED_RL] = 8;
25c089d7
YM		 1120 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1121 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1122 num_funcs;
fe56b9e6
YM		 1123 resc_num[QED_ILT] = 950;
1124
1125 for (i = 0; i < QED_MAX_RESC; i++)
1126 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1127
25c089d7
YM		 1128 qed_hw_set_feat(p_hwfn);
1129
fe56b9e6
YM		 1130 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1131 "The numbers for each resource are:\n"
1132 "SB = %d start = %d\n"
25c089d7 1133 "L2_QUEUE = %d start = %d\n"
fe56b9e6
YM		 1134 "VPORT = %d start = %d\n"
1135 "PQ = %d start = %d\n"
1136 "RL = %d start = %d\n"
25c089d7
YM		 1137 "MAC = %d start = %d\n"
1138 "VLAN = %d start = %d\n"
fe56b9e6
YM		 1139 "ILT = %d start = %d\n",
1140 p_hwfn->hw_info.resc_num[QED_SB],
1141 p_hwfn->hw_info.resc_start[QED_SB],
25c089d7
YM		 1142 p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1143 p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
fe56b9e6
YM		 1144 p_hwfn->hw_info.resc_num[QED_VPORT],
1145 p_hwfn->hw_info.resc_start[QED_VPORT],
1146 p_hwfn->hw_info.resc_num[QED_PQ],
1147 p_hwfn->hw_info.resc_start[QED_PQ],
1148 p_hwfn->hw_info.resc_num[QED_RL],
1149 p_hwfn->hw_info.resc_start[QED_RL],
25c089d7
YM		 1150 p_hwfn->hw_info.resc_num[QED_MAC],
1151 p_hwfn->hw_info.resc_start[QED_MAC],
1152 p_hwfn->hw_info.resc_num[QED_VLAN],
1153 p_hwfn->hw_info.resc_start[QED_VLAN],
fe56b9e6
YM		 1154 p_hwfn->hw_info.resc_num[QED_ILT],
1155 p_hwfn->hw_info.resc_start[QED_ILT]);
1156}
1157
1158static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
1159 struct qed_ptt *p_ptt)
1160{
cc875c2e 1161 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
fc48b7a6 1162 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
cc875c2e 1163 struct qed_mcp_link_params *link;
fe56b9e6
YM		 1164
1165 /* Read global nvm_cfg address */
1166 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1167
1168 /* Verify MCP has initialized it */
1169 if (!nvm_cfg_addr) {
1170 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1171 return -EINVAL;
1172 }
1173
1174 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1175 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1176
cc875c2e
YM		 1177 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1178 offsetof(struct nvm_cfg1, glob) +
1179 offsetof(struct nvm_cfg1_glob, core_cfg);
1180
1181 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1182
1183 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1184 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1185 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1186 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1187 break;
1188 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1189 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1190 break;
1191 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1192 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1193 break;
1194 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1195 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1196 break;
1197 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1198 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1199 break;
1200 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1201 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1202 break;
1203 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1204 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1205 break;
1206 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1207 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1208 break;
1209 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1210 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1211 break;
1212 default:
1213 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n",
1214 core_cfg);
1215 break;
1216 }
1217
cc875c2e
YM		 1218 /* Read default link configuration */
1219 link = &p_hwfn->mcp_info->link_input;
1220 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1221 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1222 link_temp = qed_rd(p_hwfn, p_ptt,
1223 port_cfg_addr +
1224 offsetof(struct nvm_cfg1_port, speed_cap_mask));
1225 link->speed.advertised_speeds =
1226 link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1227
1228 p_hwfn->mcp_info->link_capabilities.speed_capabilities =
1229 link->speed.advertised_speeds;
1230
1231 link_temp = qed_rd(p_hwfn, p_ptt,
1232 port_cfg_addr +
1233 offsetof(struct nvm_cfg1_port, link_settings));
1234 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1235 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1236 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1237 link->speed.autoneg = true;
1238 break;
1239 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1240 link->speed.forced_speed = 1000;
1241 break;
1242 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1243 link->speed.forced_speed = 10000;
1244 break;
1245 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1246 link->speed.forced_speed = 25000;
1247 break;
1248 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1249 link->speed.forced_speed = 40000;
1250 break;
1251 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1252 link->speed.forced_speed = 50000;
1253 break;
1254 case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1255 link->speed.forced_speed = 100000;
1256 break;
1257 default:
1258 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n",
1259 link_temp);
1260 }
1261
1262 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1263 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1264 link->pause.autoneg = !!(link_temp &
1265 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1266 link->pause.forced_rx = !!(link_temp &
1267 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1268 link->pause.forced_tx = !!(link_temp &
1269 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1270 link->loopback_mode = 0;
1271
1272 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1273 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1274 link->speed.forced_speed, link->speed.advertised_speeds,
1275 link->speed.autoneg, link->pause.autoneg);
1276
fe56b9e6
YM		 1277 /* Read Multi-function information from shmem */
1278 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1279 offsetof(struct nvm_cfg1, glob) +
1280 offsetof(struct nvm_cfg1_glob, generic_cont0);
1281
1282 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1283
1284 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1285 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1286
1287 switch (mf_mode) {
1288 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
fc48b7a6 1289 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
fe56b9e6
YM		 1290 break;
1291 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
fc48b7a6 1292 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
fe56b9e6 1293 break;
fc48b7a6
YM		 1294 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1295 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
fe56b9e6
YM		 1296 break;
1297 }
1298 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1299 p_hwfn->cdev->mf_mode);
1300
fc48b7a6
YM		 1301 /* Read Multi-function information from shmem */
1302 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1303 offsetof(struct nvm_cfg1, glob) +
1304 offsetof(struct nvm_cfg1_glob, device_capabilities);
1305
1306 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1307 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1308 __set_bit(QED_DEV_CAP_ETH,
1309 &p_hwfn->hw_info.device_capabilities);
1310
fe56b9e6
YM		 1311 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1312}
1313
1408cc1f
YM		 1314static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1315{
1316 u32 reg_function_hide, tmp, eng_mask;
1317 u8 num_funcs;
1318
1319 num_funcs = MAX_NUM_PFS_BB;
1320
1321 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1322 * in the other bits are selected.
1323 * Bits 1-15 are for functions 1-15, respectively, and their value is
1324 * '0' only for enabled functions (function 0 always exists and
1325 * enabled).
1326 * In case of CMT, only the "even" functions are enabled, and thus the
1327 * number of functions for both hwfns is learnt from the same bits.
1328 */
1329 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1330
1331 if (reg_function_hide & 0x1) {
1332 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1333 num_funcs = 0;
1334 eng_mask = 0xaaaa;
1335 } else {
1336 num_funcs = 1;
1337 eng_mask = 0x5554;
1338 }
1339
1340 /* Get the number of the enabled functions on the engine */
1341 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1342 while (tmp) {
1343 if (tmp & 0x1)
1344 num_funcs++;
1345 tmp >>= 0x1;
1346 }
1347 }
1348
1349 p_hwfn->num_funcs_on_engine = num_funcs;
1350
1351 DP_VERBOSE(p_hwfn,
1352 NETIF_MSG_PROBE,
1353 "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",
1354 p_hwfn->rel_pf_id,
1355 p_hwfn->abs_pf_id,
1356 p_hwfn->num_funcs_on_engine);
1357}
1358
fe56b9e6
YM		 1359static int
1360qed_get_hw_info(struct qed_hwfn *p_hwfn,
1361 struct qed_ptt *p_ptt,
1362 enum qed_pci_personality personality)
1363{
1364 u32 port_mode;
1365 int rc;
1366
32a47e72
YM		 1367 /* Since all information is common, only first hwfns should do this */
1368 if (IS_LEAD_HWFN(p_hwfn)) {
1369 rc = qed_iov_hw_info(p_hwfn);
1370 if (rc)
1371 return rc;
1372 }
1373
fe56b9e6
YM		 1374 /* Read the port mode */
1375 port_mode = qed_rd(p_hwfn, p_ptt,
1376 CNIG_REG_NW_PORT_MODE_BB_B0);
1377
1378 if (port_mode < 3) {
1379 p_hwfn->cdev->num_ports_in_engines = 1;
1380 } else if (port_mode <= 5) {
1381 p_hwfn->cdev->num_ports_in_engines = 2;
1382 } else {
1383 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1384 p_hwfn->cdev->num_ports_in_engines);
1385
1386 /* Default num_ports_in_engines to something */
1387 p_hwfn->cdev->num_ports_in_engines = 1;
1388 }
1389
1390 qed_hw_get_nvm_info(p_hwfn, p_ptt);
1391
1392 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1393 if (rc)
1394 return rc;
1395
1396 if (qed_mcp_is_init(p_hwfn))
1397 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1398 p_hwfn->mcp_info->func_info.mac);
1399 else
1400 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1401
1402 if (qed_mcp_is_init(p_hwfn)) {
1403 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1404 p_hwfn->hw_info.ovlan =
1405 p_hwfn->mcp_info->func_info.ovlan;
1406
1407 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1408 }
1409
1410 if (qed_mcp_is_init(p_hwfn)) {
1411 enum qed_pci_personality protocol;
1412
1413 protocol = p_hwfn->mcp_info->func_info.protocol;
1414 p_hwfn->hw_info.personality = protocol;
1415 }
1416
1408cc1f
YM		 1417 qed_get_num_funcs(p_hwfn, p_ptt);
1418
fe56b9e6
YM		 1419 qed_hw_get_resc(p_hwfn);
1420
1421 return rc;
1422}
1423
12e09c69 1424static int qed_get_dev_info(struct qed_dev *cdev)
fe56b9e6 1425{
fc48b7a6 1426 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 1427 u32 tmp;
1428
fc48b7a6
YM		 1429 /* Read Vendor Id / Device Id */
1430 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID,
1431 &cdev->vendor_id);
1432 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID,
1433 &cdev->device_id);
1434 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6 1435 MISCS_REG_CHIP_NUM);
fc48b7a6 1436 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1437 MISCS_REG_CHIP_REV);
1438 MASK_FIELD(CHIP_REV, cdev->chip_rev);
1439
fc48b7a6 1440 cdev->type = QED_DEV_TYPE_BB;
fe56b9e6 1441 /* Learn number of HW-functions */
fc48b7a6 1442 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1443 MISCS_REG_CMT_ENABLED_FOR_PAIR);
1444
fc48b7a6 1445 if (tmp & (1 << p_hwfn->rel_pf_id)) {
fe56b9e6
YM		 1446 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1447 cdev->num_hwfns = 2;
1448 } else {
1449 cdev->num_hwfns = 1;
1450 }
1451
fc48b7a6 1452 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1453 MISCS_REG_CHIP_TEST_REG) >> 4;
1454 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
fc48b7a6 1455 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 1456 MISCS_REG_CHIP_METAL);
1457 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1458
1459 DP_INFO(cdev->hwfns,
1460 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1461 cdev->chip_num, cdev->chip_rev,
1462 cdev->chip_bond_id, cdev->chip_metal);
12e09c69
YM		 1463
1464 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1465 DP_NOTICE(cdev->hwfns,
1466 "The chip type/rev (BB A0) is not supported!\n");
1467 return -EINVAL;
1468 }
1469
1470 return 0;
fe56b9e6
YM		 1471}
1472
1473static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1474 void __iomem *p_regview,
1475 void __iomem *p_doorbells,
1476 enum qed_pci_personality personality)
1477{
1478 int rc = 0;
1479
1480 /* Split PCI bars evenly between hwfns */
1481 p_hwfn->regview = p_regview;
1482 p_hwfn->doorbells = p_doorbells;
1483
1408cc1f
YM		 1484 if (IS_VF(p_hwfn->cdev))
1485 return qed_vf_hw_prepare(p_hwfn);
1486
fe56b9e6
YM		 1487 /* Validate that chip access is feasible */
1488 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1489 DP_ERR(p_hwfn,
1490 "Reading the ME register returns all Fs; Preventing further chip access\n");
1491 return -EINVAL;
1492 }
1493
1494 get_function_id(p_hwfn);
1495
12e09c69
YM		 1496 /* Allocate PTT pool */
1497 rc = qed_ptt_pool_alloc(p_hwfn);
fe56b9e6
YM		 1498 if (rc) {
1499 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n");
1500 goto err0;
1501 }
1502
12e09c69
YM		 1503 /* Allocate the main PTT */
1504 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1505
fe56b9e6 1506 /* First hwfn learns basic information, e.g., number of hwfns */
12e09c69
YM		 1507 if (!p_hwfn->my_id) {
1508 rc = qed_get_dev_info(p_hwfn->cdev);
1509 if (rc != 0)
1510 goto err1;
1511 }
1512
1513 qed_hw_hwfn_prepare(p_hwfn);
fe56b9e6
YM		 1514
1515 /* Initialize MCP structure */
1516 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1517 if (rc) {
1518 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1519 goto err1;
1520 }
1521
1522 /* Read the device configuration information from the HW and SHMEM */
1523 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1524 if (rc) {
1525 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1526 goto err2;
1527 }
1528
1529 /* Allocate the init RT array and initialize the init-ops engine */
1530 rc = qed_init_alloc(p_hwfn);
1531 if (rc) {
1532 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n");
1533 goto err2;
1534 }
1535
1536 return rc;
1537err2:
32a47e72
YM		 1538 if (IS_LEAD_HWFN(p_hwfn))
1539 qed_iov_free_hw_info(p_hwfn->cdev);
fe56b9e6
YM		 1540 qed_mcp_free(p_hwfn);
1541err1:
1542 qed_hw_hwfn_free(p_hwfn);
1543err0:
1544 return rc;
1545}
1546
fe56b9e6
YM		 1547int qed_hw_prepare(struct qed_dev *cdev,
1548 int personality)
1549{
c78df14e
AE		 1550 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1551 int rc;
fe56b9e6
YM		 1552
1553 /* Store the precompiled init data ptrs */
1408cc1f
YM		 1554 if (IS_PF(cdev))
1555 qed_init_iro_array(cdev);
fe56b9e6
YM		 1556
1557 /* Initialize the first hwfn - will learn number of hwfns */
c78df14e
AE		 1558 rc = qed_hw_prepare_single(p_hwfn,
1559 cdev->regview,
fe56b9e6
YM		 1560 cdev->doorbells, personality);
1561 if (rc)
1562 return rc;
1563
c78df14e 1564 personality = p_hwfn->hw_info.personality;
fe56b9e6
YM		 1565
1566 /* Initialize the rest of the hwfns */
c78df14e 1567 if (cdev->num_hwfns > 1) {
fe56b9e6 1568 void __iomem *p_regview, *p_doorbell;
c78df14e
AE		 1569 u8 __iomem *addr;
1570
1571 /* adjust bar offset for second engine */
c2035eea 1572 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
c78df14e 1573 p_regview = addr;
fe56b9e6 1574
c78df14e 1575 /* adjust doorbell bar offset for second engine */
c2035eea 1576 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
c78df14e
AE		 1577 p_doorbell = addr;
1578
1579 /* prepare second hw function */
1580 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
fe56b9e6 1581 p_doorbell, personality);
c78df14e
AE		 1582
1583 /* in case of error, need to free the previously
1584 * initiliazed hwfn 0.
1585 */
fe56b9e6 1586 if (rc) {
1408cc1f
YM		 1587 if (IS_PF(cdev)) {
1588 qed_init_free(p_hwfn);
1589 qed_mcp_free(p_hwfn);
1590 qed_hw_hwfn_free(p_hwfn);
1591 }
fe56b9e6
YM		 1592 }
1593 }
1594
c78df14e 1595 return rc;
fe56b9e6
YM		 1596}
1597
1598void qed_hw_remove(struct qed_dev *cdev)
1599{
1600 int i;
1601
1602 for_each_hwfn(cdev, i) {
1603 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1604
1408cc1f 1605 if (IS_VF(cdev)) {
0b55e27d 1606 qed_vf_pf_release(p_hwfn);
1408cc1f
YM		 1607 continue;
1608 }
1609
fe56b9e6
YM		 1610 qed_init_free(p_hwfn);
1611 qed_hw_hwfn_free(p_hwfn);
1612 qed_mcp_free(p_hwfn);
1613 }
32a47e72
YM		 1614
1615 qed_iov_free_hw_info(cdev);
fe56b9e6
YM		 1616}
1617
1618int qed_chain_alloc(struct qed_dev *cdev,
1619 enum qed_chain_use_mode intended_use,
1620 enum qed_chain_mode mode,
1621 u16 num_elems,
1622 size_t elem_size,
1623 struct qed_chain *p_chain)
1624{
1625 dma_addr_t p_pbl_phys = 0;
1626 void *p_pbl_virt = NULL;
1627 dma_addr_t p_phys = 0;
1628 void *p_virt = NULL;
1629 u16 page_cnt = 0;
1630 size_t size;
1631
1632 if (mode == QED_CHAIN_MODE_SINGLE)
1633 page_cnt = 1;
1634 else
1635 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
1636
1637 size = page_cnt * QED_CHAIN_PAGE_SIZE;
1638 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1639 size, &p_phys, GFP_KERNEL);
1640 if (!p_virt) {
1641 DP_NOTICE(cdev, "Failed to allocate chain mem\n");
1642 goto nomem;
1643 }
1644
1645 if (mode == QED_CHAIN_MODE_PBL) {
1646 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1647 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
1648 size, &p_pbl_phys,
1649 GFP_KERNEL);
1650 if (!p_pbl_virt) {
1651 DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n");
1652 goto nomem;
1653 }
1654
1655 qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt,
1656 (u8)elem_size, intended_use,
1657 p_pbl_phys, p_pbl_virt);
1658 } else {
1659 qed_chain_init(p_chain, p_virt, p_phys, page_cnt,
1660 (u8)elem_size, intended_use, mode);
1661 }
1662
1663 return 0;
1664
1665nomem:
1666 dma_free_coherent(&cdev->pdev->dev,
1667 page_cnt * QED_CHAIN_PAGE_SIZE,
1668 p_virt, p_phys);
1669 dma_free_coherent(&cdev->pdev->dev,
1670 page_cnt * QED_CHAIN_PBL_ENTRY_SIZE,
1671 p_pbl_virt, p_pbl_phys);
1672
1673 return -ENOMEM;
1674}
1675
1676void qed_chain_free(struct qed_dev *cdev,
1677 struct qed_chain *p_chain)
1678{
1679 size_t size;
1680
1681 if (!p_chain->p_virt_addr)
1682 return;
1683
1684 if (p_chain->mode == QED_CHAIN_MODE_PBL) {
1685 size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1686 dma_free_coherent(&cdev->pdev->dev, size,
1687 p_chain->pbl.p_virt_table,
1688 p_chain->pbl.p_phys_table);
1689 }
1690
1691 size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE;
1692 dma_free_coherent(&cdev->pdev->dev, size,
1693 p_chain->p_virt_addr,
1694 p_chain->p_phys_addr);
1695}
cee4d264
MC		 1696
1697int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
1698 u16 src_id, u16 *dst_id)
1699{
1700 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
1701 u16 min, max;
1702
1703 min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
1704 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
1705 DP_NOTICE(p_hwfn,
1706 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
1707 src_id, min, max);
1708
1709 return -EINVAL;
1710 }
1711
1712 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
1713
1714 return 0;
1715}
1716
1717int qed_fw_vport(struct qed_hwfn *p_hwfn,
1718 u8 src_id, u8 *dst_id)
1719{
1720 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
1721 u8 min, max;
1722
1723 min = (u8)RESC_START(p_hwfn, QED_VPORT);
1724 max = min + RESC_NUM(p_hwfn, QED_VPORT);
1725 DP_NOTICE(p_hwfn,
1726 "vport id [%d] is not valid, available indices [%d - %d]\n",
1727 src_id, min, max);
1728
1729 return -EINVAL;
1730 }
1731
1732 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
1733
1734 return 0;
1735}
1736
1737int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
1738 u8 src_id, u8 *dst_id)
1739{
1740 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
1741 u8 min, max;
1742
1743 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
1744 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
1745 DP_NOTICE(p_hwfn,
1746 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
1747 src_id, min, max);
1748
1749 return -EINVAL;
1750 }
1751
1752 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
1753
1754 return 0;
1755}
bcd197c8
MC		 1756
1757/* Calculate final WFQ values for all vports and configure them.
1758 * After this configuration each vport will have
1759 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
1760 */
1761static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1762 struct qed_ptt *p_ptt,
1763 u32 min_pf_rate)
1764{
1765 struct init_qm_vport_params *vport_params;
1766 int i;
1767
1768 vport_params = p_hwfn->qm_info.qm_vport_params;
1769
1770 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1771 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1772
1773 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
1774 min_pf_rate;
1775 qed_init_vport_wfq(p_hwfn, p_ptt,
1776 vport_params[i].first_tx_pq_id,
1777 vport_params[i].vport_wfq);
1778 }
1779}
1780
1781static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
1782 u32 min_pf_rate)
1783
1784{
1785 int i;
1786
1787 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
1788 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
1789}
1790
1791static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1792 struct qed_ptt *p_ptt,
1793 u32 min_pf_rate)
1794{
1795 struct init_qm_vport_params *vport_params;
1796 int i;
1797
1798 vport_params = p_hwfn->qm_info.qm_vport_params;
1799
1800 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1801 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
1802 qed_init_vport_wfq(p_hwfn, p_ptt,
1803 vport_params[i].first_tx_pq_id,
1804 vport_params[i].vport_wfq);
1805 }
1806}
1807
1808/* This function performs several validations for WFQ
1809 * configuration and required min rate for a given vport
1810 * 1. req_rate must be greater than one percent of min_pf_rate.
1811 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
1812 * rates to get less than one percent of min_pf_rate.
1813 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
1814 */
1815static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1816 u16 vport_id, u32 req_rate,
1817 u32 min_pf_rate)
1818{
1819 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
1820 int non_requested_count = 0, req_count = 0, i, num_vports;
1821
1822 num_vports = p_hwfn->qm_info.num_vports;
1823
1824 /* Accounting for the vports which are configured for WFQ explicitly */
1825 for (i = 0; i < num_vports; i++) {
1826 u32 tmp_speed;
1827
1828 if ((i != vport_id) &&
1829 p_hwfn->qm_info.wfq_data[i].configured) {
1830 req_count++;
1831 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1832 total_req_min_rate += tmp_speed;
1833 }
1834 }
1835
1836 /* Include current vport data as well */
1837 req_count++;
1838 total_req_min_rate += req_rate;
1839 non_requested_count = num_vports - req_count;
1840
1841 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
1842 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1843 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1844 vport_id, req_rate, min_pf_rate);
1845 return -EINVAL;
1846 }
1847
1848 if (num_vports > QED_WFQ_UNIT) {
1849 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1850 "Number of vports is greater than %d\n",
1851 QED_WFQ_UNIT);
1852 return -EINVAL;
1853 }
1854
1855 if (total_req_min_rate > min_pf_rate) {
1856 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1857 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
1858 total_req_min_rate, min_pf_rate);
1859 return -EINVAL;
1860 }
1861
1862 total_left_rate = min_pf_rate - total_req_min_rate;
1863
1864 left_rate_per_vp = total_left_rate / non_requested_count;
1865 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
1866 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1867 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1868 left_rate_per_vp, min_pf_rate);
1869 return -EINVAL;
1870 }
1871
1872 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
1873 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
1874
1875 for (i = 0; i < num_vports; i++) {
1876 if (p_hwfn->qm_info.wfq_data[i].configured)
1877 continue;
1878
1879 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
1880 }
1881
1882 return 0;
1883}
1884
1885static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
1886 struct qed_ptt *p_ptt,
1887 u32 min_pf_rate)
1888{
1889 bool use_wfq = false;
1890 int rc = 0;
1891 u16 i;
1892
1893 /* Validate all pre configured vports for wfq */
1894 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1895 u32 rate;
1896
1897 if (!p_hwfn->qm_info.wfq_data[i].configured)
1898 continue;
1899
1900 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
1901 use_wfq = true;
1902
1903 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
1904 if (rc) {
1905 DP_NOTICE(p_hwfn,
1906 "WFQ validation failed while configuring min rate\n");
1907 break;
1908 }
1909 }
1910
1911 if (!rc && use_wfq)
1912 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
1913 else
1914 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
1915
1916 return rc;
1917}
1918
1919/* API to configure WFQ from mcp link change */
1920void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
1921{
1922 int i;
1923
1924 for_each_hwfn(cdev, i) {
1925 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1926
1927 __qed_configure_vp_wfq_on_link_change(p_hwfn,
1928 p_hwfn->p_dpc_ptt,
1929 min_pf_rate);
1930 }
1931}
4b01e519
MC		 1932
1933int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
1934 struct qed_ptt *p_ptt,
1935 struct qed_mcp_link_state *p_link,
1936 u8 max_bw)
1937{
1938 int rc = 0;
1939
1940 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
1941
1942 if (!p_link->line_speed && (max_bw != 100))
1943 return rc;
1944
1945 p_link->speed = (p_link->line_speed * max_bw) / 100;
1946 p_hwfn->qm_info.pf_rl = p_link->speed;
1947
1948 /* Since the limiter also affects Tx-switched traffic, we don't want it
1949 * to limit such traffic in case there's no actual limit.
1950 * In that case, set limit to imaginary high boundary.
1951 */
1952 if (max_bw == 100)
1953 p_hwfn->qm_info.pf_rl = 100000;
1954
1955 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1956 p_hwfn->qm_info.pf_rl);
1957
1958 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1959 "Configured MAX bandwidth to be %08x Mb/sec\n",
1960 p_link->speed);
1961
1962 return rc;
1963}
1964
1965/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
1966int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
1967{
1968 int i, rc = -EINVAL;
1969
1970 if (max_bw < 1 || max_bw > 100) {
1971 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
1972 return rc;
1973 }
1974
1975 for_each_hwfn(cdev, i) {
1976 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1977 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
1978 struct qed_mcp_link_state *p_link;
1979 struct qed_ptt *p_ptt;
1980
1981 p_link = &p_lead->mcp_info->link_output;
1982
1983 p_ptt = qed_ptt_acquire(p_hwfn);
1984 if (!p_ptt)
1985 return -EBUSY;
1986
1987 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1988 p_link, max_bw);
1989
1990 qed_ptt_release(p_hwfn, p_ptt);
1991
1992 if (rc)
1993 break;
1994 }
1995
1996 return rc;
1997}
a64b02d5
MC		 1998
1999int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2000 struct qed_ptt *p_ptt,
2001 struct qed_mcp_link_state *p_link,
2002 u8 min_bw)
2003{
2004 int rc = 0;
2005
2006 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2007 p_hwfn->qm_info.pf_wfq = min_bw;
2008
2009 if (!p_link->line_speed)
2010 return rc;
2011
2012 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2013
2014 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2015
2016 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2017 "Configured MIN bandwidth to be %d Mb/sec\n",
2018 p_link->min_pf_rate);
2019
2020 return rc;
2021}
2022
2023/* Main API to configure PF min bandwidth where bw range is [1-100] */
2024int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2025{
2026 int i, rc = -EINVAL;
2027
2028 if (min_bw < 1 || min_bw > 100) {
2029 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2030 return rc;
2031 }
2032
2033 for_each_hwfn(cdev, i) {
2034 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2035 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2036 struct qed_mcp_link_state *p_link;
2037 struct qed_ptt *p_ptt;
2038
2039 p_link = &p_lead->mcp_info->link_output;
2040
2041 p_ptt = qed_ptt_acquire(p_hwfn);
2042 if (!p_ptt)
2043 return -EBUSY;
2044
2045 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2046 p_link, min_bw);
2047 if (rc) {
2048 qed_ptt_release(p_hwfn, p_ptt);
2049 return rc;
2050 }
2051
2052 if (p_link->min_pf_rate) {
2053 u32 min_rate = p_link->min_pf_rate;
2054
2055 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2056 p_ptt,
2057 min_rate);
2058 }
2059
2060 qed_ptt_release(p_hwfn, p_ptt);
2061 }
2062
2063 return rc;
2064}
Linux kernel - Deliverables
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