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qed: Bulletin and Link
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
CommitLineData
25c089d7
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <asm/param.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/etherdevice.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
20#include <linux/stddef.h>
21#include <linux/string.h>
22#include <linux/version.h>
23#include <linux/workqueue.h>
24#include <linux/bitops.h>
25#include <linux/bug.h>
26#include "qed.h"
27#include <linux/qed/qed_chain.h>
28#include "qed_cxt.h"
29#include "qed_dev_api.h"
30#include <linux/qed/qed_eth_if.h>
31#include "qed_hsi.h"
32#include "qed_hw.h"
33#include "qed_int.h"
dacd88d6 34#include "qed_l2.h"
86622ee7 35#include "qed_mcp.h"
25c089d7
YM		 36#include "qed_reg_addr.h"
37#include "qed_sp.h"
1408cc1f 38#include "qed_sriov.h"
25c089d7 39
088c8618 40
cee4d264
MC		 41#define QED_MAX_SGES_NUM 16
42#define CRC32_POLY 0x1edc6f41
43
dacd88d6
YM		 44int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
45 struct qed_sp_vport_start_params *p_params)
cee4d264 46{
cee4d264
MC		 47 struct vport_start_ramrod_data *p_ramrod = NULL;
48 struct qed_spq_entry *p_ent = NULL;
06f56b81 49 struct qed_sp_init_data init_data;
dacd88d6 50 u8 abs_vport_id = 0;
cee4d264
MC		 51 int rc = -EINVAL;
52 u16 rx_mode = 0;
cee4d264 53
088c8618 54 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
cee4d264
MC		 55 if (rc != 0)
56 return rc;
57
06f56b81
YM		 58 memset(&init_data, 0, sizeof(init_data));
59 init_data.cid = qed_spq_get_cid(p_hwfn);
088c8618 60 init_data.opaque_fid = p_params->opaque_fid;
06f56b81 61 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 62
63 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 64 ETH_RAMROD_VPORT_START,
06f56b81 65 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 66 if (rc)
67 return rc;
68
69 p_ramrod = &p_ent->ramrod.vport_start;
70 p_ramrod->vport_id = abs_vport_id;
71
088c8618
MC		 72 p_ramrod->mtu = cpu_to_le16(p_params->mtu);
73 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
74 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
cee4d264
MC		 75
76 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
77 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
78
79 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
80
81 /* TPA related fields */
82 memset(&p_ramrod->tpa_param, 0,
83 sizeof(struct eth_vport_tpa_param));
84
088c8618
MC		 85 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
86
87 switch (p_params->tpa_mode) {
88 case QED_TPA_MODE_GRO:
89 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
90 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
91 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
92 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
93 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
94 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
95 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
96 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
97 break;
98 default:
99 break;
100 }
101
cee4d264
MC		 102 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
103 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
088c8618 104 p_params->concrete_fid);
cee4d264
MC		 105
106 return qed_spq_post(p_hwfn, p_ent, NULL);
107}
108
dacd88d6
YM		 109int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
110 struct qed_sp_vport_start_params *p_params)
111{
112 if (IS_VF(p_hwfn->cdev)) {
113 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
114 p_params->mtu,
115 p_params->remove_inner_vlan,
116 p_params->tpa_mode,
117 p_params->max_buffers_per_cqe);
118 }
119
120 return qed_sp_eth_vport_start(p_hwfn, p_params);
121}
122
cee4d264
MC		 123static int
124qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
125 struct vport_update_ramrod_data *p_ramrod,
126 struct qed_rss_params *p_params)
127{
128 struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
129 u16 abs_l2_queue = 0, capabilities = 0;
130 int rc = 0, i;
131
132 if (!p_params) {
133 p_ramrod->common.update_rss_flg = 0;
134 return rc;
135 }
136
137 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
138 ETH_RSS_IND_TABLE_ENTRIES_NUM);
139
140 rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
141 if (rc)
142 return rc;
143
144 p_ramrod->common.update_rss_flg = p_params->update_rss_config;
145 rss->update_rss_capabilities = p_params->update_rss_capabilities;
146 rss->update_rss_ind_table = p_params->update_rss_ind_table;
147 rss->update_rss_key = p_params->update_rss_key;
148
149 rss->rss_mode = p_params->rss_enable ?
150 ETH_VPORT_RSS_MODE_REGULAR :
151 ETH_VPORT_RSS_MODE_DISABLED;
152
153 SET_FIELD(capabilities,
154 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
155 !!(p_params->rss_caps & QED_RSS_IPV4));
156 SET_FIELD(capabilities,
157 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
158 !!(p_params->rss_caps & QED_RSS_IPV6));
159 SET_FIELD(capabilities,
160 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
161 !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
162 SET_FIELD(capabilities,
163 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
164 !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
165 SET_FIELD(capabilities,
166 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
167 !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
168 SET_FIELD(capabilities,
169 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
170 !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
171 rss->tbl_size = p_params->rss_table_size_log;
172
173 rss->capabilities = cpu_to_le16(capabilities);
174
175 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
176 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
177 p_ramrod->common.update_rss_flg,
178 rss->rss_mode, rss->update_rss_capabilities,
179 capabilities, rss->update_rss_ind_table,
180 rss->update_rss_key);
181
182 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
183 rc = qed_fw_l2_queue(p_hwfn,
184 (u8)p_params->rss_ind_table[i],
185 &abs_l2_queue);
186 if (rc)
187 return rc;
188
189 rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
190 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
191 i, rss->indirection_table[i]);
192 }
193
194 for (i = 0; i < 10; i++)
195 rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
196
197 return rc;
198}
199
200static void
201qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
202 struct vport_update_ramrod_data *p_ramrod,
203 struct qed_filter_accept_flags accept_flags)
204{
205 p_ramrod->common.update_rx_mode_flg =
206 accept_flags.update_rx_mode_config;
207
208 p_ramrod->common.update_tx_mode_flg =
209 accept_flags.update_tx_mode_config;
210
211 /* Set Rx mode accept flags */
212 if (p_ramrod->common.update_rx_mode_flg) {
213 u8 accept_filter = accept_flags.rx_accept_filter;
214 u16 state = 0;
215
216 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
217 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
218 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
219
220 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
221 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
222
223 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
224 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
225 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
226
227 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
228 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
229 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
230
231 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
232 !!(accept_filter & QED_ACCEPT_BCAST));
233
234 p_ramrod->rx_mode.state = cpu_to_le16(state);
235 DP_VERBOSE(p_hwfn, QED_MSG_SP,
236 "p_ramrod->rx_mode.state = 0x%x\n", state);
237 }
238
239 /* Set Tx mode accept flags */
240 if (p_ramrod->common.update_tx_mode_flg) {
241 u8 accept_filter = accept_flags.tx_accept_filter;
242 u16 state = 0;
243
244 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
245 !!(accept_filter & QED_ACCEPT_NONE));
246
247 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
248 (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
249 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
250
251 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
252 !!(accept_filter & QED_ACCEPT_NONE));
253
254 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
255 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
256 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
257
258 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
259 !!(accept_filter & QED_ACCEPT_BCAST));
260
261 p_ramrod->tx_mode.state = cpu_to_le16(state);
262 DP_VERBOSE(p_hwfn, QED_MSG_SP,
263 "p_ramrod->tx_mode.state = 0x%x\n", state);
264 }
265}
266
267static void
268qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
269 struct vport_update_ramrod_data *p_ramrod,
270 struct qed_sp_vport_update_params *p_params)
271{
272 int i;
273
274 memset(&p_ramrod->approx_mcast.bins, 0,
275 sizeof(p_ramrod->approx_mcast.bins));
276
277 if (p_params->update_approx_mcast_flg) {
278 p_ramrod->common.update_approx_mcast_flg = 1;
279 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
280 u32 *p_bins = (u32 *)p_params->bins;
281 __le32 val = cpu_to_le32(p_bins[i]);
282
283 p_ramrod->approx_mcast.bins[i] = val;
284 }
285 }
286}
287
dacd88d6
YM		 288int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
289 struct qed_sp_vport_update_params *p_params,
290 enum spq_mode comp_mode,
291 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 292{
293 struct qed_rss_params *p_rss_params = p_params->rss_params;
294 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 295 struct qed_sp_init_data init_data;
cee4d264
MC		 296 struct vport_update_ramrod_data *p_ramrod = NULL;
297 struct qed_spq_entry *p_ent = NULL;
298 u8 abs_vport_id = 0;
299 int rc = -EINVAL;
300
dacd88d6
YM		 301 if (IS_VF(p_hwfn->cdev)) {
302 rc = qed_vf_pf_vport_update(p_hwfn, p_params);
303 return rc;
304 }
305
cee4d264
MC		 306 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
307 if (rc != 0)
308 return rc;
309
06f56b81
YM		 310 memset(&init_data, 0, sizeof(init_data));
311 init_data.cid = qed_spq_get_cid(p_hwfn);
312 init_data.opaque_fid = p_params->opaque_fid;
313 init_data.comp_mode = comp_mode;
314 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 315
316 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 317 ETH_RAMROD_VPORT_UPDATE,
06f56b81 318 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 319 if (rc)
320 return rc;
321
322 /* Copy input params to ramrod according to FW struct */
323 p_ramrod = &p_ent->ramrod.vport_update;
324 p_cmn = &p_ramrod->common;
325
326 p_cmn->vport_id = abs_vport_id;
327 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
328 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
329 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
330 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69
YM		 331 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
332 p_cmn->update_accept_any_vlan_flg =
333 p_params->update_accept_any_vlan_flg;
cee4d264
MC		 334 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
335 if (rc) {
336 /* Return spq entry which is taken in qed_sp_init_request()*/
337 qed_spq_return_entry(p_hwfn, p_ent);
338 return rc;
339 }
340
341 /* Update mcast bins for VFs, PF doesn't use this functionality */
342 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
343
344 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
345 return qed_spq_post(p_hwfn, p_ent, NULL);
346}
347
dacd88d6 348int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
cee4d264 349{
cee4d264 350 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 351 struct qed_sp_init_data init_data;
cee4d264
MC		 352 struct qed_spq_entry *p_ent;
353 u8 abs_vport_id = 0;
354 int rc;
355
dacd88d6
YM		 356 if (IS_VF(p_hwfn->cdev))
357 return qed_vf_pf_vport_stop(p_hwfn);
358
cee4d264
MC		 359 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
360 if (rc != 0)
361 return rc;
362
06f56b81
YM		 363 memset(&init_data, 0, sizeof(init_data));
364 init_data.cid = qed_spq_get_cid(p_hwfn);
365 init_data.opaque_fid = opaque_fid;
366 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 367
368 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 369 ETH_RAMROD_VPORT_STOP,
06f56b81 370 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 371 if (rc)
372 return rc;
373
374 p_ramrod = &p_ent->ramrod.vport_stop;
375 p_ramrod->vport_id = abs_vport_id;
376
377 return qed_spq_post(p_hwfn, p_ent, NULL);
378}
379
dacd88d6
YM		 380static int
381qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
382 struct qed_filter_accept_flags *p_accept_flags)
383{
384 struct qed_sp_vport_update_params s_params;
385
386 memset(&s_params, 0, sizeof(s_params));
387 memcpy(&s_params.accept_flags, p_accept_flags,
388 sizeof(struct qed_filter_accept_flags));
389
390 return qed_vf_pf_vport_update(p_hwfn, &s_params);
391}
392
cee4d264
MC		 393static int qed_filter_accept_cmd(struct qed_dev *cdev,
394 u8 vport,
395 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 396 u8 update_accept_any_vlan,
397 u8 accept_any_vlan,
dacd88d6
YM		 398 enum spq_mode comp_mode,
399 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 400{
401 struct qed_sp_vport_update_params vport_update_params;
402 int i, rc;
403
404 /* Prepare and send the vport rx_mode change */
405 memset(&vport_update_params, 0, sizeof(vport_update_params));
406 vport_update_params.vport_id = vport;
407 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 408 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
409 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 410
411 for_each_hwfn(cdev, i) {
412 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
413
414 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
415
dacd88d6
YM		 416 if (IS_VF(cdev)) {
417 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
418 if (rc)
419 return rc;
420 continue;
421 }
422
cee4d264
MC		 423 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
424 comp_mode, p_comp_data);
425 if (rc != 0) {
426 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
427 return rc;
428 }
429
430 DP_VERBOSE(p_hwfn, QED_MSG_SP,
431 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
432 accept_flags.rx_accept_filter,
433 accept_flags.tx_accept_filter);
3f9b4a69
YM		 434 if (update_accept_any_vlan)
435 DP_VERBOSE(p_hwfn, QED_MSG_SP,
436 "accept_any_vlan=%d configured\n",
437 accept_any_vlan);
cee4d264
MC		 438 }
439
440 return 0;
441}
442
443static int qed_sp_release_queue_cid(
444 struct qed_hwfn *p_hwfn,
445 struct qed_hw_cid_data *p_cid_data)
446{
447 if (!p_cid_data->b_cid_allocated)
448 return 0;
449
450 qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
451
452 p_cid_data->b_cid_allocated = false;
453
454 return 0;
455}
456
dacd88d6
YM		 457int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
458 u16 opaque_fid,
459 u32 cid,
460 struct qed_queue_start_common_params *params,
461 u8 stats_id,
462 u16 bd_max_bytes,
463 dma_addr_t bd_chain_phys_addr,
464 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
cee4d264
MC		 465{
466 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 467 struct qed_spq_entry *p_ent = NULL;
06f56b81 468 struct qed_sp_init_data init_data;
cee4d264
MC		 469 struct qed_hw_cid_data *p_rx_cid;
470 u16 abs_rx_q_id = 0;
471 u8 abs_vport_id = 0;
472 int rc = -EINVAL;
473
474 /* Store information for the stop */
475 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
476 p_rx_cid->cid = cid;
477 p_rx_cid->opaque_fid = opaque_fid;
478 p_rx_cid->vport_id = params->vport_id;
479
480 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id);
481 if (rc != 0)
482 return rc;
483
484 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id);
485 if (rc != 0)
486 return rc;
487
488 DP_VERBOSE(p_hwfn, QED_MSG_SP,
489 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
490 opaque_fid, cid, params->queue_id, params->vport_id,
491 params->sb);
492
06f56b81
YM		 493 /* Get SPQ entry */
494 memset(&init_data, 0, sizeof(init_data));
495 init_data.cid = cid;
496 init_data.opaque_fid = opaque_fid;
497 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 498
499 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 500 ETH_RAMROD_RX_QUEUE_START,
06f56b81 501 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 502 if (rc)
503 return rc;
504
505 p_ramrod = &p_ent->ramrod.rx_queue_start;
506
507 p_ramrod->sb_id = cpu_to_le16(params->sb);
508 p_ramrod->sb_index = params->sb_idx;
509 p_ramrod->vport_id = abs_vport_id;
510 p_ramrod->stats_counter_id = stats_id;
511 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
512 p_ramrod->complete_cqe_flg = 0;
513 p_ramrod->complete_event_flg = 1;
514
515 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
94494598 516 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
cee4d264
MC		 517
518 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
94494598 519 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
cee4d264
MC		 520
521 rc = qed_spq_post(p_hwfn, p_ent, NULL);
522
523 return rc;
524}
525
526static int
527qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
528 u16 opaque_fid,
529 struct qed_queue_start_common_params *params,
530 u16 bd_max_bytes,
531 dma_addr_t bd_chain_phys_addr,
532 dma_addr_t cqe_pbl_addr,
dacd88d6 533 u16 cqe_pbl_size, void __iomem **pp_prod)
cee4d264
MC		 534{
535 struct qed_hw_cid_data *p_rx_cid;
536 u64 init_prod_val = 0;
537 u16 abs_l2_queue = 0;
538 u8 abs_stats_id = 0;
539 int rc;
540
dacd88d6
YM		 541 if (IS_VF(p_hwfn->cdev)) {
542 return qed_vf_pf_rxq_start(p_hwfn,
543 params->queue_id,
544 params->sb,
545 params->sb_idx,
546 bd_max_bytes,
547 bd_chain_phys_addr,
548 cqe_pbl_addr, cqe_pbl_size, pp_prod);
549 }
550
cee4d264
MC		 551 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue);
552 if (rc != 0)
553 return rc;
554
555 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id);
556 if (rc != 0)
557 return rc;
558
559 *pp_prod = (u8 __iomem *)p_hwfn->regview +
560 GTT_BAR0_MAP_REG_MSDM_RAM +
561 MSTORM_PRODS_OFFSET(abs_l2_queue);
562
563 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
564 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
565 (u32 *)(&init_prod_val));
566
567 /* Allocate a CID for the queue */
568 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
569 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
570 &p_rx_cid->cid);
571 if (rc) {
572 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
573 return rc;
574 }
575 p_rx_cid->b_cid_allocated = true;
576
577 rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
578 opaque_fid,
579 p_rx_cid->cid,
580 params,
581 abs_stats_id,
582 bd_max_bytes,
583 bd_chain_phys_addr,
584 cqe_pbl_addr,
585 cqe_pbl_size);
586
587 if (rc != 0)
588 qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
589
590 return rc;
591}
592
dacd88d6
YM		 593int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
594 u16 rx_queue_id,
595 bool eq_completion_only, bool cqe_completion)
cee4d264
MC		 596{
597 struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
598 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 599 struct qed_spq_entry *p_ent = NULL;
06f56b81 600 struct qed_sp_init_data init_data;
cee4d264
MC		 601 u16 abs_rx_q_id = 0;
602 int rc = -EINVAL;
603
dacd88d6
YM		 604 if (IS_VF(p_hwfn->cdev))
605 return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion);
606
06f56b81
YM		 607 /* Get SPQ entry */
608 memset(&init_data, 0, sizeof(init_data));
609 init_data.cid = p_rx_cid->cid;
610 init_data.opaque_fid = p_rx_cid->opaque_fid;
611 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 612
613 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 614 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 615 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 616 if (rc)
617 return rc;
618
619 p_ramrod = &p_ent->ramrod.rx_queue_stop;
620
621 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
622 qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
623 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
624
625 /* Cleaning the queue requires the completion to arrive there.
626 * In addition, VFs require the answer to come as eqe to PF.
627 */
628 p_ramrod->complete_cqe_flg =
629 (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
630 !eq_completion_only) || cqe_completion;
631 p_ramrod->complete_event_flg =
632 !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
633 eq_completion_only;
634
635 rc = qed_spq_post(p_hwfn, p_ent, NULL);
636 if (rc)
637 return rc;
638
639 return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
640}
641
dacd88d6
YM		 642int qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
643 u16 opaque_fid,
644 u32 cid,
645 struct qed_queue_start_common_params *p_params,
646 u8 stats_id,
647 dma_addr_t pbl_addr,
648 u16 pbl_size,
649 union qed_qm_pq_params *p_pq_params)
cee4d264
MC		 650{
651 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 652 struct qed_spq_entry *p_ent = NULL;
06f56b81 653 struct qed_sp_init_data init_data;
cee4d264
MC		 654 struct qed_hw_cid_data *p_tx_cid;
655 u8 abs_vport_id;
656 int rc = -EINVAL;
657 u16 pq_id;
658
659 /* Store information for the stop */
660 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
661 p_tx_cid->cid = cid;
662 p_tx_cid->opaque_fid = opaque_fid;
663
664 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
665 if (rc)
666 return rc;
667
06f56b81
YM		 668 /* Get SPQ entry */
669 memset(&init_data, 0, sizeof(init_data));
670 init_data.cid = cid;
671 init_data.opaque_fid = opaque_fid;
672 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 673
06f56b81 674 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 675 ETH_RAMROD_TX_QUEUE_START,
06f56b81 676 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 677 if (rc)
678 return rc;
679
680 p_ramrod = &p_ent->ramrod.tx_queue_start;
681 p_ramrod->vport_id = abs_vport_id;
682
683 p_ramrod->sb_id = cpu_to_le16(p_params->sb);
684 p_ramrod->sb_index = p_params->sb_idx;
685 p_ramrod->stats_counter_id = stats_id;
cee4d264
MC		 686
687 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
94494598 688 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
cee4d264
MC		 689
690 pq_id = qed_get_qm_pq(p_hwfn,
691 PROTOCOLID_ETH,
692 p_pq_params);
693 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
694
695 return qed_spq_post(p_hwfn, p_ent, NULL);
696}
697
698static int
699qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
700 u16 opaque_fid,
701 struct qed_queue_start_common_params *p_params,
702 dma_addr_t pbl_addr,
dacd88d6 703 u16 pbl_size, void __iomem **pp_doorbell)
cee4d264
MC		 704{
705 struct qed_hw_cid_data *p_tx_cid;
706 union qed_qm_pq_params pq_params;
707 u8 abs_stats_id = 0;
708 int rc;
709
dacd88d6
YM		 710 if (IS_VF(p_hwfn->cdev)) {
711 return qed_vf_pf_txq_start(p_hwfn,
712 p_params->queue_id,
713 p_params->sb,
714 p_params->sb_idx,
715 pbl_addr, pbl_size, pp_doorbell);
716 }
717
cee4d264
MC		 718 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
719 if (rc)
720 return rc;
721
722 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
723 memset(p_tx_cid, 0, sizeof(*p_tx_cid));
724 memset(&pq_params, 0, sizeof(pq_params));
725
726 /* Allocate a CID for the queue */
727 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
728 &p_tx_cid->cid);
729 if (rc) {
730 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
731 return rc;
732 }
733 p_tx_cid->b_cid_allocated = true;
734
735 DP_VERBOSE(p_hwfn, QED_MSG_SP,
736 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
737 opaque_fid, p_tx_cid->cid,
738 p_params->queue_id, p_params->vport_id, p_params->sb);
739
740 rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
741 opaque_fid,
742 p_tx_cid->cid,
743 p_params,
744 abs_stats_id,
745 pbl_addr,
746 pbl_size,
747 &pq_params);
748
749 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
750 qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
751
752 if (rc)
753 qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
754
755 return rc;
756}
757
dacd88d6 758int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id)
cee4d264
MC		 759{
760 struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
cee4d264 761 struct qed_spq_entry *p_ent = NULL;
06f56b81 762 struct qed_sp_init_data init_data;
cee4d264
MC		 763 int rc = -EINVAL;
764
dacd88d6
YM		 765 if (IS_VF(p_hwfn->cdev))
766 return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id);
767
06f56b81
YM		 768 /* Get SPQ entry */
769 memset(&init_data, 0, sizeof(init_data));
770 init_data.cid = p_tx_cid->cid;
771 init_data.opaque_fid = p_tx_cid->opaque_fid;
772 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 773
774 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 775 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 776 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 777 if (rc)
778 return rc;
779
780 rc = qed_spq_post(p_hwfn, p_ent, NULL);
781 if (rc)
782 return rc;
783
784 return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
785}
786
787static enum eth_filter_action
788qed_filter_action(enum qed_filter_opcode opcode)
789{
790 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
791
792 switch (opcode) {
793 case QED_FILTER_ADD:
794 action = ETH_FILTER_ACTION_ADD;
795 break;
796 case QED_FILTER_REMOVE:
797 action = ETH_FILTER_ACTION_REMOVE;
798 break;
cee4d264 799 case QED_FILTER_FLUSH:
fc48b7a6 800 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 801 break;
802 default:
803 action = MAX_ETH_FILTER_ACTION;
804 }
805
806 return action;
807}
808
809static void qed_set_fw_mac_addr(__le16 *fw_msb,
810 __le16 *fw_mid,
811 __le16 *fw_lsb,
812 u8 *mac)
813{
814 ((u8 *)fw_msb)[0] = mac[1];
815 ((u8 *)fw_msb)[1] = mac[0];
816 ((u8 *)fw_mid)[0] = mac[3];
817 ((u8 *)fw_mid)[1] = mac[2];
818 ((u8 *)fw_lsb)[0] = mac[5];
819 ((u8 *)fw_lsb)[1] = mac[4];
820}
821
822static int
823qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
824 u16 opaque_fid,
825 struct qed_filter_ucast *p_filter_cmd,
826 struct vport_filter_update_ramrod_data **pp_ramrod,
827 struct qed_spq_entry **pp_ent,
828 enum spq_mode comp_mode,
829 struct qed_spq_comp_cb *p_comp_data)
830{
831 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
832 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 833 struct eth_filter_cmd *p_first_filter;
834 struct eth_filter_cmd *p_second_filter;
06f56b81 835 struct qed_sp_init_data init_data;
cee4d264
MC		 836 enum eth_filter_action action;
837 int rc;
838
839 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
840 &vport_to_remove_from);
841 if (rc)
842 return rc;
843
844 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
845 &vport_to_add_to);
846 if (rc)
847 return rc;
848
06f56b81
YM		 849 /* Get SPQ entry */
850 memset(&init_data, 0, sizeof(init_data));
851 init_data.cid = qed_spq_get_cid(p_hwfn);
852 init_data.opaque_fid = opaque_fid;
853 init_data.comp_mode = comp_mode;
854 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 855
856 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 857 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 858 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 859 if (rc)
860 return rc;
861
862 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
863 p_ramrod = *pp_ramrod;
864 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
865 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
866
867 switch (p_filter_cmd->opcode) {
fc48b7a6 868 case QED_FILTER_REPLACE:
cee4d264
MC		 869 case QED_FILTER_MOVE:
870 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
871 default:
872 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
873 }
874
875 p_first_filter = &p_ramrod->filter_cmds[0];
876 p_second_filter = &p_ramrod->filter_cmds[1];
877
878 switch (p_filter_cmd->type) {
879 case QED_FILTER_MAC:
880 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
881 case QED_FILTER_VLAN:
882 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
883 case QED_FILTER_MAC_VLAN:
884 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
885 case QED_FILTER_INNER_MAC:
886 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
887 case QED_FILTER_INNER_VLAN:
888 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
889 case QED_FILTER_INNER_PAIR:
890 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
891 case QED_FILTER_INNER_MAC_VNI_PAIR:
892 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
893 break;
894 case QED_FILTER_MAC_VNI_PAIR:
895 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
896 case QED_FILTER_VNI:
897 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
898 }
899
900 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
901 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
902 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
903 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
904 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
905 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
906 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
907 &p_first_filter->mac_mid,
908 &p_first_filter->mac_lsb,
909 (u8 *)p_filter_cmd->mac);
910 }
911
912 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
913 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
914 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
915 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
916 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
917
918 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
919 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
920 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
921 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
922
923 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
924 p_second_filter->type = p_first_filter->type;
925 p_second_filter->mac_msb = p_first_filter->mac_msb;
926 p_second_filter->mac_mid = p_first_filter->mac_mid;
927 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
928 p_second_filter->vlan_id = p_first_filter->vlan_id;
929 p_second_filter->vni = p_first_filter->vni;
930
931 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
932
933 p_first_filter->vport_id = vport_to_remove_from;
934
935 p_second_filter->action = ETH_FILTER_ACTION_ADD;
936 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 937 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
938 p_first_filter->vport_id = vport_to_add_to;
939 memcpy(p_second_filter, p_first_filter,
940 sizeof(*p_second_filter));
941 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
942 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 943 } else {
944 action = qed_filter_action(p_filter_cmd->opcode);
945
946 if (action == MAX_ETH_FILTER_ACTION) {
947 DP_NOTICE(p_hwfn,
948 "%d is not supported yet\n",
949 p_filter_cmd->opcode);
950 return -EINVAL;
951 }
952
953 p_first_filter->action = action;
954 p_first_filter->vport_id = (p_filter_cmd->opcode ==
955 QED_FILTER_REMOVE) ?
956 vport_to_remove_from :
957 vport_to_add_to;
958 }
959
960 return 0;
961}
962
dacd88d6
YM		 963int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
964 u16 opaque_fid,
965 struct qed_filter_ucast *p_filter_cmd,
966 enum spq_mode comp_mode,
967 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 968{
969 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
970 struct qed_spq_entry *p_ent = NULL;
971 struct eth_filter_cmd_header *p_header;
972 int rc;
973
974 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
975 &p_ramrod, &p_ent,
976 comp_mode, p_comp_data);
977 if (rc != 0) {
978 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
979 return rc;
980 }
981 p_header = &p_ramrod->filter_cmd_hdr;
982 p_header->assert_on_error = p_filter_cmd->assert_on_error;
983
984 rc = qed_spq_post(p_hwfn, p_ent, NULL);
985 if (rc != 0) {
986 DP_ERR(p_hwfn,
987 "Unicast filter ADD command failed %d\n",
988 rc);
989 return rc;
990 }
991
992 DP_VERBOSE(p_hwfn, QED_MSG_SP,
993 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
994 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
995 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
996 "REMOVE" :
997 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
998 "MOVE" : "REPLACE")),
999 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1000 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1001 "VLAN" : "MAC & VLAN"),
1002 p_ramrod->filter_cmd_hdr.cmd_cnt,
1003 p_filter_cmd->is_rx_filter,
1004 p_filter_cmd->is_tx_filter);
1005 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1006 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1007 p_filter_cmd->vport_to_add_to,
1008 p_filter_cmd->vport_to_remove_from,
1009 p_filter_cmd->mac[0],
1010 p_filter_cmd->mac[1],
1011 p_filter_cmd->mac[2],
1012 p_filter_cmd->mac[3],
1013 p_filter_cmd->mac[4],
1014 p_filter_cmd->mac[5],
1015 p_filter_cmd->vlan);
1016
1017 return 0;
1018}
1019
1020/*******************************************************************************
1021 * Description:
1022 * Calculates crc 32 on a buffer
1023 * Note: crc32_length MUST be aligned to 8
1024 * Return:
1025 ******************************************************************************/
1026static u32 qed_calc_crc32c(u8 *crc32_packet,
1027 u32 crc32_length,
1028 u32 crc32_seed,
1029 u8 complement)
1030{
1031 u32 byte = 0;
1032 u32 bit = 0;
1033 u8 msb = 0;
1034 u8 current_byte = 0;
1035 u32 crc32_result = crc32_seed;
1036
1037 if ((!crc32_packet) ||
1038 (crc32_length == 0) ||
1039 ((crc32_length % 8) != 0))
1040 return crc32_result;
1041 for (byte = 0; byte < crc32_length; byte++) {
1042 current_byte = crc32_packet[byte];
1043 for (bit = 0; bit < 8; bit++) {
1044 msb = (u8)(crc32_result >> 31);
1045 crc32_result = crc32_result << 1;
1046 if (msb != (0x1 & (current_byte >> bit))) {
1047 crc32_result = crc32_result ^ CRC32_POLY;
1048 crc32_result |= 1; /*crc32_result[0] = 1;*/
1049 }
1050 }
1051 }
1052 return crc32_result;
1053}
1054
1055static inline u32 qed_crc32c_le(u32 seed,
1056 u8 *mac,
1057 u32 len)
1058{
1059 u32 packet_buf[2] = { 0 };
1060
1061 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1062 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1063}
1064
dacd88d6 1065u8 qed_mcast_bin_from_mac(u8 *mac)
cee4d264
MC		 1066{
1067 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1068 mac, ETH_ALEN);
1069
1070 return crc & 0xff;
1071}
1072
1073static int
1074qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1075 u16 opaque_fid,
1076 struct qed_filter_mcast *p_filter_cmd,
1077 enum spq_mode comp_mode,
1078 struct qed_spq_comp_cb *p_comp_data)
1079{
1080 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1081 struct vport_update_ramrod_data *p_ramrod = NULL;
cee4d264 1082 struct qed_spq_entry *p_ent = NULL;
06f56b81 1083 struct qed_sp_init_data init_data;
cee4d264
MC		 1084 u8 abs_vport_id = 0;
1085 int rc, i;
1086
1087 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1088 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1089 &abs_vport_id);
1090 if (rc)
1091 return rc;
1092 } else {
1093 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1094 &abs_vport_id);
1095 if (rc)
1096 return rc;
1097 }
1098
06f56b81
YM		 1099 /* Get SPQ entry */
1100 memset(&init_data, 0, sizeof(init_data));
1101 init_data.cid = qed_spq_get_cid(p_hwfn);
1102 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1103 init_data.comp_mode = comp_mode;
1104 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1105
1106 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1107 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1108 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1109 if (rc) {
1110 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1111 return rc;
1112 }
1113
1114 p_ramrod = &p_ent->ramrod.vport_update;
1115 p_ramrod->common.update_approx_mcast_flg = 1;
1116
1117 /* explicitly clear out the entire vector */
1118 memset(&p_ramrod->approx_mcast.bins, 0,
1119 sizeof(p_ramrod->approx_mcast.bins));
1120 memset(bins, 0, sizeof(unsigned long) *
1121 ETH_MULTICAST_MAC_BINS_IN_REGS);
1122 /* filter ADD op is explicit set op and it removes
1123 * any existing filters for the vport
1124 */
1125 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1126 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1127 u32 bit;
1128
1129 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1130 __set_bit(bit, bins);
1131 }
1132
1133 /* Convert to correct endianity */
1134 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1135 u32 *p_bins = (u32 *)bins;
1136 struct vport_update_ramrod_mcast *approx_mcast;
1137
1138 approx_mcast = &p_ramrod->approx_mcast;
1139 approx_mcast->bins[i] = cpu_to_le32(p_bins[i]);
1140 }
1141 }
1142
1143 p_ramrod->common.vport_id = abs_vport_id;
1144
1145 return qed_spq_post(p_hwfn, p_ent, NULL);
1146}
1147
dacd88d6
YM		 1148static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1149 struct qed_filter_mcast *p_filter_cmd,
1150 enum spq_mode comp_mode,
1151 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1152{
1153 int rc = 0;
1154 int i;
1155
1156 /* only ADD and REMOVE operations are supported for multi-cast */
1157 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1158 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1159 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1160 return -EINVAL;
1161
1162 for_each_hwfn(cdev, i) {
1163 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1164
1165 u16 opaque_fid;
1166
dacd88d6
YM		 1167 if (IS_VF(cdev)) {
1168 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1169 continue;
1170 }
cee4d264
MC		 1171
1172 opaque_fid = p_hwfn->hw_info.opaque_fid;
1173
1174 rc = qed_sp_eth_filter_mcast(p_hwfn,
1175 opaque_fid,
1176 p_filter_cmd,
1177 comp_mode,
1178 p_comp_data);
1179 }
1180 return rc;
1181}
1182
1183static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1184 struct qed_filter_ucast *p_filter_cmd,
1185 enum spq_mode comp_mode,
1186 struct qed_spq_comp_cb *p_comp_data)
1187{
1188 int rc = 0;
1189 int i;
1190
1191 for_each_hwfn(cdev, i) {
1192 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1193 u16 opaque_fid;
1194
dacd88d6
YM		 1195 if (IS_VF(cdev)) {
1196 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1197 continue;
1198 }
cee4d264
MC		 1199
1200 opaque_fid = p_hwfn->hw_info.opaque_fid;
1201
1202 rc = qed_sp_eth_filter_ucast(p_hwfn,
1203 opaque_fid,
1204 p_filter_cmd,
1205 comp_mode,
1206 p_comp_data);
dacd88d6
YM		 1207 if (rc != 0)
1208 break;
cee4d264
MC		 1209 }
1210
1211 return rc;
1212}
1213
86622ee7
YM		 1214/* Statistics related code */
1215static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
1216 u32 *p_addr,
dacd88d6 1217 u32 *p_len, u16 statistics_bin)
86622ee7 1218{
dacd88d6
YM		 1219 if (IS_PF(p_hwfn->cdev)) {
1220 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1221 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1222 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1223 } else {
1224 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1225 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1226
1227 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1228 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1229 }
86622ee7
YM		 1230}
1231
1232static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
1233 struct qed_ptt *p_ptt,
1234 struct qed_eth_stats *p_stats,
1235 u16 statistics_bin)
1236{
1237 struct eth_pstorm_per_queue_stat pstats;
1238 u32 pstats_addr = 0, pstats_len = 0;
1239
1240 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1241 statistics_bin);
1242
1243 memset(&pstats, 0, sizeof(pstats));
dacd88d6
YM		 1244 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1245
1246 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1247 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1248 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1249 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1250 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1251 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1252 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
86622ee7
YM		 1253}
1254
1255static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
1256 struct qed_ptt *p_ptt,
1257 struct qed_eth_stats *p_stats,
1258 u16 statistics_bin)
1259{
86622ee7 1260 struct tstorm_per_port_stat tstats;
dacd88d6 1261 u32 tstats_addr, tstats_len;
86622ee7 1262
dacd88d6
YM		 1263 if (IS_PF(p_hwfn->cdev)) {
1264 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1265 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1266 tstats_len = sizeof(struct tstorm_per_port_stat);
1267 } else {
1268 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1269 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1270
1271 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1272 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1273 }
86622ee7
YM		 1274
1275 memset(&tstats, 0, sizeof(tstats));
dacd88d6 1276 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
86622ee7
YM		 1277
1278 p_stats->mftag_filter_discards +=
1279 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1280 p_stats->mac_filter_discards +=
1281 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1282}
1283
1284static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
1285 u32 *p_addr,
dacd88d6 1286 u32 *p_len, u16 statistics_bin)
86622ee7 1287{
dacd88d6
YM		 1288 if (IS_PF(p_hwfn->cdev)) {
1289 *p_addr = BAR0_MAP_REG_USDM_RAM +
1290 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1291 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1292 } else {
1293 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1294 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1295
1296 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1297 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1298 }
86622ee7
YM		 1299}
1300
1301static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
1302 struct qed_ptt *p_ptt,
1303 struct qed_eth_stats *p_stats,
1304 u16 statistics_bin)
1305{
1306 struct eth_ustorm_per_queue_stat ustats;
1307 u32 ustats_addr = 0, ustats_len = 0;
1308
1309 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1310 statistics_bin);
1311
1312 memset(&ustats, 0, sizeof(ustats));
dacd88d6
YM		 1313 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1314
1315 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1316 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1317 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1318 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1319 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1320 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
86622ee7
YM		 1321}
1322
1323static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
1324 u32 *p_addr,
dacd88d6 1325 u32 *p_len, u16 statistics_bin)
86622ee7 1326{
dacd88d6
YM		 1327 if (IS_PF(p_hwfn->cdev)) {
1328 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1329 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1330 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1331 } else {
1332 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1333 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1334
1335 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1336 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1337 }
86622ee7
YM		 1338}
1339
1340static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
1341 struct qed_ptt *p_ptt,
1342 struct qed_eth_stats *p_stats,
1343 u16 statistics_bin)
1344{
1345 struct eth_mstorm_per_queue_stat mstats;
1346 u32 mstats_addr = 0, mstats_len = 0;
1347
1348 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1349 statistics_bin);
1350
1351 memset(&mstats, 0, sizeof(mstats));
dacd88d6 1352 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
86622ee7 1353
dacd88d6 1354 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
86622ee7
YM		 1355 p_stats->packet_too_big_discard +=
1356 HILO_64_REGPAIR(mstats.packet_too_big_discard);
dacd88d6 1357 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
86622ee7
YM		 1358 p_stats->tpa_coalesced_pkts +=
1359 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1360 p_stats->tpa_coalesced_events +=
1361 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
dacd88d6 1362 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
86622ee7
YM		 1363 p_stats->tpa_coalesced_bytes +=
1364 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1365}
1366
1367static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
1368 struct qed_ptt *p_ptt,
1369 struct qed_eth_stats *p_stats)
1370{
1371 struct port_stats port_stats;
1372 int j;
1373
1374 memset(&port_stats, 0, sizeof(port_stats));
1375
1376 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1377 p_hwfn->mcp_info->port_addr +
1378 offsetof(struct public_port, stats),
1379 sizeof(port_stats));
1380
1381 p_stats->rx_64_byte_packets += port_stats.pmm.r64;
d4967cf3
YM		 1382 p_stats->rx_65_to_127_byte_packets += port_stats.pmm.r127;
1383 p_stats->rx_128_to_255_byte_packets += port_stats.pmm.r255;
1384 p_stats->rx_256_to_511_byte_packets += port_stats.pmm.r511;
1385 p_stats->rx_512_to_1023_byte_packets += port_stats.pmm.r1023;
1386 p_stats->rx_1024_to_1518_byte_packets += port_stats.pmm.r1518;
1387 p_stats->rx_1519_to_1522_byte_packets += port_stats.pmm.r1522;
1388 p_stats->rx_1519_to_2047_byte_packets += port_stats.pmm.r2047;
1389 p_stats->rx_2048_to_4095_byte_packets += port_stats.pmm.r4095;
1390 p_stats->rx_4096_to_9216_byte_packets += port_stats.pmm.r9216;
1391 p_stats->rx_9217_to_16383_byte_packets += port_stats.pmm.r16383;
86622ee7
YM		 1392 p_stats->rx_crc_errors += port_stats.pmm.rfcs;
1393 p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
1394 p_stats->rx_pause_frames += port_stats.pmm.rxpf;
1395 p_stats->rx_pfc_frames += port_stats.pmm.rxpp;
1396 p_stats->rx_align_errors += port_stats.pmm.raln;
1397 p_stats->rx_carrier_errors += port_stats.pmm.rfcr;
1398 p_stats->rx_oversize_packets += port_stats.pmm.rovr;
1399 p_stats->rx_jabbers += port_stats.pmm.rjbr;
1400 p_stats->rx_undersize_packets += port_stats.pmm.rund;
1401 p_stats->rx_fragments += port_stats.pmm.rfrg;
1402 p_stats->tx_64_byte_packets += port_stats.pmm.t64;
1403 p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
1404 p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
1405 p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
1406 p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
1407 p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
1408 p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
1409 p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
1410 p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
1411 p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
1412 p_stats->tx_pause_frames += port_stats.pmm.txpf;
1413 p_stats->tx_pfc_frames += port_stats.pmm.txpp;
1414 p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
1415 p_stats->tx_total_collisions += port_stats.pmm.tncl;
1416 p_stats->rx_mac_bytes += port_stats.pmm.rbyte;
1417 p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
1418 p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
1419 p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
1420 p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
1421 p_stats->tx_mac_bytes += port_stats.pmm.tbyte;
1422 p_stats->tx_mac_uc_packets += port_stats.pmm.txuca;
1423 p_stats->tx_mac_mc_packets += port_stats.pmm.txmca;
1424 p_stats->tx_mac_bc_packets += port_stats.pmm.txbca;
1425 p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
1426 for (j = 0; j < 8; j++) {
1427 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1428 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1429 }
1430}
1431
1432static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
1433 struct qed_ptt *p_ptt,
1434 struct qed_eth_stats *stats,
dacd88d6 1435 u16 statistics_bin, bool b_get_port_stats)
86622ee7
YM		 1436{
1437 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1438 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1439 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1440 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1441
dacd88d6 1442 if (b_get_port_stats && p_hwfn->mcp_info)
86622ee7
YM		 1443 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
1444}
1445
1446static void _qed_get_vport_stats(struct qed_dev *cdev,
1447 struct qed_eth_stats *stats)
1448{
dacd88d6
YM		 1449 u8 fw_vport = 0;
1450 int i;
86622ee7
YM		 1451
1452 memset(stats, 0, sizeof(*stats));
1453
1454 for_each_hwfn(cdev, i) {
1455 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dacd88d6
YM		 1456 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1457 : NULL;
1458
1459 if (IS_PF(cdev)) {
1460 /* The main vport index is relative first */
1461 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
1462 DP_ERR(p_hwfn, "No vport available!\n");
1463 goto out;
1464 }
86622ee7
YM		 1465 }
1466
dacd88d6 1467 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1468 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1469 continue;
1470 }
1471
dacd88d6
YM		 1472 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1473 IS_PF(cdev) ? true : false);
86622ee7 1474
dacd88d6
YM		 1475out:
1476 if (IS_PF(cdev) && p_ptt)
1477 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1478 }
1479}
1480
1481void qed_get_vport_stats(struct qed_dev *cdev,
1482 struct qed_eth_stats *stats)
1483{
1484 u32 i;
1485
1486 if (!cdev) {
1487 memset(stats, 0, sizeof(*stats));
1488 return;
1489 }
1490
1491 _qed_get_vport_stats(cdev, stats);
1492
1493 if (!cdev->reset_stats)
1494 return;
1495
1496 /* Reduce the statistics baseline */
1497 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1498 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1499}
1500
1501/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1502void qed_reset_vport_stats(struct qed_dev *cdev)
1503{
1504 int i;
1505
1506 for_each_hwfn(cdev, i) {
1507 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1508 struct eth_mstorm_per_queue_stat mstats;
1509 struct eth_ustorm_per_queue_stat ustats;
1510 struct eth_pstorm_per_queue_stat pstats;
dacd88d6
YM		 1511 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1512 : NULL;
86622ee7
YM		 1513 u32 addr = 0, len = 0;
1514
dacd88d6 1515 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1516 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1517 continue;
1518 }
1519
1520 memset(&mstats, 0, sizeof(mstats));
1521 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1522 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1523
1524 memset(&ustats, 0, sizeof(ustats));
1525 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1526 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1527
1528 memset(&pstats, 0, sizeof(pstats));
1529 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1530 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1531
dacd88d6
YM		 1532 if (IS_PF(cdev))
1533 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1534 }
1535
1536 /* PORT statistics are not necessarily reset, so we need to
1537 * read and create a baseline for future statistics.
1538 */
1539 if (!cdev->reset_stats)
1540 DP_INFO(cdev, "Reset stats not allocated\n");
1541 else
1542 _qed_get_vport_stats(cdev, cdev->reset_stats);
1543}
1544
25c089d7
YM		 1545static int qed_fill_eth_dev_info(struct qed_dev *cdev,
1546 struct qed_dev_eth_info *info)
1547{
1548 int i;
1549
1550 memset(info, 0, sizeof(*info));
1551
1552 info->num_tc = 1;
1553
1408cc1f
YM		 1554 if (IS_PF(cdev)) {
1555 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
1556 for_each_hwfn(cdev, i)
1557 info->num_queues +=
1558 FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
1559 if (cdev->int_params.fp_msix_cnt)
1560 info->num_queues =
1561 min_t(u8, info->num_queues,
1562 cdev->int_params.fp_msix_cnt);
1563 } else {
1564 info->num_queues = cdev->num_hwfns;
1565 }
1566
1567 info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN);
1568 ether_addr_copy(info->port_mac,
1569 cdev->hwfns[0].hw_info.hw_mac_addr);
25c089d7 1570 } else {
1408cc1f
YM		 1571 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
1572 if (cdev->num_hwfns > 1) {
1573 u8 queues = 0;
25c089d7 1574
1408cc1f
YM		 1575 qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
1576 info->num_queues += queues;
1577 }
1578
1579 qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
1580 &info->num_vlan_filters);
1581 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
1582 }
25c089d7
YM		 1583
1584 qed_fill_dev_info(cdev, &info->common);
1585
1408cc1f
YM		 1586 if (IS_VF(cdev))
1587 memset(info->common.hw_mac, 0, ETH_ALEN);
1588
25c089d7
YM		 1589 return 0;
1590}
1591
cc875c2e 1592static void qed_register_eth_ops(struct qed_dev *cdev,
1408cc1f 1593 struct qed_eth_cb_ops *ops, void *cookie)
cc875c2e 1594{
1408cc1f
YM		 1595 cdev->protocol_ops.eth = ops;
1596 cdev->ops_cookie = cookie;
1597
1598 /* For VF, we start bulletin reading */
1599 if (IS_VF(cdev))
1600 qed_vf_start_iov_wq(cdev);
cc875c2e
YM		 1601}
1602
cee4d264 1603static int qed_start_vport(struct qed_dev *cdev,
088c8618 1604 struct qed_start_vport_params *params)
cee4d264
MC		 1605{
1606 int rc, i;
1607
1608 for_each_hwfn(cdev, i) {
088c8618 1609 struct qed_sp_vport_start_params start = { 0 };
cee4d264
MC		 1610 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1611
088c8618
MC		 1612 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1613 QED_TPA_MODE_NONE;
1614 start.remove_inner_vlan = params->remove_inner_vlan;
1615 start.drop_ttl0 = params->drop_ttl0;
1616 start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1617 start.concrete_fid = p_hwfn->hw_info.concrete_fid;
1618 start.vport_id = params->vport_id;
1619 start.max_buffers_per_cqe = 16;
1620 start.mtu = params->mtu;
1621
1622 rc = qed_sp_vport_start(p_hwfn, &start);
cee4d264
MC		 1623 if (rc) {
1624 DP_ERR(cdev, "Failed to start VPORT\n");
1625 return rc;
1626 }
1627
1628 qed_hw_start_fastpath(p_hwfn);
1629
1630 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1631 "Started V-PORT %d with MTU %d\n",
088c8618 1632 start.vport_id, start.mtu);
cee4d264
MC		 1633 }
1634
9df2ed04
MC		 1635 qed_reset_vport_stats(cdev);
1636
cee4d264
MC		 1637 return 0;
1638}
1639
1640static int qed_stop_vport(struct qed_dev *cdev,
1641 u8 vport_id)
1642{
1643 int rc, i;
1644
1645 for_each_hwfn(cdev, i) {
1646 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1647
1648 rc = qed_sp_vport_stop(p_hwfn,
1649 p_hwfn->hw_info.opaque_fid,
1650 vport_id);
1651
1652 if (rc) {
1653 DP_ERR(cdev, "Failed to stop VPORT\n");
1654 return rc;
1655 }
1656 }
1657 return 0;
1658}
1659
1660static int qed_update_vport(struct qed_dev *cdev,
1661 struct qed_update_vport_params *params)
1662{
1663 struct qed_sp_vport_update_params sp_params;
1664 struct qed_rss_params sp_rss_params;
1665 int rc, i;
1666
1667 if (!cdev)
1668 return -ENODEV;
1669
1670 memset(&sp_params, 0, sizeof(sp_params));
1671 memset(&sp_rss_params, 0, sizeof(sp_rss_params));
1672
1673 /* Translate protocol params into sp params */
1674 sp_params.vport_id = params->vport_id;
1675 sp_params.update_vport_active_rx_flg =
1676 params->update_vport_active_flg;
1677 sp_params.update_vport_active_tx_flg =
1678 params->update_vport_active_flg;
1679 sp_params.vport_active_rx_flg = params->vport_active_flg;
1680 sp_params.vport_active_tx_flg = params->vport_active_flg;
3f9b4a69
YM		 1681 sp_params.accept_any_vlan = params->accept_any_vlan;
1682 sp_params.update_accept_any_vlan_flg =
1683 params->update_accept_any_vlan_flg;
cee4d264
MC		 1684
1685 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
1686 * We need to re-fix the rss values per engine for CMT.
1687 */
1688 if (cdev->num_hwfns > 1 && params->update_rss_flg) {
1689 struct qed_update_vport_rss_params *rss =
1690 &params->rss_params;
1691 int k, max = 0;
1692
1693 /* Find largest entry, since it's possible RSS needs to
1694 * be disabled [in case only 1 queue per-hwfn]
1695 */
1696 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1697 max = (max > rss->rss_ind_table[k]) ?
1698 max : rss->rss_ind_table[k];
1699
1700 /* Either fix RSS values or disable RSS */
1701 if (cdev->num_hwfns < max + 1) {
1702 int divisor = (max + cdev->num_hwfns - 1) /
1703 cdev->num_hwfns;
1704
1705 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1706 "CMT - fixing RSS values (modulo %02x)\n",
1707 divisor);
1708
1709 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1710 rss->rss_ind_table[k] =
1711 rss->rss_ind_table[k] % divisor;
1712 } else {
1713 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1714 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1715 params->update_rss_flg = 0;
1716 }
1717 }
1718
1719 /* Now, update the RSS configuration for actual configuration */
1720 if (params->update_rss_flg) {
1721 sp_rss_params.update_rss_config = 1;
1722 sp_rss_params.rss_enable = 1;
1723 sp_rss_params.update_rss_capabilities = 1;
1724 sp_rss_params.update_rss_ind_table = 1;
1725 sp_rss_params.update_rss_key = 1;
8c5ebd0c 1726 sp_rss_params.rss_caps = params->rss_params.rss_caps;
cee4d264
MC		 1727 sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
1728 memcpy(sp_rss_params.rss_ind_table,
1729 params->rss_params.rss_ind_table,
1730 QED_RSS_IND_TABLE_SIZE * sizeof(u16));
1731 memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
1732 QED_RSS_KEY_SIZE * sizeof(u32));
1733 }
1734 sp_params.rss_params = &sp_rss_params;
1735
1736 for_each_hwfn(cdev, i) {
1737 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1738
1739 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1740 rc = qed_sp_vport_update(p_hwfn, &sp_params,
1741 QED_SPQ_MODE_EBLOCK,
1742 NULL);
1743 if (rc) {
1744 DP_ERR(cdev, "Failed to update VPORT\n");
1745 return rc;
1746 }
1747
1748 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1749 "Updated V-PORT %d: active_flag %d [update %d]\n",
1750 params->vport_id, params->vport_active_flg,
1751 params->update_vport_active_flg);
1752 }
1753
1754 return 0;
1755}
1756
1757static int qed_start_rxq(struct qed_dev *cdev,
1758 struct qed_queue_start_common_params *params,
1759 u16 bd_max_bytes,
1760 dma_addr_t bd_chain_phys_addr,
1761 dma_addr_t cqe_pbl_addr,
1762 u16 cqe_pbl_size,
1763 void __iomem **pp_prod)
1764{
1765 int rc, hwfn_index;
1766 struct qed_hwfn *p_hwfn;
1767
1768 hwfn_index = params->rss_id % cdev->num_hwfns;
1769 p_hwfn = &cdev->hwfns[hwfn_index];
1770
1771 /* Fix queue ID in 100g mode */
1772 params->queue_id /= cdev->num_hwfns;
1773
1774 rc = qed_sp_eth_rx_queue_start(p_hwfn,
1775 p_hwfn->hw_info.opaque_fid,
1776 params,
1777 bd_max_bytes,
1778 bd_chain_phys_addr,
1779 cqe_pbl_addr,
1780 cqe_pbl_size,
1781 pp_prod);
1782
1783 if (rc) {
1784 DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
1785 return rc;
1786 }
1787
1788 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1789 "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1790 params->queue_id, params->rss_id, params->vport_id,
1791 params->sb);
1792
1793 return 0;
1794}
1795
1796static int qed_stop_rxq(struct qed_dev *cdev,
1797 struct qed_stop_rxq_params *params)
1798{
1799 int rc, hwfn_index;
1800 struct qed_hwfn *p_hwfn;
1801
1802 hwfn_index = params->rss_id % cdev->num_hwfns;
1803 p_hwfn = &cdev->hwfns[hwfn_index];
1804
1805 rc = qed_sp_eth_rx_queue_stop(p_hwfn,
1806 params->rx_queue_id / cdev->num_hwfns,
1807 params->eq_completion_only,
1808 false);
1809 if (rc) {
1810 DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
1811 return rc;
1812 }
1813
1814 return 0;
1815}
1816
1817static int qed_start_txq(struct qed_dev *cdev,
1818 struct qed_queue_start_common_params *p_params,
1819 dma_addr_t pbl_addr,
1820 u16 pbl_size,
1821 void __iomem **pp_doorbell)
1822{
1823 struct qed_hwfn *p_hwfn;
1824 int rc, hwfn_index;
1825
1826 hwfn_index = p_params->rss_id % cdev->num_hwfns;
1827 p_hwfn = &cdev->hwfns[hwfn_index];
1828
1829 /* Fix queue ID in 100g mode */
1830 p_params->queue_id /= cdev->num_hwfns;
1831
1832 rc = qed_sp_eth_tx_queue_start(p_hwfn,
1833 p_hwfn->hw_info.opaque_fid,
1834 p_params,
1835 pbl_addr,
1836 pbl_size,
1837 pp_doorbell);
1838
1839 if (rc) {
1840 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
1841 return rc;
1842 }
1843
1844 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1845 "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1846 p_params->queue_id, p_params->rss_id, p_params->vport_id,
1847 p_params->sb);
1848
1849 return 0;
1850}
1851
1852#define QED_HW_STOP_RETRY_LIMIT (10)
1853static int qed_fastpath_stop(struct qed_dev *cdev)
1854{
1855 qed_hw_stop_fastpath(cdev);
1856
1857 return 0;
1858}
1859
1860static int qed_stop_txq(struct qed_dev *cdev,
1861 struct qed_stop_txq_params *params)
1862{
1863 struct qed_hwfn *p_hwfn;
1864 int rc, hwfn_index;
1865
1866 hwfn_index = params->rss_id % cdev->num_hwfns;
1867 p_hwfn = &cdev->hwfns[hwfn_index];
1868
1869 rc = qed_sp_eth_tx_queue_stop(p_hwfn,
1870 params->tx_queue_id / cdev->num_hwfns);
1871 if (rc) {
1872 DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
1873 return rc;
1874 }
1875
1876 return 0;
1877}
1878
464f6645
MC		 1879static int qed_tunn_configure(struct qed_dev *cdev,
1880 struct qed_tunn_params *tunn_params)
1881{
1882 struct qed_tunn_update_params tunn_info;
1883 int i, rc;
1884
1408cc1f
YM		 1885 if (IS_VF(cdev))
1886 return 0;
1887
464f6645
MC		 1888 memset(&tunn_info, 0, sizeof(tunn_info));
1889 if (tunn_params->update_vxlan_port == 1) {
1890 tunn_info.update_vxlan_udp_port = 1;
1891 tunn_info.vxlan_udp_port = tunn_params->vxlan_port;
1892 }
1893
1894 if (tunn_params->update_geneve_port == 1) {
1895 tunn_info.update_geneve_udp_port = 1;
1896 tunn_info.geneve_udp_port = tunn_params->geneve_port;
1897 }
1898
1899 for_each_hwfn(cdev, i) {
1900 struct qed_hwfn *hwfn = &cdev->hwfns[i];
1901
1902 rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
1903 QED_SPQ_MODE_EBLOCK, NULL);
1904
1905 if (rc)
1906 return rc;
1907 }
1908
1909 return 0;
1910}
1911
cee4d264
MC		 1912static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
1913 enum qed_filter_rx_mode_type type)
1914{
1915 struct qed_filter_accept_flags accept_flags;
1916
1917 memset(&accept_flags, 0, sizeof(accept_flags));
1918
1919 accept_flags.update_rx_mode_config = 1;
1920 accept_flags.update_tx_mode_config = 1;
1921 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
1922 QED_ACCEPT_MCAST_MATCHED |
1923 QED_ACCEPT_BCAST;
1924 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
1925 QED_ACCEPT_MCAST_MATCHED |
1926 QED_ACCEPT_BCAST;
1927
1928 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
1929 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
1930 QED_ACCEPT_MCAST_UNMATCHED;
1931 else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
1932 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
1933
3f9b4a69 1934 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 1935 QED_SPQ_MODE_CB, NULL);
1936}
1937
1938static int qed_configure_filter_ucast(struct qed_dev *cdev,
1939 struct qed_filter_ucast_params *params)
1940{
1941 struct qed_filter_ucast ucast;
1942
1943 if (!params->vlan_valid && !params->mac_valid) {
1944 DP_NOTICE(
1945 cdev,
1946 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
1947 return -EINVAL;
1948 }
1949
1950 memset(&ucast, 0, sizeof(ucast));
1951 switch (params->type) {
1952 case QED_FILTER_XCAST_TYPE_ADD:
1953 ucast.opcode = QED_FILTER_ADD;
1954 break;
1955 case QED_FILTER_XCAST_TYPE_DEL:
1956 ucast.opcode = QED_FILTER_REMOVE;
1957 break;
1958 case QED_FILTER_XCAST_TYPE_REPLACE:
1959 ucast.opcode = QED_FILTER_REPLACE;
1960 break;
1961 default:
1962 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
1963 params->type);
1964 }
1965
1966 if (params->vlan_valid && params->mac_valid) {
1967 ucast.type = QED_FILTER_MAC_VLAN;
1968 ether_addr_copy(ucast.mac, params->mac);
1969 ucast.vlan = params->vlan;
1970 } else if (params->mac_valid) {
1971 ucast.type = QED_FILTER_MAC;
1972 ether_addr_copy(ucast.mac, params->mac);
1973 } else {
1974 ucast.type = QED_FILTER_VLAN;
1975 ucast.vlan = params->vlan;
1976 }
1977
1978 ucast.is_rx_filter = true;
1979 ucast.is_tx_filter = true;
1980
1981 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
1982}
1983
1984static int qed_configure_filter_mcast(struct qed_dev *cdev,
1985 struct qed_filter_mcast_params *params)
1986{
1987 struct qed_filter_mcast mcast;
1988 int i;
1989
1990 memset(&mcast, 0, sizeof(mcast));
1991 switch (params->type) {
1992 case QED_FILTER_XCAST_TYPE_ADD:
1993 mcast.opcode = QED_FILTER_ADD;
1994 break;
1995 case QED_FILTER_XCAST_TYPE_DEL:
1996 mcast.opcode = QED_FILTER_REMOVE;
1997 break;
1998 default:
1999 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2000 params->type);
2001 }
2002
2003 mcast.num_mc_addrs = params->num;
2004 for (i = 0; i < mcast.num_mc_addrs; i++)
2005 ether_addr_copy(mcast.mac[i], params->mac[i]);
2006
2007 return qed_filter_mcast_cmd(cdev, &mcast,
2008 QED_SPQ_MODE_CB, NULL);
2009}
2010
2011static int qed_configure_filter(struct qed_dev *cdev,
2012 struct qed_filter_params *params)
2013{
2014 enum qed_filter_rx_mode_type accept_flags;
2015
2016 switch (params->type) {
2017 case QED_FILTER_TYPE_UCAST:
2018 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2019 case QED_FILTER_TYPE_MCAST:
2020 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2021 case QED_FILTER_TYPE_RX_MODE:
2022 accept_flags = params->filter.accept_flags;
2023 return qed_configure_filter_rx_mode(cdev, accept_flags);
2024 default:
2025 DP_NOTICE(cdev, "Unknown filter type %d\n",
2026 (int)params->type);
2027 return -EINVAL;
2028 }
2029}
2030
2031static int qed_fp_cqe_completion(struct qed_dev *dev,
2032 u8 rss_id,
2033 struct eth_slow_path_rx_cqe *cqe)
2034{
2035 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2036 cqe);
2037}
2038
0b55e27d
YM		 2039#ifdef CONFIG_QED_SRIOV
2040extern const struct qed_iov_hv_ops qed_iov_ops_pass;
2041#endif
2042
25c089d7
YM		 2043static const struct qed_eth_ops qed_eth_ops_pass = {
2044 .common = &qed_common_ops_pass,
0b55e27d
YM		 2045#ifdef CONFIG_QED_SRIOV
2046 .iov = &qed_iov_ops_pass,
2047#endif
25c089d7 2048 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 2049 .register_ops = &qed_register_eth_ops,
cee4d264
MC		 2050 .vport_start = &qed_start_vport,
2051 .vport_stop = &qed_stop_vport,
2052 .vport_update = &qed_update_vport,
2053 .q_rx_start = &qed_start_rxq,
2054 .q_rx_stop = &qed_stop_rxq,
2055 .q_tx_start = &qed_start_txq,
2056 .q_tx_stop = &qed_stop_txq,
2057 .filter_config = &qed_configure_filter,
2058 .fastpath_stop = &qed_fastpath_stop,
2059 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 2060 .get_vport_stats = &qed_get_vport_stats,
464f6645 2061 .tunn_config = &qed_tunn_configure,
25c089d7
YM		 2062};
2063
95114344 2064const struct qed_eth_ops *qed_get_eth_ops(void)
25c089d7 2065{
25c089d7
YM		 2066 return &qed_eth_ops_pass;
2067}
2068EXPORT_SYMBOL(qed_get_eth_ops);
2069
2070void qed_put_eth_ops(void)
2071{
2072 /* TODO - reference count for module? */
2073}
2074EXPORT_SYMBOL(qed_put_eth_ops);
Linux kernel - Deliverables
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