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net/hsr: Added support for HSR v1
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
CommitLineData
25c089d7
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <asm/param.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/etherdevice.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
20#include <linux/stddef.h>
21#include <linux/string.h>
22#include <linux/version.h>
23#include <linux/workqueue.h>
24#include <linux/bitops.h>
25#include <linux/bug.h>
26#include "qed.h"
27#include <linux/qed/qed_chain.h>
28#include "qed_cxt.h"
29#include "qed_dev_api.h"
30#include <linux/qed/qed_eth_if.h>
31#include "qed_hsi.h"
32#include "qed_hw.h"
33#include "qed_int.h"
86622ee7 34#include "qed_mcp.h"
25c089d7
YM		 35#include "qed_reg_addr.h"
36#include "qed_sp.h"
37
cee4d264
MC		 38struct qed_rss_params {
39 u8 update_rss_config;
40 u8 rss_enable;
41 u8 rss_eng_id;
42 u8 update_rss_capabilities;
43 u8 update_rss_ind_table;
44 u8 update_rss_key;
45 u8 rss_caps;
46 u8 rss_table_size_log;
47 u16 rss_ind_table[QED_RSS_IND_TABLE_SIZE];
48 u32 rss_key[QED_RSS_KEY_SIZE];
49};
50
51enum qed_filter_opcode {
52 QED_FILTER_ADD,
53 QED_FILTER_REMOVE,
54 QED_FILTER_MOVE,
55 QED_FILTER_REPLACE, /* Delete all MACs and add new one instead */
56 QED_FILTER_FLUSH, /* Removes all filters */
57};
58
59enum qed_filter_ucast_type {
60 QED_FILTER_MAC,
61 QED_FILTER_VLAN,
62 QED_FILTER_MAC_VLAN,
63 QED_FILTER_INNER_MAC,
64 QED_FILTER_INNER_VLAN,
65 QED_FILTER_INNER_PAIR,
66 QED_FILTER_INNER_MAC_VNI_PAIR,
67 QED_FILTER_MAC_VNI_PAIR,
68 QED_FILTER_VNI,
69};
70
71struct qed_filter_ucast {
72 enum qed_filter_opcode opcode;
73 enum qed_filter_ucast_type type;
74 u8 is_rx_filter;
75 u8 is_tx_filter;
76 u8 vport_to_add_to;
77 u8 vport_to_remove_from;
78 unsigned char mac[ETH_ALEN];
79 u8 assert_on_error;
80 u16 vlan;
81 u32 vni;
82};
83
84struct qed_filter_mcast {
85 /* MOVE is not supported for multicast */
86 enum qed_filter_opcode opcode;
87 u8 vport_to_add_to;
88 u8 vport_to_remove_from;
89 u8 num_mc_addrs;
90#define QED_MAX_MC_ADDRS 64
91 unsigned char mac[QED_MAX_MC_ADDRS][ETH_ALEN];
92};
93
94struct qed_filter_accept_flags {
95 u8 update_rx_mode_config;
96 u8 update_tx_mode_config;
97 u8 rx_accept_filter;
98 u8 tx_accept_filter;
99#define QED_ACCEPT_NONE 0x01
100#define QED_ACCEPT_UCAST_MATCHED 0x02
101#define QED_ACCEPT_UCAST_UNMATCHED 0x04
102#define QED_ACCEPT_MCAST_MATCHED 0x08
103#define QED_ACCEPT_MCAST_UNMATCHED 0x10
104#define QED_ACCEPT_BCAST 0x20
105};
106
107struct qed_sp_vport_update_params {
108 u16 opaque_fid;
109 u8 vport_id;
110 u8 update_vport_active_rx_flg;
111 u8 vport_active_rx_flg;
112 u8 update_vport_active_tx_flg;
113 u8 vport_active_tx_flg;
114 u8 update_approx_mcast_flg;
3f9b4a69
YM		 115 u8 update_accept_any_vlan_flg;
116 u8 accept_any_vlan;
cee4d264
MC		 117 unsigned long bins[8];
118 struct qed_rss_params *rss_params;
119 struct qed_filter_accept_flags accept_flags;
120};
121
088c8618
MC		 122enum qed_tpa_mode {
123 QED_TPA_MODE_NONE,
124 QED_TPA_MODE_UNUSED,
125 QED_TPA_MODE_GRO,
126 QED_TPA_MODE_MAX
127};
128
129struct qed_sp_vport_start_params {
130 enum qed_tpa_mode tpa_mode;
131 bool remove_inner_vlan;
132 bool drop_ttl0;
133 u8 max_buffers_per_cqe;
134 u32 concrete_fid;
135 u16 opaque_fid;
136 u8 vport_id;
137 u16 mtu;
138};
139
cee4d264
MC		 140#define QED_MAX_SGES_NUM 16
141#define CRC32_POLY 0x1edc6f41
142
143static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
088c8618 144 struct qed_sp_vport_start_params *p_params)
cee4d264 145{
cee4d264
MC		 146 struct vport_start_ramrod_data *p_ramrod = NULL;
147 struct qed_spq_entry *p_ent = NULL;
06f56b81 148 struct qed_sp_init_data init_data;
cee4d264
MC		 149 int rc = -EINVAL;
150 u16 rx_mode = 0;
151 u8 abs_vport_id = 0;
152
088c8618 153 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
cee4d264
MC		 154 if (rc != 0)
155 return rc;
156
06f56b81
YM		 157 memset(&init_data, 0, sizeof(init_data));
158 init_data.cid = qed_spq_get_cid(p_hwfn);
088c8618 159 init_data.opaque_fid = p_params->opaque_fid;
06f56b81 160 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 161
162 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 163 ETH_RAMROD_VPORT_START,
06f56b81 164 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 165 if (rc)
166 return rc;
167
168 p_ramrod = &p_ent->ramrod.vport_start;
169 p_ramrod->vport_id = abs_vport_id;
170
088c8618
MC		 171 p_ramrod->mtu = cpu_to_le16(p_params->mtu);
172 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
173 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
cee4d264
MC		 174
175 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
176 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
177
178 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
179
180 /* TPA related fields */
181 memset(&p_ramrod->tpa_param, 0,
182 sizeof(struct eth_vport_tpa_param));
183
088c8618
MC		 184 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
185
186 switch (p_params->tpa_mode) {
187 case QED_TPA_MODE_GRO:
188 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
189 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
190 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
191 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
192 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
193 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
194 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
195 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
196 break;
197 default:
198 break;
199 }
200
cee4d264
MC		 201 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
202 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
088c8618 203 p_params->concrete_fid);
cee4d264
MC		 204
205 return qed_spq_post(p_hwfn, p_ent, NULL);
206}
207
208static int
209qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
210 struct vport_update_ramrod_data *p_ramrod,
211 struct qed_rss_params *p_params)
212{
213 struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
214 u16 abs_l2_queue = 0, capabilities = 0;
215 int rc = 0, i;
216
217 if (!p_params) {
218 p_ramrod->common.update_rss_flg = 0;
219 return rc;
220 }
221
222 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
223 ETH_RSS_IND_TABLE_ENTRIES_NUM);
224
225 rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
226 if (rc)
227 return rc;
228
229 p_ramrod->common.update_rss_flg = p_params->update_rss_config;
230 rss->update_rss_capabilities = p_params->update_rss_capabilities;
231 rss->update_rss_ind_table = p_params->update_rss_ind_table;
232 rss->update_rss_key = p_params->update_rss_key;
233
234 rss->rss_mode = p_params->rss_enable ?
235 ETH_VPORT_RSS_MODE_REGULAR :
236 ETH_VPORT_RSS_MODE_DISABLED;
237
238 SET_FIELD(capabilities,
239 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
240 !!(p_params->rss_caps & QED_RSS_IPV4));
241 SET_FIELD(capabilities,
242 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
243 !!(p_params->rss_caps & QED_RSS_IPV6));
244 SET_FIELD(capabilities,
245 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
246 !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
247 SET_FIELD(capabilities,
248 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
249 !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
250 SET_FIELD(capabilities,
251 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
252 !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
253 SET_FIELD(capabilities,
254 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
255 !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
256 rss->tbl_size = p_params->rss_table_size_log;
257
258 rss->capabilities = cpu_to_le16(capabilities);
259
260 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
261 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
262 p_ramrod->common.update_rss_flg,
263 rss->rss_mode, rss->update_rss_capabilities,
264 capabilities, rss->update_rss_ind_table,
265 rss->update_rss_key);
266
267 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
268 rc = qed_fw_l2_queue(p_hwfn,
269 (u8)p_params->rss_ind_table[i],
270 &abs_l2_queue);
271 if (rc)
272 return rc;
273
274 rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
275 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
276 i, rss->indirection_table[i]);
277 }
278
279 for (i = 0; i < 10; i++)
280 rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
281
282 return rc;
283}
284
285static void
286qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
287 struct vport_update_ramrod_data *p_ramrod,
288 struct qed_filter_accept_flags accept_flags)
289{
290 p_ramrod->common.update_rx_mode_flg =
291 accept_flags.update_rx_mode_config;
292
293 p_ramrod->common.update_tx_mode_flg =
294 accept_flags.update_tx_mode_config;
295
296 /* Set Rx mode accept flags */
297 if (p_ramrod->common.update_rx_mode_flg) {
298 u8 accept_filter = accept_flags.rx_accept_filter;
299 u16 state = 0;
300
301 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
302 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
303 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
304
305 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
306 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
307
308 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
309 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
310 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
311
312 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
313 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
314 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
315
316 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
317 !!(accept_filter & QED_ACCEPT_BCAST));
318
319 p_ramrod->rx_mode.state = cpu_to_le16(state);
320 DP_VERBOSE(p_hwfn, QED_MSG_SP,
321 "p_ramrod->rx_mode.state = 0x%x\n", state);
322 }
323
324 /* Set Tx mode accept flags */
325 if (p_ramrod->common.update_tx_mode_flg) {
326 u8 accept_filter = accept_flags.tx_accept_filter;
327 u16 state = 0;
328
329 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
330 !!(accept_filter & QED_ACCEPT_NONE));
331
332 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
333 (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
334 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
335
336 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
337 !!(accept_filter & QED_ACCEPT_NONE));
338
339 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
340 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
341 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
342
343 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
344 !!(accept_filter & QED_ACCEPT_BCAST));
345
346 p_ramrod->tx_mode.state = cpu_to_le16(state);
347 DP_VERBOSE(p_hwfn, QED_MSG_SP,
348 "p_ramrod->tx_mode.state = 0x%x\n", state);
349 }
350}
351
352static void
353qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
354 struct vport_update_ramrod_data *p_ramrod,
355 struct qed_sp_vport_update_params *p_params)
356{
357 int i;
358
359 memset(&p_ramrod->approx_mcast.bins, 0,
360 sizeof(p_ramrod->approx_mcast.bins));
361
362 if (p_params->update_approx_mcast_flg) {
363 p_ramrod->common.update_approx_mcast_flg = 1;
364 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
365 u32 *p_bins = (u32 *)p_params->bins;
366 __le32 val = cpu_to_le32(p_bins[i]);
367
368 p_ramrod->approx_mcast.bins[i] = val;
369 }
370 }
371}
372
373static int
374qed_sp_vport_update(struct qed_hwfn *p_hwfn,
375 struct qed_sp_vport_update_params *p_params,
376 enum spq_mode comp_mode,
377 struct qed_spq_comp_cb *p_comp_data)
378{
379 struct qed_rss_params *p_rss_params = p_params->rss_params;
380 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 381 struct qed_sp_init_data init_data;
cee4d264
MC		 382 struct vport_update_ramrod_data *p_ramrod = NULL;
383 struct qed_spq_entry *p_ent = NULL;
384 u8 abs_vport_id = 0;
385 int rc = -EINVAL;
386
387 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
388 if (rc != 0)
389 return rc;
390
06f56b81
YM		 391 memset(&init_data, 0, sizeof(init_data));
392 init_data.cid = qed_spq_get_cid(p_hwfn);
393 init_data.opaque_fid = p_params->opaque_fid;
394 init_data.comp_mode = comp_mode;
395 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 396
397 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 398 ETH_RAMROD_VPORT_UPDATE,
06f56b81 399 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 400 if (rc)
401 return rc;
402
403 /* Copy input params to ramrod according to FW struct */
404 p_ramrod = &p_ent->ramrod.vport_update;
405 p_cmn = &p_ramrod->common;
406
407 p_cmn->vport_id = abs_vport_id;
408 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
409 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
410 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
411 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69
YM		 412 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
413 p_cmn->update_accept_any_vlan_flg =
414 p_params->update_accept_any_vlan_flg;
cee4d264
MC		 415 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
416 if (rc) {
417 /* Return spq entry which is taken in qed_sp_init_request()*/
418 qed_spq_return_entry(p_hwfn, p_ent);
419 return rc;
420 }
421
422 /* Update mcast bins for VFs, PF doesn't use this functionality */
423 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
424
425 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
426 return qed_spq_post(p_hwfn, p_ent, NULL);
427}
428
429static int qed_sp_vport_stop(struct qed_hwfn *p_hwfn,
430 u16 opaque_fid,
431 u8 vport_id)
432{
cee4d264 433 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 434 struct qed_sp_init_data init_data;
cee4d264
MC		 435 struct qed_spq_entry *p_ent;
436 u8 abs_vport_id = 0;
437 int rc;
438
439 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
440 if (rc != 0)
441 return rc;
442
06f56b81
YM		 443 memset(&init_data, 0, sizeof(init_data));
444 init_data.cid = qed_spq_get_cid(p_hwfn);
445 init_data.opaque_fid = opaque_fid;
446 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 447
448 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 449 ETH_RAMROD_VPORT_STOP,
06f56b81 450 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 451 if (rc)
452 return rc;
453
454 p_ramrod = &p_ent->ramrod.vport_stop;
455 p_ramrod->vport_id = abs_vport_id;
456
457 return qed_spq_post(p_hwfn, p_ent, NULL);
458}
459
460static int qed_filter_accept_cmd(struct qed_dev *cdev,
461 u8 vport,
462 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 463 u8 update_accept_any_vlan,
464 u8 accept_any_vlan,
465 enum spq_mode comp_mode,
466 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 467{
468 struct qed_sp_vport_update_params vport_update_params;
469 int i, rc;
470
471 /* Prepare and send the vport rx_mode change */
472 memset(&vport_update_params, 0, sizeof(vport_update_params));
473 vport_update_params.vport_id = vport;
474 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 475 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
476 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 477
478 for_each_hwfn(cdev, i) {
479 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
480
481 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
482
483 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
484 comp_mode, p_comp_data);
485 if (rc != 0) {
486 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
487 return rc;
488 }
489
490 DP_VERBOSE(p_hwfn, QED_MSG_SP,
491 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
492 accept_flags.rx_accept_filter,
493 accept_flags.tx_accept_filter);
3f9b4a69
YM		 494 if (update_accept_any_vlan)
495 DP_VERBOSE(p_hwfn, QED_MSG_SP,
496 "accept_any_vlan=%d configured\n",
497 accept_any_vlan);
cee4d264
MC		 498 }
499
500 return 0;
501}
502
503static int qed_sp_release_queue_cid(
504 struct qed_hwfn *p_hwfn,
505 struct qed_hw_cid_data *p_cid_data)
506{
507 if (!p_cid_data->b_cid_allocated)
508 return 0;
509
510 qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
511
512 p_cid_data->b_cid_allocated = false;
513
514 return 0;
515}
516
517static int
518qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
519 u16 opaque_fid,
520 u32 cid,
521 struct qed_queue_start_common_params *params,
522 u8 stats_id,
523 u16 bd_max_bytes,
524 dma_addr_t bd_chain_phys_addr,
525 dma_addr_t cqe_pbl_addr,
526 u16 cqe_pbl_size)
527{
528 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 529 struct qed_spq_entry *p_ent = NULL;
06f56b81 530 struct qed_sp_init_data init_data;
cee4d264
MC		 531 struct qed_hw_cid_data *p_rx_cid;
532 u16 abs_rx_q_id = 0;
533 u8 abs_vport_id = 0;
534 int rc = -EINVAL;
535
536 /* Store information for the stop */
537 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
538 p_rx_cid->cid = cid;
539 p_rx_cid->opaque_fid = opaque_fid;
540 p_rx_cid->vport_id = params->vport_id;
541
542 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id);
543 if (rc != 0)
544 return rc;
545
546 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id);
547 if (rc != 0)
548 return rc;
549
550 DP_VERBOSE(p_hwfn, QED_MSG_SP,
551 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
552 opaque_fid, cid, params->queue_id, params->vport_id,
553 params->sb);
554
06f56b81
YM		 555 /* Get SPQ entry */
556 memset(&init_data, 0, sizeof(init_data));
557 init_data.cid = cid;
558 init_data.opaque_fid = opaque_fid;
559 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 560
561 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 562 ETH_RAMROD_RX_QUEUE_START,
06f56b81 563 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 564 if (rc)
565 return rc;
566
567 p_ramrod = &p_ent->ramrod.rx_queue_start;
568
569 p_ramrod->sb_id = cpu_to_le16(params->sb);
570 p_ramrod->sb_index = params->sb_idx;
571 p_ramrod->vport_id = abs_vport_id;
572 p_ramrod->stats_counter_id = stats_id;
573 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
574 p_ramrod->complete_cqe_flg = 0;
575 p_ramrod->complete_event_flg = 1;
576
577 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
94494598 578 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
cee4d264
MC		 579
580 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
94494598 581 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
cee4d264
MC		 582
583 rc = qed_spq_post(p_hwfn, p_ent, NULL);
584
585 return rc;
586}
587
588static int
589qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
590 u16 opaque_fid,
591 struct qed_queue_start_common_params *params,
592 u16 bd_max_bytes,
593 dma_addr_t bd_chain_phys_addr,
594 dma_addr_t cqe_pbl_addr,
595 u16 cqe_pbl_size,
596 void __iomem **pp_prod)
597{
598 struct qed_hw_cid_data *p_rx_cid;
599 u64 init_prod_val = 0;
600 u16 abs_l2_queue = 0;
601 u8 abs_stats_id = 0;
602 int rc;
603
604 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue);
605 if (rc != 0)
606 return rc;
607
608 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id);
609 if (rc != 0)
610 return rc;
611
612 *pp_prod = (u8 __iomem *)p_hwfn->regview +
613 GTT_BAR0_MAP_REG_MSDM_RAM +
614 MSTORM_PRODS_OFFSET(abs_l2_queue);
615
616 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
617 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
618 (u32 *)(&init_prod_val));
619
620 /* Allocate a CID for the queue */
621 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
622 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
623 &p_rx_cid->cid);
624 if (rc) {
625 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
626 return rc;
627 }
628 p_rx_cid->b_cid_allocated = true;
629
630 rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
631 opaque_fid,
632 p_rx_cid->cid,
633 params,
634 abs_stats_id,
635 bd_max_bytes,
636 bd_chain_phys_addr,
637 cqe_pbl_addr,
638 cqe_pbl_size);
639
640 if (rc != 0)
641 qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
642
643 return rc;
644}
645
646static int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
647 u16 rx_queue_id,
648 bool eq_completion_only,
649 bool cqe_completion)
650{
651 struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
652 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 653 struct qed_spq_entry *p_ent = NULL;
06f56b81 654 struct qed_sp_init_data init_data;
cee4d264
MC		 655 u16 abs_rx_q_id = 0;
656 int rc = -EINVAL;
657
06f56b81
YM		 658 /* Get SPQ entry */
659 memset(&init_data, 0, sizeof(init_data));
660 init_data.cid = p_rx_cid->cid;
661 init_data.opaque_fid = p_rx_cid->opaque_fid;
662 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 663
664 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 665 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 666 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 667 if (rc)
668 return rc;
669
670 p_ramrod = &p_ent->ramrod.rx_queue_stop;
671
672 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
673 qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
674 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
675
676 /* Cleaning the queue requires the completion to arrive there.
677 * In addition, VFs require the answer to come as eqe to PF.
678 */
679 p_ramrod->complete_cqe_flg =
680 (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
681 !eq_completion_only) || cqe_completion;
682 p_ramrod->complete_event_flg =
683 !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
684 eq_completion_only;
685
686 rc = qed_spq_post(p_hwfn, p_ent, NULL);
687 if (rc)
688 return rc;
689
690 return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
691}
692
693static int
694qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
695 u16 opaque_fid,
696 u32 cid,
697 struct qed_queue_start_common_params *p_params,
698 u8 stats_id,
699 dma_addr_t pbl_addr,
700 u16 pbl_size,
701 union qed_qm_pq_params *p_pq_params)
702{
703 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 704 struct qed_spq_entry *p_ent = NULL;
06f56b81 705 struct qed_sp_init_data init_data;
cee4d264
MC		 706 struct qed_hw_cid_data *p_tx_cid;
707 u8 abs_vport_id;
708 int rc = -EINVAL;
709 u16 pq_id;
710
711 /* Store information for the stop */
712 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
713 p_tx_cid->cid = cid;
714 p_tx_cid->opaque_fid = opaque_fid;
715
716 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
717 if (rc)
718 return rc;
719
06f56b81
YM		 720 /* Get SPQ entry */
721 memset(&init_data, 0, sizeof(init_data));
722 init_data.cid = cid;
723 init_data.opaque_fid = opaque_fid;
724 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 725
06f56b81 726 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 727 ETH_RAMROD_TX_QUEUE_START,
06f56b81 728 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 729 if (rc)
730 return rc;
731
732 p_ramrod = &p_ent->ramrod.tx_queue_start;
733 p_ramrod->vport_id = abs_vport_id;
734
735 p_ramrod->sb_id = cpu_to_le16(p_params->sb);
736 p_ramrod->sb_index = p_params->sb_idx;
737 p_ramrod->stats_counter_id = stats_id;
cee4d264
MC		 738
739 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
94494598 740 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
cee4d264
MC		 741
742 pq_id = qed_get_qm_pq(p_hwfn,
743 PROTOCOLID_ETH,
744 p_pq_params);
745 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
746
747 return qed_spq_post(p_hwfn, p_ent, NULL);
748}
749
750static int
751qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
752 u16 opaque_fid,
753 struct qed_queue_start_common_params *p_params,
754 dma_addr_t pbl_addr,
755 u16 pbl_size,
756 void __iomem **pp_doorbell)
757{
758 struct qed_hw_cid_data *p_tx_cid;
759 union qed_qm_pq_params pq_params;
760 u8 abs_stats_id = 0;
761 int rc;
762
763 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
764 if (rc)
765 return rc;
766
767 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
768 memset(p_tx_cid, 0, sizeof(*p_tx_cid));
769 memset(&pq_params, 0, sizeof(pq_params));
770
771 /* Allocate a CID for the queue */
772 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
773 &p_tx_cid->cid);
774 if (rc) {
775 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
776 return rc;
777 }
778 p_tx_cid->b_cid_allocated = true;
779
780 DP_VERBOSE(p_hwfn, QED_MSG_SP,
781 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
782 opaque_fid, p_tx_cid->cid,
783 p_params->queue_id, p_params->vport_id, p_params->sb);
784
785 rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
786 opaque_fid,
787 p_tx_cid->cid,
788 p_params,
789 abs_stats_id,
790 pbl_addr,
791 pbl_size,
792 &pq_params);
793
794 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
795 qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
796
797 if (rc)
798 qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
799
800 return rc;
801}
802
803static int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn,
804 u16 tx_queue_id)
805{
806 struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
cee4d264 807 struct qed_spq_entry *p_ent = NULL;
06f56b81 808 struct qed_sp_init_data init_data;
cee4d264
MC		 809 int rc = -EINVAL;
810
06f56b81
YM		 811 /* Get SPQ entry */
812 memset(&init_data, 0, sizeof(init_data));
813 init_data.cid = p_tx_cid->cid;
814 init_data.opaque_fid = p_tx_cid->opaque_fid;
815 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 816
817 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 818 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 819 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 820 if (rc)
821 return rc;
822
823 rc = qed_spq_post(p_hwfn, p_ent, NULL);
824 if (rc)
825 return rc;
826
827 return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
828}
829
830static enum eth_filter_action
831qed_filter_action(enum qed_filter_opcode opcode)
832{
833 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
834
835 switch (opcode) {
836 case QED_FILTER_ADD:
837 action = ETH_FILTER_ACTION_ADD;
838 break;
839 case QED_FILTER_REMOVE:
840 action = ETH_FILTER_ACTION_REMOVE;
841 break;
cee4d264 842 case QED_FILTER_FLUSH:
fc48b7a6 843 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 844 break;
845 default:
846 action = MAX_ETH_FILTER_ACTION;
847 }
848
849 return action;
850}
851
852static void qed_set_fw_mac_addr(__le16 *fw_msb,
853 __le16 *fw_mid,
854 __le16 *fw_lsb,
855 u8 *mac)
856{
857 ((u8 *)fw_msb)[0] = mac[1];
858 ((u8 *)fw_msb)[1] = mac[0];
859 ((u8 *)fw_mid)[0] = mac[3];
860 ((u8 *)fw_mid)[1] = mac[2];
861 ((u8 *)fw_lsb)[0] = mac[5];
862 ((u8 *)fw_lsb)[1] = mac[4];
863}
864
865static int
866qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
867 u16 opaque_fid,
868 struct qed_filter_ucast *p_filter_cmd,
869 struct vport_filter_update_ramrod_data **pp_ramrod,
870 struct qed_spq_entry **pp_ent,
871 enum spq_mode comp_mode,
872 struct qed_spq_comp_cb *p_comp_data)
873{
874 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
875 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 876 struct eth_filter_cmd *p_first_filter;
877 struct eth_filter_cmd *p_second_filter;
06f56b81 878 struct qed_sp_init_data init_data;
cee4d264
MC		 879 enum eth_filter_action action;
880 int rc;
881
882 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
883 &vport_to_remove_from);
884 if (rc)
885 return rc;
886
887 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
888 &vport_to_add_to);
889 if (rc)
890 return rc;
891
06f56b81
YM		 892 /* Get SPQ entry */
893 memset(&init_data, 0, sizeof(init_data));
894 init_data.cid = qed_spq_get_cid(p_hwfn);
895 init_data.opaque_fid = opaque_fid;
896 init_data.comp_mode = comp_mode;
897 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 898
899 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 900 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 901 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 902 if (rc)
903 return rc;
904
905 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
906 p_ramrod = *pp_ramrod;
907 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
908 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
909
910 switch (p_filter_cmd->opcode) {
fc48b7a6 911 case QED_FILTER_REPLACE:
cee4d264
MC		 912 case QED_FILTER_MOVE:
913 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
914 default:
915 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
916 }
917
918 p_first_filter = &p_ramrod->filter_cmds[0];
919 p_second_filter = &p_ramrod->filter_cmds[1];
920
921 switch (p_filter_cmd->type) {
922 case QED_FILTER_MAC:
923 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
924 case QED_FILTER_VLAN:
925 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
926 case QED_FILTER_MAC_VLAN:
927 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
928 case QED_FILTER_INNER_MAC:
929 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
930 case QED_FILTER_INNER_VLAN:
931 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
932 case QED_FILTER_INNER_PAIR:
933 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
934 case QED_FILTER_INNER_MAC_VNI_PAIR:
935 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
936 break;
937 case QED_FILTER_MAC_VNI_PAIR:
938 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
939 case QED_FILTER_VNI:
940 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
941 }
942
943 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
944 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
945 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
946 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
947 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
948 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
949 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
950 &p_first_filter->mac_mid,
951 &p_first_filter->mac_lsb,
952 (u8 *)p_filter_cmd->mac);
953 }
954
955 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
956 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
957 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
958 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
959 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
960
961 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
962 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
963 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
964 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
965
966 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
967 p_second_filter->type = p_first_filter->type;
968 p_second_filter->mac_msb = p_first_filter->mac_msb;
969 p_second_filter->mac_mid = p_first_filter->mac_mid;
970 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
971 p_second_filter->vlan_id = p_first_filter->vlan_id;
972 p_second_filter->vni = p_first_filter->vni;
973
974 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
975
976 p_first_filter->vport_id = vport_to_remove_from;
977
978 p_second_filter->action = ETH_FILTER_ACTION_ADD;
979 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 980 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
981 p_first_filter->vport_id = vport_to_add_to;
982 memcpy(p_second_filter, p_first_filter,
983 sizeof(*p_second_filter));
984 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
985 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 986 } else {
987 action = qed_filter_action(p_filter_cmd->opcode);
988
989 if (action == MAX_ETH_FILTER_ACTION) {
990 DP_NOTICE(p_hwfn,
991 "%d is not supported yet\n",
992 p_filter_cmd->opcode);
993 return -EINVAL;
994 }
995
996 p_first_filter->action = action;
997 p_first_filter->vport_id = (p_filter_cmd->opcode ==
998 QED_FILTER_REMOVE) ?
999 vport_to_remove_from :
1000 vport_to_add_to;
1001 }
1002
1003 return 0;
1004}
1005
1006static int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1007 u16 opaque_fid,
1008 struct qed_filter_ucast *p_filter_cmd,
1009 enum spq_mode comp_mode,
1010 struct qed_spq_comp_cb *p_comp_data)
1011{
1012 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
1013 struct qed_spq_entry *p_ent = NULL;
1014 struct eth_filter_cmd_header *p_header;
1015 int rc;
1016
1017 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1018 &p_ramrod, &p_ent,
1019 comp_mode, p_comp_data);
1020 if (rc != 0) {
1021 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1022 return rc;
1023 }
1024 p_header = &p_ramrod->filter_cmd_hdr;
1025 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1026
1027 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1028 if (rc != 0) {
1029 DP_ERR(p_hwfn,
1030 "Unicast filter ADD command failed %d\n",
1031 rc);
1032 return rc;
1033 }
1034
1035 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1036 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1037 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1038 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1039 "REMOVE" :
1040 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1041 "MOVE" : "REPLACE")),
1042 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1043 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1044 "VLAN" : "MAC & VLAN"),
1045 p_ramrod->filter_cmd_hdr.cmd_cnt,
1046 p_filter_cmd->is_rx_filter,
1047 p_filter_cmd->is_tx_filter);
1048 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1049 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1050 p_filter_cmd->vport_to_add_to,
1051 p_filter_cmd->vport_to_remove_from,
1052 p_filter_cmd->mac[0],
1053 p_filter_cmd->mac[1],
1054 p_filter_cmd->mac[2],
1055 p_filter_cmd->mac[3],
1056 p_filter_cmd->mac[4],
1057 p_filter_cmd->mac[5],
1058 p_filter_cmd->vlan);
1059
1060 return 0;
1061}
1062
1063/*******************************************************************************
1064 * Description:
1065 * Calculates crc 32 on a buffer
1066 * Note: crc32_length MUST be aligned to 8
1067 * Return:
1068 ******************************************************************************/
1069static u32 qed_calc_crc32c(u8 *crc32_packet,
1070 u32 crc32_length,
1071 u32 crc32_seed,
1072 u8 complement)
1073{
1074 u32 byte = 0;
1075 u32 bit = 0;
1076 u8 msb = 0;
1077 u8 current_byte = 0;
1078 u32 crc32_result = crc32_seed;
1079
1080 if ((!crc32_packet) ||
1081 (crc32_length == 0) ||
1082 ((crc32_length % 8) != 0))
1083 return crc32_result;
1084 for (byte = 0; byte < crc32_length; byte++) {
1085 current_byte = crc32_packet[byte];
1086 for (bit = 0; bit < 8; bit++) {
1087 msb = (u8)(crc32_result >> 31);
1088 crc32_result = crc32_result << 1;
1089 if (msb != (0x1 & (current_byte >> bit))) {
1090 crc32_result = crc32_result ^ CRC32_POLY;
1091 crc32_result |= 1; /*crc32_result[0] = 1;*/
1092 }
1093 }
1094 }
1095 return crc32_result;
1096}
1097
1098static inline u32 qed_crc32c_le(u32 seed,
1099 u8 *mac,
1100 u32 len)
1101{
1102 u32 packet_buf[2] = { 0 };
1103
1104 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1105 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1106}
1107
1108static u8 qed_mcast_bin_from_mac(u8 *mac)
1109{
1110 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1111 mac, ETH_ALEN);
1112
1113 return crc & 0xff;
1114}
1115
1116static int
1117qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1118 u16 opaque_fid,
1119 struct qed_filter_mcast *p_filter_cmd,
1120 enum spq_mode comp_mode,
1121 struct qed_spq_comp_cb *p_comp_data)
1122{
1123 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1124 struct vport_update_ramrod_data *p_ramrod = NULL;
cee4d264 1125 struct qed_spq_entry *p_ent = NULL;
06f56b81 1126 struct qed_sp_init_data init_data;
cee4d264
MC		 1127 u8 abs_vport_id = 0;
1128 int rc, i;
1129
1130 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1131 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1132 &abs_vport_id);
1133 if (rc)
1134 return rc;
1135 } else {
1136 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1137 &abs_vport_id);
1138 if (rc)
1139 return rc;
1140 }
1141
06f56b81
YM		 1142 /* Get SPQ entry */
1143 memset(&init_data, 0, sizeof(init_data));
1144 init_data.cid = qed_spq_get_cid(p_hwfn);
1145 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1146 init_data.comp_mode = comp_mode;
1147 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1148
1149 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1150 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1151 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1152 if (rc) {
1153 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1154 return rc;
1155 }
1156
1157 p_ramrod = &p_ent->ramrod.vport_update;
1158 p_ramrod->common.update_approx_mcast_flg = 1;
1159
1160 /* explicitly clear out the entire vector */
1161 memset(&p_ramrod->approx_mcast.bins, 0,
1162 sizeof(p_ramrod->approx_mcast.bins));
1163 memset(bins, 0, sizeof(unsigned long) *
1164 ETH_MULTICAST_MAC_BINS_IN_REGS);
1165 /* filter ADD op is explicit set op and it removes
1166 * any existing filters for the vport
1167 */
1168 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1169 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1170 u32 bit;
1171
1172 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1173 __set_bit(bit, bins);
1174 }
1175
1176 /* Convert to correct endianity */
1177 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1178 u32 *p_bins = (u32 *)bins;
1179 struct vport_update_ramrod_mcast *approx_mcast;
1180
1181 approx_mcast = &p_ramrod->approx_mcast;
1182 approx_mcast->bins[i] = cpu_to_le32(p_bins[i]);
1183 }
1184 }
1185
1186 p_ramrod->common.vport_id = abs_vport_id;
1187
1188 return qed_spq_post(p_hwfn, p_ent, NULL);
1189}
1190
1191static int
1192qed_filter_mcast_cmd(struct qed_dev *cdev,
1193 struct qed_filter_mcast *p_filter_cmd,
1194 enum spq_mode comp_mode,
1195 struct qed_spq_comp_cb *p_comp_data)
1196{
1197 int rc = 0;
1198 int i;
1199
1200 /* only ADD and REMOVE operations are supported for multi-cast */
1201 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1202 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1203 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1204 return -EINVAL;
1205
1206 for_each_hwfn(cdev, i) {
1207 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1208
1209 u16 opaque_fid;
1210
1211 if (rc != 0)
1212 break;
1213
1214 opaque_fid = p_hwfn->hw_info.opaque_fid;
1215
1216 rc = qed_sp_eth_filter_mcast(p_hwfn,
1217 opaque_fid,
1218 p_filter_cmd,
1219 comp_mode,
1220 p_comp_data);
1221 }
1222 return rc;
1223}
1224
1225static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1226 struct qed_filter_ucast *p_filter_cmd,
1227 enum spq_mode comp_mode,
1228 struct qed_spq_comp_cb *p_comp_data)
1229{
1230 int rc = 0;
1231 int i;
1232
1233 for_each_hwfn(cdev, i) {
1234 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1235 u16 opaque_fid;
1236
1237 if (rc != 0)
1238 break;
1239
1240 opaque_fid = p_hwfn->hw_info.opaque_fid;
1241
1242 rc = qed_sp_eth_filter_ucast(p_hwfn,
1243 opaque_fid,
1244 p_filter_cmd,
1245 comp_mode,
1246 p_comp_data);
1247 }
1248
1249 return rc;
1250}
1251
86622ee7
YM		 1252/* Statistics related code */
1253static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
1254 u32 *p_addr,
1255 u32 *p_len,
1256 u16 statistics_bin)
1257{
1258 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1259 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1260 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1261}
1262
1263static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
1264 struct qed_ptt *p_ptt,
1265 struct qed_eth_stats *p_stats,
1266 u16 statistics_bin)
1267{
1268 struct eth_pstorm_per_queue_stat pstats;
1269 u32 pstats_addr = 0, pstats_len = 0;
1270
1271 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1272 statistics_bin);
1273
1274 memset(&pstats, 0, sizeof(pstats));
1275 qed_memcpy_from(p_hwfn, p_ptt, &pstats,
1276 pstats_addr, pstats_len);
1277
1278 p_stats->tx_ucast_bytes +=
1279 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1280 p_stats->tx_mcast_bytes +=
1281 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1282 p_stats->tx_bcast_bytes +=
1283 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1284 p_stats->tx_ucast_pkts +=
1285 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1286 p_stats->tx_mcast_pkts +=
1287 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1288 p_stats->tx_bcast_pkts +=
1289 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1290 p_stats->tx_err_drop_pkts +=
1291 HILO_64_REGPAIR(pstats.error_drop_pkts);
1292}
1293
1294static void __qed_get_vport_tstats_addrlen(struct qed_hwfn *p_hwfn,
1295 u32 *p_addr,
1296 u32 *p_len)
1297{
1298 *p_addr = BAR0_MAP_REG_TSDM_RAM +
1299 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1300 *p_len = sizeof(struct tstorm_per_port_stat);
1301}
1302
1303static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
1304 struct qed_ptt *p_ptt,
1305 struct qed_eth_stats *p_stats,
1306 u16 statistics_bin)
1307{
1308 u32 tstats_addr = 0, tstats_len = 0;
1309 struct tstorm_per_port_stat tstats;
1310
1311 __qed_get_vport_tstats_addrlen(p_hwfn, &tstats_addr, &tstats_len);
1312
1313 memset(&tstats, 0, sizeof(tstats));
1314 qed_memcpy_from(p_hwfn, p_ptt, &tstats,
1315 tstats_addr, tstats_len);
1316
1317 p_stats->mftag_filter_discards +=
1318 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1319 p_stats->mac_filter_discards +=
1320 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1321}
1322
1323static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
1324 u32 *p_addr,
1325 u32 *p_len,
1326 u16 statistics_bin)
1327{
1328 *p_addr = BAR0_MAP_REG_USDM_RAM +
1329 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1330 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1331}
1332
1333static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
1334 struct qed_ptt *p_ptt,
1335 struct qed_eth_stats *p_stats,
1336 u16 statistics_bin)
1337{
1338 struct eth_ustorm_per_queue_stat ustats;
1339 u32 ustats_addr = 0, ustats_len = 0;
1340
1341 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1342 statistics_bin);
1343
1344 memset(&ustats, 0, sizeof(ustats));
1345 qed_memcpy_from(p_hwfn, p_ptt, &ustats,
1346 ustats_addr, ustats_len);
1347
1348 p_stats->rx_ucast_bytes +=
1349 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1350 p_stats->rx_mcast_bytes +=
1351 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1352 p_stats->rx_bcast_bytes +=
1353 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1354 p_stats->rx_ucast_pkts +=
1355 HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1356 p_stats->rx_mcast_pkts +=
1357 HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1358 p_stats->rx_bcast_pkts +=
1359 HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1360}
1361
1362static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
1363 u32 *p_addr,
1364 u32 *p_len,
1365 u16 statistics_bin)
1366{
1367 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1368 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1369 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1370}
1371
1372static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
1373 struct qed_ptt *p_ptt,
1374 struct qed_eth_stats *p_stats,
1375 u16 statistics_bin)
1376{
1377 struct eth_mstorm_per_queue_stat mstats;
1378 u32 mstats_addr = 0, mstats_len = 0;
1379
1380 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1381 statistics_bin);
1382
1383 memset(&mstats, 0, sizeof(mstats));
1384 qed_memcpy_from(p_hwfn, p_ptt, &mstats,
1385 mstats_addr, mstats_len);
1386
1387 p_stats->no_buff_discards +=
1388 HILO_64_REGPAIR(mstats.no_buff_discard);
1389 p_stats->packet_too_big_discard +=
1390 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1391 p_stats->ttl0_discard +=
1392 HILO_64_REGPAIR(mstats.ttl0_discard);
1393 p_stats->tpa_coalesced_pkts +=
1394 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1395 p_stats->tpa_coalesced_events +=
1396 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1397 p_stats->tpa_aborts_num +=
1398 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1399 p_stats->tpa_coalesced_bytes +=
1400 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1401}
1402
1403static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
1404 struct qed_ptt *p_ptt,
1405 struct qed_eth_stats *p_stats)
1406{
1407 struct port_stats port_stats;
1408 int j;
1409
1410 memset(&port_stats, 0, sizeof(port_stats));
1411
1412 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1413 p_hwfn->mcp_info->port_addr +
1414 offsetof(struct public_port, stats),
1415 sizeof(port_stats));
1416
1417 p_stats->rx_64_byte_packets += port_stats.pmm.r64;
1418 p_stats->rx_127_byte_packets += port_stats.pmm.r127;
1419 p_stats->rx_255_byte_packets += port_stats.pmm.r255;
1420 p_stats->rx_511_byte_packets += port_stats.pmm.r511;
1421 p_stats->rx_1023_byte_packets += port_stats.pmm.r1023;
1422 p_stats->rx_1518_byte_packets += port_stats.pmm.r1518;
1423 p_stats->rx_1522_byte_packets += port_stats.pmm.r1522;
1424 p_stats->rx_2047_byte_packets += port_stats.pmm.r2047;
1425 p_stats->rx_4095_byte_packets += port_stats.pmm.r4095;
1426 p_stats->rx_9216_byte_packets += port_stats.pmm.r9216;
1427 p_stats->rx_16383_byte_packets += port_stats.pmm.r16383;
1428 p_stats->rx_crc_errors += port_stats.pmm.rfcs;
1429 p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
1430 p_stats->rx_pause_frames += port_stats.pmm.rxpf;
1431 p_stats->rx_pfc_frames += port_stats.pmm.rxpp;
1432 p_stats->rx_align_errors += port_stats.pmm.raln;
1433 p_stats->rx_carrier_errors += port_stats.pmm.rfcr;
1434 p_stats->rx_oversize_packets += port_stats.pmm.rovr;
1435 p_stats->rx_jabbers += port_stats.pmm.rjbr;
1436 p_stats->rx_undersize_packets += port_stats.pmm.rund;
1437 p_stats->rx_fragments += port_stats.pmm.rfrg;
1438 p_stats->tx_64_byte_packets += port_stats.pmm.t64;
1439 p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
1440 p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
1441 p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
1442 p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
1443 p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
1444 p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
1445 p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
1446 p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
1447 p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
1448 p_stats->tx_pause_frames += port_stats.pmm.txpf;
1449 p_stats->tx_pfc_frames += port_stats.pmm.txpp;
1450 p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
1451 p_stats->tx_total_collisions += port_stats.pmm.tncl;
1452 p_stats->rx_mac_bytes += port_stats.pmm.rbyte;
1453 p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
1454 p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
1455 p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
1456 p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
1457 p_stats->tx_mac_bytes += port_stats.pmm.tbyte;
1458 p_stats->tx_mac_uc_packets += port_stats.pmm.txuca;
1459 p_stats->tx_mac_mc_packets += port_stats.pmm.txmca;
1460 p_stats->tx_mac_bc_packets += port_stats.pmm.txbca;
1461 p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
1462 for (j = 0; j < 8; j++) {
1463 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1464 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1465 }
1466}
1467
1468static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
1469 struct qed_ptt *p_ptt,
1470 struct qed_eth_stats *stats,
1471 u16 statistics_bin)
1472{
1473 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1474 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1475 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1476 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1477
1478 if (p_hwfn->mcp_info)
1479 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
1480}
1481
1482static void _qed_get_vport_stats(struct qed_dev *cdev,
1483 struct qed_eth_stats *stats)
1484{
1485 u8 fw_vport = 0;
1486 int i;
1487
1488 memset(stats, 0, sizeof(*stats));
1489
1490 for_each_hwfn(cdev, i) {
1491 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1492 struct qed_ptt *p_ptt;
1493
1494 /* The main vport index is relative first */
1495 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
1496 DP_ERR(p_hwfn, "No vport available!\n");
1497 continue;
1498 }
1499
1500 p_ptt = qed_ptt_acquire(p_hwfn);
1501 if (!p_ptt) {
1502 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1503 continue;
1504 }
1505
1506 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport);
1507
1508 qed_ptt_release(p_hwfn, p_ptt);
1509 }
1510}
1511
1512void qed_get_vport_stats(struct qed_dev *cdev,
1513 struct qed_eth_stats *stats)
1514{
1515 u32 i;
1516
1517 if (!cdev) {
1518 memset(stats, 0, sizeof(*stats));
1519 return;
1520 }
1521
1522 _qed_get_vport_stats(cdev, stats);
1523
1524 if (!cdev->reset_stats)
1525 return;
1526
1527 /* Reduce the statistics baseline */
1528 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1529 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1530}
1531
1532/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1533void qed_reset_vport_stats(struct qed_dev *cdev)
1534{
1535 int i;
1536
1537 for_each_hwfn(cdev, i) {
1538 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1539 struct eth_mstorm_per_queue_stat mstats;
1540 struct eth_ustorm_per_queue_stat ustats;
1541 struct eth_pstorm_per_queue_stat pstats;
1542 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1543 u32 addr = 0, len = 0;
1544
1545 if (!p_ptt) {
1546 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1547 continue;
1548 }
1549
1550 memset(&mstats, 0, sizeof(mstats));
1551 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1552 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1553
1554 memset(&ustats, 0, sizeof(ustats));
1555 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1556 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1557
1558 memset(&pstats, 0, sizeof(pstats));
1559 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1560 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1561
1562 qed_ptt_release(p_hwfn, p_ptt);
1563 }
1564
1565 /* PORT statistics are not necessarily reset, so we need to
1566 * read and create a baseline for future statistics.
1567 */
1568 if (!cdev->reset_stats)
1569 DP_INFO(cdev, "Reset stats not allocated\n");
1570 else
1571 _qed_get_vport_stats(cdev, cdev->reset_stats);
1572}
1573
25c089d7
YM		 1574static int qed_fill_eth_dev_info(struct qed_dev *cdev,
1575 struct qed_dev_eth_info *info)
1576{
1577 int i;
1578
1579 memset(info, 0, sizeof(*info));
1580
1581 info->num_tc = 1;
1582
1583 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
1584 for_each_hwfn(cdev, i)
1585 info->num_queues += FEAT_NUM(&cdev->hwfns[i],
1586 QED_PF_L2_QUE);
1587 if (cdev->int_params.fp_msix_cnt)
1588 info->num_queues = min_t(u8, info->num_queues,
1589 cdev->int_params.fp_msix_cnt);
1590 } else {
1591 info->num_queues = cdev->num_hwfns;
1592 }
1593
1594 info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN);
1595 ether_addr_copy(info->port_mac,
1596 cdev->hwfns[0].hw_info.hw_mac_addr);
1597
1598 qed_fill_dev_info(cdev, &info->common);
1599
1600 return 0;
1601}
1602
cc875c2e
YM		 1603static void qed_register_eth_ops(struct qed_dev *cdev,
1604 struct qed_eth_cb_ops *ops,
1605 void *cookie)
1606{
1607 cdev->protocol_ops.eth = ops;
1608 cdev->ops_cookie = cookie;
1609}
1610
cee4d264 1611static int qed_start_vport(struct qed_dev *cdev,
088c8618 1612 struct qed_start_vport_params *params)
cee4d264
MC		 1613{
1614 int rc, i;
1615
1616 for_each_hwfn(cdev, i) {
088c8618 1617 struct qed_sp_vport_start_params start = { 0 };
cee4d264
MC		 1618 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1619
088c8618
MC		 1620 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1621 QED_TPA_MODE_NONE;
1622 start.remove_inner_vlan = params->remove_inner_vlan;
1623 start.drop_ttl0 = params->drop_ttl0;
1624 start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1625 start.concrete_fid = p_hwfn->hw_info.concrete_fid;
1626 start.vport_id = params->vport_id;
1627 start.max_buffers_per_cqe = 16;
1628 start.mtu = params->mtu;
1629
1630 rc = qed_sp_vport_start(p_hwfn, &start);
cee4d264
MC		 1631 if (rc) {
1632 DP_ERR(cdev, "Failed to start VPORT\n");
1633 return rc;
1634 }
1635
1636 qed_hw_start_fastpath(p_hwfn);
1637
1638 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1639 "Started V-PORT %d with MTU %d\n",
088c8618 1640 start.vport_id, start.mtu);
cee4d264
MC		 1641 }
1642
9df2ed04
MC		 1643 qed_reset_vport_stats(cdev);
1644
cee4d264
MC		 1645 return 0;
1646}
1647
1648static int qed_stop_vport(struct qed_dev *cdev,
1649 u8 vport_id)
1650{
1651 int rc, i;
1652
1653 for_each_hwfn(cdev, i) {
1654 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1655
1656 rc = qed_sp_vport_stop(p_hwfn,
1657 p_hwfn->hw_info.opaque_fid,
1658 vport_id);
1659
1660 if (rc) {
1661 DP_ERR(cdev, "Failed to stop VPORT\n");
1662 return rc;
1663 }
1664 }
1665 return 0;
1666}
1667
1668static int qed_update_vport(struct qed_dev *cdev,
1669 struct qed_update_vport_params *params)
1670{
1671 struct qed_sp_vport_update_params sp_params;
1672 struct qed_rss_params sp_rss_params;
1673 int rc, i;
1674
1675 if (!cdev)
1676 return -ENODEV;
1677
1678 memset(&sp_params, 0, sizeof(sp_params));
1679 memset(&sp_rss_params, 0, sizeof(sp_rss_params));
1680
1681 /* Translate protocol params into sp params */
1682 sp_params.vport_id = params->vport_id;
1683 sp_params.update_vport_active_rx_flg =
1684 params->update_vport_active_flg;
1685 sp_params.update_vport_active_tx_flg =
1686 params->update_vport_active_flg;
1687 sp_params.vport_active_rx_flg = params->vport_active_flg;
1688 sp_params.vport_active_tx_flg = params->vport_active_flg;
3f9b4a69
YM		 1689 sp_params.accept_any_vlan = params->accept_any_vlan;
1690 sp_params.update_accept_any_vlan_flg =
1691 params->update_accept_any_vlan_flg;
cee4d264
MC		 1692
1693 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
1694 * We need to re-fix the rss values per engine for CMT.
1695 */
1696 if (cdev->num_hwfns > 1 && params->update_rss_flg) {
1697 struct qed_update_vport_rss_params *rss =
1698 &params->rss_params;
1699 int k, max = 0;
1700
1701 /* Find largest entry, since it's possible RSS needs to
1702 * be disabled [in case only 1 queue per-hwfn]
1703 */
1704 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1705 max = (max > rss->rss_ind_table[k]) ?
1706 max : rss->rss_ind_table[k];
1707
1708 /* Either fix RSS values or disable RSS */
1709 if (cdev->num_hwfns < max + 1) {
1710 int divisor = (max + cdev->num_hwfns - 1) /
1711 cdev->num_hwfns;
1712
1713 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1714 "CMT - fixing RSS values (modulo %02x)\n",
1715 divisor);
1716
1717 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1718 rss->rss_ind_table[k] =
1719 rss->rss_ind_table[k] % divisor;
1720 } else {
1721 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1722 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1723 params->update_rss_flg = 0;
1724 }
1725 }
1726
1727 /* Now, update the RSS configuration for actual configuration */
1728 if (params->update_rss_flg) {
1729 sp_rss_params.update_rss_config = 1;
1730 sp_rss_params.rss_enable = 1;
1731 sp_rss_params.update_rss_capabilities = 1;
1732 sp_rss_params.update_rss_ind_table = 1;
1733 sp_rss_params.update_rss_key = 1;
8c5ebd0c 1734 sp_rss_params.rss_caps = params->rss_params.rss_caps;
cee4d264
MC		 1735 sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
1736 memcpy(sp_rss_params.rss_ind_table,
1737 params->rss_params.rss_ind_table,
1738 QED_RSS_IND_TABLE_SIZE * sizeof(u16));
1739 memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
1740 QED_RSS_KEY_SIZE * sizeof(u32));
1741 }
1742 sp_params.rss_params = &sp_rss_params;
1743
1744 for_each_hwfn(cdev, i) {
1745 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1746
1747 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1748 rc = qed_sp_vport_update(p_hwfn, &sp_params,
1749 QED_SPQ_MODE_EBLOCK,
1750 NULL);
1751 if (rc) {
1752 DP_ERR(cdev, "Failed to update VPORT\n");
1753 return rc;
1754 }
1755
1756 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1757 "Updated V-PORT %d: active_flag %d [update %d]\n",
1758 params->vport_id, params->vport_active_flg,
1759 params->update_vport_active_flg);
1760 }
1761
1762 return 0;
1763}
1764
1765static int qed_start_rxq(struct qed_dev *cdev,
1766 struct qed_queue_start_common_params *params,
1767 u16 bd_max_bytes,
1768 dma_addr_t bd_chain_phys_addr,
1769 dma_addr_t cqe_pbl_addr,
1770 u16 cqe_pbl_size,
1771 void __iomem **pp_prod)
1772{
1773 int rc, hwfn_index;
1774 struct qed_hwfn *p_hwfn;
1775
1776 hwfn_index = params->rss_id % cdev->num_hwfns;
1777 p_hwfn = &cdev->hwfns[hwfn_index];
1778
1779 /* Fix queue ID in 100g mode */
1780 params->queue_id /= cdev->num_hwfns;
1781
1782 rc = qed_sp_eth_rx_queue_start(p_hwfn,
1783 p_hwfn->hw_info.opaque_fid,
1784 params,
1785 bd_max_bytes,
1786 bd_chain_phys_addr,
1787 cqe_pbl_addr,
1788 cqe_pbl_size,
1789 pp_prod);
1790
1791 if (rc) {
1792 DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
1793 return rc;
1794 }
1795
1796 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1797 "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1798 params->queue_id, params->rss_id, params->vport_id,
1799 params->sb);
1800
1801 return 0;
1802}
1803
1804static int qed_stop_rxq(struct qed_dev *cdev,
1805 struct qed_stop_rxq_params *params)
1806{
1807 int rc, hwfn_index;
1808 struct qed_hwfn *p_hwfn;
1809
1810 hwfn_index = params->rss_id % cdev->num_hwfns;
1811 p_hwfn = &cdev->hwfns[hwfn_index];
1812
1813 rc = qed_sp_eth_rx_queue_stop(p_hwfn,
1814 params->rx_queue_id / cdev->num_hwfns,
1815 params->eq_completion_only,
1816 false);
1817 if (rc) {
1818 DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
1819 return rc;
1820 }
1821
1822 return 0;
1823}
1824
1825static int qed_start_txq(struct qed_dev *cdev,
1826 struct qed_queue_start_common_params *p_params,
1827 dma_addr_t pbl_addr,
1828 u16 pbl_size,
1829 void __iomem **pp_doorbell)
1830{
1831 struct qed_hwfn *p_hwfn;
1832 int rc, hwfn_index;
1833
1834 hwfn_index = p_params->rss_id % cdev->num_hwfns;
1835 p_hwfn = &cdev->hwfns[hwfn_index];
1836
1837 /* Fix queue ID in 100g mode */
1838 p_params->queue_id /= cdev->num_hwfns;
1839
1840 rc = qed_sp_eth_tx_queue_start(p_hwfn,
1841 p_hwfn->hw_info.opaque_fid,
1842 p_params,
1843 pbl_addr,
1844 pbl_size,
1845 pp_doorbell);
1846
1847 if (rc) {
1848 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
1849 return rc;
1850 }
1851
1852 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1853 "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1854 p_params->queue_id, p_params->rss_id, p_params->vport_id,
1855 p_params->sb);
1856
1857 return 0;
1858}
1859
1860#define QED_HW_STOP_RETRY_LIMIT (10)
1861static int qed_fastpath_stop(struct qed_dev *cdev)
1862{
1863 qed_hw_stop_fastpath(cdev);
1864
1865 return 0;
1866}
1867
1868static int qed_stop_txq(struct qed_dev *cdev,
1869 struct qed_stop_txq_params *params)
1870{
1871 struct qed_hwfn *p_hwfn;
1872 int rc, hwfn_index;
1873
1874 hwfn_index = params->rss_id % cdev->num_hwfns;
1875 p_hwfn = &cdev->hwfns[hwfn_index];
1876
1877 rc = qed_sp_eth_tx_queue_stop(p_hwfn,
1878 params->tx_queue_id / cdev->num_hwfns);
1879 if (rc) {
1880 DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
1881 return rc;
1882 }
1883
1884 return 0;
1885}
1886
1887static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
1888 enum qed_filter_rx_mode_type type)
1889{
1890 struct qed_filter_accept_flags accept_flags;
1891
1892 memset(&accept_flags, 0, sizeof(accept_flags));
1893
1894 accept_flags.update_rx_mode_config = 1;
1895 accept_flags.update_tx_mode_config = 1;
1896 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
1897 QED_ACCEPT_MCAST_MATCHED |
1898 QED_ACCEPT_BCAST;
1899 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
1900 QED_ACCEPT_MCAST_MATCHED |
1901 QED_ACCEPT_BCAST;
1902
1903 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
1904 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
1905 QED_ACCEPT_MCAST_UNMATCHED;
1906 else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
1907 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
1908
3f9b4a69 1909 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 1910 QED_SPQ_MODE_CB, NULL);
1911}
1912
1913static int qed_configure_filter_ucast(struct qed_dev *cdev,
1914 struct qed_filter_ucast_params *params)
1915{
1916 struct qed_filter_ucast ucast;
1917
1918 if (!params->vlan_valid && !params->mac_valid) {
1919 DP_NOTICE(
1920 cdev,
1921 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
1922 return -EINVAL;
1923 }
1924
1925 memset(&ucast, 0, sizeof(ucast));
1926 switch (params->type) {
1927 case QED_FILTER_XCAST_TYPE_ADD:
1928 ucast.opcode = QED_FILTER_ADD;
1929 break;
1930 case QED_FILTER_XCAST_TYPE_DEL:
1931 ucast.opcode = QED_FILTER_REMOVE;
1932 break;
1933 case QED_FILTER_XCAST_TYPE_REPLACE:
1934 ucast.opcode = QED_FILTER_REPLACE;
1935 break;
1936 default:
1937 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
1938 params->type);
1939 }
1940
1941 if (params->vlan_valid && params->mac_valid) {
1942 ucast.type = QED_FILTER_MAC_VLAN;
1943 ether_addr_copy(ucast.mac, params->mac);
1944 ucast.vlan = params->vlan;
1945 } else if (params->mac_valid) {
1946 ucast.type = QED_FILTER_MAC;
1947 ether_addr_copy(ucast.mac, params->mac);
1948 } else {
1949 ucast.type = QED_FILTER_VLAN;
1950 ucast.vlan = params->vlan;
1951 }
1952
1953 ucast.is_rx_filter = true;
1954 ucast.is_tx_filter = true;
1955
1956 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
1957}
1958
1959static int qed_configure_filter_mcast(struct qed_dev *cdev,
1960 struct qed_filter_mcast_params *params)
1961{
1962 struct qed_filter_mcast mcast;
1963 int i;
1964
1965 memset(&mcast, 0, sizeof(mcast));
1966 switch (params->type) {
1967 case QED_FILTER_XCAST_TYPE_ADD:
1968 mcast.opcode = QED_FILTER_ADD;
1969 break;
1970 case QED_FILTER_XCAST_TYPE_DEL:
1971 mcast.opcode = QED_FILTER_REMOVE;
1972 break;
1973 default:
1974 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
1975 params->type);
1976 }
1977
1978 mcast.num_mc_addrs = params->num;
1979 for (i = 0; i < mcast.num_mc_addrs; i++)
1980 ether_addr_copy(mcast.mac[i], params->mac[i]);
1981
1982 return qed_filter_mcast_cmd(cdev, &mcast,
1983 QED_SPQ_MODE_CB, NULL);
1984}
1985
1986static int qed_configure_filter(struct qed_dev *cdev,
1987 struct qed_filter_params *params)
1988{
1989 enum qed_filter_rx_mode_type accept_flags;
1990
1991 switch (params->type) {
1992 case QED_FILTER_TYPE_UCAST:
1993 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
1994 case QED_FILTER_TYPE_MCAST:
1995 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
1996 case QED_FILTER_TYPE_RX_MODE:
1997 accept_flags = params->filter.accept_flags;
1998 return qed_configure_filter_rx_mode(cdev, accept_flags);
1999 default:
2000 DP_NOTICE(cdev, "Unknown filter type %d\n",
2001 (int)params->type);
2002 return -EINVAL;
2003 }
2004}
2005
2006static int qed_fp_cqe_completion(struct qed_dev *dev,
2007 u8 rss_id,
2008 struct eth_slow_path_rx_cqe *cqe)
2009{
2010 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2011 cqe);
2012}
2013
25c089d7
YM		 2014static const struct qed_eth_ops qed_eth_ops_pass = {
2015 .common = &qed_common_ops_pass,
2016 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 2017 .register_ops = &qed_register_eth_ops,
cee4d264
MC		 2018 .vport_start = &qed_start_vport,
2019 .vport_stop = &qed_stop_vport,
2020 .vport_update = &qed_update_vport,
2021 .q_rx_start = &qed_start_rxq,
2022 .q_rx_stop = &qed_stop_rxq,
2023 .q_tx_start = &qed_start_txq,
2024 .q_tx_stop = &qed_stop_txq,
2025 .filter_config = &qed_configure_filter,
2026 .fastpath_stop = &qed_fastpath_stop,
2027 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 2028 .get_vport_stats = &qed_get_vport_stats,
25c089d7
YM		 2029};
2030
95114344 2031const struct qed_eth_ops *qed_get_eth_ops(void)
25c089d7 2032{
25c089d7
YM		 2033 return &qed_eth_ops_pass;
2034}
2035EXPORT_SYMBOL(qed_get_eth_ops);
2036
2037void qed_put_eth_ops(void)
2038{
2039 /* TODO - reference count for module? */
2040}
2041EXPORT_SYMBOL(qed_put_eth_ops);
Linux kernel - Deliverables
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