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e712d52b YM |
1 | /* QLogic qede NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #ifndef _QEDE_H_ | |
10 | #define _QEDE_H_ | |
11 | #include <linux/compiler.h> | |
12 | #include <linux/version.h> | |
13 | #include <linux/workqueue.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/bitmap.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/mutex.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/qed/common_hsi.h> | |
21 | #include <linux/qed/eth_common.h> | |
22 | #include <linux/qed/qed_if.h> | |
23 | #include <linux/qed/qed_chain.h> | |
24 | #include <linux/qed/qed_eth_if.h> | |
25 | ||
26 | #define QEDE_MAJOR_VERSION 8 | |
d4ee5289 | 27 | #define QEDE_MINOR_VERSION 7 |
e712d52b YM |
28 | #define QEDE_REVISION_VERSION 0 |
29 | #define QEDE_ENGINEERING_VERSION 0 | |
30 | #define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \ | |
31 | __stringify(QEDE_MINOR_VERSION) "." \ | |
32 | __stringify(QEDE_REVISION_VERSION) "." \ | |
33 | __stringify(QEDE_ENGINEERING_VERSION) | |
34 | ||
e712d52b YM |
35 | #define DRV_MODULE_SYM qede |
36 | ||
133fac0e SK |
37 | struct qede_stats { |
38 | u64 no_buff_discards; | |
39 | u64 rx_ucast_bytes; | |
40 | u64 rx_mcast_bytes; | |
41 | u64 rx_bcast_bytes; | |
42 | u64 rx_ucast_pkts; | |
43 | u64 rx_mcast_pkts; | |
44 | u64 rx_bcast_pkts; | |
45 | u64 mftag_filter_discards; | |
46 | u64 mac_filter_discards; | |
47 | u64 tx_ucast_bytes; | |
48 | u64 tx_mcast_bytes; | |
49 | u64 tx_bcast_bytes; | |
50 | u64 tx_ucast_pkts; | |
51 | u64 tx_mcast_pkts; | |
52 | u64 tx_bcast_pkts; | |
53 | u64 tx_err_drop_pkts; | |
54 | u64 coalesced_pkts; | |
55 | u64 coalesced_events; | |
56 | u64 coalesced_aborts_num; | |
57 | u64 non_coalesced_pkts; | |
58 | u64 coalesced_bytes; | |
59 | ||
60 | /* port */ | |
61 | u64 rx_64_byte_packets; | |
62 | u64 rx_127_byte_packets; | |
63 | u64 rx_255_byte_packets; | |
64 | u64 rx_511_byte_packets; | |
65 | u64 rx_1023_byte_packets; | |
66 | u64 rx_1518_byte_packets; | |
67 | u64 rx_1522_byte_packets; | |
68 | u64 rx_2047_byte_packets; | |
69 | u64 rx_4095_byte_packets; | |
70 | u64 rx_9216_byte_packets; | |
71 | u64 rx_16383_byte_packets; | |
72 | u64 rx_crc_errors; | |
73 | u64 rx_mac_crtl_frames; | |
74 | u64 rx_pause_frames; | |
75 | u64 rx_pfc_frames; | |
76 | u64 rx_align_errors; | |
77 | u64 rx_carrier_errors; | |
78 | u64 rx_oversize_packets; | |
79 | u64 rx_jabbers; | |
80 | u64 rx_undersize_packets; | |
81 | u64 rx_fragments; | |
82 | u64 tx_64_byte_packets; | |
83 | u64 tx_65_to_127_byte_packets; | |
84 | u64 tx_128_to_255_byte_packets; | |
85 | u64 tx_256_to_511_byte_packets; | |
86 | u64 tx_512_to_1023_byte_packets; | |
87 | u64 tx_1024_to_1518_byte_packets; | |
88 | u64 tx_1519_to_2047_byte_packets; | |
89 | u64 tx_2048_to_4095_byte_packets; | |
90 | u64 tx_4096_to_9216_byte_packets; | |
91 | u64 tx_9217_to_16383_byte_packets; | |
92 | u64 tx_pause_frames; | |
93 | u64 tx_pfc_frames; | |
94 | u64 tx_lpi_entry_count; | |
95 | u64 tx_total_collisions; | |
96 | u64 brb_truncates; | |
97 | u64 brb_discards; | |
98 | u64 tx_mac_ctrl_frames; | |
99 | }; | |
100 | ||
7c1bfcad SRK |
101 | struct qede_vlan { |
102 | struct list_head list; | |
103 | u16 vid; | |
104 | bool configured; | |
105 | }; | |
106 | ||
e712d52b YM |
107 | struct qede_dev { |
108 | struct qed_dev *cdev; | |
109 | struct net_device *ndev; | |
110 | struct pci_dev *pdev; | |
111 | ||
112 | u32 dp_module; | |
113 | u8 dp_level; | |
114 | ||
115 | const struct qed_eth_ops *ops; | |
116 | ||
117 | struct qed_dev_eth_info dev_info; | |
118 | #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues) | |
119 | #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \ | |
120 | (edev)->dev_info.num_tc) | |
121 | ||
2950219d | 122 | struct qede_fastpath *fp_array; |
8edf049d | 123 | u16 req_rss; |
e712d52b YM |
124 | u16 num_rss; |
125 | u8 num_tc; | |
126 | #define QEDE_RSS_CNT(edev) ((edev)->num_rss) | |
127 | #define QEDE_TSS_CNT(edev) ((edev)->num_rss * \ | |
128 | (edev)->num_tc) | |
129 | #define QEDE_TSS_IDX(edev, txqidx) ((txqidx) % (edev)->num_rss) | |
130 | #define QEDE_TC_IDX(edev, txqidx) ((txqidx) / (edev)->num_rss) | |
2950219d YM |
131 | #define QEDE_TX_QUEUE(edev, txqidx) \ |
132 | (&(edev)->fp_array[QEDE_TSS_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX( \ | |
133 | (edev), (txqidx))]) | |
e712d52b YM |
134 | |
135 | struct qed_int_info int_info; | |
136 | unsigned char primary_mac[ETH_ALEN]; | |
137 | ||
138 | /* Smaller private varaiant of the RTNL lock */ | |
139 | struct mutex qede_lock; | |
140 | u32 state; /* Protected by qede_lock */ | |
2950219d YM |
141 | u16 rx_buf_size; |
142 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ | |
143 | #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) | |
144 | /* Max supported alignment is 256 (8 shift) | |
145 | * minimal alignment shift 6 is optimal for 57xxx HW performance | |
146 | */ | |
147 | #define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) | |
148 | /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes | |
149 | * at the end of skb->data, to avoid wasting a full cache line. | |
150 | * This reduces memory use (skb->truesize). | |
151 | */ | |
152 | #define QEDE_FW_RX_ALIGN_END \ | |
153 | max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \ | |
154 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
155 | ||
133fac0e | 156 | struct qede_stats stats; |
961acdea SRK |
157 | #define QEDE_RSS_INDIR_INITED BIT(0) |
158 | #define QEDE_RSS_KEY_INITED BIT(1) | |
159 | #define QEDE_RSS_CAPS_INITED BIT(2) | |
160 | u32 rss_params_inited; /* bit-field to track initialized rss params */ | |
2950219d YM |
161 | struct qed_update_vport_rss_params rss_params; |
162 | u16 q_num_rx_buffers; /* Must be a power of two */ | |
163 | u16 q_num_tx_buffers; /* Must be a power of two */ | |
0d8e0aa0 | 164 | |
55482edc | 165 | bool gro_disable; |
7c1bfcad SRK |
166 | struct list_head vlan_list; |
167 | u16 configured_vlans; | |
168 | u16 non_configured_vlans; | |
169 | bool accept_any_vlan; | |
0d8e0aa0 SK |
170 | struct delayed_work sp_task; |
171 | unsigned long sp_flags; | |
2950219d YM |
172 | }; |
173 | ||
174 | enum QEDE_STATE { | |
175 | QEDE_STATE_CLOSED, | |
176 | QEDE_STATE_OPEN, | |
177 | }; | |
178 | ||
179 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
180 | ||
181 | #define MAX_NUM_TC 8 | |
182 | #define MAX_NUM_PRI 8 | |
183 | ||
184 | /* The driver supports the new build_skb() API: | |
185 | * RX ring buffer contains pointer to kmalloc() data only, | |
186 | * skb are built only after the frame was DMA-ed. | |
187 | */ | |
188 | struct sw_rx_data { | |
fc48b7a6 YM |
189 | struct page *data; |
190 | dma_addr_t mapping; | |
191 | unsigned int page_offset; | |
2950219d YM |
192 | }; |
193 | ||
55482edc MC |
194 | enum qede_agg_state { |
195 | QEDE_AGG_STATE_NONE = 0, | |
196 | QEDE_AGG_STATE_START = 1, | |
197 | QEDE_AGG_STATE_ERROR = 2 | |
198 | }; | |
199 | ||
200 | struct qede_agg_info { | |
201 | struct sw_rx_data replace_buf; | |
202 | dma_addr_t replace_buf_mapping; | |
203 | struct sw_rx_data start_buf; | |
204 | dma_addr_t start_buf_mapping; | |
205 | struct eth_fast_path_rx_tpa_start_cqe start_cqe; | |
206 | enum qede_agg_state agg_state; | |
207 | struct sk_buff *skb; | |
208 | int frag_id; | |
209 | u16 vlan_tag; | |
210 | }; | |
211 | ||
2950219d YM |
212 | struct qede_rx_queue { |
213 | __le16 *hw_cons_ptr; | |
214 | struct sw_rx_data *sw_rx_ring; | |
215 | u16 sw_rx_cons; | |
216 | u16 sw_rx_prod; | |
217 | struct qed_chain rx_bd_ring; | |
218 | struct qed_chain rx_comp_ring; | |
219 | void __iomem *hw_rxq_prod_addr; | |
220 | ||
55482edc MC |
221 | /* GRO */ |
222 | struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM]; | |
223 | ||
2950219d | 224 | int rx_buf_size; |
fc48b7a6 | 225 | unsigned int rx_buf_seg_size; |
2950219d YM |
226 | |
227 | u16 num_rx_buffers; | |
228 | u16 rxq_id; | |
229 | ||
230 | u64 rx_hw_errors; | |
231 | u64 rx_alloc_errors; | |
232 | }; | |
233 | ||
234 | union db_prod { | |
235 | struct eth_db_data data; | |
236 | u32 raw; | |
237 | }; | |
238 | ||
239 | struct sw_tx_bd { | |
240 | struct sk_buff *skb; | |
241 | u8 flags; | |
242 | /* Set on the first BD descriptor when there is a split BD */ | |
243 | #define QEDE_TSO_SPLIT_BD BIT(0) | |
244 | }; | |
245 | ||
246 | struct qede_tx_queue { | |
247 | int index; /* Queue index */ | |
248 | __le16 *hw_cons_ptr; | |
249 | struct sw_tx_bd *sw_tx_ring; | |
250 | u16 sw_tx_cons; | |
251 | u16 sw_tx_prod; | |
252 | struct qed_chain tx_pbl; | |
253 | void __iomem *doorbell_addr; | |
254 | union db_prod tx_db; | |
255 | ||
256 | u16 num_tx_buffers; | |
257 | }; | |
258 | ||
259 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \ | |
260 | le32_to_cpu((bd)->addr.lo)) | |
261 | #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \ | |
262 | do { \ | |
263 | (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \ | |
264 | (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \ | |
265 | (bd)->nbytes = cpu_to_le16(len); \ | |
266 | } while (0) | |
267 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
268 | ||
269 | struct qede_fastpath { | |
270 | struct qede_dev *edev; | |
271 | u8 rss_id; | |
272 | struct napi_struct napi; | |
273 | struct qed_sb_info *sb_info; | |
274 | struct qede_rx_queue *rxq; | |
275 | struct qede_tx_queue *txqs; | |
276 | ||
277 | #define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
278 | char name[VEC_NAME_SIZE]; | |
e712d52b YM |
279 | }; |
280 | ||
281 | /* Debug print definitions */ | |
282 | #define DP_NAME(edev) ((edev)->ndev->name) | |
283 | ||
2950219d YM |
284 | #define XMIT_PLAIN 0 |
285 | #define XMIT_L4_CSUM BIT(0) | |
286 | #define XMIT_LSO BIT(1) | |
287 | #define XMIT_ENC BIT(2) | |
288 | ||
289 | #define QEDE_CSUM_ERROR BIT(0) | |
290 | #define QEDE_CSUM_UNNECESSARY BIT(1) | |
0d8e0aa0 SK |
291 | |
292 | #define QEDE_SP_RX_MODE 1 | |
293 | ||
294 | union qede_reload_args { | |
295 | u16 mtu; | |
296 | }; | |
297 | ||
133fac0e SK |
298 | void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level); |
299 | void qede_set_ethtool_ops(struct net_device *netdev); | |
300 | void qede_reload(struct qede_dev *edev, | |
301 | void (*func)(struct qede_dev *edev, | |
302 | union qede_reload_args *args), | |
303 | union qede_reload_args *args); | |
304 | int qede_change_mtu(struct net_device *dev, int new_mtu); | |
305 | void qede_fill_by_demand_stats(struct qede_dev *edev); | |
306 | ||
2950219d | 307 | #define RX_RING_SIZE_POW 13 |
01ef7e05 | 308 | #define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW)) |
2950219d YM |
309 | #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1) |
310 | #define NUM_RX_BDS_MIN 128 | |
311 | #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX | |
312 | ||
313 | #define TX_RING_SIZE_POW 13 | |
01ef7e05 | 314 | #define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW)) |
2950219d YM |
315 | #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1) |
316 | #define NUM_TX_BDS_MIN 128 | |
317 | #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX | |
318 | ||
fc48b7a6 | 319 | #define QEDE_RX_HDR_SIZE 256 |
2950219d YM |
320 | #define for_each_rss(i) for (i = 0; i < edev->num_rss; i++) |
321 | ||
e712d52b | 322 | #endif /* _QEDE_H_ */ |