projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qed*: Support PVID configuration
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
b18e170c 27#ifdef CONFIG_QEDE_VXLAN
e712d52b 28#include <net/vxlan.h>
b18e170c 29#endif
9a109dd0
MC		 30#ifdef CONFIG_QEDE_GENEVE
31#include <net/geneve.h>
32#endif
e712d52b
YM		 33#include <linux/ip.h>
34#include <net/ipv6.h>
35#include <net/tcp.h>
36#include <linux/if_ether.h>
37#include <linux/if_vlan.h>
38#include <linux/pkt_sched.h>
39#include <linux/ethtool.h>
40#include <linux/in.h>
41#include <linux/random.h>
42#include <net/ip6_checksum.h>
43#include <linux/bitops.h>
44
45#include "qede.h"
46
5abd7e92
YM		 47static char version[] =
48 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 49
5abd7e92 50MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_MODULE_VERSION);
53
54static uint debug;
55module_param(debug, uint, 0);
56MODULE_PARM_DESC(debug, " Default debug msglevel");
57
58static const struct qed_eth_ops *qed_ops;
59
60#define CHIP_NUM_57980S_40 0x1634
0e7441d7 61#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 62#define CHIP_NUM_57980S_MF 0x1636
63#define CHIP_NUM_57980S_100 0x1644
64#define CHIP_NUM_57980S_50 0x1654
65#define CHIP_NUM_57980S_25 0x1656
fefb0202 66#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 67
68#ifndef PCI_DEVICE_ID_NX2_57980E
69#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
70#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
71#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
72#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
73#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
74#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 75#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 76#endif
77
fefb0202
YM		 78enum qede_pci_private {
79 QEDE_PRIVATE_PF,
80 QEDE_PRIVATE_VF
81};
82
e712d52b 83static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
85 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
87 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
88 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
89 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
90 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
e712d52b
YM		 91 { 0 }
92};
93
94MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
95
96static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
97
98#define TX_TIMEOUT (5 * HZ)
99
100static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 101static int qede_alloc_rx_buffer(struct qede_dev *edev,
102 struct qede_rx_queue *rxq);
a2ec6172 103static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 104
fefb0202 105#ifdef CONFIG_QED_SRIOV
08feecd7
YM		 106static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
107{
108 struct qede_dev *edev = netdev_priv(ndev);
109
110 if (vlan > 4095) {
111 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
112 return -EINVAL;
113 }
114
115 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
116 vlan, vf);
117
118 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
119}
120
fefb0202
YM		 121static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
122{
123 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
124
125 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
126
127 return edev->ops->iov->configure(edev->cdev, num_vfs_param);
128}
129#endif
130
e712d52b
YM		 131static struct pci_driver qede_pci_driver = {
132 .name = "qede",
133 .id_table = qede_pci_tbl,
134 .probe = qede_probe,
135 .remove = qede_remove,
fefb0202
YM		 136#ifdef CONFIG_QED_SRIOV
137 .sriov_configure = qede_sriov_configure,
138#endif
e712d52b
YM		 139};
140
a2ec6172
SK		 141static struct qed_eth_cb_ops qede_ll_ops = {
142 {
143 .link_update = qede_link_update,
144 },
145};
146
2950219d
YM		 147static int qede_netdev_event(struct notifier_block *this, unsigned long event,
148 void *ptr)
149{
150 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
151 struct ethtool_drvinfo drvinfo;
152 struct qede_dev *edev;
153
154 /* Currently only support name change */
155 if (event != NETDEV_CHANGENAME)
156 goto done;
157
158 /* Check whether this is a qede device */
159 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
160 goto done;
161
162 memset(&drvinfo, 0, sizeof(drvinfo));
163 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
164 if (strcmp(drvinfo.driver, "qede"))
165 goto done;
166 edev = netdev_priv(ndev);
167
168 /* Notify qed of the name change */
169 if (!edev->ops || !edev->ops->common)
170 goto done;
171 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
172 "qede");
173
174done:
175 return NOTIFY_DONE;
176}
177
178static struct notifier_block qede_netdev_notifier = {
179 .notifier_call = qede_netdev_event,
180};
181
e712d52b
YM		 182static
183int __init qede_init(void)
184{
185 int ret;
e712d52b
YM		 186
187 pr_notice("qede_init: %s\n", version);
188
95114344 189 qed_ops = qed_get_eth_ops();
e712d52b
YM		 190 if (!qed_ops) {
191 pr_notice("Failed to get qed ethtool operations\n");
192 return -EINVAL;
193 }
194
2950219d
YM		 195 /* Must register notifier before pci ops, since we might miss
196 * interface rename after pci probe and netdev registeration.
197 */
198 ret = register_netdevice_notifier(&qede_netdev_notifier);
199 if (ret) {
200 pr_notice("Failed to register netdevice_notifier\n");
201 qed_put_eth_ops();
202 return -EINVAL;
203 }
204
e712d52b
YM		 205 ret = pci_register_driver(&qede_pci_driver);
206 if (ret) {
207 pr_notice("Failed to register driver\n");
2950219d 208 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 209 qed_put_eth_ops();
210 return -EINVAL;
211 }
212
213 return 0;
214}
215
216static void __exit qede_cleanup(void)
217{
218 pr_notice("qede_cleanup called\n");
219
2950219d 220 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 221 pci_unregister_driver(&qede_pci_driver);
222 qed_put_eth_ops();
223}
224
225module_init(qede_init);
226module_exit(qede_cleanup);
227
2950219d
YM		 228/* -------------------------------------------------------------------------
229 * START OF FAST-PATH
230 * -------------------------------------------------------------------------
231 */
232
233/* Unmap the data and free skb */
234static int qede_free_tx_pkt(struct qede_dev *edev,
235 struct qede_tx_queue *txq,
236 int *len)
237{
238 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
239 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
240 struct eth_tx_1st_bd *first_bd;
241 struct eth_tx_bd *tx_data_bd;
242 int bds_consumed = 0;
243 int nbds;
244 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
245 int i, split_bd_len = 0;
246
247 if (unlikely(!skb)) {
248 DP_ERR(edev,
249 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
250 idx, txq->sw_tx_cons, txq->sw_tx_prod);
251 return -1;
252 }
253
254 *len = skb->len;
255
256 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
257
258 bds_consumed++;
259
260 nbds = first_bd->data.nbds;
261
262 if (data_split) {
263 struct eth_tx_bd *split = (struct eth_tx_bd *)
264 qed_chain_consume(&txq->tx_pbl);
265 split_bd_len = BD_UNMAP_LEN(split);
266 bds_consumed++;
267 }
268 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
269 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
270
271 /* Unmap the data of the skb frags */
272 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
273 tx_data_bd = (struct eth_tx_bd *)
274 qed_chain_consume(&txq->tx_pbl);
275 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
276 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
277 }
278
279 while (bds_consumed++ < nbds)
280 qed_chain_consume(&txq->tx_pbl);
281
282 /* Free skb */
283 dev_kfree_skb_any(skb);
284 txq->sw_tx_ring[idx].skb = NULL;
285 txq->sw_tx_ring[idx].flags = 0;
286
287 return 0;
288}
289
290/* Unmap the data and free skb when mapping failed during start_xmit */
291static void qede_free_failed_tx_pkt(struct qede_dev *edev,
292 struct qede_tx_queue *txq,
293 struct eth_tx_1st_bd *first_bd,
294 int nbd,
295 bool data_split)
296{
297 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
298 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
299 struct eth_tx_bd *tx_data_bd;
300 int i, split_bd_len = 0;
301
302 /* Return prod to its position before this skb was handled */
303 qed_chain_set_prod(&txq->tx_pbl,
304 le16_to_cpu(txq->tx_db.data.bd_prod),
305 first_bd);
306
307 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
308
309 if (data_split) {
310 struct eth_tx_bd *split = (struct eth_tx_bd *)
311 qed_chain_produce(&txq->tx_pbl);
312 split_bd_len = BD_UNMAP_LEN(split);
313 nbd--;
314 }
315
316 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
317 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
318
319 /* Unmap the data of the skb frags */
320 for (i = 0; i < nbd; i++) {
321 tx_data_bd = (struct eth_tx_bd *)
322 qed_chain_produce(&txq->tx_pbl);
323 if (tx_data_bd->nbytes)
324 dma_unmap_page(&edev->pdev->dev,
325 BD_UNMAP_ADDR(tx_data_bd),
326 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
327 }
328
329 /* Return again prod to its position before this skb was handled */
330 qed_chain_set_prod(&txq->tx_pbl,
331 le16_to_cpu(txq->tx_db.data.bd_prod),
332 first_bd);
333
334 /* Free skb */
335 dev_kfree_skb_any(skb);
336 txq->sw_tx_ring[idx].skb = NULL;
337 txq->sw_tx_ring[idx].flags = 0;
338}
339
340static u32 qede_xmit_type(struct qede_dev *edev,
341 struct sk_buff *skb,
342 int *ipv6_ext)
343{
344 u32 rc = XMIT_L4_CSUM;
345 __be16 l3_proto;
346
347 if (skb->ip_summed != CHECKSUM_PARTIAL)
348 return XMIT_PLAIN;
349
350 l3_proto = vlan_get_protocol(skb);
351 if (l3_proto == htons(ETH_P_IPV6) &&
352 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
353 *ipv6_ext = 1;
354
14db81de
MC		 355 if (skb->encapsulation)
356 rc |= XMIT_ENC;
357
2950219d
YM		 358 if (skb_is_gso(skb))
359 rc |= XMIT_LSO;
360
361 return rc;
362}
363
364static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
365 struct eth_tx_2nd_bd *second_bd,
366 struct eth_tx_3rd_bd *third_bd)
367{
368 u8 l4_proto;
fc48b7a6 369 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 370
fc48b7a6 371 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 372
fc48b7a6 373 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 374 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
375 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
376
fc48b7a6 377 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 378 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
379
380 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
381 l4_proto = ipv6_hdr(skb)->nexthdr;
382 else
383 l4_proto = ip_hdr(skb)->protocol;
384
385 if (l4_proto == IPPROTO_UDP)
fc48b7a6 386 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 387
fc48b7a6 388 if (third_bd)
2950219d 389 third_bd->data.bitfields |=
fc48b7a6
YM		 390 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
391 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
392 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 393
fc48b7a6 394 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 395 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
396}
397
398static int map_frag_to_bd(struct qede_dev *edev,
399 skb_frag_t *frag,
400 struct eth_tx_bd *bd)
401{
402 dma_addr_t mapping;
403
404 /* Map skb non-linear frag data for DMA */
405 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
406 skb_frag_size(frag),
407 DMA_TO_DEVICE);
408 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
409 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
410 return -ENOMEM;
411 }
412
413 /* Setup the data pointer of the frag data */
414 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
415
416 return 0;
417}
418
14db81de
MC		 419static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
420{
421 if (is_encap_pkt)
422 return (skb_inner_transport_header(skb) +
423 inner_tcp_hdrlen(skb) - skb->data);
424 else
425 return (skb_transport_header(skb) +
426 tcp_hdrlen(skb) - skb->data);
427}
428
b1199b10
YM		 429/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
430#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
431static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
432 u8 xmit_type)
433{
434 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
435
436 if (xmit_type & XMIT_LSO) {
437 int hlen;
438
14db81de 439 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 440
441 /* linear payload would require its own BD */
442 if (skb_headlen(skb) > hlen)
443 allowed_frags--;
444 }
445
446 return (skb_shinfo(skb)->nr_frags > allowed_frags);
447}
448#endif
449
2950219d
YM		 450/* Main transmit function */
451static
452netdev_tx_t qede_start_xmit(struct sk_buff *skb,
453 struct net_device *ndev)
454{
455 struct qede_dev *edev = netdev_priv(ndev);
456 struct netdev_queue *netdev_txq;
457 struct qede_tx_queue *txq;
458 struct eth_tx_1st_bd *first_bd;
459 struct eth_tx_2nd_bd *second_bd = NULL;
460 struct eth_tx_3rd_bd *third_bd = NULL;
461 struct eth_tx_bd *tx_data_bd = NULL;
462 u16 txq_index;
463 u8 nbd = 0;
464 dma_addr_t mapping;
465 int rc, frag_idx = 0, ipv6_ext = 0;
466 u8 xmit_type;
467 u16 idx;
468 u16 hlen;
810810ff 469 bool data_split = false;
2950219d
YM		 470
471 /* Get tx-queue context and netdev index */
472 txq_index = skb_get_queue_mapping(skb);
473 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
474 txq = QEDE_TX_QUEUE(edev, txq_index);
475 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
476
2950219d
YM		 477 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) <
478 (MAX_SKB_FRAGS + 1));
479
480 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
481
b1199b10
YM		 482#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
483 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
484 if (skb_linearize(skb)) {
485 DP_NOTICE(edev,
486 "SKB linearization failed - silently dropping this SKB\n");
487 dev_kfree_skb_any(skb);
488 return NETDEV_TX_OK;
489 }
490 }
491#endif
492
2950219d
YM		 493 /* Fill the entry in the SW ring and the BDs in the FW ring */
494 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
495 txq->sw_tx_ring[idx].skb = skb;
496 first_bd = (struct eth_tx_1st_bd *)
497 qed_chain_produce(&txq->tx_pbl);
498 memset(first_bd, 0, sizeof(*first_bd));
499 first_bd->data.bd_flags.bitfields =
500 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
501
502 /* Map skb linear data for DMA and set in the first BD */
503 mapping = dma_map_single(&edev->pdev->dev, skb->data,
504 skb_headlen(skb), DMA_TO_DEVICE);
505 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
506 DP_NOTICE(edev, "SKB mapping failed\n");
507 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
508 return NETDEV_TX_OK;
509 }
510 nbd++;
511 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
512
513 /* In case there is IPv6 with extension headers or LSO we need 2nd and
514 * 3rd BDs.
515 */
516 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
517 second_bd = (struct eth_tx_2nd_bd *)
518 qed_chain_produce(&txq->tx_pbl);
519 memset(second_bd, 0, sizeof(*second_bd));
520
521 nbd++;
522 third_bd = (struct eth_tx_3rd_bd *)
523 qed_chain_produce(&txq->tx_pbl);
524 memset(third_bd, 0, sizeof(*third_bd));
525
526 nbd++;
527 /* We need to fill in additional data in second_bd... */
528 tx_data_bd = (struct eth_tx_bd *)second_bd;
529 }
530
531 if (skb_vlan_tag_present(skb)) {
532 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
533 first_bd->data.bd_flags.bitfields |=
534 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
535 }
536
537 /* Fill the parsing flags & params according to the requested offload */
538 if (xmit_type & XMIT_L4_CSUM) {
fc48b7a6
YM		 539 u16 temp = 1 << ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT;
540
2950219d
YM		 541 /* We don't re-calculate IP checksum as it is already done by
542 * the upper stack
543 */
544 first_bd->data.bd_flags.bitfields |=
545 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
546
14db81de
MC		 547 if (xmit_type & XMIT_ENC) {
548 first_bd->data.bd_flags.bitfields |=
549 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
550 } else {
551 /* In cases when OS doesn't indicate for inner offloads
552 * when packet is tunnelled, we need to override the HW
553 * tunnel configuration so that packets are treated as
554 * regular non tunnelled packets and no inner offloads
555 * are done by the hardware.
556 */
557 first_bd->data.bitfields |= cpu_to_le16(temp);
558 }
fc48b7a6 559
2950219d
YM		 560 /* If the packet is IPv6 with extension header, indicate that
561 * to FW and pass few params, since the device cracker doesn't
562 * support parsing IPv6 with extension header/s.
563 */
564 if (unlikely(ipv6_ext))
565 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
566 }
567
568 if (xmit_type & XMIT_LSO) {
569 first_bd->data.bd_flags.bitfields |=
570 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
571 third_bd->data.lso_mss =
572 cpu_to_le16(skb_shinfo(skb)->gso_size);
573
14db81de
MC		 574 if (unlikely(xmit_type & XMIT_ENC)) {
575 first_bd->data.bd_flags.bitfields |=
576 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
577 hlen = qede_get_skb_hlen(skb, true);
578 } else {
579 first_bd->data.bd_flags.bitfields |=
580 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
581 hlen = qede_get_skb_hlen(skb, false);
582 }
2950219d
YM		 583
584 /* @@@TBD - if will not be removed need to check */
585 third_bd->data.bitfields |=
fc48b7a6 586 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 587
588 /* Make life easier for FW guys who can't deal with header and
589 * data on same BD. If we need to split, use the second bd...
590 */
591 if (unlikely(skb_headlen(skb) > hlen)) {
592 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
593 "TSO split header size is %d (%x:%x)\n",
594 first_bd->nbytes, first_bd->addr.hi,
595 first_bd->addr.lo);
596
597 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
598 le32_to_cpu(first_bd->addr.lo)) +
599 hlen;
600
601 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
602 le16_to_cpu(first_bd->nbytes) -
603 hlen);
604
605 /* this marks the BD as one that has no
606 * individual mapping
607 */
608 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
609
610 first_bd->nbytes = cpu_to_le16(hlen);
611
612 tx_data_bd = (struct eth_tx_bd *)third_bd;
613 data_split = true;
614 }
615 }
616
617 /* Handle fragmented skb */
618 /* special handle for frags inside 2nd and 3rd bds.. */
619 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
620 rc = map_frag_to_bd(edev,
621 &skb_shinfo(skb)->frags[frag_idx],
622 tx_data_bd);
623 if (rc) {
624 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
625 data_split);
626 return NETDEV_TX_OK;
627 }
628
629 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
630 tx_data_bd = (struct eth_tx_bd *)third_bd;
631 else
632 tx_data_bd = NULL;
633
634 frag_idx++;
635 }
636
637 /* map last frags into 4th, 5th .... */
638 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
639 tx_data_bd = (struct eth_tx_bd *)
640 qed_chain_produce(&txq->tx_pbl);
641
642 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
643
644 rc = map_frag_to_bd(edev,
645 &skb_shinfo(skb)->frags[frag_idx],
646 tx_data_bd);
647 if (rc) {
648 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
649 data_split);
650 return NETDEV_TX_OK;
651 }
652 }
653
654 /* update the first BD with the actual num BDs */
655 first_bd->data.nbds = nbd;
656
657 netdev_tx_sent_queue(netdev_txq, skb->len);
658
659 skb_tx_timestamp(skb);
660
661 /* Advance packet producer only before sending the packet since mapping
662 * of pages may fail.
663 */
664 txq->sw_tx_prod++;
665
666 /* 'next page' entries are counted in the producer value */
667 txq->tx_db.data.bd_prod =
668 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
669
670 /* wmb makes sure that the BDs data is updated before updating the
671 * producer, otherwise FW may read old data from the BDs.
672 */
673 wmb();
674 barrier();
675 writel(txq->tx_db.raw, txq->doorbell_addr);
676
677 /* mmiowb is needed to synchronize doorbell writes from more than one
678 * processor. It guarantees that the write arrives to the device before
679 * the queue lock is released and another start_xmit is called (possibly
680 * on another CPU). Without this barrier, the next doorbell can bypass
681 * this doorbell. This is applicable to IA64/Altix systems.
682 */
683 mmiowb();
684
685 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
686 < (MAX_SKB_FRAGS + 1))) {
687 netif_tx_stop_queue(netdev_txq);
688 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
689 "Stop queue was called\n");
690 /* paired memory barrier is in qede_tx_int(), we have to keep
691 * ordering of set_bit() in netif_tx_stop_queue() and read of
692 * fp->bd_tx_cons
693 */
694 smp_mb();
695
696 if (qed_chain_get_elem_left(&txq->tx_pbl)
697 >= (MAX_SKB_FRAGS + 1) &&
698 (edev->state == QEDE_STATE_OPEN)) {
699 netif_tx_wake_queue(netdev_txq);
700 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
701 "Wake queue was called\n");
702 }
703 }
704
705 return NETDEV_TX_OK;
706}
707
16f46bf0 708int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 709{
710 u16 hw_bd_cons;
711
712 /* Tell compiler that consumer and producer can change */
713 barrier();
714 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
715 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
716 return 0;
717
718 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
719}
720
721static int qede_tx_int(struct qede_dev *edev,
722 struct qede_tx_queue *txq)
723{
724 struct netdev_queue *netdev_txq;
725 u16 hw_bd_cons;
726 unsigned int pkts_compl = 0, bytes_compl = 0;
727 int rc;
728
729 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
730
731 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
732 barrier();
733
734 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
735 int len = 0;
736
737 rc = qede_free_tx_pkt(edev, txq, &len);
738 if (rc) {
739 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
740 hw_bd_cons,
741 qed_chain_get_cons_idx(&txq->tx_pbl));
742 break;
743 }
744
745 bytes_compl += len;
746 pkts_compl++;
747 txq->sw_tx_cons++;
748 }
749
750 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
751
752 /* Need to make the tx_bd_cons update visible to start_xmit()
753 * before checking for netif_tx_queue_stopped(). Without the
754 * memory barrier, there is a small possibility that
755 * start_xmit() will miss it and cause the queue to be stopped
756 * forever.
757 * On the other hand we need an rmb() here to ensure the proper
758 * ordering of bit testing in the following
759 * netif_tx_queue_stopped(txq) call.
760 */
761 smp_mb();
762
763 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
764 /* Taking tx_lock is needed to prevent reenabling the queue
765 * while it's empty. This could have happen if rx_action() gets
766 * suspended in qede_tx_int() after the condition before
767 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
768 *
769 * stops the queue->sees fresh tx_bd_cons->releases the queue->
770 * sends some packets consuming the whole queue again->
771 * stops the queue
772 */
773
774 __netif_tx_lock(netdev_txq, smp_processor_id());
775
776 if ((netif_tx_queue_stopped(netdev_txq)) &&
777 (edev->state == QEDE_STATE_OPEN) &&
778 (qed_chain_get_elem_left(&txq->tx_pbl)
779 >= (MAX_SKB_FRAGS + 1))) {
780 netif_tx_wake_queue(netdev_txq);
781 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
782 "Wake queue was called\n");
783 }
784
785 __netif_tx_unlock(netdev_txq);
786 }
787
788 return 0;
789}
790
16f46bf0 791bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 792{
793 u16 hw_comp_cons, sw_comp_cons;
794
795 /* Tell compiler that status block fields can change */
796 barrier();
797
798 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
799 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
800
801 return hw_comp_cons != sw_comp_cons;
802}
803
804static bool qede_has_tx_work(struct qede_fastpath *fp)
805{
806 u8 tc;
807
808 for (tc = 0; tc < fp->edev->num_tc; tc++)
809 if (qede_txq_has_work(&fp->txqs[tc]))
810 return true;
811 return false;
812}
813
f86af2df
MC		 814static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
815{
816 qed_chain_consume(&rxq->rx_bd_ring);
817 rxq->sw_rx_cons++;
818}
819
fc48b7a6
YM		 820/* This function reuses the buffer(from an offset) from
821 * consumer index to producer index in the bd ring
2950219d 822 */
fc48b7a6
YM		 823static inline void qede_reuse_page(struct qede_dev *edev,
824 struct qede_rx_queue *rxq,
825 struct sw_rx_data *curr_cons)
2950219d 826{
2950219d 827 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 828 struct sw_rx_data *curr_prod;
829 dma_addr_t new_mapping;
2950219d 830
fc48b7a6
YM		 831 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
832 *curr_prod = *curr_cons;
2950219d 833
fc48b7a6
YM		 834 new_mapping = curr_prod->mapping + curr_prod->page_offset;
835
836 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
837 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 838
2950219d 839 rxq->sw_rx_prod++;
fc48b7a6
YM		 840 curr_cons->data = NULL;
841}
842
f86af2df
MC		 843/* In case of allocation failures reuse buffers
844 * from consumer index to produce buffers for firmware
845 */
16f46bf0
SRK		 846void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
847 struct qede_dev *edev, u8 count)
f86af2df
MC		 848{
849 struct sw_rx_data *curr_cons;
850
851 for (; count > 0; count--) {
852 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
853 qede_reuse_page(edev, rxq, curr_cons);
854 qede_rx_bd_ring_consume(rxq);
855 }
856}
857
fc48b7a6
YM		 858static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
859 struct qede_rx_queue *rxq,
860 struct sw_rx_data *curr_cons)
861{
862 /* Move to the next segment in the page */
863 curr_cons->page_offset += rxq->rx_buf_seg_size;
864
865 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 866 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
867 /* Since we failed to allocate new buffer
868 * current buffer can be used again.
869 */
870 curr_cons->page_offset -= rxq->rx_buf_seg_size;
871
fc48b7a6 872 return -ENOMEM;
f86af2df 873 }
fc48b7a6
YM		 874
875 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
876 PAGE_SIZE, DMA_FROM_DEVICE);
877 } else {
878 /* Increment refcount of the page as we don't want
879 * network stack to take the ownership of the page
880 * which can be recycled multiple times by the driver.
881 */
882 atomic_inc(&curr_cons->data->_count);
883 qede_reuse_page(edev, rxq, curr_cons);
884 }
885
886 return 0;
2950219d
YM		 887}
888
889static inline void qede_update_rx_prod(struct qede_dev *edev,
890 struct qede_rx_queue *rxq)
891{
892 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
893 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
894 struct eth_rx_prod_data rx_prods = {0};
895
896 /* Update producers */
897 rx_prods.bd_prod = cpu_to_le16(bd_prod);
898 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
899
900 /* Make sure that the BD and SGE data is updated before updating the
901 * producers since FW might read the BD/SGE right after the producer
902 * is updated.
903 */
904 wmb();
905
906 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
907 (u32 *)&rx_prods);
908
909 /* mmiowb is needed to synchronize doorbell writes from more than one
910 * processor. It guarantees that the write arrives to the device before
911 * the napi lock is released and another qede_poll is called (possibly
912 * on another CPU). Without this barrier, the next doorbell can bypass
913 * this doorbell. This is applicable to IA64/Altix systems.
914 */
915 mmiowb();
916}
917
918static u32 qede_get_rxhash(struct qede_dev *edev,
919 u8 bitfields,
920 __le32 rss_hash,
921 enum pkt_hash_types *rxhash_type)
922{
923 enum rss_hash_type htype;
924
925 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
926
927 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
928 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
929 (htype == RSS_HASH_TYPE_IPV6)) ?
930 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
931 return le32_to_cpu(rss_hash);
932 }
933 *rxhash_type = PKT_HASH_TYPE_NONE;
934 return 0;
935}
936
937static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
938{
939 skb_checksum_none_assert(skb);
940
941 if (csum_flag & QEDE_CSUM_UNNECESSARY)
942 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 943
944 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
945 skb->csum_level = 1;
2950219d
YM		 946}
947
948static inline void qede_skb_receive(struct qede_dev *edev,
949 struct qede_fastpath *fp,
950 struct sk_buff *skb,
951 u16 vlan_tag)
952{
953 if (vlan_tag)
954 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
955 vlan_tag);
956
957 napi_gro_receive(&fp->napi, skb);
958}
959
55482edc
MC		 960static void qede_set_gro_params(struct qede_dev *edev,
961 struct sk_buff *skb,
962 struct eth_fast_path_rx_tpa_start_cqe *cqe)
963{
964 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
965
966 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
967 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
968 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
969 else
970 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
971
972 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
973 cqe->header_len;
974}
975
976static int qede_fill_frag_skb(struct qede_dev *edev,
977 struct qede_rx_queue *rxq,
978 u8 tpa_agg_index,
979 u16 len_on_bd)
980{
981 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
982 NUM_RX_BDS_MAX];
983 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
984 struct sk_buff *skb = tpa_info->skb;
985
986 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
987 goto out;
988
989 /* Add one frag and update the appropriate fields in the skb */
990 skb_fill_page_desc(skb, tpa_info->frag_id++,
991 current_bd->data, current_bd->page_offset,
992 len_on_bd);
993
994 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 995 /* Incr page ref count to reuse on allocation failure
996 * so that it doesn't get freed while freeing SKB.
997 */
998 atomic_inc(&current_bd->data->_count);
55482edc
MC		 999 goto out;
1000 }
1001
1002 qed_chain_consume(&rxq->rx_bd_ring);
1003 rxq->sw_rx_cons++;
1004
1005 skb->data_len += len_on_bd;
1006 skb->truesize += rxq->rx_buf_seg_size;
1007 skb->len += len_on_bd;
1008
1009 return 0;
1010
1011out:
f86af2df
MC		 1012 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1013 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1014 return -ENOMEM;
1015}
1016
1017static void qede_tpa_start(struct qede_dev *edev,
1018 struct qede_rx_queue *rxq,
1019 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1020{
1021 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1022 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1023 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
1024 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
1025 dma_addr_t mapping = tpa_info->replace_buf_mapping;
1026 struct sw_rx_data *sw_rx_data_cons;
1027 struct sw_rx_data *sw_rx_data_prod;
1028 enum pkt_hash_types rxhash_type;
1029 u32 rxhash;
1030
1031 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1032 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1033
1034 /* Use pre-allocated replacement buffer - we can't release the agg.
1035 * start until its over and we don't want to risk allocation failing
1036 * here, so re-allocate when aggregation will be over.
1037 */
1038 dma_unmap_addr_set(sw_rx_data_prod, mapping,
1039 dma_unmap_addr(replace_buf, mapping));
1040
1041 sw_rx_data_prod->data = replace_buf->data;
1042 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1043 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1044 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1045
1046 rxq->sw_rx_prod++;
1047
1048 /* move partial skb from cons to pool (don't unmap yet)
1049 * save mapping, incase we drop the packet later on.
1050 */
1051 tpa_info->start_buf = *sw_rx_data_cons;
1052 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1053 le32_to_cpu(rx_bd_cons->addr.lo));
1054
1055 tpa_info->start_buf_mapping = mapping;
1056 rxq->sw_rx_cons++;
1057
1058 /* set tpa state to start only if we are able to allocate skb
1059 * for this aggregation, otherwise mark as error and aggregation will
1060 * be dropped
1061 */
1062 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1063 le16_to_cpu(cqe->len_on_first_bd));
1064 if (unlikely(!tpa_info->skb)) {
f86af2df 1065 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1066 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1067 goto cons_buf;
55482edc
MC		 1068 }
1069
1070 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1071 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1072
1073 /* Start filling in the aggregation info */
1074 tpa_info->frag_id = 0;
1075 tpa_info->agg_state = QEDE_AGG_STATE_START;
1076
1077 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1078 cqe->rss_hash, &rxhash_type);
1079 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1080 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1081 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1082 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1083 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1084 else
1085 tpa_info->vlan_tag = 0;
1086
1087 /* This is needed in order to enable forwarding support */
1088 qede_set_gro_params(edev, tpa_info->skb, cqe);
1089
f86af2df 1090cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1091 if (likely(cqe->ext_bd_len_list[0]))
1092 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1093 le16_to_cpu(cqe->ext_bd_len_list[0]));
1094
1095 if (unlikely(cqe->ext_bd_len_list[1])) {
1096 DP_ERR(edev,
1097 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1098 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1099 }
1100}
1101
88f09bd5 1102#ifdef CONFIG_INET
55482edc
MC		 1103static void qede_gro_ip_csum(struct sk_buff *skb)
1104{
1105 const struct iphdr *iph = ip_hdr(skb);
1106 struct tcphdr *th;
1107
55482edc
MC		 1108 skb_set_transport_header(skb, sizeof(struct iphdr));
1109 th = tcp_hdr(skb);
1110
1111 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1112 iph->saddr, iph->daddr, 0);
1113
1114 tcp_gro_complete(skb);
1115}
1116
1117static void qede_gro_ipv6_csum(struct sk_buff *skb)
1118{
1119 struct ipv6hdr *iph = ipv6_hdr(skb);
1120 struct tcphdr *th;
1121
55482edc
MC		 1122 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1123 th = tcp_hdr(skb);
1124
1125 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1126 &iph->saddr, &iph->daddr, 0);
1127 tcp_gro_complete(skb);
1128}
88f09bd5 1129#endif
55482edc
MC		 1130
1131static void qede_gro_receive(struct qede_dev *edev,
1132 struct qede_fastpath *fp,
1133 struct sk_buff *skb,
1134 u16 vlan_tag)
1135{
ee2fa8e6
MC		 1136 /* FW can send a single MTU sized packet from gro flow
1137 * due to aggregation timeout/last segment etc. which
1138 * is not expected to be a gro packet. If a skb has zero
1139 * frags then simply push it in the stack as non gso skb.
1140 */
1141 if (unlikely(!skb->data_len)) {
1142 skb_shinfo(skb)->gso_type = 0;
1143 skb_shinfo(skb)->gso_size = 0;
1144 goto send_skb;
1145 }
1146
88f09bd5 1147#ifdef CONFIG_INET
55482edc 1148 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1149 skb_set_network_header(skb, 0);
1150
55482edc
MC		 1151 switch (skb->protocol) {
1152 case htons(ETH_P_IP):
1153 qede_gro_ip_csum(skb);
1154 break;
1155 case htons(ETH_P_IPV6):
1156 qede_gro_ipv6_csum(skb);
1157 break;
1158 default:
1159 DP_ERR(edev,
1160 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1161 ntohs(skb->protocol));
1162 }
1163 }
88f09bd5 1164#endif
ee2fa8e6
MC		 1165
1166send_skb:
55482edc
MC		 1167 skb_record_rx_queue(skb, fp->rss_id);
1168 qede_skb_receive(edev, fp, skb, vlan_tag);
1169}
1170
1171static inline void qede_tpa_cont(struct qede_dev *edev,
1172 struct qede_rx_queue *rxq,
1173 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1174{
1175 int i;
1176
1177 for (i = 0; cqe->len_list[i]; i++)
1178 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1179 le16_to_cpu(cqe->len_list[i]));
1180
1181 if (unlikely(i > 1))
1182 DP_ERR(edev,
1183 "Strange - TPA cont with more than a single len_list entry\n");
1184}
1185
1186static void qede_tpa_end(struct qede_dev *edev,
1187 struct qede_fastpath *fp,
1188 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1189{
1190 struct qede_rx_queue *rxq = fp->rxq;
1191 struct qede_agg_info *tpa_info;
1192 struct sk_buff *skb;
1193 int i;
1194
1195 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1196 skb = tpa_info->skb;
1197
1198 for (i = 0; cqe->len_list[i]; i++)
1199 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1200 le16_to_cpu(cqe->len_list[i]));
1201 if (unlikely(i > 1))
1202 DP_ERR(edev,
1203 "Strange - TPA emd with more than a single len_list entry\n");
1204
1205 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1206 goto err;
1207
1208 /* Sanity */
1209 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1210 DP_ERR(edev,
1211 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1212 cqe->num_of_bds, tpa_info->frag_id);
1213 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1214 DP_ERR(edev,
1215 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1216 le16_to_cpu(cqe->total_packet_len), skb->len);
1217
1218 memcpy(skb->data,
1219 page_address(tpa_info->start_buf.data) +
1220 tpa_info->start_cqe.placement_offset +
1221 tpa_info->start_buf.page_offset,
1222 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1223
1224 /* Recycle [mapped] start buffer for the next replacement */
1225 tpa_info->replace_buf = tpa_info->start_buf;
1226 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1227
1228 /* Finalize the SKB */
1229 skb->protocol = eth_type_trans(skb, edev->ndev);
1230 skb->ip_summed = CHECKSUM_UNNECESSARY;
1231
1232 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1233 * to skb_shinfo(skb)->gso_segs
1234 */
1235 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1236
1237 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1238
1239 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1240
1241 return;
1242err:
1243 /* The BD starting the aggregation is still mapped; Re-use it for
1244 * future aggregations [as replacement buffer]
1245 */
1246 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1247 sizeof(struct sw_rx_data));
1248 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1249 tpa_info->start_buf.data = NULL;
1250 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1251 dev_kfree_skb_any(tpa_info->skb);
1252 tpa_info->skb = NULL;
1253}
1254
14db81de
MC		 1255static bool qede_tunn_exist(u16 flag)
1256{
1257 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1258 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1259}
1260
1261static u8 qede_check_tunn_csum(u16 flag)
1262{
1263 u16 csum_flag = 0;
1264 u8 tcsum = 0;
1265
1266 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1267 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1268 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1269 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1270
1271 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1272 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1273 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1274 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1275 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1276 }
1277
1278 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1279 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1280 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1281 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1282
1283 if (csum_flag & flag)
1284 return QEDE_CSUM_ERROR;
1285
1286 return QEDE_CSUM_UNNECESSARY | tcsum;
1287}
1288
1289static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1290{
1291 u16 csum_flag = 0;
1292 u8 csum = 0;
1293
14db81de
MC		 1294 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1295 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1296 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1297 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1298 csum = QEDE_CSUM_UNNECESSARY;
1299 }
1300
1301 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1302 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1303
1304 if (csum_flag & flag)
1305 return QEDE_CSUM_ERROR;
1306
1307 return csum;
1308}
1309
14db81de
MC		 1310static u8 qede_check_csum(u16 flag)
1311{
1312 if (!qede_tunn_exist(flag))
1313 return qede_check_notunn_csum(flag);
1314 else
1315 return qede_check_tunn_csum(flag);
1316}
1317
2950219d
YM		 1318static int qede_rx_int(struct qede_fastpath *fp, int budget)
1319{
1320 struct qede_dev *edev = fp->edev;
1321 struct qede_rx_queue *rxq = fp->rxq;
1322
1323 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1324 int rx_pkt = 0;
1325 u8 csum_flag;
1326
1327 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1328 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1329
1330 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1331 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1332 * read before it is written by FW, then FW writes CQE and SB, and then
1333 * the CPU reads the hw_comp_cons, it will use an old CQE.
1334 */
1335 rmb();
1336
1337 /* Loop to complete all indicated BDs */
1338 while (sw_comp_cons != hw_comp_cons) {
1339 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1340 enum pkt_hash_types rxhash_type;
1341 enum eth_rx_cqe_type cqe_type;
1342 struct sw_rx_data *sw_rx_data;
1343 union eth_rx_cqe *cqe;
1344 struct sk_buff *skb;
fc48b7a6
YM		 1345 struct page *data;
1346 __le16 flags;
2950219d
YM		 1347 u16 len, pad;
1348 u32 rx_hash;
2950219d
YM		 1349
1350 /* Get the CQE from the completion ring */
1351 cqe = (union eth_rx_cqe *)
1352 qed_chain_consume(&rxq->rx_comp_ring);
1353 cqe_type = cqe->fast_path_regular.type;
1354
1355 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1356 edev->ops->eth_cqe_completion(
1357 edev->cdev, fp->rss_id,
1358 (struct eth_slow_path_rx_cqe *)cqe);
1359 goto next_cqe;
1360 }
1361
55482edc
MC		 1362 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1363 switch (cqe_type) {
1364 case ETH_RX_CQE_TYPE_TPA_START:
1365 qede_tpa_start(edev, rxq,
1366 &cqe->fast_path_tpa_start);
1367 goto next_cqe;
1368 case ETH_RX_CQE_TYPE_TPA_CONT:
1369 qede_tpa_cont(edev, rxq,
1370 &cqe->fast_path_tpa_cont);
1371 goto next_cqe;
1372 case ETH_RX_CQE_TYPE_TPA_END:
1373 qede_tpa_end(edev, fp,
1374 &cqe->fast_path_tpa_end);
1375 goto next_rx_only;
1376 default:
1377 break;
1378 }
1379 }
1380
2950219d
YM		 1381 /* Get the data from the SW ring */
1382 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1383 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1384 data = sw_rx_data->data;
1385
1386 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1387 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1388 pad = fp_cqe->placement_offset;
fc48b7a6 1389 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1390
fc48b7a6
YM		 1391 /* If this is an error packet then drop it */
1392 parse_flag = le16_to_cpu(flags);
2950219d 1393
fc48b7a6
YM		 1394 csum_flag = qede_check_csum(parse_flag);
1395 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
1396 DP_NOTICE(edev,
1397 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1398 sw_comp_cons, parse_flag);
1399 rxq->rx_hw_errors++;
f86af2df
MC		 1400 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1401 goto next_cqe;
fc48b7a6 1402 }
2950219d 1403
fc48b7a6
YM		 1404 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1405 if (unlikely(!skb)) {
2950219d 1406 DP_NOTICE(edev,
fc48b7a6 1407 "Build_skb failed, dropping incoming packet\n");
f86af2df 1408 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1409 rxq->rx_alloc_errors++;
f86af2df 1410 goto next_cqe;
fc48b7a6
YM		 1411 }
1412
1413 /* Copy data into SKB */
1414 if (len + pad <= QEDE_RX_HDR_SIZE) {
1415 memcpy(skb_put(skb, len),
1416 page_address(data) + pad +
1417 sw_rx_data->page_offset, len);
1418 qede_reuse_page(edev, rxq, sw_rx_data);
1419 } else {
1420 struct skb_frag_struct *frag;
1421 unsigned int pull_len;
1422 unsigned char *va;
1423
1424 frag = &skb_shinfo(skb)->frags[0];
1425
1426 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1427 pad + sw_rx_data->page_offset,
1428 len, rxq->rx_buf_seg_size);
1429
1430 va = skb_frag_address(frag);
1431 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1432
1433 /* Align the pull_len to optimize memcpy */
1434 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1435
1436 skb_frag_size_sub(frag, pull_len);
1437 frag->page_offset += pull_len;
1438 skb->data_len -= pull_len;
1439 skb->tail += pull_len;
1440
1441 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1442 sw_rx_data))) {
1443 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1444 /* Incr page ref count to reuse on allocation
1445 * failure so that it doesn't get freed while
1446 * freeing SKB.
1447 */
1448
1449 atomic_inc(&sw_rx_data->data->_count);
fc48b7a6 1450 rxq->rx_alloc_errors++;
f86af2df
MC		 1451 qede_recycle_rx_bd_ring(rxq, edev,
1452 fp_cqe->bd_num);
1453 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1454 goto next_cqe;
1455 }
2950219d
YM		 1456 }
1457
f86af2df
MC		 1458 qede_rx_bd_ring_consume(rxq);
1459
fc48b7a6
YM		 1460 if (fp_cqe->bd_num != 1) {
1461 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1462 u8 num_frags;
1463
1464 pkt_len -= len;
1465
1466 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1467 num_frags--) {
1468 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1469 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1470 if (unlikely(!cur_size)) {
1471 DP_ERR(edev,
1472 "Still got %d BDs for mapping jumbo, but length became 0\n",
1473 num_frags);
1474 qede_recycle_rx_bd_ring(rxq, edev,
1475 num_frags);
1476 dev_kfree_skb_any(skb);
1477 goto next_cqe;
1478 }
fc48b7a6 1479
f86af2df
MC		 1480 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1481 qede_recycle_rx_bd_ring(rxq, edev,
1482 num_frags);
1483 dev_kfree_skb_any(skb);
fc48b7a6 1484 goto next_cqe;
f86af2df 1485 }
fc48b7a6 1486
fc48b7a6
YM		 1487 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1488 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1489 qede_rx_bd_ring_consume(rxq);
1490
fc48b7a6
YM		 1491 dma_unmap_page(&edev->pdev->dev,
1492 sw_rx_data->mapping,
1493 PAGE_SIZE, DMA_FROM_DEVICE);
1494
1495 skb_fill_page_desc(skb,
1496 skb_shinfo(skb)->nr_frags++,
1497 sw_rx_data->data, 0,
1498 cur_size);
1499
1500 skb->truesize += PAGE_SIZE;
1501 skb->data_len += cur_size;
1502 skb->len += cur_size;
1503 pkt_len -= cur_size;
1504 }
2950219d 1505
f86af2df 1506 if (unlikely(pkt_len))
fc48b7a6
YM		 1507 DP_ERR(edev,
1508 "Mapped all BDs of jumbo, but still have %d bytes\n",
1509 pkt_len);
1510 }
2950219d
YM		 1511
1512 skb->protocol = eth_type_trans(skb, edev->ndev);
1513
1514 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1515 fp_cqe->rss_hash,
1516 &rxhash_type);
1517
1518 skb_set_hash(skb, rx_hash, rxhash_type);
1519
1520 qede_set_skb_csum(skb, csum_flag);
1521
1522 skb_record_rx_queue(skb, fp->rss_id);
1523
1524 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1525next_rx_only:
2950219d
YM		 1526 rx_pkt++;
1527
1528next_cqe: /* don't consume bd rx buffer */
1529 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1530 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1531 /* CR TPA - revisit how to handle budget in TPA perhaps
1532 * increase on "end"
1533 */
1534 if (rx_pkt == budget)
1535 break;
1536 } /* repeat while sw_comp_cons != hw_comp_cons... */
1537
1538 /* Update producers */
1539 qede_update_rx_prod(edev, rxq);
1540
1541 return rx_pkt;
1542}
1543
1544static int qede_poll(struct napi_struct *napi, int budget)
1545{
1546 int work_done = 0;
1547 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
1548 napi);
1549 struct qede_dev *edev = fp->edev;
1550
1551 while (1) {
1552 u8 tc;
1553
1554 for (tc = 0; tc < edev->num_tc; tc++)
1555 if (qede_txq_has_work(&fp->txqs[tc]))
1556 qede_tx_int(edev, &fp->txqs[tc]);
1557
1558 if (qede_has_rx_work(fp->rxq)) {
1559 work_done += qede_rx_int(fp, budget - work_done);
1560
1561 /* must not complete if we consumed full budget */
1562 if (work_done >= budget)
1563 break;
1564 }
1565
1566 /* Fall out from the NAPI loop if needed */
1567 if (!(qede_has_rx_work(fp->rxq) || qede_has_tx_work(fp))) {
1568 qed_sb_update_sb_idx(fp->sb_info);
1569 /* *_has_*_work() reads the status block,
1570 * thus we need to ensure that status block indices
1571 * have been actually read (qed_sb_update_sb_idx)
1572 * prior to this check (*_has_*_work) so that
1573 * we won't write the "newer" value of the status block
1574 * to HW (if there was a DMA right after
1575 * qede_has_rx_work and if there is no rmb, the memory
1576 * reading (qed_sb_update_sb_idx) may be postponed
1577 * to right before *_ack_sb). In this case there
1578 * will never be another interrupt until there is
1579 * another update of the status block, while there
1580 * is still unhandled work.
1581 */
1582 rmb();
1583
1584 if (!(qede_has_rx_work(fp->rxq) ||
1585 qede_has_tx_work(fp))) {
1586 napi_complete(napi);
1587 /* Update and reenable interrupts */
1588 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1589 1 /*update*/);
1590 break;
1591 }
1592 }
1593 }
1594
1595 return work_done;
1596}
1597
1598static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1599{
1600 struct qede_fastpath *fp = fp_cookie;
1601
1602 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1603
1604 napi_schedule_irqoff(&fp->napi);
1605 return IRQ_HANDLED;
1606}
1607
1608/* -------------------------------------------------------------------------
1609 * END OF FAST-PATH
1610 * -------------------------------------------------------------------------
1611 */
1612
1613static int qede_open(struct net_device *ndev);
1614static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1615static int qede_set_mac_addr(struct net_device *ndev, void *p);
1616static void qede_set_rx_mode(struct net_device *ndev);
1617static void qede_config_rx_mode(struct net_device *ndev);
1618
1619static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1620 enum qed_filter_xcast_params_type opcode,
1621 unsigned char mac[ETH_ALEN])
1622{
1623 struct qed_filter_params filter_cmd;
1624
1625 memset(&filter_cmd, 0, sizeof(filter_cmd));
1626 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1627 filter_cmd.filter.ucast.type = opcode;
1628 filter_cmd.filter.ucast.mac_valid = 1;
1629 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1630
1631 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1632}
1633
7c1bfcad
SRK		 1634static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1635 enum qed_filter_xcast_params_type opcode,
1636 u16 vid)
1637{
1638 struct qed_filter_params filter_cmd;
1639
1640 memset(&filter_cmd, 0, sizeof(filter_cmd));
1641 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1642 filter_cmd.filter.ucast.type = opcode;
1643 filter_cmd.filter.ucast.vlan_valid = 1;
1644 filter_cmd.filter.ucast.vlan = vid;
1645
1646 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1647}
1648
133fac0e
SK		 1649void qede_fill_by_demand_stats(struct qede_dev *edev)
1650{
1651 struct qed_eth_stats stats;
1652
1653 edev->ops->get_vport_stats(edev->cdev, &stats);
1654 edev->stats.no_buff_discards = stats.no_buff_discards;
1655 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1656 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1657 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1658 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1659 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1660 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1661 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1662 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1663
1664 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1665 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1666 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1667 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1668 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1669 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1670 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1671 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1672 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1673 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1674 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1675 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1676
1677 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1678 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1679 edev->stats.rx_128_to_255_byte_packets =
1680 stats.rx_128_to_255_byte_packets;
1681 edev->stats.rx_256_to_511_byte_packets =
1682 stats.rx_256_to_511_byte_packets;
1683 edev->stats.rx_512_to_1023_byte_packets =
1684 stats.rx_512_to_1023_byte_packets;
1685 edev->stats.rx_1024_to_1518_byte_packets =
1686 stats.rx_1024_to_1518_byte_packets;
1687 edev->stats.rx_1519_to_1522_byte_packets =
1688 stats.rx_1519_to_1522_byte_packets;
1689 edev->stats.rx_1519_to_2047_byte_packets =
1690 stats.rx_1519_to_2047_byte_packets;
1691 edev->stats.rx_2048_to_4095_byte_packets =
1692 stats.rx_2048_to_4095_byte_packets;
1693 edev->stats.rx_4096_to_9216_byte_packets =
1694 stats.rx_4096_to_9216_byte_packets;
1695 edev->stats.rx_9217_to_16383_byte_packets =
1696 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1697 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1698 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1699 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1700 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1701 edev->stats.rx_align_errors = stats.rx_align_errors;
1702 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1703 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1704 edev->stats.rx_jabbers = stats.rx_jabbers;
1705 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1706 edev->stats.rx_fragments = stats.rx_fragments;
1707 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1708 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1709 edev->stats.tx_128_to_255_byte_packets =
1710 stats.tx_128_to_255_byte_packets;
1711 edev->stats.tx_256_to_511_byte_packets =
1712 stats.tx_256_to_511_byte_packets;
1713 edev->stats.tx_512_to_1023_byte_packets =
1714 stats.tx_512_to_1023_byte_packets;
1715 edev->stats.tx_1024_to_1518_byte_packets =
1716 stats.tx_1024_to_1518_byte_packets;
1717 edev->stats.tx_1519_to_2047_byte_packets =
1718 stats.tx_1519_to_2047_byte_packets;
1719 edev->stats.tx_2048_to_4095_byte_packets =
1720 stats.tx_2048_to_4095_byte_packets;
1721 edev->stats.tx_4096_to_9216_byte_packets =
1722 stats.tx_4096_to_9216_byte_packets;
1723 edev->stats.tx_9217_to_16383_byte_packets =
1724 stats.tx_9217_to_16383_byte_packets;
1725 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1726 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1727 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1728 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1729 edev->stats.brb_truncates = stats.brb_truncates;
1730 edev->stats.brb_discards = stats.brb_discards;
1731 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1732}
1733
1734static struct rtnl_link_stats64 *qede_get_stats64(
1735 struct net_device *dev,
1736 struct rtnl_link_stats64 *stats)
1737{
1738 struct qede_dev *edev = netdev_priv(dev);
1739
1740 qede_fill_by_demand_stats(edev);
1741
1742 stats->rx_packets = edev->stats.rx_ucast_pkts +
1743 edev->stats.rx_mcast_pkts +
1744 edev->stats.rx_bcast_pkts;
1745 stats->tx_packets = edev->stats.tx_ucast_pkts +
1746 edev->stats.tx_mcast_pkts +
1747 edev->stats.tx_bcast_pkts;
1748
1749 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1750 edev->stats.rx_mcast_bytes +
1751 edev->stats.rx_bcast_bytes;
1752
1753 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1754 edev->stats.tx_mcast_bytes +
1755 edev->stats.tx_bcast_bytes;
1756
1757 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1758 stats->multicast = edev->stats.rx_mcast_pkts +
1759 edev->stats.rx_bcast_pkts;
1760
1761 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1762
1763 stats->collisions = edev->stats.tx_total_collisions;
1764 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1765 stats->rx_frame_errors = edev->stats.rx_align_errors;
1766
1767 return stats;
1768}
1769
7c1bfcad
SRK		 1770static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1771{
1772 struct qed_update_vport_params params;
1773 int rc;
1774
1775 /* Proceed only if action actually needs to be performed */
1776 if (edev->accept_any_vlan == action)
1777 return;
1778
1779 memset(&params, 0, sizeof(params));
1780
1781 params.vport_id = 0;
1782 params.accept_any_vlan = action;
1783 params.update_accept_any_vlan_flg = 1;
1784
1785 rc = edev->ops->vport_update(edev->cdev, &params);
1786 if (rc) {
1787 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1788 action ? "enable" : "disable");
1789 } else {
1790 DP_INFO(edev, "%s accept-any-vlan\n",
1791 action ? "enabled" : "disabled");
1792 edev->accept_any_vlan = action;
1793 }
1794}
1795
1796static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1797{
1798 struct qede_dev *edev = netdev_priv(dev);
1799 struct qede_vlan *vlan, *tmp;
1800 int rc;
1801
1802 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1803
1804 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1805 if (!vlan) {
1806 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1807 return -ENOMEM;
1808 }
1809 INIT_LIST_HEAD(&vlan->list);
1810 vlan->vid = vid;
1811 vlan->configured = false;
1812
1813 /* Verify vlan isn't already configured */
1814 list_for_each_entry(tmp, &edev->vlan_list, list) {
1815 if (tmp->vid == vlan->vid) {
1816 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1817 "vlan already configured\n");
1818 kfree(vlan);
1819 return -EEXIST;
1820 }
1821 }
1822
1823 /* If interface is down, cache this VLAN ID and return */
1824 if (edev->state != QEDE_STATE_OPEN) {
1825 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1826 "Interface is down, VLAN %d will be configured when interface is up\n",
1827 vid);
1828 if (vid != 0)
1829 edev->non_configured_vlans++;
1830 list_add(&vlan->list, &edev->vlan_list);
1831
1832 return 0;
1833 }
1834
1835 /* Check for the filter limit.
1836 * Note - vlan0 has a reserved filter and can be added without
1837 * worrying about quota
1838 */
1839 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1840 (vlan->vid == 0)) {
1841 rc = qede_set_ucast_rx_vlan(edev,
1842 QED_FILTER_XCAST_TYPE_ADD,
1843 vlan->vid);
1844 if (rc) {
1845 DP_ERR(edev, "Failed to configure VLAN %d\n",
1846 vlan->vid);
1847 kfree(vlan);
1848 return -EINVAL;
1849 }
1850 vlan->configured = true;
1851
1852 /* vlan0 filter isn't consuming out of our quota */
1853 if (vlan->vid != 0)
1854 edev->configured_vlans++;
1855 } else {
1856 /* Out of quota; Activate accept-any-VLAN mode */
1857 if (!edev->non_configured_vlans)
1858 qede_config_accept_any_vlan(edev, true);
1859
1860 edev->non_configured_vlans++;
1861 }
1862
1863 list_add(&vlan->list, &edev->vlan_list);
1864
1865 return 0;
1866}
1867
1868static void qede_del_vlan_from_list(struct qede_dev *edev,
1869 struct qede_vlan *vlan)
1870{
1871 /* vlan0 filter isn't consuming out of our quota */
1872 if (vlan->vid != 0) {
1873 if (vlan->configured)
1874 edev->configured_vlans--;
1875 else
1876 edev->non_configured_vlans--;
1877 }
1878
1879 list_del(&vlan->list);
1880 kfree(vlan);
1881}
1882
1883static int qede_configure_vlan_filters(struct qede_dev *edev)
1884{
1885 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1886 struct qed_dev_eth_info *dev_info;
1887 struct qede_vlan *vlan = NULL;
1888
1889 if (list_empty(&edev->vlan_list))
1890 return 0;
1891
1892 dev_info = &edev->dev_info;
1893
1894 /* Configure non-configured vlans */
1895 list_for_each_entry(vlan, &edev->vlan_list, list) {
1896 if (vlan->configured)
1897 continue;
1898
1899 /* We have used all our credits, now enable accept_any_vlan */
1900 if ((vlan->vid != 0) &&
1901 (edev->configured_vlans == dev_info->num_vlan_filters)) {
1902 accept_any_vlan = 1;
1903 continue;
1904 }
1905
1906 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
1907
1908 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
1909 vlan->vid);
1910 if (rc) {
1911 DP_ERR(edev, "Failed to configure VLAN %u\n",
1912 vlan->vid);
1913 real_rc = rc;
1914 continue;
1915 }
1916
1917 vlan->configured = true;
1918 /* vlan0 filter doesn't consume our VLAN filter's quota */
1919 if (vlan->vid != 0) {
1920 edev->non_configured_vlans--;
1921 edev->configured_vlans++;
1922 }
1923 }
1924
1925 /* enable accept_any_vlan mode if we have more VLANs than credits,
1926 * or remove accept_any_vlan mode if we've actually removed
1927 * a non-configured vlan, and all remaining vlans are truly configured.
1928 */
1929
1930 if (accept_any_vlan)
1931 qede_config_accept_any_vlan(edev, true);
1932 else if (!edev->non_configured_vlans)
1933 qede_config_accept_any_vlan(edev, false);
1934
1935 return real_rc;
1936}
1937
1938static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
1939{
1940 struct qede_dev *edev = netdev_priv(dev);
1941 struct qede_vlan *vlan = NULL;
1942 int rc;
1943
1944 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
1945
1946 /* Find whether entry exists */
1947 list_for_each_entry(vlan, &edev->vlan_list, list)
1948 if (vlan->vid == vid)
1949 break;
1950
1951 if (!vlan || (vlan->vid != vid)) {
1952 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1953 "Vlan isn't configured\n");
1954 return 0;
1955 }
1956
1957 if (edev->state != QEDE_STATE_OPEN) {
1958 /* As interface is already down, we don't have a VPORT
1959 * instance to remove vlan filter. So just update vlan list
1960 */
1961 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1962 "Interface is down, removing VLAN from list only\n");
1963 qede_del_vlan_from_list(edev, vlan);
1964 return 0;
1965 }
1966
1967 /* Remove vlan */
1968 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL, vid);
1969 if (rc) {
1970 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
1971 return -EINVAL;
1972 }
1973
1974 qede_del_vlan_from_list(edev, vlan);
1975
1976 /* We have removed a VLAN - try to see if we can
1977 * configure non-configured VLAN from the list.
1978 */
1979 rc = qede_configure_vlan_filters(edev);
1980
1981 return rc;
1982}
1983
1984static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
1985{
1986 struct qede_vlan *vlan = NULL;
1987
1988 if (list_empty(&edev->vlan_list))
1989 return;
1990
1991 list_for_each_entry(vlan, &edev->vlan_list, list) {
1992 if (!vlan->configured)
1993 continue;
1994
1995 vlan->configured = false;
1996
1997 /* vlan0 filter isn't consuming out of our quota */
1998 if (vlan->vid != 0) {
1999 edev->non_configured_vlans++;
2000 edev->configured_vlans--;
2001 }
2002
2003 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2004 "marked vlan %d as non-configured\n",
2005 vlan->vid);
2006 }
2007
2008 edev->accept_any_vlan = false;
2009}
2010
b18e170c
MC		 2011#ifdef CONFIG_QEDE_VXLAN
2012static void qede_add_vxlan_port(struct net_device *dev,
2013 sa_family_t sa_family, __be16 port)
2014{
2015 struct qede_dev *edev = netdev_priv(dev);
2016 u16 t_port = ntohs(port);
2017
2018 if (edev->vxlan_dst_port)
2019 return;
2020
2021 edev->vxlan_dst_port = t_port;
2022
2023 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d", t_port);
2024
2025 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2026 schedule_delayed_work(&edev->sp_task, 0);
2027}
2028
2029static void qede_del_vxlan_port(struct net_device *dev,
2030 sa_family_t sa_family, __be16 port)
2031{
2032 struct qede_dev *edev = netdev_priv(dev);
2033 u16 t_port = ntohs(port);
2034
2035 if (t_port != edev->vxlan_dst_port)
2036 return;
2037
2038 edev->vxlan_dst_port = 0;
2039
2040 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d", t_port);
2041
2042 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2043 schedule_delayed_work(&edev->sp_task, 0);
2044}
2045#endif
2046
9a109dd0
MC		 2047#ifdef CONFIG_QEDE_GENEVE
2048static void qede_add_geneve_port(struct net_device *dev,
2049 sa_family_t sa_family, __be16 port)
2050{
2051 struct qede_dev *edev = netdev_priv(dev);
2052 u16 t_port = ntohs(port);
2053
2054 if (edev->geneve_dst_port)
2055 return;
2056
2057 edev->geneve_dst_port = t_port;
2058
2059 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d", t_port);
2060 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2061 schedule_delayed_work(&edev->sp_task, 0);
2062}
2063
2064static void qede_del_geneve_port(struct net_device *dev,
2065 sa_family_t sa_family, __be16 port)
2066{
2067 struct qede_dev *edev = netdev_priv(dev);
2068 u16 t_port = ntohs(port);
2069
2070 if (t_port != edev->geneve_dst_port)
2071 return;
2072
2073 edev->geneve_dst_port = 0;
2074
2075 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d", t_port);
2076 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2077 schedule_delayed_work(&edev->sp_task, 0);
2078}
2079#endif
2080
2950219d
YM		 2081static const struct net_device_ops qede_netdev_ops = {
2082 .ndo_open = qede_open,
2083 .ndo_stop = qede_close,
2084 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2085 .ndo_set_rx_mode = qede_set_rx_mode,
2086 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2087 .ndo_validate_addr = eth_validate_addr,
133fac0e 2088 .ndo_change_mtu = qede_change_mtu,
08feecd7
YM		 2089#ifdef CONFIG_QED_SRIOV
2090 .ndo_set_vf_vlan = qede_set_vf_vlan,
2091#endif
7c1bfcad
SRK		 2092 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2093 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
133fac0e 2094 .ndo_get_stats64 = qede_get_stats64,
b18e170c
MC		 2095#ifdef CONFIG_QEDE_VXLAN
2096 .ndo_add_vxlan_port = qede_add_vxlan_port,
2097 .ndo_del_vxlan_port = qede_del_vxlan_port,
2098#endif
9a109dd0
MC		 2099#ifdef CONFIG_QEDE_GENEVE
2100 .ndo_add_geneve_port = qede_add_geneve_port,
2101 .ndo_del_geneve_port = qede_del_geneve_port,
2102#endif
2950219d
YM		 2103};
2104
e712d52b
YM		 2105/* -------------------------------------------------------------------------
2106 * START OF PROBE / REMOVE
2107 * -------------------------------------------------------------------------
2108 */
2109
2110static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2111 struct pci_dev *pdev,
2112 struct qed_dev_eth_info *info,
2113 u32 dp_module,
2114 u8 dp_level)
2115{
2116 struct net_device *ndev;
2117 struct qede_dev *edev;
2118
2119 ndev = alloc_etherdev_mqs(sizeof(*edev),
2120 info->num_queues,
2121 info->num_queues);
2122 if (!ndev) {
2123 pr_err("etherdev allocation failed\n");
2124 return NULL;
2125 }
2126
2127 edev = netdev_priv(ndev);
2128 edev->ndev = ndev;
2129 edev->cdev = cdev;
2130 edev->pdev = pdev;
2131 edev->dp_module = dp_module;
2132 edev->dp_level = dp_level;
2133 edev->ops = qed_ops;
2950219d
YM		 2134 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2135 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2136
e712d52b
YM		 2137 SET_NETDEV_DEV(ndev, &pdev->dev);
2138
133fac0e 2139 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2140 memcpy(&edev->dev_info, info, sizeof(*info));
2141
2142 edev->num_tc = edev->dev_info.num_tc;
2143
7c1bfcad
SRK		 2144 INIT_LIST_HEAD(&edev->vlan_list);
2145
e712d52b
YM		 2146 return edev;
2147}
2148
2149static void qede_init_ndev(struct qede_dev *edev)
2150{
2151 struct net_device *ndev = edev->ndev;
2152 struct pci_dev *pdev = edev->pdev;
2153 u32 hw_features;
2154
2155 pci_set_drvdata(pdev, ndev);
2156
2157 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2158 ndev->base_addr = ndev->mem_start;
2159 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2160 ndev->irq = edev->dev_info.common.pci_irq;
2161
2162 ndev->watchdog_timeo = TX_TIMEOUT;
2163
2950219d
YM		 2164 ndev->netdev_ops = &qede_netdev_ops;
2165
133fac0e
SK		 2166 qede_set_ethtool_ops(ndev);
2167
e712d52b
YM		 2168 /* user-changeble features */
2169 hw_features = NETIF_F_GRO | NETIF_F_SG |
2170 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2171 NETIF_F_TSO | NETIF_F_TSO6;
2172
14db81de
MC		 2173 /* Encap features*/
2174 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2175 NETIF_F_TSO_ECN;
2176 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2177 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2178 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2179 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2180
e712d52b
YM		 2181 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2182 NETIF_F_HIGHDMA;
2183 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2184 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2185 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2186
2187 ndev->hw_features = hw_features;
2188
2189 /* Set network device HW mac */
2190 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2191}
2192
2193/* This function converts from 32b param to two params of level and module
2194 * Input 32b decoding:
2195 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2196 * 'happy' flow, e.g. memory allocation failed.
2197 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2198 * and provide important parameters.
2199 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2200 * module. VERBOSE prints are for tracking the specific flow in low level.
2201 *
2202 * Notice that the level should be that of the lowest required logs.
2203 */
133fac0e 2204void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2205{
2206 *p_dp_level = QED_LEVEL_NOTICE;
2207 *p_dp_module = 0;
2208
2209 if (debug & QED_LOG_VERBOSE_MASK) {
2210 *p_dp_level = QED_LEVEL_VERBOSE;
2211 *p_dp_module = (debug & 0x3FFFFFFF);
2212 } else if (debug & QED_LOG_INFO_MASK) {
2213 *p_dp_level = QED_LEVEL_INFO;
2214 } else if (debug & QED_LOG_NOTICE_MASK) {
2215 *p_dp_level = QED_LEVEL_NOTICE;
2216 }
2217}
2218
2950219d
YM		 2219static void qede_free_fp_array(struct qede_dev *edev)
2220{
2221 if (edev->fp_array) {
2222 struct qede_fastpath *fp;
2223 int i;
2224
2225 for_each_rss(i) {
2226 fp = &edev->fp_array[i];
2227
2228 kfree(fp->sb_info);
2229 kfree(fp->rxq);
2230 kfree(fp->txqs);
2231 }
2232 kfree(edev->fp_array);
2233 }
2234 edev->num_rss = 0;
2235}
2236
2237static int qede_alloc_fp_array(struct qede_dev *edev)
2238{
2239 struct qede_fastpath *fp;
2240 int i;
2241
2242 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2243 sizeof(*edev->fp_array), GFP_KERNEL);
2244 if (!edev->fp_array) {
2245 DP_NOTICE(edev, "fp array allocation failed\n");
2246 goto err;
2247 }
2248
2249 for_each_rss(i) {
2250 fp = &edev->fp_array[i];
2251
2252 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2253 if (!fp->sb_info) {
2254 DP_NOTICE(edev, "sb info struct allocation failed\n");
2255 goto err;
2256 }
2257
2258 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2259 if (!fp->rxq) {
2260 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2261 goto err;
2262 }
2263
2264 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2265 if (!fp->txqs) {
2266 DP_NOTICE(edev, "TXQ array allocation failed\n");
2267 goto err;
2268 }
2269 }
2270
2271 return 0;
2272err:
2273 qede_free_fp_array(edev);
2274 return -ENOMEM;
2275}
2276
0d8e0aa0
SK		 2277static void qede_sp_task(struct work_struct *work)
2278{
2279 struct qede_dev *edev = container_of(work, struct qede_dev,
2280 sp_task.work);
b18e170c
MC		 2281 struct qed_dev *cdev = edev->cdev;
2282
0d8e0aa0
SK		 2283 mutex_lock(&edev->qede_lock);
2284
2285 if (edev->state == QEDE_STATE_OPEN) {
2286 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2287 qede_config_rx_mode(edev->ndev);
2288 }
2289
b18e170c
MC		 2290 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2291 struct qed_tunn_params tunn_params;
2292
2293 memset(&tunn_params, 0, sizeof(tunn_params));
2294 tunn_params.update_vxlan_port = 1;
2295 tunn_params.vxlan_port = edev->vxlan_dst_port;
2296 qed_ops->tunn_config(cdev, &tunn_params);
2297 }
2298
9a109dd0
MC		 2299 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2300 struct qed_tunn_params tunn_params;
2301
2302 memset(&tunn_params, 0, sizeof(tunn_params));
2303 tunn_params.update_geneve_port = 1;
2304 tunn_params.geneve_port = edev->geneve_dst_port;
2305 qed_ops->tunn_config(cdev, &tunn_params);
2306 }
2307
0d8e0aa0
SK		 2308 mutex_unlock(&edev->qede_lock);
2309}
2310
e712d52b
YM		 2311static void qede_update_pf_params(struct qed_dev *cdev)
2312{
2313 struct qed_pf_params pf_params;
2314
8e0ddc04 2315 /* 64 rx + 64 tx */
e712d52b 2316 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2317 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2318 qed_ops->common->update_pf_params(cdev, &pf_params);
2319}
2320
2321enum qede_probe_mode {
2322 QEDE_PROBE_NORMAL,
2323};
2324
2325static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2326 bool is_vf, enum qede_probe_mode mode)
e712d52b 2327{
1408cc1f 2328 struct qed_probe_params probe_params;
e712d52b
YM		 2329 struct qed_slowpath_params params;
2330 struct qed_dev_eth_info dev_info;
2331 struct qede_dev *edev;
2332 struct qed_dev *cdev;
2333 int rc;
2334
2335 if (unlikely(dp_level & QED_LEVEL_INFO))
2336 pr_notice("Starting qede probe\n");
2337
1408cc1f
YM		 2338 memset(&probe_params, 0, sizeof(probe_params));
2339 probe_params.protocol = QED_PROTOCOL_ETH;
2340 probe_params.dp_module = dp_module;
2341 probe_params.dp_level = dp_level;
2342 probe_params.is_vf = is_vf;
2343 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2344 if (!cdev) {
2345 rc = -ENODEV;
2346 goto err0;
2347 }
2348
2349 qede_update_pf_params(cdev);
2350
2351 /* Start the Slowpath-process */
2352 memset(&params, 0, sizeof(struct qed_slowpath_params));
2353 params.int_mode = QED_INT_MODE_MSIX;
2354 params.drv_major = QEDE_MAJOR_VERSION;
2355 params.drv_minor = QEDE_MINOR_VERSION;
2356 params.drv_rev = QEDE_REVISION_VERSION;
2357 params.drv_eng = QEDE_ENGINEERING_VERSION;
2358 strlcpy(params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2359 rc = qed_ops->common->slowpath_start(cdev, &params);
2360 if (rc) {
2361 pr_notice("Cannot start slowpath\n");
2362 goto err1;
2363 }
2364
2365 /* Learn information crucial for qede to progress */
2366 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2367 if (rc)
2368 goto err2;
2369
2370 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2371 dp_level);
2372 if (!edev) {
2373 rc = -ENOMEM;
2374 goto err2;
2375 }
2376
fefb0202
YM		 2377 if (is_vf)
2378 edev->flags |= QEDE_FLAG_IS_VF;
2379
e712d52b
YM		 2380 qede_init_ndev(edev);
2381
2950219d
YM		 2382 rc = register_netdev(edev->ndev);
2383 if (rc) {
2384 DP_NOTICE(edev, "Cannot register net-device\n");
2385 goto err3;
2386 }
2387
e712d52b
YM		 2388 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2389
a2ec6172
SK		 2390 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2391
0d8e0aa0
SK		 2392 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2393 mutex_init(&edev->qede_lock);
2394
e712d52b
YM		 2395 DP_INFO(edev, "Ending successfully qede probe\n");
2396
2397 return 0;
2398
2950219d
YM		 2399err3:
2400 free_netdev(edev->ndev);
e712d52b
YM		 2401err2:
2402 qed_ops->common->slowpath_stop(cdev);
2403err1:
2404 qed_ops->common->remove(cdev);
2405err0:
2406 return rc;
2407}
2408
2409static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2410{
fefb0202 2411 bool is_vf = false;
e712d52b
YM		 2412 u32 dp_module = 0;
2413 u8 dp_level = 0;
2414
fefb0202
YM		 2415 switch ((enum qede_pci_private)id->driver_data) {
2416 case QEDE_PRIVATE_VF:
2417 if (debug & QED_LOG_VERBOSE_MASK)
2418 dev_err(&pdev->dev, "Probing a VF\n");
2419 is_vf = true;
2420 break;
2421 default:
2422 if (debug & QED_LOG_VERBOSE_MASK)
2423 dev_err(&pdev->dev, "Probing a PF\n");
2424 }
2425
e712d52b
YM		 2426 qede_config_debug(debug, &dp_module, &dp_level);
2427
fefb0202 2428 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2429 QEDE_PROBE_NORMAL);
2430}
2431
2432enum qede_remove_mode {
2433 QEDE_REMOVE_NORMAL,
2434};
2435
2436static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2437{
2438 struct net_device *ndev = pci_get_drvdata(pdev);
2439 struct qede_dev *edev = netdev_priv(ndev);
2440 struct qed_dev *cdev = edev->cdev;
2441
2442 DP_INFO(edev, "Starting qede_remove\n");
2443
0d8e0aa0 2444 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2445 unregister_netdev(ndev);
2446
e712d52b
YM		 2447 edev->ops->common->set_power_state(cdev, PCI_D0);
2448
2449 pci_set_drvdata(pdev, NULL);
2450
2451 free_netdev(ndev);
2452
2453 /* Use global ops since we've freed edev */
2454 qed_ops->common->slowpath_stop(cdev);
2455 qed_ops->common->remove(cdev);
2456
2457 pr_notice("Ending successfully qede_remove\n");
2458}
2459
2460static void qede_remove(struct pci_dev *pdev)
2461{
2462 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2463}
2950219d
YM		 2464
2465/* -------------------------------------------------------------------------
2466 * START OF LOAD / UNLOAD
2467 * -------------------------------------------------------------------------
2468 */
2469
2470static int qede_set_num_queues(struct qede_dev *edev)
2471{
2472 int rc;
2473 u16 rss_num;
2474
2475 /* Setup queues according to possible resources*/
8edf049d
SK		 2476 if (edev->req_rss)
2477 rss_num = edev->req_rss;
2478 else
2479 rss_num = netif_get_num_default_rss_queues() *
2480 edev->dev_info.common.num_hwfns;
2950219d
YM		 2481
2482 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2483
2484 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2485 if (rc > 0) {
2486 /* Managed to request interrupts for our queues */
2487 edev->num_rss = rc;
2488 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2489 QEDE_RSS_CNT(edev), rss_num);
2490 rc = 0;
2491 }
2492 return rc;
2493}
2494
2495static void qede_free_mem_sb(struct qede_dev *edev,
2496 struct qed_sb_info *sb_info)
2497{
2498 if (sb_info->sb_virt)
2499 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2500 (void *)sb_info->sb_virt, sb_info->sb_phys);
2501}
2502
2503/* This function allocates fast-path status block memory */
2504static int qede_alloc_mem_sb(struct qede_dev *edev,
2505 struct qed_sb_info *sb_info,
2506 u16 sb_id)
2507{
2508 struct status_block *sb_virt;
2509 dma_addr_t sb_phys;
2510 int rc;
2511
2512 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
2513 sizeof(*sb_virt),
2514 &sb_phys, GFP_KERNEL);
2515 if (!sb_virt) {
2516 DP_ERR(edev, "Status block allocation failed\n");
2517 return -ENOMEM;
2518 }
2519
2520 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2521 sb_virt, sb_phys, sb_id,
2522 QED_SB_TYPE_L2_QUEUE);
2523 if (rc) {
2524 DP_ERR(edev, "Status block initialization failed\n");
2525 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2526 sb_virt, sb_phys);
2527 return rc;
2528 }
2529
2530 return 0;
2531}
2532
2533static void qede_free_rx_buffers(struct qede_dev *edev,
2534 struct qede_rx_queue *rxq)
2535{
2536 u16 i;
2537
2538 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2539 struct sw_rx_data *rx_buf;
fc48b7a6 2540 struct page *data;
2950219d
YM		 2541
2542 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2543 data = rx_buf->data;
2544
fc48b7a6
YM		 2545 dma_unmap_page(&edev->pdev->dev,
2546 rx_buf->mapping,
2547 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2548
2549 rx_buf->data = NULL;
fc48b7a6 2550 __free_page(data);
2950219d
YM		 2551 }
2552}
2553
55482edc
MC		 2554static void qede_free_sge_mem(struct qede_dev *edev,
2555 struct qede_rx_queue *rxq) {
2556 int i;
2557
2558 if (edev->gro_disable)
2559 return;
2560
2561 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2562 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2563 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2564
f86af2df 2565 if (replace_buf->data) {
55482edc
MC		 2566 dma_unmap_page(&edev->pdev->dev,
2567 dma_unmap_addr(replace_buf, mapping),
2568 PAGE_SIZE, DMA_FROM_DEVICE);
2569 __free_page(replace_buf->data);
2570 }
2571 }
2572}
2573
2950219d
YM		 2574static void qede_free_mem_rxq(struct qede_dev *edev,
2575 struct qede_rx_queue *rxq)
2576{
55482edc
MC		 2577 qede_free_sge_mem(edev, rxq);
2578
2950219d
YM		 2579 /* Free rx buffers */
2580 qede_free_rx_buffers(edev, rxq);
2581
2582 /* Free the parallel SW ring */
2583 kfree(rxq->sw_rx_ring);
2584
2585 /* Free the real RQ ring used by FW */
2586 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2587 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2588}
2589
2590static int qede_alloc_rx_buffer(struct qede_dev *edev,
2591 struct qede_rx_queue *rxq)
2592{
2593 struct sw_rx_data *sw_rx_data;
2594 struct eth_rx_bd *rx_bd;
2595 dma_addr_t mapping;
fc48b7a6 2596 struct page *data;
2950219d 2597 u16 rx_buf_size;
2950219d
YM		 2598
2599 rx_buf_size = rxq->rx_buf_size;
2600
fc48b7a6 2601 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2602 if (unlikely(!data)) {
fc48b7a6 2603 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2604 return -ENOMEM;
2605 }
2606
fc48b7a6
YM		 2607 /* Map the entire page as it would be used
2608 * for multiple RX buffer segment size mapping.
2609 */
2610 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2611 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2612 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2613 __free_page(data);
2950219d
YM		 2614 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2615 return -ENOMEM;
2616 }
2617
2618 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2619 sw_rx_data->page_offset = 0;
2950219d 2620 sw_rx_data->data = data;
fc48b7a6 2621 sw_rx_data->mapping = mapping;
2950219d
YM		 2622
2623 /* Advance PROD and get BD pointer */
2624 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2625 WARN_ON(!rx_bd);
2626 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2627 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2628
2629 rxq->sw_rx_prod++;
2630
2631 return 0;
2632}
2633
55482edc
MC		 2634static int qede_alloc_sge_mem(struct qede_dev *edev,
2635 struct qede_rx_queue *rxq)
2636{
2637 dma_addr_t mapping;
2638 int i;
2639
2640 if (edev->gro_disable)
2641 return 0;
2642
2643 if (edev->ndev->mtu > PAGE_SIZE) {
2644 edev->gro_disable = 1;
2645 return 0;
2646 }
2647
2648 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2649 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2650 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2651
2652 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2653 if (unlikely(!replace_buf->data)) {
2654 DP_NOTICE(edev,
2655 "Failed to allocate TPA skb pool [replacement buffer]\n");
2656 goto err;
2657 }
2658
2659 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2660 rxq->rx_buf_size, DMA_FROM_DEVICE);
2661 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2662 DP_NOTICE(edev,
2663 "Failed to map TPA replacement buffer\n");
2664 goto err;
2665 }
2666
2667 dma_unmap_addr_set(replace_buf, mapping, mapping);
2668 tpa_info->replace_buf.page_offset = 0;
2669
2670 tpa_info->replace_buf_mapping = mapping;
2671 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2672 }
2673
2674 return 0;
2675err:
2676 qede_free_sge_mem(edev, rxq);
2677 edev->gro_disable = 1;
2678 return -ENOMEM;
2679}
2680
2950219d
YM		 2681/* This function allocates all memory needed per Rx queue */
2682static int qede_alloc_mem_rxq(struct qede_dev *edev,
2683 struct qede_rx_queue *rxq)
2684{
f86af2df 2685 int i, rc, size;
2950219d
YM		 2686
2687 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2688
fc48b7a6
YM		 2689 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD +
2690 edev->ndev->mtu;
2691 if (rxq->rx_buf_size > PAGE_SIZE)
2692 rxq->rx_buf_size = PAGE_SIZE;
2693
2694 /* Segment size to spilt a page in multiple equal parts */
2695 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2696
2697 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2698 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2699 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2700 if (!rxq->sw_rx_ring) {
2701 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2702 rc = -ENOMEM;
2950219d
YM		 2703 goto err;
2704 }
2705
2706 /* Allocate FW Rx ring */
2707 rc = edev->ops->common->chain_alloc(edev->cdev,
2708 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2709 QED_CHAIN_MODE_NEXT_PTR,
fc48b7a6 2710 RX_RING_SIZE,
2950219d
YM		 2711 sizeof(struct eth_rx_bd),
2712 &rxq->rx_bd_ring);
2713
2714 if (rc)
2715 goto err;
2716
2717 /* Allocate FW completion ring */
2718 rc = edev->ops->common->chain_alloc(edev->cdev,
2719 QED_CHAIN_USE_TO_CONSUME,
2720 QED_CHAIN_MODE_PBL,
fc48b7a6 2721 RX_RING_SIZE,
2950219d
YM		 2722 sizeof(union eth_rx_cqe),
2723 &rxq->rx_comp_ring);
2724 if (rc)
2725 goto err;
2726
2727 /* Allocate buffers for the Rx ring */
2728 for (i = 0; i < rxq->num_rx_buffers; i++) {
2729 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2730 if (rc) {
2731 DP_ERR(edev,
2732 "Rx buffers allocation failed at index %d\n", i);
2733 goto err;
2734 }
2950219d
YM		 2735 }
2736
f86af2df 2737 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2738err:
f86af2df 2739 return rc;
2950219d
YM		 2740}
2741
2742static void qede_free_mem_txq(struct qede_dev *edev,
2743 struct qede_tx_queue *txq)
2744{
2745 /* Free the parallel SW ring */
2746 kfree(txq->sw_tx_ring);
2747
2748 /* Free the real RQ ring used by FW */
2749 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2750}
2751
2752/* This function allocates all memory needed per Tx queue */
2753static int qede_alloc_mem_txq(struct qede_dev *edev,
2754 struct qede_tx_queue *txq)
2755{
2756 int size, rc;
2757 union eth_tx_bd_types *p_virt;
2758
2759 txq->num_tx_buffers = edev->q_num_tx_buffers;
2760
2761 /* Allocate the parallel driver ring for Tx buffers */
2762 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2763 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2764 if (!txq->sw_tx_ring) {
2765 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2766 goto err;
2767 }
2768
2769 rc = edev->ops->common->chain_alloc(edev->cdev,
2770 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2771 QED_CHAIN_MODE_PBL,
2772 NUM_TX_BDS_MAX,
2773 sizeof(*p_virt),
2774 &txq->tx_pbl);
2775 if (rc)
2776 goto err;
2777
2778 return 0;
2779
2780err:
2781 qede_free_mem_txq(edev, txq);
2782 return -ENOMEM;
2783}
2784
2785/* This function frees all memory of a single fp */
2786static void qede_free_mem_fp(struct qede_dev *edev,
2787 struct qede_fastpath *fp)
2788{
2789 int tc;
2790
2791 qede_free_mem_sb(edev, fp->sb_info);
2792
2793 qede_free_mem_rxq(edev, fp->rxq);
2794
2795 for (tc = 0; tc < edev->num_tc; tc++)
2796 qede_free_mem_txq(edev, &fp->txqs[tc]);
2797}
2798
2799/* This function allocates all memory needed for a single fp (i.e. an entity
2800 * which contains status block, one rx queue and multiple per-TC tx queues.
2801 */
2802static int qede_alloc_mem_fp(struct qede_dev *edev,
2803 struct qede_fastpath *fp)
2804{
2805 int rc, tc;
2806
2807 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2808 if (rc)
2809 goto err;
2810
2811 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2812 if (rc)
2813 goto err;
2814
2815 for (tc = 0; tc < edev->num_tc; tc++) {
2816 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2817 if (rc)
2818 goto err;
2819 }
2820
2821 return 0;
2950219d 2822err:
f86af2df 2823 return rc;
2950219d
YM		 2824}
2825
2826static void qede_free_mem_load(struct qede_dev *edev)
2827{
2828 int i;
2829
2830 for_each_rss(i) {
2831 struct qede_fastpath *fp = &edev->fp_array[i];
2832
2833 qede_free_mem_fp(edev, fp);
2834 }
2835}
2836
2837/* This function allocates all qede memory at NIC load. */
2838static int qede_alloc_mem_load(struct qede_dev *edev)
2839{
2840 int rc = 0, rss_id;
2841
2842 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2843 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2844
2845 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2846 if (rc) {
2950219d 2847 DP_ERR(edev,
f86af2df
MC		 2848 "Failed to allocate memory for fastpath - rss id = %d\n",
2849 rss_id);
2850 qede_free_mem_load(edev);
2851 return rc;
2950219d 2852 }
2950219d
YM		 2853 }
2854
2855 return 0;
2856}
2857
2858/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2859static void qede_init_fp(struct qede_dev *edev)
2860{
2861 int rss_id, txq_index, tc;
2862 struct qede_fastpath *fp;
2863
2864 for_each_rss(rss_id) {
2865 fp = &edev->fp_array[rss_id];
2866
2867 fp->edev = edev;
2868 fp->rss_id = rss_id;
2869
2870 memset((void *)&fp->napi, 0, sizeof(fp->napi));
2871
2872 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
2873
2874 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
2875 fp->rxq->rxq_id = rss_id;
2876
2877 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
2878 for (tc = 0; tc < edev->num_tc; tc++) {
2879 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
2880 fp->txqs[tc].index = txq_index;
2881 }
2882
2883 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
2884 edev->ndev->name, rss_id);
2885 }
55482edc
MC		 2886
2887 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 2888}
2889
2890static int qede_set_real_num_queues(struct qede_dev *edev)
2891{
2892 int rc = 0;
2893
2894 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
2895 if (rc) {
2896 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
2897 return rc;
2898 }
2899 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
2900 if (rc) {
2901 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
2902 return rc;
2903 }
2904
2905 return 0;
2906}
2907
2908static void qede_napi_disable_remove(struct qede_dev *edev)
2909{
2910 int i;
2911
2912 for_each_rss(i) {
2913 napi_disable(&edev->fp_array[i].napi);
2914
2915 netif_napi_del(&edev->fp_array[i].napi);
2916 }
2917}
2918
2919static void qede_napi_add_enable(struct qede_dev *edev)
2920{
2921 int i;
2922
2923 /* Add NAPI objects */
2924 for_each_rss(i) {
2925 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
2926 qede_poll, NAPI_POLL_WEIGHT);
2927 napi_enable(&edev->fp_array[i].napi);
2928 }
2929}
2930
2931static void qede_sync_free_irqs(struct qede_dev *edev)
2932{
2933 int i;
2934
2935 for (i = 0; i < edev->int_info.used_cnt; i++) {
2936 if (edev->int_info.msix_cnt) {
2937 synchronize_irq(edev->int_info.msix[i].vector);
2938 free_irq(edev->int_info.msix[i].vector,
2939 &edev->fp_array[i]);
2940 } else {
2941 edev->ops->common->simd_handler_clean(edev->cdev, i);
2942 }
2943 }
2944
2945 edev->int_info.used_cnt = 0;
2946}
2947
2948static int qede_req_msix_irqs(struct qede_dev *edev)
2949{
2950 int i, rc;
2951
2952 /* Sanitize number of interrupts == number of prepared RSS queues */
2953 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
2954 DP_ERR(edev,
2955 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
2956 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
2957 return -EINVAL;
2958 }
2959
2960 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
2961 rc = request_irq(edev->int_info.msix[i].vector,
2962 qede_msix_fp_int, 0, edev->fp_array[i].name,
2963 &edev->fp_array[i]);
2964 if (rc) {
2965 DP_ERR(edev, "Request fp %d irq failed\n", i);
2966 qede_sync_free_irqs(edev);
2967 return rc;
2968 }
2969 DP_VERBOSE(edev, NETIF_MSG_INTR,
2970 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
2971 edev->fp_array[i].name, i,
2972 &edev->fp_array[i]);
2973 edev->int_info.used_cnt++;
2974 }
2975
2976 return 0;
2977}
2978
2979static void qede_simd_fp_handler(void *cookie)
2980{
2981 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
2982
2983 napi_schedule_irqoff(&fp->napi);
2984}
2985
2986static int qede_setup_irqs(struct qede_dev *edev)
2987{
2988 int i, rc = 0;
2989
2990 /* Learn Interrupt configuration */
2991 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
2992 if (rc)
2993 return rc;
2994
2995 if (edev->int_info.msix_cnt) {
2996 rc = qede_req_msix_irqs(edev);
2997 if (rc)
2998 return rc;
2999 edev->ndev->irq = edev->int_info.msix[0].vector;
3000 } else {
3001 const struct qed_common_ops *ops;
3002
3003 /* qed should learn receive the RSS ids and callbacks */
3004 ops = edev->ops->common;
3005 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
3006 ops->simd_handler_config(edev->cdev,
3007 &edev->fp_array[i], i,
3008 qede_simd_fp_handler);
3009 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
3010 }
3011 return 0;
3012}
3013
3014static int qede_drain_txq(struct qede_dev *edev,
3015 struct qede_tx_queue *txq,
3016 bool allow_drain)
3017{
3018 int rc, cnt = 1000;
3019
3020 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3021 if (!cnt) {
3022 if (allow_drain) {
3023 DP_NOTICE(edev,
3024 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3025 txq->index);
3026 rc = edev->ops->common->drain(edev->cdev);
3027 if (rc)
3028 return rc;
3029 return qede_drain_txq(edev, txq, false);
3030 }
3031 DP_NOTICE(edev,
3032 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3033 txq->index, txq->sw_tx_prod,
3034 txq->sw_tx_cons);
3035 return -ENODEV;
3036 }
3037 cnt--;
3038 usleep_range(1000, 2000);
3039 barrier();
3040 }
3041
3042 /* FW finished processing, wait for HW to transmit all tx packets */
3043 usleep_range(1000, 2000);
3044
3045 return 0;
3046}
3047
3048static int qede_stop_queues(struct qede_dev *edev)
3049{
3050 struct qed_update_vport_params vport_update_params;
3051 struct qed_dev *cdev = edev->cdev;
3052 int rc, tc, i;
3053
3054 /* Disable the vport */
3055 memset(&vport_update_params, 0, sizeof(vport_update_params));
3056 vport_update_params.vport_id = 0;
3057 vport_update_params.update_vport_active_flg = 1;
3058 vport_update_params.vport_active_flg = 0;
3059 vport_update_params.update_rss_flg = 0;
3060
3061 rc = edev->ops->vport_update(cdev, &vport_update_params);
3062 if (rc) {
3063 DP_ERR(edev, "Failed to update vport\n");
3064 return rc;
3065 }
3066
3067 /* Flush Tx queues. If needed, request drain from MCP */
3068 for_each_rss(i) {
3069 struct qede_fastpath *fp = &edev->fp_array[i];
3070
3071 for (tc = 0; tc < edev->num_tc; tc++) {
3072 struct qede_tx_queue *txq = &fp->txqs[tc];
3073
3074 rc = qede_drain_txq(edev, txq, true);
3075 if (rc)
3076 return rc;
3077 }
3078 }
3079
3080 /* Stop all Queues in reverse order*/
3081 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3082 struct qed_stop_rxq_params rx_params;
3083
3084 /* Stop the Tx Queue(s)*/
3085 for (tc = 0; tc < edev->num_tc; tc++) {
3086 struct qed_stop_txq_params tx_params;
3087
3088 tx_params.rss_id = i;
3089 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3090 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3091 if (rc) {
3092 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3093 tx_params.tx_queue_id);
3094 return rc;
3095 }
3096 }
3097
3098 /* Stop the Rx Queue*/
3099 memset(&rx_params, 0, sizeof(rx_params));
3100 rx_params.rss_id = i;
3101 rx_params.rx_queue_id = i;
3102
3103 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3104 if (rc) {
3105 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3106 return rc;
3107 }
3108 }
3109
3110 /* Stop the vport */
3111 rc = edev->ops->vport_stop(cdev, 0);
3112 if (rc)
3113 DP_ERR(edev, "Failed to stop VPORT\n");
3114
3115 return rc;
3116}
3117
3118static int qede_start_queues(struct qede_dev *edev)
3119{
3120 int rc, tc, i;
088c8618 3121 int vlan_removal_en = 1;
2950219d 3122 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3123 struct qed_update_vport_params vport_update_params;
3124 struct qed_queue_start_common_params q_params;
fefb0202 3125 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3126 struct qed_start_vport_params start = {0};
961acdea 3127 bool reset_rss_indir = false;
2950219d
YM		 3128
3129 if (!edev->num_rss) {
3130 DP_ERR(edev,
3131 "Cannot update V-VPORT as active as there are no Rx queues\n");
3132 return -EINVAL;
3133 }
3134
55482edc 3135 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3136 start.mtu = edev->ndev->mtu;
3137 start.vport_id = 0;
3138 start.drop_ttl0 = true;
3139 start.remove_inner_vlan = vlan_removal_en;
3140
3141 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3142
3143 if (rc) {
3144 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3145 return rc;
3146 }
3147
3148 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3149 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3150 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3151
3152 for_each_rss(i) {
3153 struct qede_fastpath *fp = &edev->fp_array[i];
3154 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3155
3156 memset(&q_params, 0, sizeof(q_params));
3157 q_params.rss_id = i;
3158 q_params.queue_id = i;
3159 q_params.vport_id = 0;
3160 q_params.sb = fp->sb_info->igu_sb_id;
3161 q_params.sb_idx = RX_PI;
3162
3163 rc = edev->ops->q_rx_start(cdev, &q_params,
3164 fp->rxq->rx_buf_size,
3165 fp->rxq->rx_bd_ring.p_phys_addr,
3166 phys_table,
3167 fp->rxq->rx_comp_ring.page_cnt,
3168 &fp->rxq->hw_rxq_prod_addr);
3169 if (rc) {
3170 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3171 return rc;
3172 }
3173
3174 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3175
3176 qede_update_rx_prod(edev, fp->rxq);
3177
3178 for (tc = 0; tc < edev->num_tc; tc++) {
3179 struct qede_tx_queue *txq = &fp->txqs[tc];
3180 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3181
3182 memset(&q_params, 0, sizeof(q_params));
3183 q_params.rss_id = i;
3184 q_params.queue_id = txq_index;
3185 q_params.vport_id = 0;
3186 q_params.sb = fp->sb_info->igu_sb_id;
3187 q_params.sb_idx = TX_PI(tc);
3188
3189 rc = edev->ops->q_tx_start(cdev, &q_params,
3190 txq->tx_pbl.pbl.p_phys_table,
3191 txq->tx_pbl.page_cnt,
3192 &txq->doorbell_addr);
3193 if (rc) {
3194 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3195 txq_index, rc);
3196 return rc;
3197 }
3198
3199 txq->hw_cons_ptr =
3200 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3201 SET_FIELD(txq->tx_db.data.params,
3202 ETH_DB_DATA_DEST, DB_DEST_XCM);
3203 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3204 DB_AGG_CMD_SET);
3205 SET_FIELD(txq->tx_db.data.params,
3206 ETH_DB_DATA_AGG_VAL_SEL,
3207 DQ_XCM_ETH_TX_BD_PROD_CMD);
3208
3209 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3210 }
3211 }
3212
3213 /* Prepare and send the vport enable */
3214 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3215 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3216 vport_update_params.update_vport_active_flg = 1;
3217 vport_update_params.vport_active_flg = 1;
3218
3219 /* Fill struct with RSS params */
3220 if (QEDE_RSS_CNT(edev) > 1) {
3221 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3222
3223 /* Need to validate current RSS config uses valid entries */
3224 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3225 if (edev->rss_params.rss_ind_table[i] >=
3226 edev->num_rss) {
3227 reset_rss_indir = true;
3228 break;
3229 }
3230 }
3231
3232 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3233 reset_rss_indir) {
3234 u16 val;
3235
3236 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3237 u16 indir_val;
3238
3239 val = QEDE_RSS_CNT(edev);
3240 indir_val = ethtool_rxfh_indir_default(i, val);
3241 edev->rss_params.rss_ind_table[i] = indir_val;
3242 }
3243 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3244 }
3245
3246 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3247 netdev_rss_key_fill(edev->rss_params.rss_key,
3248 sizeof(edev->rss_params.rss_key));
3249 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3250 }
3251
3252 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3253 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3254 QED_RSS_IPV6 |
3255 QED_RSS_IPV4_TCP |
3256 QED_RSS_IPV6_TCP;
3257 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3258 }
3259
3260 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3261 sizeof(vport_update_params.rss_params));
2950219d 3262 } else {
961acdea
SRK		 3263 memset(&vport_update_params.rss_params, 0,
3264 sizeof(vport_update_params.rss_params));
2950219d 3265 }
2950219d
YM		 3266
3267 rc = edev->ops->vport_update(cdev, &vport_update_params);
3268 if (rc) {
3269 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3270 return rc;
3271 }
3272
3273 return 0;
3274}
3275
0d8e0aa0
SK		 3276static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3277 enum qed_filter_xcast_params_type opcode,
3278 unsigned char *mac, int num_macs)
3279{
3280 struct qed_filter_params filter_cmd;
3281 int i;
3282
3283 memset(&filter_cmd, 0, sizeof(filter_cmd));
3284 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3285 filter_cmd.filter.mcast.type = opcode;
3286 filter_cmd.filter.mcast.num = num_macs;
3287
3288 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3289 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3290
3291 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3292}
3293
2950219d
YM		 3294enum qede_unload_mode {
3295 QEDE_UNLOAD_NORMAL,
3296};
3297
3298static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3299{
a2ec6172 3300 struct qed_link_params link_params;
2950219d
YM		 3301 int rc;
3302
3303 DP_INFO(edev, "Starting qede unload\n");
3304
0d8e0aa0
SK		 3305 mutex_lock(&edev->qede_lock);
3306 edev->state = QEDE_STATE_CLOSED;
3307
2950219d
YM		 3308 /* Close OS Tx */
3309 netif_tx_disable(edev->ndev);
3310 netif_carrier_off(edev->ndev);
3311
a2ec6172
SK		 3312 /* Reset the link */
3313 memset(&link_params, 0, sizeof(link_params));
3314 link_params.link_up = false;
3315 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3316 rc = qede_stop_queues(edev);
3317 if (rc) {
3318 qede_sync_free_irqs(edev);
3319 goto out;
3320 }
3321
3322 DP_INFO(edev, "Stopped Queues\n");
3323
7c1bfcad 3324 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3325 edev->ops->fastpath_stop(edev->cdev);
3326
3327 /* Release the interrupts */
3328 qede_sync_free_irqs(edev);
3329 edev->ops->common->set_fp_int(edev->cdev, 0);
3330
3331 qede_napi_disable_remove(edev);
3332
3333 qede_free_mem_load(edev);
3334 qede_free_fp_array(edev);
3335
3336out:
3337 mutex_unlock(&edev->qede_lock);
3338 DP_INFO(edev, "Ending qede unload\n");
3339}
3340
3341enum qede_load_mode {
3342 QEDE_LOAD_NORMAL,
3343};
3344
3345static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3346{
a2ec6172
SK		 3347 struct qed_link_params link_params;
3348 struct qed_link_output link_output;
2950219d
YM		 3349 int rc;
3350
3351 DP_INFO(edev, "Starting qede load\n");
3352
3353 rc = qede_set_num_queues(edev);
3354 if (rc)
3355 goto err0;
3356
3357 rc = qede_alloc_fp_array(edev);
3358 if (rc)
3359 goto err0;
3360
3361 qede_init_fp(edev);
3362
3363 rc = qede_alloc_mem_load(edev);
3364 if (rc)
3365 goto err1;
3366 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3367 QEDE_RSS_CNT(edev), edev->num_tc);
3368
3369 rc = qede_set_real_num_queues(edev);
3370 if (rc)
3371 goto err2;
3372
3373 qede_napi_add_enable(edev);
3374 DP_INFO(edev, "Napi added and enabled\n");
3375
3376 rc = qede_setup_irqs(edev);
3377 if (rc)
3378 goto err3;
3379 DP_INFO(edev, "Setup IRQs succeeded\n");
3380
3381 rc = qede_start_queues(edev);
3382 if (rc)
3383 goto err4;
3384 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3385
3386 /* Add primary mac and set Rx filters */
3387 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3388
0d8e0aa0
SK		 3389 mutex_lock(&edev->qede_lock);
3390 edev->state = QEDE_STATE_OPEN;
3391 mutex_unlock(&edev->qede_lock);
a2ec6172 3392
7c1bfcad
SRK		 3393 /* Program un-configured VLANs */
3394 qede_configure_vlan_filters(edev);
3395
a2ec6172
SK		 3396 /* Ask for link-up using current configuration */
3397 memset(&link_params, 0, sizeof(link_params));
3398 link_params.link_up = true;
3399 edev->ops->common->set_link(edev->cdev, &link_params);
3400
3401 /* Query whether link is already-up */
3402 memset(&link_output, 0, sizeof(link_output));
3403 edev->ops->common->get_link(edev->cdev, &link_output);
3404 qede_link_update(edev, &link_output);
3405
2950219d
YM		 3406 DP_INFO(edev, "Ending successfully qede load\n");
3407
3408 return 0;
3409
3410err4:
3411 qede_sync_free_irqs(edev);
3412 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3413err3:
3414 qede_napi_disable_remove(edev);
3415err2:
3416 qede_free_mem_load(edev);
3417err1:
3418 edev->ops->common->set_fp_int(edev->cdev, 0);
3419 qede_free_fp_array(edev);
3420 edev->num_rss = 0;
3421err0:
3422 return rc;
3423}
3424
133fac0e
SK		 3425void qede_reload(struct qede_dev *edev,
3426 void (*func)(struct qede_dev *, union qede_reload_args *),
3427 union qede_reload_args *args)
3428{
3429 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3430 /* Call function handler to update parameters
3431 * needed for function load.
3432 */
3433 if (func)
3434 func(edev, args);
3435
3436 qede_load(edev, QEDE_LOAD_NORMAL);
3437
3438 mutex_lock(&edev->qede_lock);
3439 qede_config_rx_mode(edev->ndev);
3440 mutex_unlock(&edev->qede_lock);
3441}
3442
2950219d
YM		 3443/* called with rtnl_lock */
3444static int qede_open(struct net_device *ndev)
3445{
3446 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3447 int rc;
2950219d
YM		 3448
3449 netif_carrier_off(ndev);
3450
3451 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3452
b18e170c
MC		 3453 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3454
3455 if (rc)
3456 return rc;
3457
3458#ifdef CONFIG_QEDE_VXLAN
3459 vxlan_get_rx_port(ndev);
9a109dd0
MC		 3460#endif
3461#ifdef CONFIG_QEDE_GENEVE
3462 geneve_get_rx_port(ndev);
b18e170c
MC		 3463#endif
3464 return 0;
2950219d
YM		 3465}
3466
3467static int qede_close(struct net_device *ndev)
3468{
3469 struct qede_dev *edev = netdev_priv(ndev);
3470
3471 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3472
3473 return 0;
3474}
0d8e0aa0 3475
a2ec6172
SK		 3476static void qede_link_update(void *dev, struct qed_link_output *link)
3477{
3478 struct qede_dev *edev = dev;
3479
3480 if (!netif_running(edev->ndev)) {
3481 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3482 return;
3483 }
3484
3485 if (link->link_up) {
8e025ae2
YM		 3486 if (!netif_carrier_ok(edev->ndev)) {
3487 DP_NOTICE(edev, "Link is up\n");
3488 netif_tx_start_all_queues(edev->ndev);
3489 netif_carrier_on(edev->ndev);
3490 }
a2ec6172 3491 } else {
8e025ae2
YM		 3492 if (netif_carrier_ok(edev->ndev)) {
3493 DP_NOTICE(edev, "Link is down\n");
3494 netif_tx_disable(edev->ndev);
3495 netif_carrier_off(edev->ndev);
3496 }
a2ec6172
SK		 3497 }
3498}
3499
0d8e0aa0
SK		 3500static int qede_set_mac_addr(struct net_device *ndev, void *p)
3501{
3502 struct qede_dev *edev = netdev_priv(ndev);
3503 struct sockaddr *addr = p;
3504 int rc;
3505
3506 ASSERT_RTNL(); /* @@@TBD To be removed */
3507
3508 DP_INFO(edev, "Set_mac_addr called\n");
3509
3510 if (!is_valid_ether_addr(addr->sa_data)) {
3511 DP_NOTICE(edev, "The MAC address is not valid\n");
3512 return -EFAULT;
3513 }
3514
3515 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3516
3517 if (!netif_running(ndev)) {
3518 DP_NOTICE(edev, "The device is currently down\n");
3519 return 0;
3520 }
3521
3522 /* Remove the previous primary mac */
3523 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3524 edev->primary_mac);
3525 if (rc)
3526 return rc;
3527
3528 /* Add MAC filter according to the new unicast HW MAC address */
3529 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3530 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3531 edev->primary_mac);
3532}
3533
3534static int
3535qede_configure_mcast_filtering(struct net_device *ndev,
3536 enum qed_filter_rx_mode_type *accept_flags)
3537{
3538 struct qede_dev *edev = netdev_priv(ndev);
3539 unsigned char *mc_macs, *temp;
3540 struct netdev_hw_addr *ha;
3541 int rc = 0, mc_count;
3542 size_t size;
3543
3544 size = 64 * ETH_ALEN;
3545
3546 mc_macs = kzalloc(size, GFP_KERNEL);
3547 if (!mc_macs) {
3548 DP_NOTICE(edev,
3549 "Failed to allocate memory for multicast MACs\n");
3550 rc = -ENOMEM;
3551 goto exit;
3552 }
3553
3554 temp = mc_macs;
3555
3556 /* Remove all previously configured MAC filters */
3557 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3558 mc_macs, 1);
3559 if (rc)
3560 goto exit;
3561
3562 netif_addr_lock_bh(ndev);
3563
3564 mc_count = netdev_mc_count(ndev);
3565 if (mc_count < 64) {
3566 netdev_for_each_mc_addr(ha, ndev) {
3567 ether_addr_copy(temp, ha->addr);
3568 temp += ETH_ALEN;
3569 }
3570 }
3571
3572 netif_addr_unlock_bh(ndev);
3573
3574 /* Check for all multicast @@@TBD resource allocation */
3575 if ((ndev->flags & IFF_ALLMULTI) ||
3576 (mc_count > 64)) {
3577 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3578 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3579 } else {
3580 /* Add all multicast MAC filters */
3581 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3582 mc_macs, mc_count);
3583 }
3584
3585exit:
3586 kfree(mc_macs);
3587 return rc;
3588}
3589
3590static void qede_set_rx_mode(struct net_device *ndev)
3591{
3592 struct qede_dev *edev = netdev_priv(ndev);
3593
3594 DP_INFO(edev, "qede_set_rx_mode called\n");
3595
3596 if (edev->state != QEDE_STATE_OPEN) {
3597 DP_INFO(edev,
3598 "qede_set_rx_mode called while interface is down\n");
3599 } else {
3600 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3601 schedule_delayed_work(&edev->sp_task, 0);
3602 }
3603}
3604
3605/* Must be called with qede_lock held */
3606static void qede_config_rx_mode(struct net_device *ndev)
3607{
3608 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3609 struct qede_dev *edev = netdev_priv(ndev);
3610 struct qed_filter_params rx_mode;
3611 unsigned char *uc_macs, *temp;
3612 struct netdev_hw_addr *ha;
3613 int rc, uc_count;
3614 size_t size;
3615
3616 netif_addr_lock_bh(ndev);
3617
3618 uc_count = netdev_uc_count(ndev);
3619 size = uc_count * ETH_ALEN;
3620
3621 uc_macs = kzalloc(size, GFP_ATOMIC);
3622 if (!uc_macs) {
3623 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3624 netif_addr_unlock_bh(ndev);
3625 return;
3626 }
3627
3628 temp = uc_macs;
3629 netdev_for_each_uc_addr(ha, ndev) {
3630 ether_addr_copy(temp, ha->addr);
3631 temp += ETH_ALEN;
3632 }
3633
3634 netif_addr_unlock_bh(ndev);
3635
3636 /* Configure the struct for the Rx mode */
3637 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3638 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3639
3640 /* Remove all previous unicast secondary macs and multicast macs
3641 * (configrue / leave the primary mac)
3642 */
3643 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3644 edev->primary_mac);
3645 if (rc)
3646 goto out;
3647
3648 /* Check for promiscuous */
3649 if ((ndev->flags & IFF_PROMISC) ||
3650 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3651 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3652 } else {
3653 /* Add MAC filters according to the unicast secondary macs */
3654 int i;
3655
3656 temp = uc_macs;
3657 for (i = 0; i < uc_count; i++) {
3658 rc = qede_set_ucast_rx_mac(edev,
3659 QED_FILTER_XCAST_TYPE_ADD,
3660 temp);
3661 if (rc)
3662 goto out;
3663
3664 temp += ETH_ALEN;
3665 }
3666
3667 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3668 if (rc)
3669 goto out;
3670 }
3671
7c1bfcad
SRK		 3672 /* take care of VLAN mode */
3673 if (ndev->flags & IFF_PROMISC) {
3674 qede_config_accept_any_vlan(edev, true);
3675 } else if (!edev->non_configured_vlans) {
3676 /* It's possible that accept_any_vlan mode is set due to a
3677 * previous setting of IFF_PROMISC. If vlan credits are
3678 * sufficient, disable accept_any_vlan.
3679 */
3680 qede_config_accept_any_vlan(edev, false);
3681 }
3682
0d8e0aa0
SK		 3683 rx_mode.filter.accept_flags = accept_flags;
3684 edev->ops->filter_config(edev->cdev, &rx_mode);
3685out:
3686 kfree(uc_macs);
3687}
Linux kernel - Deliverables
This page took 0.233349 seconds and 5 git commands to generate.