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qed: Prevent VFs from pause flooding
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
f9f082a9 27#include <net/udp_tunnel.h>
e712d52b
YM		 28#include <linux/ip.h>
29#include <net/ipv6.h>
30#include <net/tcp.h>
31#include <linux/if_ether.h>
32#include <linux/if_vlan.h>
33#include <linux/pkt_sched.h>
34#include <linux/ethtool.h>
35#include <linux/in.h>
36#include <linux/random.h>
37#include <net/ip6_checksum.h>
38#include <linux/bitops.h>
39
40#include "qede.h"
41
5abd7e92
YM		 42static char version[] =
43 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 44
5abd7e92 45MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
49static uint debug;
50module_param(debug, uint, 0);
51MODULE_PARM_DESC(debug, " Default debug msglevel");
52
53static const struct qed_eth_ops *qed_ops;
54
55#define CHIP_NUM_57980S_40 0x1634
0e7441d7 56#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 57#define CHIP_NUM_57980S_MF 0x1636
58#define CHIP_NUM_57980S_100 0x1644
59#define CHIP_NUM_57980S_50 0x1654
60#define CHIP_NUM_57980S_25 0x1656
fefb0202 61#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 62
63#ifndef PCI_DEVICE_ID_NX2_57980E
64#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
65#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
66#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
67#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
68#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
69#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 70#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 71#endif
72
fefb0202
YM		 73enum qede_pci_private {
74 QEDE_PRIVATE_PF,
75 QEDE_PRIVATE_VF
76};
77
e712d52b 78static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 79 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
80 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
81 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
82 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
83 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 85#ifdef CONFIG_QED_SRIOV
fefb0202 86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
14b84e86 87#endif
e712d52b
YM		 88 { 0 }
89};
90
91MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
92
93static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
94
95#define TX_TIMEOUT (5 * HZ)
96
97static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 98static int qede_alloc_rx_buffer(struct qede_dev *edev,
99 struct qede_rx_queue *rxq);
a2ec6172 100static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 101
fefb0202 102#ifdef CONFIG_QED_SRIOV
08feecd7
YM		 103static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
104{
105 struct qede_dev *edev = netdev_priv(ndev);
106
107 if (vlan > 4095) {
108 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
109 return -EINVAL;
110 }
111
112 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
113 vlan, vf);
114
115 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
116}
117
eff16960
YM		 118static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
119{
120 struct qede_dev *edev = netdev_priv(ndev);
121
122 DP_VERBOSE(edev, QED_MSG_IOV,
123 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
124 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
125
126 if (!is_valid_ether_addr(mac)) {
127 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
128 return -EINVAL;
129 }
130
131 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
132}
133
fefb0202
YM		 134static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
135{
136 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e
YM		 137 struct qed_dev_info *qed_info = &edev->dev_info.common;
138 int rc;
fefb0202
YM		 139
140 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
141
831bfb0e
YM		 142 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
143
144 /* Enable/Disable Tx switching for PF */
145 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
146 qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
147 struct qed_update_vport_params params;
148
149 memset(&params, 0, sizeof(params));
150 params.vport_id = 0;
151 params.update_tx_switching_flg = 1;
152 params.tx_switching_flg = num_vfs_param ? 1 : 0;
153 edev->ops->vport_update(edev->cdev, &params);
154 }
155
156 return rc;
fefb0202
YM		 157}
158#endif
159
e712d52b
YM		 160static struct pci_driver qede_pci_driver = {
161 .name = "qede",
162 .id_table = qede_pci_tbl,
163 .probe = qede_probe,
164 .remove = qede_remove,
fefb0202
YM		 165#ifdef CONFIG_QED_SRIOV
166 .sriov_configure = qede_sriov_configure,
167#endif
e712d52b
YM		 168};
169
eff16960
YM		 170static void qede_force_mac(void *dev, u8 *mac)
171{
172 struct qede_dev *edev = dev;
173
174 ether_addr_copy(edev->ndev->dev_addr, mac);
175 ether_addr_copy(edev->primary_mac, mac);
176}
177
a2ec6172
SK		 178static struct qed_eth_cb_ops qede_ll_ops = {
179 {
180 .link_update = qede_link_update,
181 },
eff16960 182 .force_mac = qede_force_mac,
a2ec6172
SK		 183};
184
2950219d
YM		 185static int qede_netdev_event(struct notifier_block *this, unsigned long event,
186 void *ptr)
187{
188 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
189 struct ethtool_drvinfo drvinfo;
190 struct qede_dev *edev;
191
192 /* Currently only support name change */
193 if (event != NETDEV_CHANGENAME)
194 goto done;
195
196 /* Check whether this is a qede device */
197 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
198 goto done;
199
200 memset(&drvinfo, 0, sizeof(drvinfo));
201 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
202 if (strcmp(drvinfo.driver, "qede"))
203 goto done;
204 edev = netdev_priv(ndev);
205
206 /* Notify qed of the name change */
207 if (!edev->ops || !edev->ops->common)
208 goto done;
209 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
210 "qede");
211
212done:
213 return NOTIFY_DONE;
214}
215
216static struct notifier_block qede_netdev_notifier = {
217 .notifier_call = qede_netdev_event,
218};
219
e712d52b
YM		 220static
221int __init qede_init(void)
222{
223 int ret;
e712d52b 224
525ef5c0 225 pr_info("qede_init: %s\n", version);
e712d52b 226
95114344 227 qed_ops = qed_get_eth_ops();
e712d52b
YM		 228 if (!qed_ops) {
229 pr_notice("Failed to get qed ethtool operations\n");
230 return -EINVAL;
231 }
232
2950219d
YM		 233 /* Must register notifier before pci ops, since we might miss
234 * interface rename after pci probe and netdev registeration.
235 */
236 ret = register_netdevice_notifier(&qede_netdev_notifier);
237 if (ret) {
238 pr_notice("Failed to register netdevice_notifier\n");
239 qed_put_eth_ops();
240 return -EINVAL;
241 }
242
e712d52b
YM		 243 ret = pci_register_driver(&qede_pci_driver);
244 if (ret) {
245 pr_notice("Failed to register driver\n");
2950219d 246 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 247 qed_put_eth_ops();
248 return -EINVAL;
249 }
250
251 return 0;
252}
253
254static void __exit qede_cleanup(void)
255{
525ef5c0
YM		 256 if (debug & QED_LOG_INFO_MASK)
257 pr_info("qede_cleanup called\n");
e712d52b 258
2950219d 259 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 260 pci_unregister_driver(&qede_pci_driver);
261 qed_put_eth_ops();
262}
263
264module_init(qede_init);
265module_exit(qede_cleanup);
266
2950219d
YM		 267/* -------------------------------------------------------------------------
268 * START OF FAST-PATH
269 * -------------------------------------------------------------------------
270 */
271
272/* Unmap the data and free skb */
273static int qede_free_tx_pkt(struct qede_dev *edev,
1a635e48 274 struct qede_tx_queue *txq, int *len)
2950219d
YM		 275{
276 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
277 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
278 struct eth_tx_1st_bd *first_bd;
279 struct eth_tx_bd *tx_data_bd;
280 int bds_consumed = 0;
281 int nbds;
282 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
283 int i, split_bd_len = 0;
284
285 if (unlikely(!skb)) {
286 DP_ERR(edev,
287 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
288 idx, txq->sw_tx_cons, txq->sw_tx_prod);
289 return -1;
290 }
291
292 *len = skb->len;
293
294 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
295
296 bds_consumed++;
297
298 nbds = first_bd->data.nbds;
299
300 if (data_split) {
301 struct eth_tx_bd *split = (struct eth_tx_bd *)
302 qed_chain_consume(&txq->tx_pbl);
303 split_bd_len = BD_UNMAP_LEN(split);
304 bds_consumed++;
305 }
306 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
307 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
308
309 /* Unmap the data of the skb frags */
310 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
311 tx_data_bd = (struct eth_tx_bd *)
312 qed_chain_consume(&txq->tx_pbl);
313 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
314 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
315 }
316
317 while (bds_consumed++ < nbds)
318 qed_chain_consume(&txq->tx_pbl);
319
320 /* Free skb */
321 dev_kfree_skb_any(skb);
322 txq->sw_tx_ring[idx].skb = NULL;
323 txq->sw_tx_ring[idx].flags = 0;
324
325 return 0;
326}
327
328/* Unmap the data and free skb when mapping failed during start_xmit */
329static void qede_free_failed_tx_pkt(struct qede_dev *edev,
330 struct qede_tx_queue *txq,
331 struct eth_tx_1st_bd *first_bd,
1a635e48 332 int nbd, bool data_split)
2950219d
YM		 333{
334 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
335 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
336 struct eth_tx_bd *tx_data_bd;
337 int i, split_bd_len = 0;
338
339 /* Return prod to its position before this skb was handled */
340 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 341 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 342
343 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
344
345 if (data_split) {
346 struct eth_tx_bd *split = (struct eth_tx_bd *)
347 qed_chain_produce(&txq->tx_pbl);
348 split_bd_len = BD_UNMAP_LEN(split);
349 nbd--;
350 }
351
352 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
353 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
354
355 /* Unmap the data of the skb frags */
356 for (i = 0; i < nbd; i++) {
357 tx_data_bd = (struct eth_tx_bd *)
358 qed_chain_produce(&txq->tx_pbl);
359 if (tx_data_bd->nbytes)
360 dma_unmap_page(&edev->pdev->dev,
361 BD_UNMAP_ADDR(tx_data_bd),
362 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
363 }
364
365 /* Return again prod to its position before this skb was handled */
366 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 367 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 368
369 /* Free skb */
370 dev_kfree_skb_any(skb);
371 txq->sw_tx_ring[idx].skb = NULL;
372 txq->sw_tx_ring[idx].flags = 0;
373}
374
375static u32 qede_xmit_type(struct qede_dev *edev,
1a635e48 376 struct sk_buff *skb, int *ipv6_ext)
2950219d
YM		 377{
378 u32 rc = XMIT_L4_CSUM;
379 __be16 l3_proto;
380
381 if (skb->ip_summed != CHECKSUM_PARTIAL)
382 return XMIT_PLAIN;
383
384 l3_proto = vlan_get_protocol(skb);
385 if (l3_proto == htons(ETH_P_IPV6) &&
386 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
387 *ipv6_ext = 1;
388
14db81de
MC		 389 if (skb->encapsulation)
390 rc |= XMIT_ENC;
391
2950219d
YM		 392 if (skb_is_gso(skb))
393 rc |= XMIT_LSO;
394
395 return rc;
396}
397
398static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
399 struct eth_tx_2nd_bd *second_bd,
400 struct eth_tx_3rd_bd *third_bd)
401{
402 u8 l4_proto;
fc48b7a6 403 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 404
fc48b7a6 405 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 406
fc48b7a6 407 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 408 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
409 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
410
fc48b7a6 411 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 412 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
413
414 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
415 l4_proto = ipv6_hdr(skb)->nexthdr;
416 else
417 l4_proto = ip_hdr(skb)->protocol;
418
419 if (l4_proto == IPPROTO_UDP)
fc48b7a6 420 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 421
fc48b7a6 422 if (third_bd)
2950219d 423 third_bd->data.bitfields |=
fc48b7a6
YM		 424 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
425 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
426 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 427
fc48b7a6 428 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 429 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
430}
431
432static int map_frag_to_bd(struct qede_dev *edev,
1a635e48 433 skb_frag_t *frag, struct eth_tx_bd *bd)
2950219d
YM		 434{
435 dma_addr_t mapping;
436
437 /* Map skb non-linear frag data for DMA */
438 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
1a635e48 439 skb_frag_size(frag), DMA_TO_DEVICE);
2950219d
YM		 440 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
441 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
442 return -ENOMEM;
443 }
444
445 /* Setup the data pointer of the frag data */
446 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
447
448 return 0;
449}
450
14db81de
MC		 451static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
452{
453 if (is_encap_pkt)
454 return (skb_inner_transport_header(skb) +
455 inner_tcp_hdrlen(skb) - skb->data);
456 else
457 return (skb_transport_header(skb) +
458 tcp_hdrlen(skb) - skb->data);
459}
460
b1199b10
YM		 461/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
462#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
463static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
464 u8 xmit_type)
465{
466 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
467
468 if (xmit_type & XMIT_LSO) {
469 int hlen;
470
14db81de 471 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 472
473 /* linear payload would require its own BD */
474 if (skb_headlen(skb) > hlen)
475 allowed_frags--;
476 }
477
478 return (skb_shinfo(skb)->nr_frags > allowed_frags);
479}
480#endif
481
312e0676
MC		 482static inline void qede_update_tx_producer(struct qede_tx_queue *txq)
483{
484 /* wmb makes sure that the BDs data is updated before updating the
485 * producer, otherwise FW may read old data from the BDs.
486 */
487 wmb();
488 barrier();
489 writel(txq->tx_db.raw, txq->doorbell_addr);
490
491 /* mmiowb is needed to synchronize doorbell writes from more than one
492 * processor. It guarantees that the write arrives to the device before
493 * the queue lock is released and another start_xmit is called (possibly
494 * on another CPU). Without this barrier, the next doorbell can bypass
495 * this doorbell. This is applicable to IA64/Altix systems.
496 */
497 mmiowb();
498}
499
2950219d 500/* Main transmit function */
1a635e48
YM		 501static netdev_tx_t qede_start_xmit(struct sk_buff *skb,
502 struct net_device *ndev)
2950219d
YM		 503{
504 struct qede_dev *edev = netdev_priv(ndev);
505 struct netdev_queue *netdev_txq;
506 struct qede_tx_queue *txq;
507 struct eth_tx_1st_bd *first_bd;
508 struct eth_tx_2nd_bd *second_bd = NULL;
509 struct eth_tx_3rd_bd *third_bd = NULL;
510 struct eth_tx_bd *tx_data_bd = NULL;
511 u16 txq_index;
512 u8 nbd = 0;
513 dma_addr_t mapping;
514 int rc, frag_idx = 0, ipv6_ext = 0;
515 u8 xmit_type;
516 u16 idx;
517 u16 hlen;
810810ff 518 bool data_split = false;
2950219d
YM		 519
520 /* Get tx-queue context and netdev index */
521 txq_index = skb_get_queue_mapping(skb);
522 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
523 txq = QEDE_TX_QUEUE(edev, txq_index);
524 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
525
1a635e48 526 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) < (MAX_SKB_FRAGS + 1));
2950219d
YM		 527
528 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
529
b1199b10
YM		 530#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
531 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
532 if (skb_linearize(skb)) {
533 DP_NOTICE(edev,
534 "SKB linearization failed - silently dropping this SKB\n");
535 dev_kfree_skb_any(skb);
536 return NETDEV_TX_OK;
537 }
538 }
539#endif
540
2950219d
YM		 541 /* Fill the entry in the SW ring and the BDs in the FW ring */
542 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
543 txq->sw_tx_ring[idx].skb = skb;
544 first_bd = (struct eth_tx_1st_bd *)
545 qed_chain_produce(&txq->tx_pbl);
546 memset(first_bd, 0, sizeof(*first_bd));
547 first_bd->data.bd_flags.bitfields =
548 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
549
550 /* Map skb linear data for DMA and set in the first BD */
551 mapping = dma_map_single(&edev->pdev->dev, skb->data,
552 skb_headlen(skb), DMA_TO_DEVICE);
553 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
554 DP_NOTICE(edev, "SKB mapping failed\n");
555 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
312e0676 556 qede_update_tx_producer(txq);
2950219d
YM		 557 return NETDEV_TX_OK;
558 }
559 nbd++;
560 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
561
562 /* In case there is IPv6 with extension headers or LSO we need 2nd and
563 * 3rd BDs.
564 */
565 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
566 second_bd = (struct eth_tx_2nd_bd *)
567 qed_chain_produce(&txq->tx_pbl);
568 memset(second_bd, 0, sizeof(*second_bd));
569
570 nbd++;
571 third_bd = (struct eth_tx_3rd_bd *)
572 qed_chain_produce(&txq->tx_pbl);
573 memset(third_bd, 0, sizeof(*third_bd));
574
575 nbd++;
576 /* We need to fill in additional data in second_bd... */
577 tx_data_bd = (struct eth_tx_bd *)second_bd;
578 }
579
580 if (skb_vlan_tag_present(skb)) {
581 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
582 first_bd->data.bd_flags.bitfields |=
583 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
584 }
585
586 /* Fill the parsing flags & params according to the requested offload */
587 if (xmit_type & XMIT_L4_CSUM) {
588 /* We don't re-calculate IP checksum as it is already done by
589 * the upper stack
590 */
591 first_bd->data.bd_flags.bitfields |=
592 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
593
14db81de
MC		 594 if (xmit_type & XMIT_ENC) {
595 first_bd->data.bd_flags.bitfields |=
596 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
351a4ded
YM		 597 first_bd->data.bitfields |=
598 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
14db81de 599 }
fc48b7a6 600
2950219d
YM		 601 /* If the packet is IPv6 with extension header, indicate that
602 * to FW and pass few params, since the device cracker doesn't
603 * support parsing IPv6 with extension header/s.
604 */
605 if (unlikely(ipv6_ext))
606 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
607 }
608
609 if (xmit_type & XMIT_LSO) {
610 first_bd->data.bd_flags.bitfields |=
611 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
612 third_bd->data.lso_mss =
613 cpu_to_le16(skb_shinfo(skb)->gso_size);
614
14db81de
MC		 615 if (unlikely(xmit_type & XMIT_ENC)) {
616 first_bd->data.bd_flags.bitfields |=
617 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
618 hlen = qede_get_skb_hlen(skb, true);
619 } else {
620 first_bd->data.bd_flags.bitfields |=
621 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
622 hlen = qede_get_skb_hlen(skb, false);
623 }
2950219d
YM		 624
625 /* @@@TBD - if will not be removed need to check */
626 third_bd->data.bitfields |=
fc48b7a6 627 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 628
629 /* Make life easier for FW guys who can't deal with header and
630 * data on same BD. If we need to split, use the second bd...
631 */
632 if (unlikely(skb_headlen(skb) > hlen)) {
633 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
634 "TSO split header size is %d (%x:%x)\n",
635 first_bd->nbytes, first_bd->addr.hi,
636 first_bd->addr.lo);
637
638 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
639 le32_to_cpu(first_bd->addr.lo)) +
640 hlen;
641
642 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
643 le16_to_cpu(first_bd->nbytes) -
644 hlen);
645
646 /* this marks the BD as one that has no
647 * individual mapping
648 */
649 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
650
651 first_bd->nbytes = cpu_to_le16(hlen);
652
653 tx_data_bd = (struct eth_tx_bd *)third_bd;
654 data_split = true;
655 }
351a4ded
YM		 656 } else {
657 first_bd->data.bitfields |=
658 (skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) <<
659 ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2950219d
YM		 660 }
661
662 /* Handle fragmented skb */
663 /* special handle for frags inside 2nd and 3rd bds.. */
664 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
665 rc = map_frag_to_bd(edev,
666 &skb_shinfo(skb)->frags[frag_idx],
667 tx_data_bd);
668 if (rc) {
669 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
670 data_split);
312e0676 671 qede_update_tx_producer(txq);
2950219d
YM		 672 return NETDEV_TX_OK;
673 }
674
675 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
676 tx_data_bd = (struct eth_tx_bd *)third_bd;
677 else
678 tx_data_bd = NULL;
679
680 frag_idx++;
681 }
682
683 /* map last frags into 4th, 5th .... */
684 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
685 tx_data_bd = (struct eth_tx_bd *)
686 qed_chain_produce(&txq->tx_pbl);
687
688 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
689
690 rc = map_frag_to_bd(edev,
691 &skb_shinfo(skb)->frags[frag_idx],
692 tx_data_bd);
693 if (rc) {
694 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
695 data_split);
312e0676 696 qede_update_tx_producer(txq);
2950219d
YM		 697 return NETDEV_TX_OK;
698 }
699 }
700
701 /* update the first BD with the actual num BDs */
702 first_bd->data.nbds = nbd;
703
704 netdev_tx_sent_queue(netdev_txq, skb->len);
705
706 skb_tx_timestamp(skb);
707
708 /* Advance packet producer only before sending the packet since mapping
709 * of pages may fail.
710 */
711 txq->sw_tx_prod++;
712
713 /* 'next page' entries are counted in the producer value */
714 txq->tx_db.data.bd_prod =
715 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
716
312e0676
MC		 717 if (!skb->xmit_more || netif_tx_queue_stopped(netdev_txq))
718 qede_update_tx_producer(txq);
2950219d
YM		 719
720 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
721 < (MAX_SKB_FRAGS + 1))) {
722 netif_tx_stop_queue(netdev_txq);
68db9ec2 723 txq->stopped_cnt++;
2950219d
YM		 724 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
725 "Stop queue was called\n");
726 /* paired memory barrier is in qede_tx_int(), we have to keep
727 * ordering of set_bit() in netif_tx_stop_queue() and read of
728 * fp->bd_tx_cons
729 */
730 smp_mb();
731
732 if (qed_chain_get_elem_left(&txq->tx_pbl)
733 >= (MAX_SKB_FRAGS + 1) &&
734 (edev->state == QEDE_STATE_OPEN)) {
735 netif_tx_wake_queue(netdev_txq);
736 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
737 "Wake queue was called\n");
738 }
739 }
740
741 return NETDEV_TX_OK;
742}
743
16f46bf0 744int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 745{
746 u16 hw_bd_cons;
747
748 /* Tell compiler that consumer and producer can change */
749 barrier();
750 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
751 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
752 return 0;
753
754 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
755}
756
1a635e48 757static int qede_tx_int(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 758{
759 struct netdev_queue *netdev_txq;
760 u16 hw_bd_cons;
761 unsigned int pkts_compl = 0, bytes_compl = 0;
762 int rc;
763
764 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
765
766 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
767 barrier();
768
769 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
770 int len = 0;
771
772 rc = qede_free_tx_pkt(edev, txq, &len);
773 if (rc) {
774 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
775 hw_bd_cons,
776 qed_chain_get_cons_idx(&txq->tx_pbl));
777 break;
778 }
779
780 bytes_compl += len;
781 pkts_compl++;
782 txq->sw_tx_cons++;
68db9ec2 783 txq->xmit_pkts++;
2950219d
YM		 784 }
785
786 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
787
788 /* Need to make the tx_bd_cons update visible to start_xmit()
789 * before checking for netif_tx_queue_stopped(). Without the
790 * memory barrier, there is a small possibility that
791 * start_xmit() will miss it and cause the queue to be stopped
792 * forever.
793 * On the other hand we need an rmb() here to ensure the proper
794 * ordering of bit testing in the following
795 * netif_tx_queue_stopped(txq) call.
796 */
797 smp_mb();
798
799 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
800 /* Taking tx_lock is needed to prevent reenabling the queue
801 * while it's empty. This could have happen if rx_action() gets
802 * suspended in qede_tx_int() after the condition before
803 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
804 *
805 * stops the queue->sees fresh tx_bd_cons->releases the queue->
806 * sends some packets consuming the whole queue again->
807 * stops the queue
808 */
809
810 __netif_tx_lock(netdev_txq, smp_processor_id());
811
812 if ((netif_tx_queue_stopped(netdev_txq)) &&
813 (edev->state == QEDE_STATE_OPEN) &&
814 (qed_chain_get_elem_left(&txq->tx_pbl)
815 >= (MAX_SKB_FRAGS + 1))) {
816 netif_tx_wake_queue(netdev_txq);
817 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
818 "Wake queue was called\n");
819 }
820
821 __netif_tx_unlock(netdev_txq);
822 }
823
824 return 0;
825}
826
16f46bf0 827bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 828{
829 u16 hw_comp_cons, sw_comp_cons;
830
831 /* Tell compiler that status block fields can change */
832 barrier();
833
834 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
835 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
836
837 return hw_comp_cons != sw_comp_cons;
838}
839
840static bool qede_has_tx_work(struct qede_fastpath *fp)
841{
842 u8 tc;
843
844 for (tc = 0; tc < fp->edev->num_tc; tc++)
845 if (qede_txq_has_work(&fp->txqs[tc]))
846 return true;
847 return false;
848}
849
f86af2df
MC		 850static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
851{
852 qed_chain_consume(&rxq->rx_bd_ring);
853 rxq->sw_rx_cons++;
854}
855
fc48b7a6
YM		 856/* This function reuses the buffer(from an offset) from
857 * consumer index to producer index in the bd ring
2950219d 858 */
fc48b7a6
YM		 859static inline void qede_reuse_page(struct qede_dev *edev,
860 struct qede_rx_queue *rxq,
861 struct sw_rx_data *curr_cons)
2950219d 862{
2950219d 863 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 864 struct sw_rx_data *curr_prod;
865 dma_addr_t new_mapping;
2950219d 866
fc48b7a6
YM		 867 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
868 *curr_prod = *curr_cons;
2950219d 869
fc48b7a6
YM		 870 new_mapping = curr_prod->mapping + curr_prod->page_offset;
871
872 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
873 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 874
2950219d 875 rxq->sw_rx_prod++;
fc48b7a6
YM		 876 curr_cons->data = NULL;
877}
878
f86af2df
MC		 879/* In case of allocation failures reuse buffers
880 * from consumer index to produce buffers for firmware
881 */
16f46bf0
SRK		 882void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
883 struct qede_dev *edev, u8 count)
f86af2df
MC		 884{
885 struct sw_rx_data *curr_cons;
886
887 for (; count > 0; count--) {
888 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
889 qede_reuse_page(edev, rxq, curr_cons);
890 qede_rx_bd_ring_consume(rxq);
891 }
892}
893
fc48b7a6
YM		 894static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
895 struct qede_rx_queue *rxq,
896 struct sw_rx_data *curr_cons)
897{
898 /* Move to the next segment in the page */
899 curr_cons->page_offset += rxq->rx_buf_seg_size;
900
901 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 902 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
903 /* Since we failed to allocate new buffer
904 * current buffer can be used again.
905 */
906 curr_cons->page_offset -= rxq->rx_buf_seg_size;
907
fc48b7a6 908 return -ENOMEM;
f86af2df 909 }
fc48b7a6
YM		 910
911 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
912 PAGE_SIZE, DMA_FROM_DEVICE);
913 } else {
914 /* Increment refcount of the page as we don't want
915 * network stack to take the ownership of the page
916 * which can be recycled multiple times by the driver.
917 */
6d061f9f 918 page_ref_inc(curr_cons->data);
fc48b7a6
YM		 919 qede_reuse_page(edev, rxq, curr_cons);
920 }
921
922 return 0;
2950219d
YM		 923}
924
925static inline void qede_update_rx_prod(struct qede_dev *edev,
926 struct qede_rx_queue *rxq)
927{
928 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
929 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
930 struct eth_rx_prod_data rx_prods = {0};
931
932 /* Update producers */
933 rx_prods.bd_prod = cpu_to_le16(bd_prod);
934 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
935
936 /* Make sure that the BD and SGE data is updated before updating the
937 * producers since FW might read the BD/SGE right after the producer
938 * is updated.
939 */
940 wmb();
941
942 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
943 (u32 *)&rx_prods);
944
945 /* mmiowb is needed to synchronize doorbell writes from more than one
946 * processor. It guarantees that the write arrives to the device before
947 * the napi lock is released and another qede_poll is called (possibly
948 * on another CPU). Without this barrier, the next doorbell can bypass
949 * this doorbell. This is applicable to IA64/Altix systems.
950 */
951 mmiowb();
952}
953
954static u32 qede_get_rxhash(struct qede_dev *edev,
955 u8 bitfields,
1a635e48 956 __le32 rss_hash, enum pkt_hash_types *rxhash_type)
2950219d
YM		 957{
958 enum rss_hash_type htype;
959
960 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
961
962 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
963 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
964 (htype == RSS_HASH_TYPE_IPV6)) ?
965 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
966 return le32_to_cpu(rss_hash);
967 }
968 *rxhash_type = PKT_HASH_TYPE_NONE;
969 return 0;
970}
971
972static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
973{
974 skb_checksum_none_assert(skb);
975
976 if (csum_flag & QEDE_CSUM_UNNECESSARY)
977 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 978
979 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
980 skb->csum_level = 1;
2950219d
YM		 981}
982
983static inline void qede_skb_receive(struct qede_dev *edev,
984 struct qede_fastpath *fp,
1a635e48 985 struct sk_buff *skb, u16 vlan_tag)
2950219d
YM		 986{
987 if (vlan_tag)
1a635e48 988 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
2950219d
YM		 989
990 napi_gro_receive(&fp->napi, skb);
991}
992
55482edc
MC		 993static void qede_set_gro_params(struct qede_dev *edev,
994 struct sk_buff *skb,
995 struct eth_fast_path_rx_tpa_start_cqe *cqe)
996{
997 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
998
999 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
1000 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
1001 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
1002 else
1003 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1004
1005 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
1006 cqe->header_len;
1007}
1008
1009static int qede_fill_frag_skb(struct qede_dev *edev,
1010 struct qede_rx_queue *rxq,
1a635e48 1011 u8 tpa_agg_index, u16 len_on_bd)
55482edc
MC		 1012{
1013 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
1014 NUM_RX_BDS_MAX];
1015 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
1016 struct sk_buff *skb = tpa_info->skb;
1017
1018 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1019 goto out;
1020
1021 /* Add one frag and update the appropriate fields in the skb */
1022 skb_fill_page_desc(skb, tpa_info->frag_id++,
1023 current_bd->data, current_bd->page_offset,
1024 len_on_bd);
1025
1026 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 1027 /* Incr page ref count to reuse on allocation failure
1028 * so that it doesn't get freed while freeing SKB.
1029 */
0139aa7b 1030 page_ref_inc(current_bd->data);
55482edc
MC		 1031 goto out;
1032 }
1033
1034 qed_chain_consume(&rxq->rx_bd_ring);
1035 rxq->sw_rx_cons++;
1036
1037 skb->data_len += len_on_bd;
1038 skb->truesize += rxq->rx_buf_seg_size;
1039 skb->len += len_on_bd;
1040
1041 return 0;
1042
1043out:
f86af2df
MC		 1044 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1045 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1046 return -ENOMEM;
1047}
1048
1049static void qede_tpa_start(struct qede_dev *edev,
1050 struct qede_rx_queue *rxq,
1051 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1052{
1053 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1054 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1055 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
1056 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
1057 dma_addr_t mapping = tpa_info->replace_buf_mapping;
1058 struct sw_rx_data *sw_rx_data_cons;
1059 struct sw_rx_data *sw_rx_data_prod;
1060 enum pkt_hash_types rxhash_type;
1061 u32 rxhash;
1062
1063 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1064 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1065
1066 /* Use pre-allocated replacement buffer - we can't release the agg.
1067 * start until its over and we don't want to risk allocation failing
1068 * here, so re-allocate when aggregation will be over.
1069 */
09ec8e7f 1070 sw_rx_data_prod->mapping = replace_buf->mapping;
55482edc
MC		 1071
1072 sw_rx_data_prod->data = replace_buf->data;
1073 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1074 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1075 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1076
1077 rxq->sw_rx_prod++;
1078
1079 /* move partial skb from cons to pool (don't unmap yet)
1080 * save mapping, incase we drop the packet later on.
1081 */
1082 tpa_info->start_buf = *sw_rx_data_cons;
1083 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1084 le32_to_cpu(rx_bd_cons->addr.lo));
1085
1086 tpa_info->start_buf_mapping = mapping;
1087 rxq->sw_rx_cons++;
1088
1089 /* set tpa state to start only if we are able to allocate skb
1090 * for this aggregation, otherwise mark as error and aggregation will
1091 * be dropped
1092 */
1093 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1094 le16_to_cpu(cqe->len_on_first_bd));
1095 if (unlikely(!tpa_info->skb)) {
f86af2df 1096 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1097 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1098 goto cons_buf;
55482edc
MC		 1099 }
1100
1101 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1102 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1103
1104 /* Start filling in the aggregation info */
1105 tpa_info->frag_id = 0;
1106 tpa_info->agg_state = QEDE_AGG_STATE_START;
1107
1108 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1109 cqe->rss_hash, &rxhash_type);
1110 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1111 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1112 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1113 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1114 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1115 else
1116 tpa_info->vlan_tag = 0;
1117
1118 /* This is needed in order to enable forwarding support */
1119 qede_set_gro_params(edev, tpa_info->skb, cqe);
1120
f86af2df 1121cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1122 if (likely(cqe->ext_bd_len_list[0]))
1123 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1124 le16_to_cpu(cqe->ext_bd_len_list[0]));
1125
1126 if (unlikely(cqe->ext_bd_len_list[1])) {
1127 DP_ERR(edev,
1128 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1129 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1130 }
1131}
1132
88f09bd5 1133#ifdef CONFIG_INET
55482edc
MC		 1134static void qede_gro_ip_csum(struct sk_buff *skb)
1135{
1136 const struct iphdr *iph = ip_hdr(skb);
1137 struct tcphdr *th;
1138
55482edc
MC		 1139 skb_set_transport_header(skb, sizeof(struct iphdr));
1140 th = tcp_hdr(skb);
1141
1142 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1143 iph->saddr, iph->daddr, 0);
1144
1145 tcp_gro_complete(skb);
1146}
1147
1148static void qede_gro_ipv6_csum(struct sk_buff *skb)
1149{
1150 struct ipv6hdr *iph = ipv6_hdr(skb);
1151 struct tcphdr *th;
1152
55482edc
MC		 1153 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1154 th = tcp_hdr(skb);
1155
1156 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1157 &iph->saddr, &iph->daddr, 0);
1158 tcp_gro_complete(skb);
1159}
88f09bd5 1160#endif
55482edc
MC		 1161
1162static void qede_gro_receive(struct qede_dev *edev,
1163 struct qede_fastpath *fp,
1164 struct sk_buff *skb,
1165 u16 vlan_tag)
1166{
ee2fa8e6
MC		 1167 /* FW can send a single MTU sized packet from gro flow
1168 * due to aggregation timeout/last segment etc. which
1169 * is not expected to be a gro packet. If a skb has zero
1170 * frags then simply push it in the stack as non gso skb.
1171 */
1172 if (unlikely(!skb->data_len)) {
1173 skb_shinfo(skb)->gso_type = 0;
1174 skb_shinfo(skb)->gso_size = 0;
1175 goto send_skb;
1176 }
1177
88f09bd5 1178#ifdef CONFIG_INET
55482edc 1179 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1180 skb_set_network_header(skb, 0);
1181
55482edc
MC		 1182 switch (skb->protocol) {
1183 case htons(ETH_P_IP):
1184 qede_gro_ip_csum(skb);
1185 break;
1186 case htons(ETH_P_IPV6):
1187 qede_gro_ipv6_csum(skb);
1188 break;
1189 default:
1190 DP_ERR(edev,
1191 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1192 ntohs(skb->protocol));
1193 }
1194 }
88f09bd5 1195#endif
ee2fa8e6
MC		 1196
1197send_skb:
55482edc
MC		 1198 skb_record_rx_queue(skb, fp->rss_id);
1199 qede_skb_receive(edev, fp, skb, vlan_tag);
1200}
1201
1202static inline void qede_tpa_cont(struct qede_dev *edev,
1203 struct qede_rx_queue *rxq,
1204 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1205{
1206 int i;
1207
1208 for (i = 0; cqe->len_list[i]; i++)
1209 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1210 le16_to_cpu(cqe->len_list[i]));
1211
1212 if (unlikely(i > 1))
1213 DP_ERR(edev,
1214 "Strange - TPA cont with more than a single len_list entry\n");
1215}
1216
1217static void qede_tpa_end(struct qede_dev *edev,
1218 struct qede_fastpath *fp,
1219 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1220{
1221 struct qede_rx_queue *rxq = fp->rxq;
1222 struct qede_agg_info *tpa_info;
1223 struct sk_buff *skb;
1224 int i;
1225
1226 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1227 skb = tpa_info->skb;
1228
1229 for (i = 0; cqe->len_list[i]; i++)
1230 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1231 le16_to_cpu(cqe->len_list[i]));
1232 if (unlikely(i > 1))
1233 DP_ERR(edev,
1234 "Strange - TPA emd with more than a single len_list entry\n");
1235
1236 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1237 goto err;
1238
1239 /* Sanity */
1240 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1241 DP_ERR(edev,
1242 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1243 cqe->num_of_bds, tpa_info->frag_id);
1244 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1245 DP_ERR(edev,
1246 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1247 le16_to_cpu(cqe->total_packet_len), skb->len);
1248
1249 memcpy(skb->data,
1250 page_address(tpa_info->start_buf.data) +
1251 tpa_info->start_cqe.placement_offset +
1252 tpa_info->start_buf.page_offset,
1253 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1254
1255 /* Recycle [mapped] start buffer for the next replacement */
1256 tpa_info->replace_buf = tpa_info->start_buf;
1257 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1258
1259 /* Finalize the SKB */
1260 skb->protocol = eth_type_trans(skb, edev->ndev);
1261 skb->ip_summed = CHECKSUM_UNNECESSARY;
1262
1263 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1264 * to skb_shinfo(skb)->gso_segs
1265 */
1266 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1267
1268 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1269
1270 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1271
1272 return;
1273err:
1274 /* The BD starting the aggregation is still mapped; Re-use it for
1275 * future aggregations [as replacement buffer]
1276 */
1277 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1278 sizeof(struct sw_rx_data));
1279 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1280 tpa_info->start_buf.data = NULL;
1281 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1282 dev_kfree_skb_any(tpa_info->skb);
1283 tpa_info->skb = NULL;
1284}
1285
14db81de
MC		 1286static bool qede_tunn_exist(u16 flag)
1287{
1288 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1289 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1290}
1291
1292static u8 qede_check_tunn_csum(u16 flag)
1293{
1294 u16 csum_flag = 0;
1295 u8 tcsum = 0;
1296
1297 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1298 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1299 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1300 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1301
1302 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1303 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1304 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1305 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1306 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1307 }
1308
1309 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1310 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1311 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1312 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1313
1314 if (csum_flag & flag)
1315 return QEDE_CSUM_ERROR;
1316
1317 return QEDE_CSUM_UNNECESSARY | tcsum;
1318}
1319
1320static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1321{
1322 u16 csum_flag = 0;
1323 u8 csum = 0;
1324
14db81de
MC		 1325 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1326 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1327 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1328 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1329 csum = QEDE_CSUM_UNNECESSARY;
1330 }
1331
1332 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1333 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1334
1335 if (csum_flag & flag)
1336 return QEDE_CSUM_ERROR;
1337
1338 return csum;
1339}
1340
14db81de
MC		 1341static u8 qede_check_csum(u16 flag)
1342{
1343 if (!qede_tunn_exist(flag))
1344 return qede_check_notunn_csum(flag);
1345 else
1346 return qede_check_tunn_csum(flag);
1347}
1348
c72a6125
MC		 1349static bool qede_pkt_is_ip_fragmented(struct eth_fast_path_rx_reg_cqe *cqe,
1350 u16 flag)
1351{
1352 u8 tun_pars_flg = cqe->tunnel_pars_flags.flags;
1353
1354 if ((tun_pars_flg & (ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK <<
1355 ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT)) ||
1356 (flag & (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1357 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT)))
1358 return true;
1359
1360 return false;
1361}
1362
2950219d
YM		 1363static int qede_rx_int(struct qede_fastpath *fp, int budget)
1364{
1365 struct qede_dev *edev = fp->edev;
1366 struct qede_rx_queue *rxq = fp->rxq;
1367
1368 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1369 int rx_pkt = 0;
1370 u8 csum_flag;
1371
1372 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1373 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1374
1375 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1376 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1377 * read before it is written by FW, then FW writes CQE and SB, and then
1378 * the CPU reads the hw_comp_cons, it will use an old CQE.
1379 */
1380 rmb();
1381
1382 /* Loop to complete all indicated BDs */
1383 while (sw_comp_cons != hw_comp_cons) {
1384 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1385 enum pkt_hash_types rxhash_type;
1386 enum eth_rx_cqe_type cqe_type;
1387 struct sw_rx_data *sw_rx_data;
1388 union eth_rx_cqe *cqe;
1389 struct sk_buff *skb;
fc48b7a6
YM		 1390 struct page *data;
1391 __le16 flags;
2950219d
YM		 1392 u16 len, pad;
1393 u32 rx_hash;
2950219d
YM		 1394
1395 /* Get the CQE from the completion ring */
1396 cqe = (union eth_rx_cqe *)
1397 qed_chain_consume(&rxq->rx_comp_ring);
1398 cqe_type = cqe->fast_path_regular.type;
1399
1400 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1401 edev->ops->eth_cqe_completion(
1402 edev->cdev, fp->rss_id,
1403 (struct eth_slow_path_rx_cqe *)cqe);
1404 goto next_cqe;
1405 }
1406
55482edc
MC		 1407 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1408 switch (cqe_type) {
1409 case ETH_RX_CQE_TYPE_TPA_START:
1410 qede_tpa_start(edev, rxq,
1411 &cqe->fast_path_tpa_start);
1412 goto next_cqe;
1413 case ETH_RX_CQE_TYPE_TPA_CONT:
1414 qede_tpa_cont(edev, rxq,
1415 &cqe->fast_path_tpa_cont);
1416 goto next_cqe;
1417 case ETH_RX_CQE_TYPE_TPA_END:
1418 qede_tpa_end(edev, fp,
1419 &cqe->fast_path_tpa_end);
1420 goto next_rx_only;
1421 default:
1422 break;
1423 }
1424 }
1425
2950219d
YM		 1426 /* Get the data from the SW ring */
1427 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1428 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1429 data = sw_rx_data->data;
1430
1431 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1432 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1433 pad = fp_cqe->placement_offset;
fc48b7a6 1434 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1435
fc48b7a6
YM		 1436 /* If this is an error packet then drop it */
1437 parse_flag = le16_to_cpu(flags);
2950219d 1438
fc48b7a6
YM		 1439 csum_flag = qede_check_csum(parse_flag);
1440 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
c72a6125
MC		 1441 if (qede_pkt_is_ip_fragmented(&cqe->fast_path_regular,
1442 parse_flag)) {
1443 rxq->rx_ip_frags++;
1444 goto alloc_skb;
1445 }
1446
fc48b7a6
YM		 1447 DP_NOTICE(edev,
1448 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1449 sw_comp_cons, parse_flag);
1450 rxq->rx_hw_errors++;
f86af2df
MC		 1451 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1452 goto next_cqe;
fc48b7a6 1453 }
2950219d 1454
c72a6125 1455alloc_skb:
fc48b7a6
YM		 1456 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1457 if (unlikely(!skb)) {
2950219d 1458 DP_NOTICE(edev,
525ef5c0 1459 "skb allocation failed, dropping incoming packet\n");
f86af2df 1460 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1461 rxq->rx_alloc_errors++;
f86af2df 1462 goto next_cqe;
fc48b7a6
YM		 1463 }
1464
1465 /* Copy data into SKB */
3d789994 1466 if (len + pad <= edev->rx_copybreak) {
fc48b7a6
YM		 1467 memcpy(skb_put(skb, len),
1468 page_address(data) + pad +
1469 sw_rx_data->page_offset, len);
1470 qede_reuse_page(edev, rxq, sw_rx_data);
1471 } else {
1472 struct skb_frag_struct *frag;
1473 unsigned int pull_len;
1474 unsigned char *va;
1475
1476 frag = &skb_shinfo(skb)->frags[0];
1477
1478 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1479 pad + sw_rx_data->page_offset,
1480 len, rxq->rx_buf_seg_size);
1481
1482 va = skb_frag_address(frag);
1483 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1484
1485 /* Align the pull_len to optimize memcpy */
1486 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1487
1488 skb_frag_size_sub(frag, pull_len);
1489 frag->page_offset += pull_len;
1490 skb->data_len -= pull_len;
1491 skb->tail += pull_len;
1492
1493 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1494 sw_rx_data))) {
1495 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1496 /* Incr page ref count to reuse on allocation
1497 * failure so that it doesn't get freed while
1498 * freeing SKB.
1499 */
1500
0139aa7b 1501 page_ref_inc(sw_rx_data->data);
fc48b7a6 1502 rxq->rx_alloc_errors++;
f86af2df
MC		 1503 qede_recycle_rx_bd_ring(rxq, edev,
1504 fp_cqe->bd_num);
1505 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1506 goto next_cqe;
1507 }
2950219d
YM		 1508 }
1509
f86af2df
MC		 1510 qede_rx_bd_ring_consume(rxq);
1511
fc48b7a6
YM		 1512 if (fp_cqe->bd_num != 1) {
1513 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1514 u8 num_frags;
1515
1516 pkt_len -= len;
1517
1518 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1519 num_frags--) {
1520 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1521 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1522 if (unlikely(!cur_size)) {
1523 DP_ERR(edev,
1524 "Still got %d BDs for mapping jumbo, but length became 0\n",
1525 num_frags);
1526 qede_recycle_rx_bd_ring(rxq, edev,
1527 num_frags);
1528 dev_kfree_skb_any(skb);
1529 goto next_cqe;
1530 }
fc48b7a6 1531
f86af2df
MC		 1532 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1533 qede_recycle_rx_bd_ring(rxq, edev,
1534 num_frags);
1535 dev_kfree_skb_any(skb);
fc48b7a6 1536 goto next_cqe;
f86af2df 1537 }
fc48b7a6 1538
fc48b7a6
YM		 1539 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1540 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1541 qede_rx_bd_ring_consume(rxq);
1542
fc48b7a6
YM		 1543 dma_unmap_page(&edev->pdev->dev,
1544 sw_rx_data->mapping,
1545 PAGE_SIZE, DMA_FROM_DEVICE);
1546
1547 skb_fill_page_desc(skb,
1548 skb_shinfo(skb)->nr_frags++,
1549 sw_rx_data->data, 0,
1550 cur_size);
1551
1552 skb->truesize += PAGE_SIZE;
1553 skb->data_len += cur_size;
1554 skb->len += cur_size;
1555 pkt_len -= cur_size;
1556 }
2950219d 1557
f86af2df 1558 if (unlikely(pkt_len))
fc48b7a6
YM		 1559 DP_ERR(edev,
1560 "Mapped all BDs of jumbo, but still have %d bytes\n",
1561 pkt_len);
1562 }
2950219d
YM		 1563
1564 skb->protocol = eth_type_trans(skb, edev->ndev);
1565
1566 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1a635e48 1567 fp_cqe->rss_hash, &rxhash_type);
2950219d
YM		 1568
1569 skb_set_hash(skb, rx_hash, rxhash_type);
1570
1571 qede_set_skb_csum(skb, csum_flag);
1572
1573 skb_record_rx_queue(skb, fp->rss_id);
1574
1575 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1576next_rx_only:
2950219d
YM		 1577 rx_pkt++;
1578
1579next_cqe: /* don't consume bd rx buffer */
1580 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1581 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1582 /* CR TPA - revisit how to handle budget in TPA perhaps
1583 * increase on "end"
1584 */
1585 if (rx_pkt == budget)
1586 break;
1587 } /* repeat while sw_comp_cons != hw_comp_cons... */
1588
1589 /* Update producers */
1590 qede_update_rx_prod(edev, rxq);
1591
68db9ec2
SRK		 1592 rxq->rcv_pkts += rx_pkt;
1593
2950219d
YM		 1594 return rx_pkt;
1595}
1596
1597static int qede_poll(struct napi_struct *napi, int budget)
1598{
2950219d 1599 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
c774169d 1600 napi);
2950219d 1601 struct qede_dev *edev = fp->edev;
c774169d
MC		 1602 int rx_work_done = 0;
1603 u8 tc;
2950219d 1604
c774169d
MC		 1605 for (tc = 0; tc < edev->num_tc; tc++)
1606 if (qede_txq_has_work(&fp->txqs[tc]))
1607 qede_tx_int(edev, &fp->txqs[tc]);
1608
1609 rx_work_done = qede_has_rx_work(fp->rxq) ?
1610 qede_rx_int(fp, budget) : 0;
1611 if (rx_work_done < budget) {
1612 qed_sb_update_sb_idx(fp->sb_info);
1613 /* *_has_*_work() reads the status block,
1614 * thus we need to ensure that status block indices
1615 * have been actually read (qed_sb_update_sb_idx)
1616 * prior to this check (*_has_*_work) so that
1617 * we won't write the "newer" value of the status block
1618 * to HW (if there was a DMA right after
1619 * qede_has_rx_work and if there is no rmb, the memory
1620 * reading (qed_sb_update_sb_idx) may be postponed
1621 * to right before *_ack_sb). In this case there
1622 * will never be another interrupt until there is
1623 * another update of the status block, while there
1624 * is still unhandled work.
1625 */
1626 rmb();
2950219d
YM		 1627
1628 /* Fall out from the NAPI loop if needed */
c774169d
MC		 1629 if (!(qede_has_rx_work(fp->rxq) ||
1630 qede_has_tx_work(fp))) {
1631 napi_complete(napi);
1632
1633 /* Update and reenable interrupts */
1634 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1635 1 /*update*/);
1636 } else {
1637 rx_work_done = budget;
2950219d
YM		 1638 }
1639 }
1640
c774169d 1641 return rx_work_done;
2950219d
YM		 1642}
1643
1644static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1645{
1646 struct qede_fastpath *fp = fp_cookie;
1647
1648 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1649
1650 napi_schedule_irqoff(&fp->napi);
1651 return IRQ_HANDLED;
1652}
1653
1654/* -------------------------------------------------------------------------
1655 * END OF FAST-PATH
1656 * -------------------------------------------------------------------------
1657 */
1658
1659static int qede_open(struct net_device *ndev);
1660static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1661static int qede_set_mac_addr(struct net_device *ndev, void *p);
1662static void qede_set_rx_mode(struct net_device *ndev);
1663static void qede_config_rx_mode(struct net_device *ndev);
1664
1665static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1666 enum qed_filter_xcast_params_type opcode,
1667 unsigned char mac[ETH_ALEN])
1668{
1669 struct qed_filter_params filter_cmd;
1670
1671 memset(&filter_cmd, 0, sizeof(filter_cmd));
1672 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1673 filter_cmd.filter.ucast.type = opcode;
1674 filter_cmd.filter.ucast.mac_valid = 1;
1675 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1676
1677 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1678}
1679
7c1bfcad
SRK		 1680static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1681 enum qed_filter_xcast_params_type opcode,
1682 u16 vid)
1683{
1684 struct qed_filter_params filter_cmd;
1685
1686 memset(&filter_cmd, 0, sizeof(filter_cmd));
1687 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1688 filter_cmd.filter.ucast.type = opcode;
1689 filter_cmd.filter.ucast.vlan_valid = 1;
1690 filter_cmd.filter.ucast.vlan = vid;
1691
1692 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1693}
1694
133fac0e
SK		 1695void qede_fill_by_demand_stats(struct qede_dev *edev)
1696{
1697 struct qed_eth_stats stats;
1698
1699 edev->ops->get_vport_stats(edev->cdev, &stats);
1700 edev->stats.no_buff_discards = stats.no_buff_discards;
1a5a366f
SRK		 1701 edev->stats.packet_too_big_discard = stats.packet_too_big_discard;
1702 edev->stats.ttl0_discard = stats.ttl0_discard;
133fac0e
SK		 1703 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1704 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1705 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1706 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1707 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1708 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1709 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1710 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1711
1712 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1713 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1714 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1715 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1716 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1717 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1718 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1719 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1720 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1721 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1722 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1723 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1724
1725 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1726 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1727 edev->stats.rx_128_to_255_byte_packets =
1728 stats.rx_128_to_255_byte_packets;
1729 edev->stats.rx_256_to_511_byte_packets =
1730 stats.rx_256_to_511_byte_packets;
1731 edev->stats.rx_512_to_1023_byte_packets =
1732 stats.rx_512_to_1023_byte_packets;
1733 edev->stats.rx_1024_to_1518_byte_packets =
1734 stats.rx_1024_to_1518_byte_packets;
1735 edev->stats.rx_1519_to_1522_byte_packets =
1736 stats.rx_1519_to_1522_byte_packets;
1737 edev->stats.rx_1519_to_2047_byte_packets =
1738 stats.rx_1519_to_2047_byte_packets;
1739 edev->stats.rx_2048_to_4095_byte_packets =
1740 stats.rx_2048_to_4095_byte_packets;
1741 edev->stats.rx_4096_to_9216_byte_packets =
1742 stats.rx_4096_to_9216_byte_packets;
1743 edev->stats.rx_9217_to_16383_byte_packets =
1744 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1745 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1746 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1747 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1748 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1749 edev->stats.rx_align_errors = stats.rx_align_errors;
1750 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1751 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1752 edev->stats.rx_jabbers = stats.rx_jabbers;
1753 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1754 edev->stats.rx_fragments = stats.rx_fragments;
1755 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1756 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1757 edev->stats.tx_128_to_255_byte_packets =
1758 stats.tx_128_to_255_byte_packets;
1759 edev->stats.tx_256_to_511_byte_packets =
1760 stats.tx_256_to_511_byte_packets;
1761 edev->stats.tx_512_to_1023_byte_packets =
1762 stats.tx_512_to_1023_byte_packets;
1763 edev->stats.tx_1024_to_1518_byte_packets =
1764 stats.tx_1024_to_1518_byte_packets;
1765 edev->stats.tx_1519_to_2047_byte_packets =
1766 stats.tx_1519_to_2047_byte_packets;
1767 edev->stats.tx_2048_to_4095_byte_packets =
1768 stats.tx_2048_to_4095_byte_packets;
1769 edev->stats.tx_4096_to_9216_byte_packets =
1770 stats.tx_4096_to_9216_byte_packets;
1771 edev->stats.tx_9217_to_16383_byte_packets =
1772 stats.tx_9217_to_16383_byte_packets;
1773 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1774 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1775 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1776 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1777 edev->stats.brb_truncates = stats.brb_truncates;
1778 edev->stats.brb_discards = stats.brb_discards;
1779 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1780}
1781
1a635e48
YM		 1782static
1783struct rtnl_link_stats64 *qede_get_stats64(struct net_device *dev,
1784 struct rtnl_link_stats64 *stats)
133fac0e
SK		 1785{
1786 struct qede_dev *edev = netdev_priv(dev);
1787
1788 qede_fill_by_demand_stats(edev);
1789
1790 stats->rx_packets = edev->stats.rx_ucast_pkts +
1791 edev->stats.rx_mcast_pkts +
1792 edev->stats.rx_bcast_pkts;
1793 stats->tx_packets = edev->stats.tx_ucast_pkts +
1794 edev->stats.tx_mcast_pkts +
1795 edev->stats.tx_bcast_pkts;
1796
1797 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1798 edev->stats.rx_mcast_bytes +
1799 edev->stats.rx_bcast_bytes;
1800
1801 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1802 edev->stats.tx_mcast_bytes +
1803 edev->stats.tx_bcast_bytes;
1804
1805 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1806 stats->multicast = edev->stats.rx_mcast_pkts +
1807 edev->stats.rx_bcast_pkts;
1808
1809 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1810
1811 stats->collisions = edev->stats.tx_total_collisions;
1812 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1813 stats->rx_frame_errors = edev->stats.rx_align_errors;
1814
1815 return stats;
1816}
1817
733def6a 1818#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 1819static int qede_get_vf_config(struct net_device *dev, int vfidx,
1820 struct ifla_vf_info *ivi)
1821{
1822 struct qede_dev *edev = netdev_priv(dev);
1823
1824 if (!edev->ops)
1825 return -EINVAL;
1826
1827 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
1828}
1829
733def6a
YM		 1830static int qede_set_vf_rate(struct net_device *dev, int vfidx,
1831 int min_tx_rate, int max_tx_rate)
1832{
1833 struct qede_dev *edev = netdev_priv(dev);
1834
be7b6d64 1835 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 1836 max_tx_rate);
1837}
1838
6ddc7608
YM		 1839static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
1840{
1841 struct qede_dev *edev = netdev_priv(dev);
1842
1843 if (!edev->ops)
1844 return -EINVAL;
1845
1846 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
1847}
1848
733def6a
YM		 1849static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
1850 int link_state)
1851{
1852 struct qede_dev *edev = netdev_priv(dev);
1853
1854 if (!edev->ops)
1855 return -EINVAL;
1856
1857 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
1858}
1859#endif
1860
7c1bfcad
SRK		 1861static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1862{
1863 struct qed_update_vport_params params;
1864 int rc;
1865
1866 /* Proceed only if action actually needs to be performed */
1867 if (edev->accept_any_vlan == action)
1868 return;
1869
1870 memset(&params, 0, sizeof(params));
1871
1872 params.vport_id = 0;
1873 params.accept_any_vlan = action;
1874 params.update_accept_any_vlan_flg = 1;
1875
1876 rc = edev->ops->vport_update(edev->cdev, &params);
1877 if (rc) {
1878 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1879 action ? "enable" : "disable");
1880 } else {
1881 DP_INFO(edev, "%s accept-any-vlan\n",
1882 action ? "enabled" : "disabled");
1883 edev->accept_any_vlan = action;
1884 }
1885}
1886
1887static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1888{
1889 struct qede_dev *edev = netdev_priv(dev);
1890 struct qede_vlan *vlan, *tmp;
1891 int rc;
1892
1893 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1894
1895 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1896 if (!vlan) {
1897 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1898 return -ENOMEM;
1899 }
1900 INIT_LIST_HEAD(&vlan->list);
1901 vlan->vid = vid;
1902 vlan->configured = false;
1903
1904 /* Verify vlan isn't already configured */
1905 list_for_each_entry(tmp, &edev->vlan_list, list) {
1906 if (tmp->vid == vlan->vid) {
1907 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1908 "vlan already configured\n");
1909 kfree(vlan);
1910 return -EEXIST;
1911 }
1912 }
1913
1914 /* If interface is down, cache this VLAN ID and return */
1915 if (edev->state != QEDE_STATE_OPEN) {
1916 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1917 "Interface is down, VLAN %d will be configured when interface is up\n",
1918 vid);
1919 if (vid != 0)
1920 edev->non_configured_vlans++;
1921 list_add(&vlan->list, &edev->vlan_list);
1922
1923 return 0;
1924 }
1925
1926 /* Check for the filter limit.
1927 * Note - vlan0 has a reserved filter and can be added without
1928 * worrying about quota
1929 */
1930 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1931 (vlan->vid == 0)) {
1932 rc = qede_set_ucast_rx_vlan(edev,
1933 QED_FILTER_XCAST_TYPE_ADD,
1934 vlan->vid);
1935 if (rc) {
1936 DP_ERR(edev, "Failed to configure VLAN %d\n",
1937 vlan->vid);
1938 kfree(vlan);
1939 return -EINVAL;
1940 }
1941 vlan->configured = true;
1942
1943 /* vlan0 filter isn't consuming out of our quota */
1944 if (vlan->vid != 0)
1945 edev->configured_vlans++;
1946 } else {
1947 /* Out of quota; Activate accept-any-VLAN mode */
1948 if (!edev->non_configured_vlans)
1949 qede_config_accept_any_vlan(edev, true);
1950
1951 edev->non_configured_vlans++;
1952 }
1953
1954 list_add(&vlan->list, &edev->vlan_list);
1955
1956 return 0;
1957}
1958
1959static void qede_del_vlan_from_list(struct qede_dev *edev,
1960 struct qede_vlan *vlan)
1961{
1962 /* vlan0 filter isn't consuming out of our quota */
1963 if (vlan->vid != 0) {
1964 if (vlan->configured)
1965 edev->configured_vlans--;
1966 else
1967 edev->non_configured_vlans--;
1968 }
1969
1970 list_del(&vlan->list);
1971 kfree(vlan);
1972}
1973
1974static int qede_configure_vlan_filters(struct qede_dev *edev)
1975{
1976 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1977 struct qed_dev_eth_info *dev_info;
1978 struct qede_vlan *vlan = NULL;
1979
1980 if (list_empty(&edev->vlan_list))
1981 return 0;
1982
1983 dev_info = &edev->dev_info;
1984
1985 /* Configure non-configured vlans */
1986 list_for_each_entry(vlan, &edev->vlan_list, list) {
1987 if (vlan->configured)
1988 continue;
1989
1990 /* We have used all our credits, now enable accept_any_vlan */
1991 if ((vlan->vid != 0) &&
1992 (edev->configured_vlans == dev_info->num_vlan_filters)) {
1993 accept_any_vlan = 1;
1994 continue;
1995 }
1996
1997 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
1998
1999 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
2000 vlan->vid);
2001 if (rc) {
2002 DP_ERR(edev, "Failed to configure VLAN %u\n",
2003 vlan->vid);
2004 real_rc = rc;
2005 continue;
2006 }
2007
2008 vlan->configured = true;
2009 /* vlan0 filter doesn't consume our VLAN filter's quota */
2010 if (vlan->vid != 0) {
2011 edev->non_configured_vlans--;
2012 edev->configured_vlans++;
2013 }
2014 }
2015
2016 /* enable accept_any_vlan mode if we have more VLANs than credits,
2017 * or remove accept_any_vlan mode if we've actually removed
2018 * a non-configured vlan, and all remaining vlans are truly configured.
2019 */
2020
2021 if (accept_any_vlan)
2022 qede_config_accept_any_vlan(edev, true);
2023 else if (!edev->non_configured_vlans)
2024 qede_config_accept_any_vlan(edev, false);
2025
2026 return real_rc;
2027}
2028
2029static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
2030{
2031 struct qede_dev *edev = netdev_priv(dev);
2032 struct qede_vlan *vlan = NULL;
2033 int rc;
2034
2035 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
2036
2037 /* Find whether entry exists */
2038 list_for_each_entry(vlan, &edev->vlan_list, list)
2039 if (vlan->vid == vid)
2040 break;
2041
2042 if (!vlan || (vlan->vid != vid)) {
2043 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
2044 "Vlan isn't configured\n");
2045 return 0;
2046 }
2047
2048 if (edev->state != QEDE_STATE_OPEN) {
2049 /* As interface is already down, we don't have a VPORT
2050 * instance to remove vlan filter. So just update vlan list
2051 */
2052 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2053 "Interface is down, removing VLAN from list only\n");
2054 qede_del_vlan_from_list(edev, vlan);
2055 return 0;
2056 }
2057
2058 /* Remove vlan */
c524e2f5
YM		 2059 if (vlan->configured) {
2060 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL,
2061 vid);
2062 if (rc) {
2063 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
2064 return -EINVAL;
2065 }
7c1bfcad
SRK		 2066 }
2067
2068 qede_del_vlan_from_list(edev, vlan);
2069
2070 /* We have removed a VLAN - try to see if we can
2071 * configure non-configured VLAN from the list.
2072 */
2073 rc = qede_configure_vlan_filters(edev);
2074
2075 return rc;
2076}
2077
2078static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
2079{
2080 struct qede_vlan *vlan = NULL;
2081
2082 if (list_empty(&edev->vlan_list))
2083 return;
2084
2085 list_for_each_entry(vlan, &edev->vlan_list, list) {
2086 if (!vlan->configured)
2087 continue;
2088
2089 vlan->configured = false;
2090
2091 /* vlan0 filter isn't consuming out of our quota */
2092 if (vlan->vid != 0) {
2093 edev->non_configured_vlans++;
2094 edev->configured_vlans--;
2095 }
2096
2097 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1a635e48 2098 "marked vlan %d as non-configured\n", vlan->vid);
7c1bfcad
SRK		 2099 }
2100
2101 edev->accept_any_vlan = false;
2102}
2103
ce2b885c
YM		 2104int qede_set_features(struct net_device *dev, netdev_features_t features)
2105{
2106 struct qede_dev *edev = netdev_priv(dev);
2107 netdev_features_t changes = features ^ dev->features;
2108 bool need_reload = false;
2109
2110 /* No action needed if hardware GRO is disabled during driver load */
2111 if (changes & NETIF_F_GRO) {
2112 if (dev->features & NETIF_F_GRO)
2113 need_reload = !edev->gro_disable;
2114 else
2115 need_reload = edev->gro_disable;
2116 }
2117
2118 if (need_reload && netif_running(edev->ndev)) {
2119 dev->features = features;
2120 qede_reload(edev, NULL, NULL);
2121 return 1;
2122 }
2123
2124 return 0;
2125}
2126
f9f082a9
AD		 2127static void qede_udp_tunnel_add(struct net_device *dev,
2128 struct udp_tunnel_info *ti)
b18e170c
MC		 2129{
2130 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2131 u16 t_port = ntohs(ti->port);
b18e170c 2132
f9f082a9
AD		 2133 switch (ti->type) {
2134 case UDP_TUNNEL_TYPE_VXLAN:
2135 if (edev->vxlan_dst_port)
2136 return;
b18e170c 2137
f9f082a9 2138 edev->vxlan_dst_port = t_port;
b18e170c 2139
525ef5c0 2140 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d\n",
f9f082a9 2141 t_port);
b18e170c 2142
f9f082a9
AD		 2143 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2144 break;
2145 case UDP_TUNNEL_TYPE_GENEVE:
2146 if (edev->geneve_dst_port)
2147 return;
b18e170c 2148
f9f082a9 2149 edev->geneve_dst_port = t_port;
b18e170c 2150
525ef5c0 2151 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d\n",
f9f082a9
AD		 2152 t_port);
2153 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2154 break;
2155 default:
b18e170c 2156 return;
f9f082a9 2157 }
b18e170c 2158
b18e170c
MC		 2159 schedule_delayed_work(&edev->sp_task, 0);
2160}
b18e170c 2161
f9f082a9
AD		 2162static void qede_udp_tunnel_del(struct net_device *dev,
2163 struct udp_tunnel_info *ti)
9a109dd0
MC		 2164{
2165 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2166 u16 t_port = ntohs(ti->port);
9a109dd0 2167
f9f082a9
AD		 2168 switch (ti->type) {
2169 case UDP_TUNNEL_TYPE_VXLAN:
2170 if (t_port != edev->vxlan_dst_port)
2171 return;
9a109dd0 2172
f9f082a9 2173 edev->vxlan_dst_port = 0;
9a109dd0 2174
525ef5c0 2175 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d\n",
f9f082a9 2176 t_port);
9a109dd0 2177
f9f082a9
AD		 2178 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2179 break;
2180 case UDP_TUNNEL_TYPE_GENEVE:
2181 if (t_port != edev->geneve_dst_port)
2182 return;
9a109dd0 2183
f9f082a9 2184 edev->geneve_dst_port = 0;
9a109dd0 2185
525ef5c0 2186 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d\n",
f9f082a9
AD		 2187 t_port);
2188 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2189 break;
2190 default:
2191 return;
2192 }
9a109dd0 2193
9a109dd0
MC		 2194 schedule_delayed_work(&edev->sp_task, 0);
2195}
9a109dd0 2196
2950219d
YM		 2197static const struct net_device_ops qede_netdev_ops = {
2198 .ndo_open = qede_open,
2199 .ndo_stop = qede_close,
2200 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2201 .ndo_set_rx_mode = qede_set_rx_mode,
2202 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2203 .ndo_validate_addr = eth_validate_addr,
133fac0e 2204 .ndo_change_mtu = qede_change_mtu,
08feecd7 2205#ifdef CONFIG_QED_SRIOV
eff16960 2206 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7
YM		 2207 .ndo_set_vf_vlan = qede_set_vf_vlan,
2208#endif
7c1bfcad
SRK		 2209 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2210 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
ce2b885c 2211 .ndo_set_features = qede_set_features,
133fac0e 2212 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 2213#ifdef CONFIG_QED_SRIOV
2214 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 2215 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 2216 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 2217 .ndo_set_vf_rate = qede_set_vf_rate,
2218#endif
f9f082a9
AD		 2219 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
2220 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
2950219d
YM		 2221};
2222
e712d52b
YM		 2223/* -------------------------------------------------------------------------
2224 * START OF PROBE / REMOVE
2225 * -------------------------------------------------------------------------
2226 */
2227
2228static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2229 struct pci_dev *pdev,
2230 struct qed_dev_eth_info *info,
1a635e48 2231 u32 dp_module, u8 dp_level)
e712d52b
YM		 2232{
2233 struct net_device *ndev;
2234 struct qede_dev *edev;
2235
2236 ndev = alloc_etherdev_mqs(sizeof(*edev),
1a635e48 2237 info->num_queues, info->num_queues);
e712d52b
YM		 2238 if (!ndev) {
2239 pr_err("etherdev allocation failed\n");
2240 return NULL;
2241 }
2242
2243 edev = netdev_priv(ndev);
2244 edev->ndev = ndev;
2245 edev->cdev = cdev;
2246 edev->pdev = pdev;
2247 edev->dp_module = dp_module;
2248 edev->dp_level = dp_level;
2249 edev->ops = qed_ops;
2950219d
YM		 2250 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2251 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2252
525ef5c0
YM		 2253 DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
2254 info->num_queues, info->num_queues);
2255
e712d52b
YM		 2256 SET_NETDEV_DEV(ndev, &pdev->dev);
2257
133fac0e 2258 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2259 memcpy(&edev->dev_info, info, sizeof(*info));
2260
2261 edev->num_tc = edev->dev_info.num_tc;
2262
7c1bfcad
SRK		 2263 INIT_LIST_HEAD(&edev->vlan_list);
2264
e712d52b
YM		 2265 return edev;
2266}
2267
2268static void qede_init_ndev(struct qede_dev *edev)
2269{
2270 struct net_device *ndev = edev->ndev;
2271 struct pci_dev *pdev = edev->pdev;
2272 u32 hw_features;
2273
2274 pci_set_drvdata(pdev, ndev);
2275
2276 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2277 ndev->base_addr = ndev->mem_start;
2278 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2279 ndev->irq = edev->dev_info.common.pci_irq;
2280
2281 ndev->watchdog_timeo = TX_TIMEOUT;
2282
2950219d
YM		 2283 ndev->netdev_ops = &qede_netdev_ops;
2284
133fac0e
SK		 2285 qede_set_ethtool_ops(ndev);
2286
e712d52b
YM		 2287 /* user-changeble features */
2288 hw_features = NETIF_F_GRO | NETIF_F_SG |
2289 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2290 NETIF_F_TSO | NETIF_F_TSO6;
2291
14db81de
MC		 2292 /* Encap features*/
2293 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2294 NETIF_F_TSO_ECN;
2295 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2296 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2297 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2298 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2299
e712d52b
YM		 2300 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2301 NETIF_F_HIGHDMA;
2302 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2303 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2304 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2305
2306 ndev->hw_features = hw_features;
2307
2308 /* Set network device HW mac */
2309 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2310}
2311
2312/* This function converts from 32b param to two params of level and module
2313 * Input 32b decoding:
2314 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2315 * 'happy' flow, e.g. memory allocation failed.
2316 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2317 * and provide important parameters.
2318 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2319 * module. VERBOSE prints are for tracking the specific flow in low level.
2320 *
2321 * Notice that the level should be that of the lowest required logs.
2322 */
133fac0e 2323void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2324{
2325 *p_dp_level = QED_LEVEL_NOTICE;
2326 *p_dp_module = 0;
2327
2328 if (debug & QED_LOG_VERBOSE_MASK) {
2329 *p_dp_level = QED_LEVEL_VERBOSE;
2330 *p_dp_module = (debug & 0x3FFFFFFF);
2331 } else if (debug & QED_LOG_INFO_MASK) {
2332 *p_dp_level = QED_LEVEL_INFO;
2333 } else if (debug & QED_LOG_NOTICE_MASK) {
2334 *p_dp_level = QED_LEVEL_NOTICE;
2335 }
2336}
2337
2950219d
YM		 2338static void qede_free_fp_array(struct qede_dev *edev)
2339{
2340 if (edev->fp_array) {
2341 struct qede_fastpath *fp;
2342 int i;
2343
2344 for_each_rss(i) {
2345 fp = &edev->fp_array[i];
2346
2347 kfree(fp->sb_info);
2348 kfree(fp->rxq);
2349 kfree(fp->txqs);
2350 }
2351 kfree(edev->fp_array);
2352 }
2353 edev->num_rss = 0;
2354}
2355
2356static int qede_alloc_fp_array(struct qede_dev *edev)
2357{
2358 struct qede_fastpath *fp;
2359 int i;
2360
2361 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2362 sizeof(*edev->fp_array), GFP_KERNEL);
2363 if (!edev->fp_array) {
2364 DP_NOTICE(edev, "fp array allocation failed\n");
2365 goto err;
2366 }
2367
2368 for_each_rss(i) {
2369 fp = &edev->fp_array[i];
2370
2371 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2372 if (!fp->sb_info) {
2373 DP_NOTICE(edev, "sb info struct allocation failed\n");
2374 goto err;
2375 }
2376
2377 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2378 if (!fp->rxq) {
2379 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2380 goto err;
2381 }
2382
2383 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2384 if (!fp->txqs) {
2385 DP_NOTICE(edev, "TXQ array allocation failed\n");
2386 goto err;
2387 }
2388 }
2389
2390 return 0;
2391err:
2392 qede_free_fp_array(edev);
2393 return -ENOMEM;
2394}
2395
0d8e0aa0
SK		 2396static void qede_sp_task(struct work_struct *work)
2397{
2398 struct qede_dev *edev = container_of(work, struct qede_dev,
2399 sp_task.work);
b18e170c
MC		 2400 struct qed_dev *cdev = edev->cdev;
2401
0d8e0aa0
SK		 2402 mutex_lock(&edev->qede_lock);
2403
2404 if (edev->state == QEDE_STATE_OPEN) {
2405 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2406 qede_config_rx_mode(edev->ndev);
2407 }
2408
b18e170c
MC		 2409 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2410 struct qed_tunn_params tunn_params;
2411
2412 memset(&tunn_params, 0, sizeof(tunn_params));
2413 tunn_params.update_vxlan_port = 1;
2414 tunn_params.vxlan_port = edev->vxlan_dst_port;
2415 qed_ops->tunn_config(cdev, &tunn_params);
2416 }
2417
9a109dd0
MC		 2418 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2419 struct qed_tunn_params tunn_params;
2420
2421 memset(&tunn_params, 0, sizeof(tunn_params));
2422 tunn_params.update_geneve_port = 1;
2423 tunn_params.geneve_port = edev->geneve_dst_port;
2424 qed_ops->tunn_config(cdev, &tunn_params);
2425 }
2426
0d8e0aa0
SK		 2427 mutex_unlock(&edev->qede_lock);
2428}
2429
e712d52b
YM		 2430static void qede_update_pf_params(struct qed_dev *cdev)
2431{
2432 struct qed_pf_params pf_params;
2433
8e0ddc04 2434 /* 64 rx + 64 tx */
e712d52b 2435 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2436 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2437 qed_ops->common->update_pf_params(cdev, &pf_params);
2438}
2439
2440enum qede_probe_mode {
2441 QEDE_PROBE_NORMAL,
2442};
2443
2444static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2445 bool is_vf, enum qede_probe_mode mode)
e712d52b 2446{
1408cc1f 2447 struct qed_probe_params probe_params;
1a635e48 2448 struct qed_slowpath_params sp_params;
e712d52b
YM		 2449 struct qed_dev_eth_info dev_info;
2450 struct qede_dev *edev;
2451 struct qed_dev *cdev;
2452 int rc;
2453
2454 if (unlikely(dp_level & QED_LEVEL_INFO))
2455 pr_notice("Starting qede probe\n");
2456
1408cc1f
YM		 2457 memset(&probe_params, 0, sizeof(probe_params));
2458 probe_params.protocol = QED_PROTOCOL_ETH;
2459 probe_params.dp_module = dp_module;
2460 probe_params.dp_level = dp_level;
2461 probe_params.is_vf = is_vf;
2462 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2463 if (!cdev) {
2464 rc = -ENODEV;
2465 goto err0;
2466 }
2467
2468 qede_update_pf_params(cdev);
2469
2470 /* Start the Slowpath-process */
1a635e48
YM		 2471 memset(&sp_params, 0, sizeof(sp_params));
2472 sp_params.int_mode = QED_INT_MODE_MSIX;
2473 sp_params.drv_major = QEDE_MAJOR_VERSION;
2474 sp_params.drv_minor = QEDE_MINOR_VERSION;
2475 sp_params.drv_rev = QEDE_REVISION_VERSION;
2476 sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
2477 strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2478 rc = qed_ops->common->slowpath_start(cdev, &sp_params);
e712d52b
YM		 2479 if (rc) {
2480 pr_notice("Cannot start slowpath\n");
2481 goto err1;
2482 }
2483
2484 /* Learn information crucial for qede to progress */
2485 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2486 if (rc)
2487 goto err2;
2488
2489 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2490 dp_level);
2491 if (!edev) {
2492 rc = -ENOMEM;
2493 goto err2;
2494 }
2495
fefb0202
YM		 2496 if (is_vf)
2497 edev->flags |= QEDE_FLAG_IS_VF;
2498
e712d52b
YM		 2499 qede_init_ndev(edev);
2500
2950219d
YM		 2501 rc = register_netdev(edev->ndev);
2502 if (rc) {
2503 DP_NOTICE(edev, "Cannot register net-device\n");
2504 goto err3;
2505 }
2506
e712d52b
YM		 2507 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2508
a2ec6172
SK		 2509 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2510
489e45ae
SRK		 2511#ifdef CONFIG_DCB
2512 qede_set_dcbnl_ops(edev->ndev);
2513#endif
2514
0d8e0aa0
SK		 2515 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2516 mutex_init(&edev->qede_lock);
3d789994 2517 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
0d8e0aa0 2518
e712d52b
YM		 2519 DP_INFO(edev, "Ending successfully qede probe\n");
2520
2521 return 0;
2522
2950219d
YM		 2523err3:
2524 free_netdev(edev->ndev);
e712d52b
YM		 2525err2:
2526 qed_ops->common->slowpath_stop(cdev);
2527err1:
2528 qed_ops->common->remove(cdev);
2529err0:
2530 return rc;
2531}
2532
2533static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2534{
fefb0202 2535 bool is_vf = false;
e712d52b
YM		 2536 u32 dp_module = 0;
2537 u8 dp_level = 0;
2538
fefb0202
YM		 2539 switch ((enum qede_pci_private)id->driver_data) {
2540 case QEDE_PRIVATE_VF:
2541 if (debug & QED_LOG_VERBOSE_MASK)
2542 dev_err(&pdev->dev, "Probing a VF\n");
2543 is_vf = true;
2544 break;
2545 default:
2546 if (debug & QED_LOG_VERBOSE_MASK)
2547 dev_err(&pdev->dev, "Probing a PF\n");
2548 }
2549
e712d52b
YM		 2550 qede_config_debug(debug, &dp_module, &dp_level);
2551
fefb0202 2552 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2553 QEDE_PROBE_NORMAL);
2554}
2555
2556enum qede_remove_mode {
2557 QEDE_REMOVE_NORMAL,
2558};
2559
2560static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2561{
2562 struct net_device *ndev = pci_get_drvdata(pdev);
2563 struct qede_dev *edev = netdev_priv(ndev);
2564 struct qed_dev *cdev = edev->cdev;
2565
2566 DP_INFO(edev, "Starting qede_remove\n");
2567
0d8e0aa0 2568 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2569 unregister_netdev(ndev);
2570
e712d52b
YM		 2571 edev->ops->common->set_power_state(cdev, PCI_D0);
2572
2573 pci_set_drvdata(pdev, NULL);
2574
2575 free_netdev(ndev);
2576
2577 /* Use global ops since we've freed edev */
2578 qed_ops->common->slowpath_stop(cdev);
2579 qed_ops->common->remove(cdev);
2580
525ef5c0 2581 dev_info(&pdev->dev, "Ending qede_remove successfully\n");
e712d52b
YM		 2582}
2583
2584static void qede_remove(struct pci_dev *pdev)
2585{
2586 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2587}
2950219d
YM		 2588
2589/* -------------------------------------------------------------------------
2590 * START OF LOAD / UNLOAD
2591 * -------------------------------------------------------------------------
2592 */
2593
2594static int qede_set_num_queues(struct qede_dev *edev)
2595{
2596 int rc;
2597 u16 rss_num;
2598
2599 /* Setup queues according to possible resources*/
8edf049d
SK		 2600 if (edev->req_rss)
2601 rss_num = edev->req_rss;
2602 else
2603 rss_num = netif_get_num_default_rss_queues() *
2604 edev->dev_info.common.num_hwfns;
2950219d
YM		 2605
2606 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2607
2608 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2609 if (rc > 0) {
2610 /* Managed to request interrupts for our queues */
2611 edev->num_rss = rc;
2612 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2613 QEDE_RSS_CNT(edev), rss_num);
2614 rc = 0;
2615 }
2616 return rc;
2617}
2618
2619static void qede_free_mem_sb(struct qede_dev *edev,
2620 struct qed_sb_info *sb_info)
2621{
2622 if (sb_info->sb_virt)
2623 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2624 (void *)sb_info->sb_virt, sb_info->sb_phys);
2625}
2626
2627/* This function allocates fast-path status block memory */
2628static int qede_alloc_mem_sb(struct qede_dev *edev,
1a635e48 2629 struct qed_sb_info *sb_info, u16 sb_id)
2950219d
YM		 2630{
2631 struct status_block *sb_virt;
2632 dma_addr_t sb_phys;
2633 int rc;
2634
2635 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1a635e48 2636 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
2950219d
YM		 2637 if (!sb_virt) {
2638 DP_ERR(edev, "Status block allocation failed\n");
2639 return -ENOMEM;
2640 }
2641
2642 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2643 sb_virt, sb_phys, sb_id,
2644 QED_SB_TYPE_L2_QUEUE);
2645 if (rc) {
2646 DP_ERR(edev, "Status block initialization failed\n");
2647 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2648 sb_virt, sb_phys);
2649 return rc;
2650 }
2651
2652 return 0;
2653}
2654
2655static void qede_free_rx_buffers(struct qede_dev *edev,
2656 struct qede_rx_queue *rxq)
2657{
2658 u16 i;
2659
2660 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2661 struct sw_rx_data *rx_buf;
fc48b7a6 2662 struct page *data;
2950219d
YM		 2663
2664 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2665 data = rx_buf->data;
2666
fc48b7a6 2667 dma_unmap_page(&edev->pdev->dev,
1a635e48 2668 rx_buf->mapping, PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2669
2670 rx_buf->data = NULL;
fc48b7a6 2671 __free_page(data);
2950219d
YM		 2672 }
2673}
2674
1a635e48
YM		 2675static void qede_free_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
2676{
55482edc
MC		 2677 int i;
2678
2679 if (edev->gro_disable)
2680 return;
2681
2682 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2683 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2684 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2685
f86af2df 2686 if (replace_buf->data) {
55482edc 2687 dma_unmap_page(&edev->pdev->dev,
09ec8e7f 2688 replace_buf->mapping,
55482edc
MC		 2689 PAGE_SIZE, DMA_FROM_DEVICE);
2690 __free_page(replace_buf->data);
2691 }
2692 }
2693}
2694
1a635e48 2695static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2696{
55482edc
MC		 2697 qede_free_sge_mem(edev, rxq);
2698
2950219d
YM		 2699 /* Free rx buffers */
2700 qede_free_rx_buffers(edev, rxq);
2701
2702 /* Free the parallel SW ring */
2703 kfree(rxq->sw_rx_ring);
2704
2705 /* Free the real RQ ring used by FW */
2706 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2707 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2708}
2709
2710static int qede_alloc_rx_buffer(struct qede_dev *edev,
2711 struct qede_rx_queue *rxq)
2712{
2713 struct sw_rx_data *sw_rx_data;
2714 struct eth_rx_bd *rx_bd;
2715 dma_addr_t mapping;
fc48b7a6 2716 struct page *data;
2950219d 2717
fc48b7a6 2718 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2719 if (unlikely(!data)) {
fc48b7a6 2720 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2721 return -ENOMEM;
2722 }
2723
fc48b7a6
YM		 2724 /* Map the entire page as it would be used
2725 * for multiple RX buffer segment size mapping.
2726 */
2727 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2728 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2729 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2730 __free_page(data);
2950219d
YM		 2731 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2732 return -ENOMEM;
2733 }
2734
2735 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2736 sw_rx_data->page_offset = 0;
2950219d 2737 sw_rx_data->data = data;
fc48b7a6 2738 sw_rx_data->mapping = mapping;
2950219d
YM		 2739
2740 /* Advance PROD and get BD pointer */
2741 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2742 WARN_ON(!rx_bd);
2743 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2744 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2745
2746 rxq->sw_rx_prod++;
2747
2748 return 0;
2749}
2750
1a635e48 2751static int qede_alloc_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
55482edc
MC		 2752{
2753 dma_addr_t mapping;
2754 int i;
2755
2756 if (edev->gro_disable)
2757 return 0;
2758
2759 if (edev->ndev->mtu > PAGE_SIZE) {
2760 edev->gro_disable = 1;
2761 return 0;
2762 }
2763
2764 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2765 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2766 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2767
2768 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2769 if (unlikely(!replace_buf->data)) {
2770 DP_NOTICE(edev,
2771 "Failed to allocate TPA skb pool [replacement buffer]\n");
2772 goto err;
2773 }
2774
2775 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2776 rxq->rx_buf_size, DMA_FROM_DEVICE);
2777 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2778 DP_NOTICE(edev,
2779 "Failed to map TPA replacement buffer\n");
2780 goto err;
2781 }
2782
09ec8e7f 2783 replace_buf->mapping = mapping;
55482edc
MC		 2784 tpa_info->replace_buf.page_offset = 0;
2785
2786 tpa_info->replace_buf_mapping = mapping;
2787 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2788 }
2789
2790 return 0;
2791err:
2792 qede_free_sge_mem(edev, rxq);
2793 edev->gro_disable = 1;
2794 return -ENOMEM;
2795}
2796
2950219d 2797/* This function allocates all memory needed per Rx queue */
1a635e48 2798static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2799{
f86af2df 2800 int i, rc, size;
2950219d
YM		 2801
2802 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2803
1a635e48
YM		 2804 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
2805
fc48b7a6
YM		 2806 if (rxq->rx_buf_size > PAGE_SIZE)
2807 rxq->rx_buf_size = PAGE_SIZE;
2808
2809 /* Segment size to spilt a page in multiple equal parts */
2810 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2811
2812 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2813 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2814 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2815 if (!rxq->sw_rx_ring) {
2816 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2817 rc = -ENOMEM;
2950219d
YM		 2818 goto err;
2819 }
2820
2821 /* Allocate FW Rx ring */
2822 rc = edev->ops->common->chain_alloc(edev->cdev,
2823 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2824 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 2825 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2826 RX_RING_SIZE,
2950219d
YM		 2827 sizeof(struct eth_rx_bd),
2828 &rxq->rx_bd_ring);
2829
2830 if (rc)
2831 goto err;
2832
2833 /* Allocate FW completion ring */
2834 rc = edev->ops->common->chain_alloc(edev->cdev,
2835 QED_CHAIN_USE_TO_CONSUME,
2836 QED_CHAIN_MODE_PBL,
a91eb52a 2837 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2838 RX_RING_SIZE,
2950219d
YM		 2839 sizeof(union eth_rx_cqe),
2840 &rxq->rx_comp_ring);
2841 if (rc)
2842 goto err;
2843
2844 /* Allocate buffers for the Rx ring */
2845 for (i = 0; i < rxq->num_rx_buffers; i++) {
2846 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2847 if (rc) {
2848 DP_ERR(edev,
2849 "Rx buffers allocation failed at index %d\n", i);
2850 goto err;
2851 }
2950219d
YM		 2852 }
2853
f86af2df 2854 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2855err:
f86af2df 2856 return rc;
2950219d
YM		 2857}
2858
1a635e48 2859static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 2860{
2861 /* Free the parallel SW ring */
2862 kfree(txq->sw_tx_ring);
2863
2864 /* Free the real RQ ring used by FW */
2865 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2866}
2867
2868/* This function allocates all memory needed per Tx queue */
1a635e48 2869static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 2870{
2871 int size, rc;
2872 union eth_tx_bd_types *p_virt;
2873
2874 txq->num_tx_buffers = edev->q_num_tx_buffers;
2875
2876 /* Allocate the parallel driver ring for Tx buffers */
2877 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2878 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2879 if (!txq->sw_tx_ring) {
2880 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2881 goto err;
2882 }
2883
2884 rc = edev->ops->common->chain_alloc(edev->cdev,
2885 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2886 QED_CHAIN_MODE_PBL,
a91eb52a 2887 QED_CHAIN_CNT_TYPE_U16,
2950219d 2888 NUM_TX_BDS_MAX,
a91eb52a 2889 sizeof(*p_virt), &txq->tx_pbl);
2950219d
YM		 2890 if (rc)
2891 goto err;
2892
2893 return 0;
2894
2895err:
2896 qede_free_mem_txq(edev, txq);
2897 return -ENOMEM;
2898}
2899
2900/* This function frees all memory of a single fp */
1a635e48 2901static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d
YM		 2902{
2903 int tc;
2904
2905 qede_free_mem_sb(edev, fp->sb_info);
2906
2907 qede_free_mem_rxq(edev, fp->rxq);
2908
2909 for (tc = 0; tc < edev->num_tc; tc++)
2910 qede_free_mem_txq(edev, &fp->txqs[tc]);
2911}
2912
2913/* This function allocates all memory needed for a single fp (i.e. an entity
2914 * which contains status block, one rx queue and multiple per-TC tx queues.
2915 */
1a635e48 2916static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d
YM		 2917{
2918 int rc, tc;
2919
2920 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2921 if (rc)
2922 goto err;
2923
2924 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2925 if (rc)
2926 goto err;
2927
2928 for (tc = 0; tc < edev->num_tc; tc++) {
2929 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2930 if (rc)
2931 goto err;
2932 }
2933
2934 return 0;
2950219d 2935err:
f86af2df 2936 return rc;
2950219d
YM		 2937}
2938
2939static void qede_free_mem_load(struct qede_dev *edev)
2940{
2941 int i;
2942
2943 for_each_rss(i) {
2944 struct qede_fastpath *fp = &edev->fp_array[i];
2945
2946 qede_free_mem_fp(edev, fp);
2947 }
2948}
2949
2950/* This function allocates all qede memory at NIC load. */
2951static int qede_alloc_mem_load(struct qede_dev *edev)
2952{
2953 int rc = 0, rss_id;
2954
2955 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2956 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2957
2958 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2959 if (rc) {
2950219d 2960 DP_ERR(edev,
f86af2df
MC		 2961 "Failed to allocate memory for fastpath - rss id = %d\n",
2962 rss_id);
2963 qede_free_mem_load(edev);
2964 return rc;
2950219d 2965 }
2950219d
YM		 2966 }
2967
2968 return 0;
2969}
2970
2971/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2972static void qede_init_fp(struct qede_dev *edev)
2973{
2974 int rss_id, txq_index, tc;
2975 struct qede_fastpath *fp;
2976
2977 for_each_rss(rss_id) {
2978 fp = &edev->fp_array[rss_id];
2979
2980 fp->edev = edev;
2981 fp->rss_id = rss_id;
2982
2983 memset((void *)&fp->napi, 0, sizeof(fp->napi));
2984
2985 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
2986
2987 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
2988 fp->rxq->rxq_id = rss_id;
2989
2990 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
2991 for (tc = 0; tc < edev->num_tc; tc++) {
2992 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
2993 fp->txqs[tc].index = txq_index;
2994 }
2995
2996 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
2997 edev->ndev->name, rss_id);
2998 }
55482edc
MC		 2999
3000 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 3001}
3002
3003static int qede_set_real_num_queues(struct qede_dev *edev)
3004{
3005 int rc = 0;
3006
3007 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
3008 if (rc) {
3009 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
3010 return rc;
3011 }
3012 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
3013 if (rc) {
3014 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
3015 return rc;
3016 }
3017
3018 return 0;
3019}
3020
3021static void qede_napi_disable_remove(struct qede_dev *edev)
3022{
3023 int i;
3024
3025 for_each_rss(i) {
3026 napi_disable(&edev->fp_array[i].napi);
3027
3028 netif_napi_del(&edev->fp_array[i].napi);
3029 }
3030}
3031
3032static void qede_napi_add_enable(struct qede_dev *edev)
3033{
3034 int i;
3035
3036 /* Add NAPI objects */
3037 for_each_rss(i) {
3038 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
3039 qede_poll, NAPI_POLL_WEIGHT);
3040 napi_enable(&edev->fp_array[i].napi);
3041 }
3042}
3043
3044static void qede_sync_free_irqs(struct qede_dev *edev)
3045{
3046 int i;
3047
3048 for (i = 0; i < edev->int_info.used_cnt; i++) {
3049 if (edev->int_info.msix_cnt) {
3050 synchronize_irq(edev->int_info.msix[i].vector);
3051 free_irq(edev->int_info.msix[i].vector,
3052 &edev->fp_array[i]);
3053 } else {
3054 edev->ops->common->simd_handler_clean(edev->cdev, i);
3055 }
3056 }
3057
3058 edev->int_info.used_cnt = 0;
3059}
3060
3061static int qede_req_msix_irqs(struct qede_dev *edev)
3062{
3063 int i, rc;
3064
3065 /* Sanitize number of interrupts == number of prepared RSS queues */
3066 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
3067 DP_ERR(edev,
3068 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
3069 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
3070 return -EINVAL;
3071 }
3072
3073 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
3074 rc = request_irq(edev->int_info.msix[i].vector,
3075 qede_msix_fp_int, 0, edev->fp_array[i].name,
3076 &edev->fp_array[i]);
3077 if (rc) {
3078 DP_ERR(edev, "Request fp %d irq failed\n", i);
3079 qede_sync_free_irqs(edev);
3080 return rc;
3081 }
3082 DP_VERBOSE(edev, NETIF_MSG_INTR,
3083 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
3084 edev->fp_array[i].name, i,
3085 &edev->fp_array[i]);
3086 edev->int_info.used_cnt++;
3087 }
3088
3089 return 0;
3090}
3091
3092static void qede_simd_fp_handler(void *cookie)
3093{
3094 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
3095
3096 napi_schedule_irqoff(&fp->napi);
3097}
3098
3099static int qede_setup_irqs(struct qede_dev *edev)
3100{
3101 int i, rc = 0;
3102
3103 /* Learn Interrupt configuration */
3104 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
3105 if (rc)
3106 return rc;
3107
3108 if (edev->int_info.msix_cnt) {
3109 rc = qede_req_msix_irqs(edev);
3110 if (rc)
3111 return rc;
3112 edev->ndev->irq = edev->int_info.msix[0].vector;
3113 } else {
3114 const struct qed_common_ops *ops;
3115
3116 /* qed should learn receive the RSS ids and callbacks */
3117 ops = edev->ops->common;
3118 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
3119 ops->simd_handler_config(edev->cdev,
3120 &edev->fp_array[i], i,
3121 qede_simd_fp_handler);
3122 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
3123 }
3124 return 0;
3125}
3126
3127static int qede_drain_txq(struct qede_dev *edev,
1a635e48 3128 struct qede_tx_queue *txq, bool allow_drain)
2950219d
YM		 3129{
3130 int rc, cnt = 1000;
3131
3132 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3133 if (!cnt) {
3134 if (allow_drain) {
3135 DP_NOTICE(edev,
3136 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3137 txq->index);
3138 rc = edev->ops->common->drain(edev->cdev);
3139 if (rc)
3140 return rc;
3141 return qede_drain_txq(edev, txq, false);
3142 }
3143 DP_NOTICE(edev,
3144 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3145 txq->index, txq->sw_tx_prod,
3146 txq->sw_tx_cons);
3147 return -ENODEV;
3148 }
3149 cnt--;
3150 usleep_range(1000, 2000);
3151 barrier();
3152 }
3153
3154 /* FW finished processing, wait for HW to transmit all tx packets */
3155 usleep_range(1000, 2000);
3156
3157 return 0;
3158}
3159
3160static int qede_stop_queues(struct qede_dev *edev)
3161{
3162 struct qed_update_vport_params vport_update_params;
3163 struct qed_dev *cdev = edev->cdev;
3164 int rc, tc, i;
3165
3166 /* Disable the vport */
3167 memset(&vport_update_params, 0, sizeof(vport_update_params));
3168 vport_update_params.vport_id = 0;
3169 vport_update_params.update_vport_active_flg = 1;
3170 vport_update_params.vport_active_flg = 0;
3171 vport_update_params.update_rss_flg = 0;
3172
3173 rc = edev->ops->vport_update(cdev, &vport_update_params);
3174 if (rc) {
3175 DP_ERR(edev, "Failed to update vport\n");
3176 return rc;
3177 }
3178
3179 /* Flush Tx queues. If needed, request drain from MCP */
3180 for_each_rss(i) {
3181 struct qede_fastpath *fp = &edev->fp_array[i];
3182
3183 for (tc = 0; tc < edev->num_tc; tc++) {
3184 struct qede_tx_queue *txq = &fp->txqs[tc];
3185
3186 rc = qede_drain_txq(edev, txq, true);
3187 if (rc)
3188 return rc;
3189 }
3190 }
3191
3192 /* Stop all Queues in reverse order*/
3193 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3194 struct qed_stop_rxq_params rx_params;
3195
3196 /* Stop the Tx Queue(s)*/
3197 for (tc = 0; tc < edev->num_tc; tc++) {
3198 struct qed_stop_txq_params tx_params;
3199
3200 tx_params.rss_id = i;
3201 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3202 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3203 if (rc) {
3204 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3205 tx_params.tx_queue_id);
3206 return rc;
3207 }
3208 }
3209
3210 /* Stop the Rx Queue*/
3211 memset(&rx_params, 0, sizeof(rx_params));
3212 rx_params.rss_id = i;
3213 rx_params.rx_queue_id = i;
3214
3215 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3216 if (rc) {
3217 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3218 return rc;
3219 }
3220 }
3221
3222 /* Stop the vport */
3223 rc = edev->ops->vport_stop(cdev, 0);
3224 if (rc)
3225 DP_ERR(edev, "Failed to stop VPORT\n");
3226
3227 return rc;
3228}
3229
a0d26d5a 3230static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d
YM		 3231{
3232 int rc, tc, i;
088c8618 3233 int vlan_removal_en = 1;
2950219d 3234 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3235 struct qed_update_vport_params vport_update_params;
3236 struct qed_queue_start_common_params q_params;
fefb0202 3237 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3238 struct qed_start_vport_params start = {0};
961acdea 3239 bool reset_rss_indir = false;
2950219d
YM		 3240
3241 if (!edev->num_rss) {
3242 DP_ERR(edev,
3243 "Cannot update V-VPORT as active as there are no Rx queues\n");
3244 return -EINVAL;
3245 }
3246
55482edc 3247 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3248 start.mtu = edev->ndev->mtu;
3249 start.vport_id = 0;
3250 start.drop_ttl0 = true;
3251 start.remove_inner_vlan = vlan_removal_en;
7f7a144f 3252 start.clear_stats = clear_stats;
088c8618
MC		 3253
3254 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3255
3256 if (rc) {
3257 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3258 return rc;
3259 }
3260
3261 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3262 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3263 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3264
3265 for_each_rss(i) {
3266 struct qede_fastpath *fp = &edev->fp_array[i];
3267 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3268
3269 memset(&q_params, 0, sizeof(q_params));
3270 q_params.rss_id = i;
3271 q_params.queue_id = i;
3272 q_params.vport_id = 0;
3273 q_params.sb = fp->sb_info->igu_sb_id;
3274 q_params.sb_idx = RX_PI;
3275
3276 rc = edev->ops->q_rx_start(cdev, &q_params,
3277 fp->rxq->rx_buf_size,
3278 fp->rxq->rx_bd_ring.p_phys_addr,
3279 phys_table,
3280 fp->rxq->rx_comp_ring.page_cnt,
3281 &fp->rxq->hw_rxq_prod_addr);
3282 if (rc) {
3283 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3284 return rc;
3285 }
3286
3287 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3288
3289 qede_update_rx_prod(edev, fp->rxq);
3290
3291 for (tc = 0; tc < edev->num_tc; tc++) {
3292 struct qede_tx_queue *txq = &fp->txqs[tc];
3293 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3294
3295 memset(&q_params, 0, sizeof(q_params));
3296 q_params.rss_id = i;
3297 q_params.queue_id = txq_index;
3298 q_params.vport_id = 0;
3299 q_params.sb = fp->sb_info->igu_sb_id;
3300 q_params.sb_idx = TX_PI(tc);
3301
3302 rc = edev->ops->q_tx_start(cdev, &q_params,
3303 txq->tx_pbl.pbl.p_phys_table,
3304 txq->tx_pbl.page_cnt,
3305 &txq->doorbell_addr);
3306 if (rc) {
3307 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3308 txq_index, rc);
3309 return rc;
3310 }
3311
3312 txq->hw_cons_ptr =
3313 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3314 SET_FIELD(txq->tx_db.data.params,
3315 ETH_DB_DATA_DEST, DB_DEST_XCM);
3316 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3317 DB_AGG_CMD_SET);
3318 SET_FIELD(txq->tx_db.data.params,
3319 ETH_DB_DATA_AGG_VAL_SEL,
3320 DQ_XCM_ETH_TX_BD_PROD_CMD);
3321
3322 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3323 }
3324 }
3325
3326 /* Prepare and send the vport enable */
3327 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3328 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3329 vport_update_params.update_vport_active_flg = 1;
3330 vport_update_params.vport_active_flg = 1;
3331
831bfb0e
YM		 3332 if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
3333 qed_info->tx_switching) {
3334 vport_update_params.update_tx_switching_flg = 1;
3335 vport_update_params.tx_switching_flg = 1;
3336 }
3337
2950219d
YM		 3338 /* Fill struct with RSS params */
3339 if (QEDE_RSS_CNT(edev) > 1) {
3340 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3341
3342 /* Need to validate current RSS config uses valid entries */
3343 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3344 if (edev->rss_params.rss_ind_table[i] >=
3345 edev->num_rss) {
3346 reset_rss_indir = true;
3347 break;
3348 }
3349 }
3350
3351 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3352 reset_rss_indir) {
3353 u16 val;
3354
3355 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3356 u16 indir_val;
3357
3358 val = QEDE_RSS_CNT(edev);
3359 indir_val = ethtool_rxfh_indir_default(i, val);
3360 edev->rss_params.rss_ind_table[i] = indir_val;
3361 }
3362 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3363 }
3364
3365 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3366 netdev_rss_key_fill(edev->rss_params.rss_key,
3367 sizeof(edev->rss_params.rss_key));
3368 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3369 }
3370
3371 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3372 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3373 QED_RSS_IPV6 |
3374 QED_RSS_IPV4_TCP |
3375 QED_RSS_IPV6_TCP;
3376 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3377 }
3378
3379 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3380 sizeof(vport_update_params.rss_params));
2950219d 3381 } else {
961acdea
SRK		 3382 memset(&vport_update_params.rss_params, 0,
3383 sizeof(vport_update_params.rss_params));
2950219d 3384 }
2950219d
YM		 3385
3386 rc = edev->ops->vport_update(cdev, &vport_update_params);
3387 if (rc) {
3388 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3389 return rc;
3390 }
3391
3392 return 0;
3393}
3394
0d8e0aa0
SK		 3395static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3396 enum qed_filter_xcast_params_type opcode,
3397 unsigned char *mac, int num_macs)
3398{
3399 struct qed_filter_params filter_cmd;
3400 int i;
3401
3402 memset(&filter_cmd, 0, sizeof(filter_cmd));
3403 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3404 filter_cmd.filter.mcast.type = opcode;
3405 filter_cmd.filter.mcast.num = num_macs;
3406
3407 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3408 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3409
3410 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3411}
3412
2950219d
YM		 3413enum qede_unload_mode {
3414 QEDE_UNLOAD_NORMAL,
3415};
3416
3417static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3418{
a2ec6172 3419 struct qed_link_params link_params;
2950219d
YM		 3420 int rc;
3421
3422 DP_INFO(edev, "Starting qede unload\n");
3423
0d8e0aa0
SK		 3424 mutex_lock(&edev->qede_lock);
3425 edev->state = QEDE_STATE_CLOSED;
3426
2950219d
YM		 3427 /* Close OS Tx */
3428 netif_tx_disable(edev->ndev);
3429 netif_carrier_off(edev->ndev);
3430
a2ec6172
SK		 3431 /* Reset the link */
3432 memset(&link_params, 0, sizeof(link_params));
3433 link_params.link_up = false;
3434 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3435 rc = qede_stop_queues(edev);
3436 if (rc) {
3437 qede_sync_free_irqs(edev);
3438 goto out;
3439 }
3440
3441 DP_INFO(edev, "Stopped Queues\n");
3442
7c1bfcad 3443 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3444 edev->ops->fastpath_stop(edev->cdev);
3445
3446 /* Release the interrupts */
3447 qede_sync_free_irqs(edev);
3448 edev->ops->common->set_fp_int(edev->cdev, 0);
3449
3450 qede_napi_disable_remove(edev);
3451
3452 qede_free_mem_load(edev);
3453 qede_free_fp_array(edev);
3454
3455out:
3456 mutex_unlock(&edev->qede_lock);
3457 DP_INFO(edev, "Ending qede unload\n");
3458}
3459
3460enum qede_load_mode {
3461 QEDE_LOAD_NORMAL,
a0d26d5a 3462 QEDE_LOAD_RELOAD,
2950219d
YM		 3463};
3464
3465static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3466{
a2ec6172
SK		 3467 struct qed_link_params link_params;
3468 struct qed_link_output link_output;
2950219d
YM		 3469 int rc;
3470
3471 DP_INFO(edev, "Starting qede load\n");
3472
3473 rc = qede_set_num_queues(edev);
3474 if (rc)
3475 goto err0;
3476
3477 rc = qede_alloc_fp_array(edev);
3478 if (rc)
3479 goto err0;
3480
3481 qede_init_fp(edev);
3482
3483 rc = qede_alloc_mem_load(edev);
3484 if (rc)
3485 goto err1;
3486 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3487 QEDE_RSS_CNT(edev), edev->num_tc);
3488
3489 rc = qede_set_real_num_queues(edev);
3490 if (rc)
3491 goto err2;
3492
3493 qede_napi_add_enable(edev);
3494 DP_INFO(edev, "Napi added and enabled\n");
3495
3496 rc = qede_setup_irqs(edev);
3497 if (rc)
3498 goto err3;
3499 DP_INFO(edev, "Setup IRQs succeeded\n");
3500
a0d26d5a 3501 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 3502 if (rc)
3503 goto err4;
3504 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3505
3506 /* Add primary mac and set Rx filters */
3507 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3508
0d8e0aa0
SK		 3509 mutex_lock(&edev->qede_lock);
3510 edev->state = QEDE_STATE_OPEN;
3511 mutex_unlock(&edev->qede_lock);
a2ec6172 3512
7c1bfcad
SRK		 3513 /* Program un-configured VLANs */
3514 qede_configure_vlan_filters(edev);
3515
a2ec6172
SK		 3516 /* Ask for link-up using current configuration */
3517 memset(&link_params, 0, sizeof(link_params));
3518 link_params.link_up = true;
3519 edev->ops->common->set_link(edev->cdev, &link_params);
3520
3521 /* Query whether link is already-up */
3522 memset(&link_output, 0, sizeof(link_output));
3523 edev->ops->common->get_link(edev->cdev, &link_output);
3524 qede_link_update(edev, &link_output);
3525
2950219d
YM		 3526 DP_INFO(edev, "Ending successfully qede load\n");
3527
3528 return 0;
3529
3530err4:
3531 qede_sync_free_irqs(edev);
3532 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3533err3:
3534 qede_napi_disable_remove(edev);
3535err2:
3536 qede_free_mem_load(edev);
3537err1:
3538 edev->ops->common->set_fp_int(edev->cdev, 0);
3539 qede_free_fp_array(edev);
3540 edev->num_rss = 0;
3541err0:
3542 return rc;
3543}
3544
133fac0e
SK		 3545void qede_reload(struct qede_dev *edev,
3546 void (*func)(struct qede_dev *, union qede_reload_args *),
3547 union qede_reload_args *args)
3548{
3549 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3550 /* Call function handler to update parameters
3551 * needed for function load.
3552 */
3553 if (func)
3554 func(edev, args);
3555
a0d26d5a 3556 qede_load(edev, QEDE_LOAD_RELOAD);
133fac0e
SK		 3557
3558 mutex_lock(&edev->qede_lock);
3559 qede_config_rx_mode(edev->ndev);
3560 mutex_unlock(&edev->qede_lock);
3561}
3562
2950219d
YM		 3563/* called with rtnl_lock */
3564static int qede_open(struct net_device *ndev)
3565{
3566 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3567 int rc;
2950219d
YM		 3568
3569 netif_carrier_off(ndev);
3570
3571 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3572
b18e170c
MC		 3573 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3574
3575 if (rc)
3576 return rc;
3577
f9f082a9
AD		 3578 udp_tunnel_get_rx_info(ndev);
3579
b18e170c 3580 return 0;
2950219d
YM		 3581}
3582
3583static int qede_close(struct net_device *ndev)
3584{
3585 struct qede_dev *edev = netdev_priv(ndev);
3586
3587 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3588
3589 return 0;
3590}
0d8e0aa0 3591
a2ec6172
SK		 3592static void qede_link_update(void *dev, struct qed_link_output *link)
3593{
3594 struct qede_dev *edev = dev;
3595
3596 if (!netif_running(edev->ndev)) {
3597 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3598 return;
3599 }
3600
3601 if (link->link_up) {
8e025ae2
YM		 3602 if (!netif_carrier_ok(edev->ndev)) {
3603 DP_NOTICE(edev, "Link is up\n");
3604 netif_tx_start_all_queues(edev->ndev);
3605 netif_carrier_on(edev->ndev);
3606 }
a2ec6172 3607 } else {
8e025ae2
YM		 3608 if (netif_carrier_ok(edev->ndev)) {
3609 DP_NOTICE(edev, "Link is down\n");
3610 netif_tx_disable(edev->ndev);
3611 netif_carrier_off(edev->ndev);
3612 }
a2ec6172
SK		 3613 }
3614}
3615
0d8e0aa0
SK		 3616static int qede_set_mac_addr(struct net_device *ndev, void *p)
3617{
3618 struct qede_dev *edev = netdev_priv(ndev);
3619 struct sockaddr *addr = p;
3620 int rc;
3621
3622 ASSERT_RTNL(); /* @@@TBD To be removed */
3623
3624 DP_INFO(edev, "Set_mac_addr called\n");
3625
3626 if (!is_valid_ether_addr(addr->sa_data)) {
3627 DP_NOTICE(edev, "The MAC address is not valid\n");
3628 return -EFAULT;
3629 }
3630
eff16960
YM		 3631 if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
3632 DP_NOTICE(edev, "qed prevents setting MAC\n");
3633 return -EINVAL;
3634 }
3635
0d8e0aa0
SK		 3636 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3637
3638 if (!netif_running(ndev)) {
3639 DP_NOTICE(edev, "The device is currently down\n");
3640 return 0;
3641 }
3642
3643 /* Remove the previous primary mac */
3644 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3645 edev->primary_mac);
3646 if (rc)
3647 return rc;
3648
3649 /* Add MAC filter according to the new unicast HW MAC address */
3650 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3651 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3652 edev->primary_mac);
3653}
3654
3655static int
3656qede_configure_mcast_filtering(struct net_device *ndev,
3657 enum qed_filter_rx_mode_type *accept_flags)
3658{
3659 struct qede_dev *edev = netdev_priv(ndev);
3660 unsigned char *mc_macs, *temp;
3661 struct netdev_hw_addr *ha;
3662 int rc = 0, mc_count;
3663 size_t size;
3664
3665 size = 64 * ETH_ALEN;
3666
3667 mc_macs = kzalloc(size, GFP_KERNEL);
3668 if (!mc_macs) {
3669 DP_NOTICE(edev,
3670 "Failed to allocate memory for multicast MACs\n");
3671 rc = -ENOMEM;
3672 goto exit;
3673 }
3674
3675 temp = mc_macs;
3676
3677 /* Remove all previously configured MAC filters */
3678 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3679 mc_macs, 1);
3680 if (rc)
3681 goto exit;
3682
3683 netif_addr_lock_bh(ndev);
3684
3685 mc_count = netdev_mc_count(ndev);
3686 if (mc_count < 64) {
3687 netdev_for_each_mc_addr(ha, ndev) {
3688 ether_addr_copy(temp, ha->addr);
3689 temp += ETH_ALEN;
3690 }
3691 }
3692
3693 netif_addr_unlock_bh(ndev);
3694
3695 /* Check for all multicast @@@TBD resource allocation */
3696 if ((ndev->flags & IFF_ALLMULTI) ||
3697 (mc_count > 64)) {
3698 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3699 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3700 } else {
3701 /* Add all multicast MAC filters */
3702 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3703 mc_macs, mc_count);
3704 }
3705
3706exit:
3707 kfree(mc_macs);
3708 return rc;
3709}
3710
3711static void qede_set_rx_mode(struct net_device *ndev)
3712{
3713 struct qede_dev *edev = netdev_priv(ndev);
3714
3715 DP_INFO(edev, "qede_set_rx_mode called\n");
3716
3717 if (edev->state != QEDE_STATE_OPEN) {
3718 DP_INFO(edev,
3719 "qede_set_rx_mode called while interface is down\n");
3720 } else {
3721 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3722 schedule_delayed_work(&edev->sp_task, 0);
3723 }
3724}
3725
3726/* Must be called with qede_lock held */
3727static void qede_config_rx_mode(struct net_device *ndev)
3728{
3729 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3730 struct qede_dev *edev = netdev_priv(ndev);
3731 struct qed_filter_params rx_mode;
3732 unsigned char *uc_macs, *temp;
3733 struct netdev_hw_addr *ha;
3734 int rc, uc_count;
3735 size_t size;
3736
3737 netif_addr_lock_bh(ndev);
3738
3739 uc_count = netdev_uc_count(ndev);
3740 size = uc_count * ETH_ALEN;
3741
3742 uc_macs = kzalloc(size, GFP_ATOMIC);
3743 if (!uc_macs) {
3744 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3745 netif_addr_unlock_bh(ndev);
3746 return;
3747 }
3748
3749 temp = uc_macs;
3750 netdev_for_each_uc_addr(ha, ndev) {
3751 ether_addr_copy(temp, ha->addr);
3752 temp += ETH_ALEN;
3753 }
3754
3755 netif_addr_unlock_bh(ndev);
3756
3757 /* Configure the struct for the Rx mode */
3758 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3759 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3760
3761 /* Remove all previous unicast secondary macs and multicast macs
3762 * (configrue / leave the primary mac)
3763 */
3764 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3765 edev->primary_mac);
3766 if (rc)
3767 goto out;
3768
3769 /* Check for promiscuous */
3770 if ((ndev->flags & IFF_PROMISC) ||
3771 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3772 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3773 } else {
3774 /* Add MAC filters according to the unicast secondary macs */
3775 int i;
3776
3777 temp = uc_macs;
3778 for (i = 0; i < uc_count; i++) {
3779 rc = qede_set_ucast_rx_mac(edev,
3780 QED_FILTER_XCAST_TYPE_ADD,
3781 temp);
3782 if (rc)
3783 goto out;
3784
3785 temp += ETH_ALEN;
3786 }
3787
3788 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3789 if (rc)
3790 goto out;
3791 }
3792
7c1bfcad
SRK		 3793 /* take care of VLAN mode */
3794 if (ndev->flags & IFF_PROMISC) {
3795 qede_config_accept_any_vlan(edev, true);
3796 } else if (!edev->non_configured_vlans) {
3797 /* It's possible that accept_any_vlan mode is set due to a
3798 * previous setting of IFF_PROMISC. If vlan credits are
3799 * sufficient, disable accept_any_vlan.
3800 */
3801 qede_config_accept_any_vlan(edev, false);
3802 }
3803
0d8e0aa0
SK		 3804 rx_mode.filter.accept_flags = accept_flags;
3805 edev->ops->filter_config(edev->cdev, &rx_mode);
3806out:
3807 kfree(uc_macs);
3808}
Linux kernel - Deliverables
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