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qede: Add support for capturing additional stats in ethtool-stats display.
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
f9f082a9 27#include <net/udp_tunnel.h>
e712d52b
YM		 28#include <linux/ip.h>
29#include <net/ipv6.h>
30#include <net/tcp.h>
31#include <linux/if_ether.h>
32#include <linux/if_vlan.h>
33#include <linux/pkt_sched.h>
34#include <linux/ethtool.h>
35#include <linux/in.h>
36#include <linux/random.h>
37#include <net/ip6_checksum.h>
38#include <linux/bitops.h>
39
40#include "qede.h"
41
5abd7e92
YM		 42static char version[] =
43 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 44
5abd7e92 45MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
49static uint debug;
50module_param(debug, uint, 0);
51MODULE_PARM_DESC(debug, " Default debug msglevel");
52
53static const struct qed_eth_ops *qed_ops;
54
55#define CHIP_NUM_57980S_40 0x1634
0e7441d7 56#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 57#define CHIP_NUM_57980S_MF 0x1636
58#define CHIP_NUM_57980S_100 0x1644
59#define CHIP_NUM_57980S_50 0x1654
60#define CHIP_NUM_57980S_25 0x1656
fefb0202 61#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 62
63#ifndef PCI_DEVICE_ID_NX2_57980E
64#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
65#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
66#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
67#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
68#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
69#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 70#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 71#endif
72
fefb0202
YM		 73enum qede_pci_private {
74 QEDE_PRIVATE_PF,
75 QEDE_PRIVATE_VF
76};
77
e712d52b 78static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 79 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
80 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
81 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
82 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
83 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 85#ifdef CONFIG_QED_SRIOV
fefb0202 86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
14b84e86 87#endif
e712d52b
YM		 88 { 0 }
89};
90
91MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
92
93static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
94
95#define TX_TIMEOUT (5 * HZ)
96
97static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 98static int qede_alloc_rx_buffer(struct qede_dev *edev,
99 struct qede_rx_queue *rxq);
a2ec6172 100static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 101
fefb0202 102#ifdef CONFIG_QED_SRIOV
08feecd7
YM		 103static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
104{
105 struct qede_dev *edev = netdev_priv(ndev);
106
107 if (vlan > 4095) {
108 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
109 return -EINVAL;
110 }
111
112 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
113 vlan, vf);
114
115 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
116}
117
eff16960
YM		 118static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
119{
120 struct qede_dev *edev = netdev_priv(ndev);
121
122 DP_VERBOSE(edev, QED_MSG_IOV,
123 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
124 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
125
126 if (!is_valid_ether_addr(mac)) {
127 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
128 return -EINVAL;
129 }
130
131 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
132}
133
fefb0202
YM		 134static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
135{
136 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e
YM		 137 struct qed_dev_info *qed_info = &edev->dev_info.common;
138 int rc;
fefb0202
YM		 139
140 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
141
831bfb0e
YM		 142 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
143
144 /* Enable/Disable Tx switching for PF */
145 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
146 qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
147 struct qed_update_vport_params params;
148
149 memset(&params, 0, sizeof(params));
150 params.vport_id = 0;
151 params.update_tx_switching_flg = 1;
152 params.tx_switching_flg = num_vfs_param ? 1 : 0;
153 edev->ops->vport_update(edev->cdev, &params);
154 }
155
156 return rc;
fefb0202
YM		 157}
158#endif
159
e712d52b
YM		 160static struct pci_driver qede_pci_driver = {
161 .name = "qede",
162 .id_table = qede_pci_tbl,
163 .probe = qede_probe,
164 .remove = qede_remove,
fefb0202
YM		 165#ifdef CONFIG_QED_SRIOV
166 .sriov_configure = qede_sriov_configure,
167#endif
e712d52b
YM		 168};
169
eff16960
YM		 170static void qede_force_mac(void *dev, u8 *mac)
171{
172 struct qede_dev *edev = dev;
173
174 ether_addr_copy(edev->ndev->dev_addr, mac);
175 ether_addr_copy(edev->primary_mac, mac);
176}
177
a2ec6172
SK		 178static struct qed_eth_cb_ops qede_ll_ops = {
179 {
180 .link_update = qede_link_update,
181 },
eff16960 182 .force_mac = qede_force_mac,
a2ec6172
SK		 183};
184
2950219d
YM		 185static int qede_netdev_event(struct notifier_block *this, unsigned long event,
186 void *ptr)
187{
188 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
189 struct ethtool_drvinfo drvinfo;
190 struct qede_dev *edev;
191
192 /* Currently only support name change */
193 if (event != NETDEV_CHANGENAME)
194 goto done;
195
196 /* Check whether this is a qede device */
197 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
198 goto done;
199
200 memset(&drvinfo, 0, sizeof(drvinfo));
201 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
202 if (strcmp(drvinfo.driver, "qede"))
203 goto done;
204 edev = netdev_priv(ndev);
205
206 /* Notify qed of the name change */
207 if (!edev->ops || !edev->ops->common)
208 goto done;
209 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
210 "qede");
211
212done:
213 return NOTIFY_DONE;
214}
215
216static struct notifier_block qede_netdev_notifier = {
217 .notifier_call = qede_netdev_event,
218};
219
e712d52b
YM		 220static
221int __init qede_init(void)
222{
223 int ret;
e712d52b 224
525ef5c0 225 pr_info("qede_init: %s\n", version);
e712d52b 226
95114344 227 qed_ops = qed_get_eth_ops();
e712d52b
YM		 228 if (!qed_ops) {
229 pr_notice("Failed to get qed ethtool operations\n");
230 return -EINVAL;
231 }
232
2950219d
YM		 233 /* Must register notifier before pci ops, since we might miss
234 * interface rename after pci probe and netdev registeration.
235 */
236 ret = register_netdevice_notifier(&qede_netdev_notifier);
237 if (ret) {
238 pr_notice("Failed to register netdevice_notifier\n");
239 qed_put_eth_ops();
240 return -EINVAL;
241 }
242
e712d52b
YM		 243 ret = pci_register_driver(&qede_pci_driver);
244 if (ret) {
245 pr_notice("Failed to register driver\n");
2950219d 246 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 247 qed_put_eth_ops();
248 return -EINVAL;
249 }
250
251 return 0;
252}
253
254static void __exit qede_cleanup(void)
255{
525ef5c0
YM		 256 if (debug & QED_LOG_INFO_MASK)
257 pr_info("qede_cleanup called\n");
e712d52b 258
2950219d 259 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 260 pci_unregister_driver(&qede_pci_driver);
261 qed_put_eth_ops();
262}
263
264module_init(qede_init);
265module_exit(qede_cleanup);
266
2950219d
YM		 267/* -------------------------------------------------------------------------
268 * START OF FAST-PATH
269 * -------------------------------------------------------------------------
270 */
271
272/* Unmap the data and free skb */
273static int qede_free_tx_pkt(struct qede_dev *edev,
1a635e48 274 struct qede_tx_queue *txq, int *len)
2950219d
YM		 275{
276 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
277 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
278 struct eth_tx_1st_bd *first_bd;
279 struct eth_tx_bd *tx_data_bd;
280 int bds_consumed = 0;
281 int nbds;
282 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
283 int i, split_bd_len = 0;
284
285 if (unlikely(!skb)) {
286 DP_ERR(edev,
287 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
288 idx, txq->sw_tx_cons, txq->sw_tx_prod);
289 return -1;
290 }
291
292 *len = skb->len;
293
294 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
295
296 bds_consumed++;
297
298 nbds = first_bd->data.nbds;
299
300 if (data_split) {
301 struct eth_tx_bd *split = (struct eth_tx_bd *)
302 qed_chain_consume(&txq->tx_pbl);
303 split_bd_len = BD_UNMAP_LEN(split);
304 bds_consumed++;
305 }
306 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
307 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
308
309 /* Unmap the data of the skb frags */
310 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
311 tx_data_bd = (struct eth_tx_bd *)
312 qed_chain_consume(&txq->tx_pbl);
313 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
314 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
315 }
316
317 while (bds_consumed++ < nbds)
318 qed_chain_consume(&txq->tx_pbl);
319
320 /* Free skb */
321 dev_kfree_skb_any(skb);
322 txq->sw_tx_ring[idx].skb = NULL;
323 txq->sw_tx_ring[idx].flags = 0;
324
325 return 0;
326}
327
328/* Unmap the data and free skb when mapping failed during start_xmit */
329static void qede_free_failed_tx_pkt(struct qede_dev *edev,
330 struct qede_tx_queue *txq,
331 struct eth_tx_1st_bd *first_bd,
1a635e48 332 int nbd, bool data_split)
2950219d
YM		 333{
334 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
335 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
336 struct eth_tx_bd *tx_data_bd;
337 int i, split_bd_len = 0;
338
339 /* Return prod to its position before this skb was handled */
340 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 341 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 342
343 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
344
345 if (data_split) {
346 struct eth_tx_bd *split = (struct eth_tx_bd *)
347 qed_chain_produce(&txq->tx_pbl);
348 split_bd_len = BD_UNMAP_LEN(split);
349 nbd--;
350 }
351
352 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
353 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
354
355 /* Unmap the data of the skb frags */
356 for (i = 0; i < nbd; i++) {
357 tx_data_bd = (struct eth_tx_bd *)
358 qed_chain_produce(&txq->tx_pbl);
359 if (tx_data_bd->nbytes)
360 dma_unmap_page(&edev->pdev->dev,
361 BD_UNMAP_ADDR(tx_data_bd),
362 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
363 }
364
365 /* Return again prod to its position before this skb was handled */
366 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 367 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 368
369 /* Free skb */
370 dev_kfree_skb_any(skb);
371 txq->sw_tx_ring[idx].skb = NULL;
372 txq->sw_tx_ring[idx].flags = 0;
373}
374
375static u32 qede_xmit_type(struct qede_dev *edev,
1a635e48 376 struct sk_buff *skb, int *ipv6_ext)
2950219d
YM		 377{
378 u32 rc = XMIT_L4_CSUM;
379 __be16 l3_proto;
380
381 if (skb->ip_summed != CHECKSUM_PARTIAL)
382 return XMIT_PLAIN;
383
384 l3_proto = vlan_get_protocol(skb);
385 if (l3_proto == htons(ETH_P_IPV6) &&
386 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
387 *ipv6_ext = 1;
388
14db81de
MC		 389 if (skb->encapsulation)
390 rc |= XMIT_ENC;
391
2950219d
YM		 392 if (skb_is_gso(skb))
393 rc |= XMIT_LSO;
394
395 return rc;
396}
397
398static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
399 struct eth_tx_2nd_bd *second_bd,
400 struct eth_tx_3rd_bd *third_bd)
401{
402 u8 l4_proto;
fc48b7a6 403 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 404
fc48b7a6 405 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 406
fc48b7a6 407 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 408 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
409 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
410
fc48b7a6 411 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 412 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
413
414 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
415 l4_proto = ipv6_hdr(skb)->nexthdr;
416 else
417 l4_proto = ip_hdr(skb)->protocol;
418
419 if (l4_proto == IPPROTO_UDP)
fc48b7a6 420 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 421
fc48b7a6 422 if (third_bd)
2950219d 423 third_bd->data.bitfields |=
fc48b7a6
YM		 424 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
425 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
426 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 427
fc48b7a6 428 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 429 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
430}
431
432static int map_frag_to_bd(struct qede_dev *edev,
1a635e48 433 skb_frag_t *frag, struct eth_tx_bd *bd)
2950219d
YM		 434{
435 dma_addr_t mapping;
436
437 /* Map skb non-linear frag data for DMA */
438 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
1a635e48 439 skb_frag_size(frag), DMA_TO_DEVICE);
2950219d
YM		 440 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
441 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
442 return -ENOMEM;
443 }
444
445 /* Setup the data pointer of the frag data */
446 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
447
448 return 0;
449}
450
14db81de
MC		 451static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
452{
453 if (is_encap_pkt)
454 return (skb_inner_transport_header(skb) +
455 inner_tcp_hdrlen(skb) - skb->data);
456 else
457 return (skb_transport_header(skb) +
458 tcp_hdrlen(skb) - skb->data);
459}
460
b1199b10
YM		 461/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
462#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
463static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
464 u8 xmit_type)
465{
466 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
467
468 if (xmit_type & XMIT_LSO) {
469 int hlen;
470
14db81de 471 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 472
473 /* linear payload would require its own BD */
474 if (skb_headlen(skb) > hlen)
475 allowed_frags--;
476 }
477
478 return (skb_shinfo(skb)->nr_frags > allowed_frags);
479}
480#endif
481
312e0676
MC		 482static inline void qede_update_tx_producer(struct qede_tx_queue *txq)
483{
484 /* wmb makes sure that the BDs data is updated before updating the
485 * producer, otherwise FW may read old data from the BDs.
486 */
487 wmb();
488 barrier();
489 writel(txq->tx_db.raw, txq->doorbell_addr);
490
491 /* mmiowb is needed to synchronize doorbell writes from more than one
492 * processor. It guarantees that the write arrives to the device before
493 * the queue lock is released and another start_xmit is called (possibly
494 * on another CPU). Without this barrier, the next doorbell can bypass
495 * this doorbell. This is applicable to IA64/Altix systems.
496 */
497 mmiowb();
498}
499
2950219d 500/* Main transmit function */
1a635e48
YM		 501static netdev_tx_t qede_start_xmit(struct sk_buff *skb,
502 struct net_device *ndev)
2950219d
YM		 503{
504 struct qede_dev *edev = netdev_priv(ndev);
505 struct netdev_queue *netdev_txq;
506 struct qede_tx_queue *txq;
507 struct eth_tx_1st_bd *first_bd;
508 struct eth_tx_2nd_bd *second_bd = NULL;
509 struct eth_tx_3rd_bd *third_bd = NULL;
510 struct eth_tx_bd *tx_data_bd = NULL;
511 u16 txq_index;
512 u8 nbd = 0;
513 dma_addr_t mapping;
514 int rc, frag_idx = 0, ipv6_ext = 0;
515 u8 xmit_type;
516 u16 idx;
517 u16 hlen;
810810ff 518 bool data_split = false;
2950219d
YM		 519
520 /* Get tx-queue context and netdev index */
521 txq_index = skb_get_queue_mapping(skb);
522 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
523 txq = QEDE_TX_QUEUE(edev, txq_index);
524 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
525
1a635e48 526 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) < (MAX_SKB_FRAGS + 1));
2950219d
YM		 527
528 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
529
b1199b10
YM		 530#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
531 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
532 if (skb_linearize(skb)) {
533 DP_NOTICE(edev,
534 "SKB linearization failed - silently dropping this SKB\n");
535 dev_kfree_skb_any(skb);
536 return NETDEV_TX_OK;
537 }
538 }
539#endif
540
2950219d
YM		 541 /* Fill the entry in the SW ring and the BDs in the FW ring */
542 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
543 txq->sw_tx_ring[idx].skb = skb;
544 first_bd = (struct eth_tx_1st_bd *)
545 qed_chain_produce(&txq->tx_pbl);
546 memset(first_bd, 0, sizeof(*first_bd));
547 first_bd->data.bd_flags.bitfields =
548 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
549
550 /* Map skb linear data for DMA and set in the first BD */
551 mapping = dma_map_single(&edev->pdev->dev, skb->data,
552 skb_headlen(skb), DMA_TO_DEVICE);
553 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
554 DP_NOTICE(edev, "SKB mapping failed\n");
555 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
312e0676 556 qede_update_tx_producer(txq);
2950219d
YM		 557 return NETDEV_TX_OK;
558 }
559 nbd++;
560 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
561
562 /* In case there is IPv6 with extension headers or LSO we need 2nd and
563 * 3rd BDs.
564 */
565 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
566 second_bd = (struct eth_tx_2nd_bd *)
567 qed_chain_produce(&txq->tx_pbl);
568 memset(second_bd, 0, sizeof(*second_bd));
569
570 nbd++;
571 third_bd = (struct eth_tx_3rd_bd *)
572 qed_chain_produce(&txq->tx_pbl);
573 memset(third_bd, 0, sizeof(*third_bd));
574
575 nbd++;
576 /* We need to fill in additional data in second_bd... */
577 tx_data_bd = (struct eth_tx_bd *)second_bd;
578 }
579
580 if (skb_vlan_tag_present(skb)) {
581 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
582 first_bd->data.bd_flags.bitfields |=
583 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
584 }
585
586 /* Fill the parsing flags & params according to the requested offload */
587 if (xmit_type & XMIT_L4_CSUM) {
588 /* We don't re-calculate IP checksum as it is already done by
589 * the upper stack
590 */
591 first_bd->data.bd_flags.bitfields |=
592 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
593
14db81de
MC		 594 if (xmit_type & XMIT_ENC) {
595 first_bd->data.bd_flags.bitfields |=
596 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
351a4ded
YM		 597 first_bd->data.bitfields |=
598 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
14db81de 599 }
fc48b7a6 600
2950219d
YM		 601 /* If the packet is IPv6 with extension header, indicate that
602 * to FW and pass few params, since the device cracker doesn't
603 * support parsing IPv6 with extension header/s.
604 */
605 if (unlikely(ipv6_ext))
606 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
607 }
608
609 if (xmit_type & XMIT_LSO) {
610 first_bd->data.bd_flags.bitfields |=
611 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
612 third_bd->data.lso_mss =
613 cpu_to_le16(skb_shinfo(skb)->gso_size);
614
14db81de
MC		 615 if (unlikely(xmit_type & XMIT_ENC)) {
616 first_bd->data.bd_flags.bitfields |=
617 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
618 hlen = qede_get_skb_hlen(skb, true);
619 } else {
620 first_bd->data.bd_flags.bitfields |=
621 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
622 hlen = qede_get_skb_hlen(skb, false);
623 }
2950219d
YM		 624
625 /* @@@TBD - if will not be removed need to check */
626 third_bd->data.bitfields |=
fc48b7a6 627 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 628
629 /* Make life easier for FW guys who can't deal with header and
630 * data on same BD. If we need to split, use the second bd...
631 */
632 if (unlikely(skb_headlen(skb) > hlen)) {
633 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
634 "TSO split header size is %d (%x:%x)\n",
635 first_bd->nbytes, first_bd->addr.hi,
636 first_bd->addr.lo);
637
638 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
639 le32_to_cpu(first_bd->addr.lo)) +
640 hlen;
641
642 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
643 le16_to_cpu(first_bd->nbytes) -
644 hlen);
645
646 /* this marks the BD as one that has no
647 * individual mapping
648 */
649 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
650
651 first_bd->nbytes = cpu_to_le16(hlen);
652
653 tx_data_bd = (struct eth_tx_bd *)third_bd;
654 data_split = true;
655 }
351a4ded
YM		 656 } else {
657 first_bd->data.bitfields |=
658 (skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) <<
659 ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2950219d
YM		 660 }
661
662 /* Handle fragmented skb */
663 /* special handle for frags inside 2nd and 3rd bds.. */
664 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
665 rc = map_frag_to_bd(edev,
666 &skb_shinfo(skb)->frags[frag_idx],
667 tx_data_bd);
668 if (rc) {
669 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
670 data_split);
312e0676 671 qede_update_tx_producer(txq);
2950219d
YM		 672 return NETDEV_TX_OK;
673 }
674
675 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
676 tx_data_bd = (struct eth_tx_bd *)third_bd;
677 else
678 tx_data_bd = NULL;
679
680 frag_idx++;
681 }
682
683 /* map last frags into 4th, 5th .... */
684 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
685 tx_data_bd = (struct eth_tx_bd *)
686 qed_chain_produce(&txq->tx_pbl);
687
688 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
689
690 rc = map_frag_to_bd(edev,
691 &skb_shinfo(skb)->frags[frag_idx],
692 tx_data_bd);
693 if (rc) {
694 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
695 data_split);
312e0676 696 qede_update_tx_producer(txq);
2950219d
YM		 697 return NETDEV_TX_OK;
698 }
699 }
700
701 /* update the first BD with the actual num BDs */
702 first_bd->data.nbds = nbd;
703
704 netdev_tx_sent_queue(netdev_txq, skb->len);
705
706 skb_tx_timestamp(skb);
707
708 /* Advance packet producer only before sending the packet since mapping
709 * of pages may fail.
710 */
711 txq->sw_tx_prod++;
712
713 /* 'next page' entries are counted in the producer value */
714 txq->tx_db.data.bd_prod =
715 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
716
312e0676
MC		 717 if (!skb->xmit_more || netif_tx_queue_stopped(netdev_txq))
718 qede_update_tx_producer(txq);
2950219d
YM		 719
720 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
721 < (MAX_SKB_FRAGS + 1))) {
722 netif_tx_stop_queue(netdev_txq);
723 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
724 "Stop queue was called\n");
725 /* paired memory barrier is in qede_tx_int(), we have to keep
726 * ordering of set_bit() in netif_tx_stop_queue() and read of
727 * fp->bd_tx_cons
728 */
729 smp_mb();
730
731 if (qed_chain_get_elem_left(&txq->tx_pbl)
732 >= (MAX_SKB_FRAGS + 1) &&
733 (edev->state == QEDE_STATE_OPEN)) {
734 netif_tx_wake_queue(netdev_txq);
735 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
736 "Wake queue was called\n");
737 }
738 }
739
740 return NETDEV_TX_OK;
741}
742
16f46bf0 743int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 744{
745 u16 hw_bd_cons;
746
747 /* Tell compiler that consumer and producer can change */
748 barrier();
749 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
750 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
751 return 0;
752
753 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
754}
755
1a635e48 756static int qede_tx_int(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 757{
758 struct netdev_queue *netdev_txq;
759 u16 hw_bd_cons;
760 unsigned int pkts_compl = 0, bytes_compl = 0;
761 int rc;
762
763 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
764
765 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
766 barrier();
767
768 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
769 int len = 0;
770
771 rc = qede_free_tx_pkt(edev, txq, &len);
772 if (rc) {
773 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
774 hw_bd_cons,
775 qed_chain_get_cons_idx(&txq->tx_pbl));
776 break;
777 }
778
779 bytes_compl += len;
780 pkts_compl++;
781 txq->sw_tx_cons++;
782 }
783
784 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
785
786 /* Need to make the tx_bd_cons update visible to start_xmit()
787 * before checking for netif_tx_queue_stopped(). Without the
788 * memory barrier, there is a small possibility that
789 * start_xmit() will miss it and cause the queue to be stopped
790 * forever.
791 * On the other hand we need an rmb() here to ensure the proper
792 * ordering of bit testing in the following
793 * netif_tx_queue_stopped(txq) call.
794 */
795 smp_mb();
796
797 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
798 /* Taking tx_lock is needed to prevent reenabling the queue
799 * while it's empty. This could have happen if rx_action() gets
800 * suspended in qede_tx_int() after the condition before
801 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
802 *
803 * stops the queue->sees fresh tx_bd_cons->releases the queue->
804 * sends some packets consuming the whole queue again->
805 * stops the queue
806 */
807
808 __netif_tx_lock(netdev_txq, smp_processor_id());
809
810 if ((netif_tx_queue_stopped(netdev_txq)) &&
811 (edev->state == QEDE_STATE_OPEN) &&
812 (qed_chain_get_elem_left(&txq->tx_pbl)
813 >= (MAX_SKB_FRAGS + 1))) {
814 netif_tx_wake_queue(netdev_txq);
815 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
816 "Wake queue was called\n");
817 }
818
819 __netif_tx_unlock(netdev_txq);
820 }
821
822 return 0;
823}
824
16f46bf0 825bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 826{
827 u16 hw_comp_cons, sw_comp_cons;
828
829 /* Tell compiler that status block fields can change */
830 barrier();
831
832 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
833 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
834
835 return hw_comp_cons != sw_comp_cons;
836}
837
838static bool qede_has_tx_work(struct qede_fastpath *fp)
839{
840 u8 tc;
841
842 for (tc = 0; tc < fp->edev->num_tc; tc++)
843 if (qede_txq_has_work(&fp->txqs[tc]))
844 return true;
845 return false;
846}
847
f86af2df
MC		 848static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
849{
850 qed_chain_consume(&rxq->rx_bd_ring);
851 rxq->sw_rx_cons++;
852}
853
fc48b7a6
YM		 854/* This function reuses the buffer(from an offset) from
855 * consumer index to producer index in the bd ring
2950219d 856 */
fc48b7a6
YM		 857static inline void qede_reuse_page(struct qede_dev *edev,
858 struct qede_rx_queue *rxq,
859 struct sw_rx_data *curr_cons)
2950219d 860{
2950219d 861 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 862 struct sw_rx_data *curr_prod;
863 dma_addr_t new_mapping;
2950219d 864
fc48b7a6
YM		 865 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
866 *curr_prod = *curr_cons;
2950219d 867
fc48b7a6
YM		 868 new_mapping = curr_prod->mapping + curr_prod->page_offset;
869
870 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
871 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 872
2950219d 873 rxq->sw_rx_prod++;
fc48b7a6
YM		 874 curr_cons->data = NULL;
875}
876
f86af2df
MC		 877/* In case of allocation failures reuse buffers
878 * from consumer index to produce buffers for firmware
879 */
16f46bf0
SRK		 880void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
881 struct qede_dev *edev, u8 count)
f86af2df
MC		 882{
883 struct sw_rx_data *curr_cons;
884
885 for (; count > 0; count--) {
886 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
887 qede_reuse_page(edev, rxq, curr_cons);
888 qede_rx_bd_ring_consume(rxq);
889 }
890}
891
fc48b7a6
YM		 892static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
893 struct qede_rx_queue *rxq,
894 struct sw_rx_data *curr_cons)
895{
896 /* Move to the next segment in the page */
897 curr_cons->page_offset += rxq->rx_buf_seg_size;
898
899 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 900 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
901 /* Since we failed to allocate new buffer
902 * current buffer can be used again.
903 */
904 curr_cons->page_offset -= rxq->rx_buf_seg_size;
905
fc48b7a6 906 return -ENOMEM;
f86af2df 907 }
fc48b7a6
YM		 908
909 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
910 PAGE_SIZE, DMA_FROM_DEVICE);
911 } else {
912 /* Increment refcount of the page as we don't want
913 * network stack to take the ownership of the page
914 * which can be recycled multiple times by the driver.
915 */
6d061f9f 916 page_ref_inc(curr_cons->data);
fc48b7a6
YM		 917 qede_reuse_page(edev, rxq, curr_cons);
918 }
919
920 return 0;
2950219d
YM		 921}
922
923static inline void qede_update_rx_prod(struct qede_dev *edev,
924 struct qede_rx_queue *rxq)
925{
926 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
927 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
928 struct eth_rx_prod_data rx_prods = {0};
929
930 /* Update producers */
931 rx_prods.bd_prod = cpu_to_le16(bd_prod);
932 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
933
934 /* Make sure that the BD and SGE data is updated before updating the
935 * producers since FW might read the BD/SGE right after the producer
936 * is updated.
937 */
938 wmb();
939
940 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
941 (u32 *)&rx_prods);
942
943 /* mmiowb is needed to synchronize doorbell writes from more than one
944 * processor. It guarantees that the write arrives to the device before
945 * the napi lock is released and another qede_poll is called (possibly
946 * on another CPU). Without this barrier, the next doorbell can bypass
947 * this doorbell. This is applicable to IA64/Altix systems.
948 */
949 mmiowb();
950}
951
952static u32 qede_get_rxhash(struct qede_dev *edev,
953 u8 bitfields,
1a635e48 954 __le32 rss_hash, enum pkt_hash_types *rxhash_type)
2950219d
YM		 955{
956 enum rss_hash_type htype;
957
958 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
959
960 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
961 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
962 (htype == RSS_HASH_TYPE_IPV6)) ?
963 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
964 return le32_to_cpu(rss_hash);
965 }
966 *rxhash_type = PKT_HASH_TYPE_NONE;
967 return 0;
968}
969
970static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
971{
972 skb_checksum_none_assert(skb);
973
974 if (csum_flag & QEDE_CSUM_UNNECESSARY)
975 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 976
977 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
978 skb->csum_level = 1;
2950219d
YM		 979}
980
981static inline void qede_skb_receive(struct qede_dev *edev,
982 struct qede_fastpath *fp,
1a635e48 983 struct sk_buff *skb, u16 vlan_tag)
2950219d
YM		 984{
985 if (vlan_tag)
1a635e48 986 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
2950219d
YM		 987
988 napi_gro_receive(&fp->napi, skb);
989}
990
55482edc
MC		 991static void qede_set_gro_params(struct qede_dev *edev,
992 struct sk_buff *skb,
993 struct eth_fast_path_rx_tpa_start_cqe *cqe)
994{
995 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
996
997 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
998 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
999 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
1000 else
1001 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1002
1003 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
1004 cqe->header_len;
1005}
1006
1007static int qede_fill_frag_skb(struct qede_dev *edev,
1008 struct qede_rx_queue *rxq,
1a635e48 1009 u8 tpa_agg_index, u16 len_on_bd)
55482edc
MC		 1010{
1011 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
1012 NUM_RX_BDS_MAX];
1013 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
1014 struct sk_buff *skb = tpa_info->skb;
1015
1016 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1017 goto out;
1018
1019 /* Add one frag and update the appropriate fields in the skb */
1020 skb_fill_page_desc(skb, tpa_info->frag_id++,
1021 current_bd->data, current_bd->page_offset,
1022 len_on_bd);
1023
1024 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 1025 /* Incr page ref count to reuse on allocation failure
1026 * so that it doesn't get freed while freeing SKB.
1027 */
0139aa7b 1028 page_ref_inc(current_bd->data);
55482edc
MC		 1029 goto out;
1030 }
1031
1032 qed_chain_consume(&rxq->rx_bd_ring);
1033 rxq->sw_rx_cons++;
1034
1035 skb->data_len += len_on_bd;
1036 skb->truesize += rxq->rx_buf_seg_size;
1037 skb->len += len_on_bd;
1038
1039 return 0;
1040
1041out:
f86af2df
MC		 1042 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1043 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1044 return -ENOMEM;
1045}
1046
1047static void qede_tpa_start(struct qede_dev *edev,
1048 struct qede_rx_queue *rxq,
1049 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1050{
1051 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1052 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1053 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
1054 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
1055 dma_addr_t mapping = tpa_info->replace_buf_mapping;
1056 struct sw_rx_data *sw_rx_data_cons;
1057 struct sw_rx_data *sw_rx_data_prod;
1058 enum pkt_hash_types rxhash_type;
1059 u32 rxhash;
1060
1061 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1062 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1063
1064 /* Use pre-allocated replacement buffer - we can't release the agg.
1065 * start until its over and we don't want to risk allocation failing
1066 * here, so re-allocate when aggregation will be over.
1067 */
09ec8e7f 1068 sw_rx_data_prod->mapping = replace_buf->mapping;
55482edc
MC		 1069
1070 sw_rx_data_prod->data = replace_buf->data;
1071 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1072 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1073 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1074
1075 rxq->sw_rx_prod++;
1076
1077 /* move partial skb from cons to pool (don't unmap yet)
1078 * save mapping, incase we drop the packet later on.
1079 */
1080 tpa_info->start_buf = *sw_rx_data_cons;
1081 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1082 le32_to_cpu(rx_bd_cons->addr.lo));
1083
1084 tpa_info->start_buf_mapping = mapping;
1085 rxq->sw_rx_cons++;
1086
1087 /* set tpa state to start only if we are able to allocate skb
1088 * for this aggregation, otherwise mark as error and aggregation will
1089 * be dropped
1090 */
1091 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1092 le16_to_cpu(cqe->len_on_first_bd));
1093 if (unlikely(!tpa_info->skb)) {
f86af2df 1094 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1095 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1096 goto cons_buf;
55482edc
MC		 1097 }
1098
1099 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1100 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1101
1102 /* Start filling in the aggregation info */
1103 tpa_info->frag_id = 0;
1104 tpa_info->agg_state = QEDE_AGG_STATE_START;
1105
1106 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1107 cqe->rss_hash, &rxhash_type);
1108 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1109 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1110 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1111 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1112 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1113 else
1114 tpa_info->vlan_tag = 0;
1115
1116 /* This is needed in order to enable forwarding support */
1117 qede_set_gro_params(edev, tpa_info->skb, cqe);
1118
f86af2df 1119cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1120 if (likely(cqe->ext_bd_len_list[0]))
1121 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1122 le16_to_cpu(cqe->ext_bd_len_list[0]));
1123
1124 if (unlikely(cqe->ext_bd_len_list[1])) {
1125 DP_ERR(edev,
1126 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1127 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1128 }
1129}
1130
88f09bd5 1131#ifdef CONFIG_INET
55482edc
MC		 1132static void qede_gro_ip_csum(struct sk_buff *skb)
1133{
1134 const struct iphdr *iph = ip_hdr(skb);
1135 struct tcphdr *th;
1136
55482edc
MC		 1137 skb_set_transport_header(skb, sizeof(struct iphdr));
1138 th = tcp_hdr(skb);
1139
1140 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1141 iph->saddr, iph->daddr, 0);
1142
1143 tcp_gro_complete(skb);
1144}
1145
1146static void qede_gro_ipv6_csum(struct sk_buff *skb)
1147{
1148 struct ipv6hdr *iph = ipv6_hdr(skb);
1149 struct tcphdr *th;
1150
55482edc
MC		 1151 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1152 th = tcp_hdr(skb);
1153
1154 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1155 &iph->saddr, &iph->daddr, 0);
1156 tcp_gro_complete(skb);
1157}
88f09bd5 1158#endif
55482edc
MC		 1159
1160static void qede_gro_receive(struct qede_dev *edev,
1161 struct qede_fastpath *fp,
1162 struct sk_buff *skb,
1163 u16 vlan_tag)
1164{
ee2fa8e6
MC		 1165 /* FW can send a single MTU sized packet from gro flow
1166 * due to aggregation timeout/last segment etc. which
1167 * is not expected to be a gro packet. If a skb has zero
1168 * frags then simply push it in the stack as non gso skb.
1169 */
1170 if (unlikely(!skb->data_len)) {
1171 skb_shinfo(skb)->gso_type = 0;
1172 skb_shinfo(skb)->gso_size = 0;
1173 goto send_skb;
1174 }
1175
88f09bd5 1176#ifdef CONFIG_INET
55482edc 1177 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1178 skb_set_network_header(skb, 0);
1179
55482edc
MC		 1180 switch (skb->protocol) {
1181 case htons(ETH_P_IP):
1182 qede_gro_ip_csum(skb);
1183 break;
1184 case htons(ETH_P_IPV6):
1185 qede_gro_ipv6_csum(skb);
1186 break;
1187 default:
1188 DP_ERR(edev,
1189 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1190 ntohs(skb->protocol));
1191 }
1192 }
88f09bd5 1193#endif
ee2fa8e6
MC		 1194
1195send_skb:
55482edc
MC		 1196 skb_record_rx_queue(skb, fp->rss_id);
1197 qede_skb_receive(edev, fp, skb, vlan_tag);
1198}
1199
1200static inline void qede_tpa_cont(struct qede_dev *edev,
1201 struct qede_rx_queue *rxq,
1202 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1203{
1204 int i;
1205
1206 for (i = 0; cqe->len_list[i]; i++)
1207 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1208 le16_to_cpu(cqe->len_list[i]));
1209
1210 if (unlikely(i > 1))
1211 DP_ERR(edev,
1212 "Strange - TPA cont with more than a single len_list entry\n");
1213}
1214
1215static void qede_tpa_end(struct qede_dev *edev,
1216 struct qede_fastpath *fp,
1217 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1218{
1219 struct qede_rx_queue *rxq = fp->rxq;
1220 struct qede_agg_info *tpa_info;
1221 struct sk_buff *skb;
1222 int i;
1223
1224 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1225 skb = tpa_info->skb;
1226
1227 for (i = 0; cqe->len_list[i]; i++)
1228 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1229 le16_to_cpu(cqe->len_list[i]));
1230 if (unlikely(i > 1))
1231 DP_ERR(edev,
1232 "Strange - TPA emd with more than a single len_list entry\n");
1233
1234 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1235 goto err;
1236
1237 /* Sanity */
1238 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1239 DP_ERR(edev,
1240 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1241 cqe->num_of_bds, tpa_info->frag_id);
1242 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1243 DP_ERR(edev,
1244 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1245 le16_to_cpu(cqe->total_packet_len), skb->len);
1246
1247 memcpy(skb->data,
1248 page_address(tpa_info->start_buf.data) +
1249 tpa_info->start_cqe.placement_offset +
1250 tpa_info->start_buf.page_offset,
1251 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1252
1253 /* Recycle [mapped] start buffer for the next replacement */
1254 tpa_info->replace_buf = tpa_info->start_buf;
1255 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1256
1257 /* Finalize the SKB */
1258 skb->protocol = eth_type_trans(skb, edev->ndev);
1259 skb->ip_summed = CHECKSUM_UNNECESSARY;
1260
1261 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1262 * to skb_shinfo(skb)->gso_segs
1263 */
1264 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1265
1266 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1267
1268 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1269
1270 return;
1271err:
1272 /* The BD starting the aggregation is still mapped; Re-use it for
1273 * future aggregations [as replacement buffer]
1274 */
1275 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1276 sizeof(struct sw_rx_data));
1277 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1278 tpa_info->start_buf.data = NULL;
1279 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1280 dev_kfree_skb_any(tpa_info->skb);
1281 tpa_info->skb = NULL;
1282}
1283
14db81de
MC		 1284static bool qede_tunn_exist(u16 flag)
1285{
1286 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1287 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1288}
1289
1290static u8 qede_check_tunn_csum(u16 flag)
1291{
1292 u16 csum_flag = 0;
1293 u8 tcsum = 0;
1294
1295 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1296 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1297 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1298 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1299
1300 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1301 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1302 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1303 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1304 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1305 }
1306
1307 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1308 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1309 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1310 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1311
1312 if (csum_flag & flag)
1313 return QEDE_CSUM_ERROR;
1314
1315 return QEDE_CSUM_UNNECESSARY | tcsum;
1316}
1317
1318static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1319{
1320 u16 csum_flag = 0;
1321 u8 csum = 0;
1322
14db81de
MC		 1323 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1324 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1325 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1326 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1327 csum = QEDE_CSUM_UNNECESSARY;
1328 }
1329
1330 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1331 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1332
1333 if (csum_flag & flag)
1334 return QEDE_CSUM_ERROR;
1335
1336 return csum;
1337}
1338
14db81de
MC		 1339static u8 qede_check_csum(u16 flag)
1340{
1341 if (!qede_tunn_exist(flag))
1342 return qede_check_notunn_csum(flag);
1343 else
1344 return qede_check_tunn_csum(flag);
1345}
1346
c72a6125
MC		 1347static bool qede_pkt_is_ip_fragmented(struct eth_fast_path_rx_reg_cqe *cqe,
1348 u16 flag)
1349{
1350 u8 tun_pars_flg = cqe->tunnel_pars_flags.flags;
1351
1352 if ((tun_pars_flg & (ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK <<
1353 ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT)) ||
1354 (flag & (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1355 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT)))
1356 return true;
1357
1358 return false;
1359}
1360
2950219d
YM		 1361static int qede_rx_int(struct qede_fastpath *fp, int budget)
1362{
1363 struct qede_dev *edev = fp->edev;
1364 struct qede_rx_queue *rxq = fp->rxq;
1365
1366 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1367 int rx_pkt = 0;
1368 u8 csum_flag;
1369
1370 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1371 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1372
1373 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1374 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1375 * read before it is written by FW, then FW writes CQE and SB, and then
1376 * the CPU reads the hw_comp_cons, it will use an old CQE.
1377 */
1378 rmb();
1379
1380 /* Loop to complete all indicated BDs */
1381 while (sw_comp_cons != hw_comp_cons) {
1382 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1383 enum pkt_hash_types rxhash_type;
1384 enum eth_rx_cqe_type cqe_type;
1385 struct sw_rx_data *sw_rx_data;
1386 union eth_rx_cqe *cqe;
1387 struct sk_buff *skb;
fc48b7a6
YM		 1388 struct page *data;
1389 __le16 flags;
2950219d
YM		 1390 u16 len, pad;
1391 u32 rx_hash;
2950219d
YM		 1392
1393 /* Get the CQE from the completion ring */
1394 cqe = (union eth_rx_cqe *)
1395 qed_chain_consume(&rxq->rx_comp_ring);
1396 cqe_type = cqe->fast_path_regular.type;
1397
1398 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1399 edev->ops->eth_cqe_completion(
1400 edev->cdev, fp->rss_id,
1401 (struct eth_slow_path_rx_cqe *)cqe);
1402 goto next_cqe;
1403 }
1404
55482edc
MC		 1405 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1406 switch (cqe_type) {
1407 case ETH_RX_CQE_TYPE_TPA_START:
1408 qede_tpa_start(edev, rxq,
1409 &cqe->fast_path_tpa_start);
1410 goto next_cqe;
1411 case ETH_RX_CQE_TYPE_TPA_CONT:
1412 qede_tpa_cont(edev, rxq,
1413 &cqe->fast_path_tpa_cont);
1414 goto next_cqe;
1415 case ETH_RX_CQE_TYPE_TPA_END:
1416 qede_tpa_end(edev, fp,
1417 &cqe->fast_path_tpa_end);
1418 goto next_rx_only;
1419 default:
1420 break;
1421 }
1422 }
1423
2950219d
YM		 1424 /* Get the data from the SW ring */
1425 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1426 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1427 data = sw_rx_data->data;
1428
1429 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1430 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1431 pad = fp_cqe->placement_offset;
fc48b7a6 1432 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1433
fc48b7a6
YM		 1434 /* If this is an error packet then drop it */
1435 parse_flag = le16_to_cpu(flags);
2950219d 1436
fc48b7a6
YM		 1437 csum_flag = qede_check_csum(parse_flag);
1438 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
c72a6125
MC		 1439 if (qede_pkt_is_ip_fragmented(&cqe->fast_path_regular,
1440 parse_flag)) {
1441 rxq->rx_ip_frags++;
1442 goto alloc_skb;
1443 }
1444
fc48b7a6
YM		 1445 DP_NOTICE(edev,
1446 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1447 sw_comp_cons, parse_flag);
1448 rxq->rx_hw_errors++;
f86af2df
MC		 1449 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1450 goto next_cqe;
fc48b7a6 1451 }
2950219d 1452
c72a6125 1453alloc_skb:
fc48b7a6
YM		 1454 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1455 if (unlikely(!skb)) {
2950219d 1456 DP_NOTICE(edev,
525ef5c0 1457 "skb allocation failed, dropping incoming packet\n");
f86af2df 1458 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1459 rxq->rx_alloc_errors++;
f86af2df 1460 goto next_cqe;
fc48b7a6
YM		 1461 }
1462
1463 /* Copy data into SKB */
3d789994 1464 if (len + pad <= edev->rx_copybreak) {
fc48b7a6
YM		 1465 memcpy(skb_put(skb, len),
1466 page_address(data) + pad +
1467 sw_rx_data->page_offset, len);
1468 qede_reuse_page(edev, rxq, sw_rx_data);
1469 } else {
1470 struct skb_frag_struct *frag;
1471 unsigned int pull_len;
1472 unsigned char *va;
1473
1474 frag = &skb_shinfo(skb)->frags[0];
1475
1476 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1477 pad + sw_rx_data->page_offset,
1478 len, rxq->rx_buf_seg_size);
1479
1480 va = skb_frag_address(frag);
1481 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1482
1483 /* Align the pull_len to optimize memcpy */
1484 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1485
1486 skb_frag_size_sub(frag, pull_len);
1487 frag->page_offset += pull_len;
1488 skb->data_len -= pull_len;
1489 skb->tail += pull_len;
1490
1491 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1492 sw_rx_data))) {
1493 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1494 /* Incr page ref count to reuse on allocation
1495 * failure so that it doesn't get freed while
1496 * freeing SKB.
1497 */
1498
0139aa7b 1499 page_ref_inc(sw_rx_data->data);
fc48b7a6 1500 rxq->rx_alloc_errors++;
f86af2df
MC		 1501 qede_recycle_rx_bd_ring(rxq, edev,
1502 fp_cqe->bd_num);
1503 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1504 goto next_cqe;
1505 }
2950219d
YM		 1506 }
1507
f86af2df
MC		 1508 qede_rx_bd_ring_consume(rxq);
1509
fc48b7a6
YM		 1510 if (fp_cqe->bd_num != 1) {
1511 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1512 u8 num_frags;
1513
1514 pkt_len -= len;
1515
1516 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1517 num_frags--) {
1518 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1519 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1520 if (unlikely(!cur_size)) {
1521 DP_ERR(edev,
1522 "Still got %d BDs for mapping jumbo, but length became 0\n",
1523 num_frags);
1524 qede_recycle_rx_bd_ring(rxq, edev,
1525 num_frags);
1526 dev_kfree_skb_any(skb);
1527 goto next_cqe;
1528 }
fc48b7a6 1529
f86af2df
MC		 1530 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1531 qede_recycle_rx_bd_ring(rxq, edev,
1532 num_frags);
1533 dev_kfree_skb_any(skb);
fc48b7a6 1534 goto next_cqe;
f86af2df 1535 }
fc48b7a6 1536
fc48b7a6
YM		 1537 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1538 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1539 qede_rx_bd_ring_consume(rxq);
1540
fc48b7a6
YM		 1541 dma_unmap_page(&edev->pdev->dev,
1542 sw_rx_data->mapping,
1543 PAGE_SIZE, DMA_FROM_DEVICE);
1544
1545 skb_fill_page_desc(skb,
1546 skb_shinfo(skb)->nr_frags++,
1547 sw_rx_data->data, 0,
1548 cur_size);
1549
1550 skb->truesize += PAGE_SIZE;
1551 skb->data_len += cur_size;
1552 skb->len += cur_size;
1553 pkt_len -= cur_size;
1554 }
2950219d 1555
f86af2df 1556 if (unlikely(pkt_len))
fc48b7a6
YM		 1557 DP_ERR(edev,
1558 "Mapped all BDs of jumbo, but still have %d bytes\n",
1559 pkt_len);
1560 }
2950219d
YM		 1561
1562 skb->protocol = eth_type_trans(skb, edev->ndev);
1563
1564 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1a635e48 1565 fp_cqe->rss_hash, &rxhash_type);
2950219d
YM		 1566
1567 skb_set_hash(skb, rx_hash, rxhash_type);
1568
1569 qede_set_skb_csum(skb, csum_flag);
1570
1571 skb_record_rx_queue(skb, fp->rss_id);
1572
1573 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1574next_rx_only:
2950219d
YM		 1575 rx_pkt++;
1576
1577next_cqe: /* don't consume bd rx buffer */
1578 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1579 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1580 /* CR TPA - revisit how to handle budget in TPA perhaps
1581 * increase on "end"
1582 */
1583 if (rx_pkt == budget)
1584 break;
1585 } /* repeat while sw_comp_cons != hw_comp_cons... */
1586
1587 /* Update producers */
1588 qede_update_rx_prod(edev, rxq);
1589
1590 return rx_pkt;
1591}
1592
1593static int qede_poll(struct napi_struct *napi, int budget)
1594{
2950219d 1595 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
c774169d 1596 napi);
2950219d 1597 struct qede_dev *edev = fp->edev;
c774169d
MC		 1598 int rx_work_done = 0;
1599 u8 tc;
2950219d 1600
c774169d
MC		 1601 for (tc = 0; tc < edev->num_tc; tc++)
1602 if (qede_txq_has_work(&fp->txqs[tc]))
1603 qede_tx_int(edev, &fp->txqs[tc]);
1604
1605 rx_work_done = qede_has_rx_work(fp->rxq) ?
1606 qede_rx_int(fp, budget) : 0;
1607 if (rx_work_done < budget) {
1608 qed_sb_update_sb_idx(fp->sb_info);
1609 /* *_has_*_work() reads the status block,
1610 * thus we need to ensure that status block indices
1611 * have been actually read (qed_sb_update_sb_idx)
1612 * prior to this check (*_has_*_work) so that
1613 * we won't write the "newer" value of the status block
1614 * to HW (if there was a DMA right after
1615 * qede_has_rx_work and if there is no rmb, the memory
1616 * reading (qed_sb_update_sb_idx) may be postponed
1617 * to right before *_ack_sb). In this case there
1618 * will never be another interrupt until there is
1619 * another update of the status block, while there
1620 * is still unhandled work.
1621 */
1622 rmb();
2950219d
YM		 1623
1624 /* Fall out from the NAPI loop if needed */
c774169d
MC		 1625 if (!(qede_has_rx_work(fp->rxq) ||
1626 qede_has_tx_work(fp))) {
1627 napi_complete(napi);
1628
1629 /* Update and reenable interrupts */
1630 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1631 1 /*update*/);
1632 } else {
1633 rx_work_done = budget;
2950219d
YM		 1634 }
1635 }
1636
c774169d 1637 return rx_work_done;
2950219d
YM		 1638}
1639
1640static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1641{
1642 struct qede_fastpath *fp = fp_cookie;
1643
1644 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1645
1646 napi_schedule_irqoff(&fp->napi);
1647 return IRQ_HANDLED;
1648}
1649
1650/* -------------------------------------------------------------------------
1651 * END OF FAST-PATH
1652 * -------------------------------------------------------------------------
1653 */
1654
1655static int qede_open(struct net_device *ndev);
1656static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1657static int qede_set_mac_addr(struct net_device *ndev, void *p);
1658static void qede_set_rx_mode(struct net_device *ndev);
1659static void qede_config_rx_mode(struct net_device *ndev);
1660
1661static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1662 enum qed_filter_xcast_params_type opcode,
1663 unsigned char mac[ETH_ALEN])
1664{
1665 struct qed_filter_params filter_cmd;
1666
1667 memset(&filter_cmd, 0, sizeof(filter_cmd));
1668 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1669 filter_cmd.filter.ucast.type = opcode;
1670 filter_cmd.filter.ucast.mac_valid = 1;
1671 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1672
1673 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1674}
1675
7c1bfcad
SRK		 1676static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1677 enum qed_filter_xcast_params_type opcode,
1678 u16 vid)
1679{
1680 struct qed_filter_params filter_cmd;
1681
1682 memset(&filter_cmd, 0, sizeof(filter_cmd));
1683 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1684 filter_cmd.filter.ucast.type = opcode;
1685 filter_cmd.filter.ucast.vlan_valid = 1;
1686 filter_cmd.filter.ucast.vlan = vid;
1687
1688 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1689}
1690
133fac0e
SK		 1691void qede_fill_by_demand_stats(struct qede_dev *edev)
1692{
1693 struct qed_eth_stats stats;
1694
1695 edev->ops->get_vport_stats(edev->cdev, &stats);
1696 edev->stats.no_buff_discards = stats.no_buff_discards;
1a5a366f
SRK		 1697 edev->stats.packet_too_big_discard = stats.packet_too_big_discard;
1698 edev->stats.ttl0_discard = stats.ttl0_discard;
133fac0e
SK		 1699 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1700 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1701 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1702 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1703 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1704 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1705 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1706 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1707
1708 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1709 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1710 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1711 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1712 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1713 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1714 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1715 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1716 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1717 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1718 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1719 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1720
1721 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1722 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1723 edev->stats.rx_128_to_255_byte_packets =
1724 stats.rx_128_to_255_byte_packets;
1725 edev->stats.rx_256_to_511_byte_packets =
1726 stats.rx_256_to_511_byte_packets;
1727 edev->stats.rx_512_to_1023_byte_packets =
1728 stats.rx_512_to_1023_byte_packets;
1729 edev->stats.rx_1024_to_1518_byte_packets =
1730 stats.rx_1024_to_1518_byte_packets;
1731 edev->stats.rx_1519_to_1522_byte_packets =
1732 stats.rx_1519_to_1522_byte_packets;
1733 edev->stats.rx_1519_to_2047_byte_packets =
1734 stats.rx_1519_to_2047_byte_packets;
1735 edev->stats.rx_2048_to_4095_byte_packets =
1736 stats.rx_2048_to_4095_byte_packets;
1737 edev->stats.rx_4096_to_9216_byte_packets =
1738 stats.rx_4096_to_9216_byte_packets;
1739 edev->stats.rx_9217_to_16383_byte_packets =
1740 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1741 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1742 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1743 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1744 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1745 edev->stats.rx_align_errors = stats.rx_align_errors;
1746 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1747 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1748 edev->stats.rx_jabbers = stats.rx_jabbers;
1749 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1750 edev->stats.rx_fragments = stats.rx_fragments;
1751 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1752 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1753 edev->stats.tx_128_to_255_byte_packets =
1754 stats.tx_128_to_255_byte_packets;
1755 edev->stats.tx_256_to_511_byte_packets =
1756 stats.tx_256_to_511_byte_packets;
1757 edev->stats.tx_512_to_1023_byte_packets =
1758 stats.tx_512_to_1023_byte_packets;
1759 edev->stats.tx_1024_to_1518_byte_packets =
1760 stats.tx_1024_to_1518_byte_packets;
1761 edev->stats.tx_1519_to_2047_byte_packets =
1762 stats.tx_1519_to_2047_byte_packets;
1763 edev->stats.tx_2048_to_4095_byte_packets =
1764 stats.tx_2048_to_4095_byte_packets;
1765 edev->stats.tx_4096_to_9216_byte_packets =
1766 stats.tx_4096_to_9216_byte_packets;
1767 edev->stats.tx_9217_to_16383_byte_packets =
1768 stats.tx_9217_to_16383_byte_packets;
1769 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1770 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1771 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1772 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1773 edev->stats.brb_truncates = stats.brb_truncates;
1774 edev->stats.brb_discards = stats.brb_discards;
1775 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1776}
1777
1a635e48
YM		 1778static
1779struct rtnl_link_stats64 *qede_get_stats64(struct net_device *dev,
1780 struct rtnl_link_stats64 *stats)
133fac0e
SK		 1781{
1782 struct qede_dev *edev = netdev_priv(dev);
1783
1784 qede_fill_by_demand_stats(edev);
1785
1786 stats->rx_packets = edev->stats.rx_ucast_pkts +
1787 edev->stats.rx_mcast_pkts +
1788 edev->stats.rx_bcast_pkts;
1789 stats->tx_packets = edev->stats.tx_ucast_pkts +
1790 edev->stats.tx_mcast_pkts +
1791 edev->stats.tx_bcast_pkts;
1792
1793 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1794 edev->stats.rx_mcast_bytes +
1795 edev->stats.rx_bcast_bytes;
1796
1797 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1798 edev->stats.tx_mcast_bytes +
1799 edev->stats.tx_bcast_bytes;
1800
1801 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1802 stats->multicast = edev->stats.rx_mcast_pkts +
1803 edev->stats.rx_bcast_pkts;
1804
1805 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1806
1807 stats->collisions = edev->stats.tx_total_collisions;
1808 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1809 stats->rx_frame_errors = edev->stats.rx_align_errors;
1810
1811 return stats;
1812}
1813
733def6a 1814#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 1815static int qede_get_vf_config(struct net_device *dev, int vfidx,
1816 struct ifla_vf_info *ivi)
1817{
1818 struct qede_dev *edev = netdev_priv(dev);
1819
1820 if (!edev->ops)
1821 return -EINVAL;
1822
1823 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
1824}
1825
733def6a
YM		 1826static int qede_set_vf_rate(struct net_device *dev, int vfidx,
1827 int min_tx_rate, int max_tx_rate)
1828{
1829 struct qede_dev *edev = netdev_priv(dev);
1830
be7b6d64 1831 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 1832 max_tx_rate);
1833}
1834
6ddc7608
YM		 1835static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
1836{
1837 struct qede_dev *edev = netdev_priv(dev);
1838
1839 if (!edev->ops)
1840 return -EINVAL;
1841
1842 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
1843}
1844
733def6a
YM		 1845static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
1846 int link_state)
1847{
1848 struct qede_dev *edev = netdev_priv(dev);
1849
1850 if (!edev->ops)
1851 return -EINVAL;
1852
1853 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
1854}
1855#endif
1856
7c1bfcad
SRK		 1857static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1858{
1859 struct qed_update_vport_params params;
1860 int rc;
1861
1862 /* Proceed only if action actually needs to be performed */
1863 if (edev->accept_any_vlan == action)
1864 return;
1865
1866 memset(&params, 0, sizeof(params));
1867
1868 params.vport_id = 0;
1869 params.accept_any_vlan = action;
1870 params.update_accept_any_vlan_flg = 1;
1871
1872 rc = edev->ops->vport_update(edev->cdev, &params);
1873 if (rc) {
1874 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1875 action ? "enable" : "disable");
1876 } else {
1877 DP_INFO(edev, "%s accept-any-vlan\n",
1878 action ? "enabled" : "disabled");
1879 edev->accept_any_vlan = action;
1880 }
1881}
1882
1883static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1884{
1885 struct qede_dev *edev = netdev_priv(dev);
1886 struct qede_vlan *vlan, *tmp;
1887 int rc;
1888
1889 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1890
1891 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1892 if (!vlan) {
1893 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1894 return -ENOMEM;
1895 }
1896 INIT_LIST_HEAD(&vlan->list);
1897 vlan->vid = vid;
1898 vlan->configured = false;
1899
1900 /* Verify vlan isn't already configured */
1901 list_for_each_entry(tmp, &edev->vlan_list, list) {
1902 if (tmp->vid == vlan->vid) {
1903 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1904 "vlan already configured\n");
1905 kfree(vlan);
1906 return -EEXIST;
1907 }
1908 }
1909
1910 /* If interface is down, cache this VLAN ID and return */
1911 if (edev->state != QEDE_STATE_OPEN) {
1912 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1913 "Interface is down, VLAN %d will be configured when interface is up\n",
1914 vid);
1915 if (vid != 0)
1916 edev->non_configured_vlans++;
1917 list_add(&vlan->list, &edev->vlan_list);
1918
1919 return 0;
1920 }
1921
1922 /* Check for the filter limit.
1923 * Note - vlan0 has a reserved filter and can be added without
1924 * worrying about quota
1925 */
1926 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1927 (vlan->vid == 0)) {
1928 rc = qede_set_ucast_rx_vlan(edev,
1929 QED_FILTER_XCAST_TYPE_ADD,
1930 vlan->vid);
1931 if (rc) {
1932 DP_ERR(edev, "Failed to configure VLAN %d\n",
1933 vlan->vid);
1934 kfree(vlan);
1935 return -EINVAL;
1936 }
1937 vlan->configured = true;
1938
1939 /* vlan0 filter isn't consuming out of our quota */
1940 if (vlan->vid != 0)
1941 edev->configured_vlans++;
1942 } else {
1943 /* Out of quota; Activate accept-any-VLAN mode */
1944 if (!edev->non_configured_vlans)
1945 qede_config_accept_any_vlan(edev, true);
1946
1947 edev->non_configured_vlans++;
1948 }
1949
1950 list_add(&vlan->list, &edev->vlan_list);
1951
1952 return 0;
1953}
1954
1955static void qede_del_vlan_from_list(struct qede_dev *edev,
1956 struct qede_vlan *vlan)
1957{
1958 /* vlan0 filter isn't consuming out of our quota */
1959 if (vlan->vid != 0) {
1960 if (vlan->configured)
1961 edev->configured_vlans--;
1962 else
1963 edev->non_configured_vlans--;
1964 }
1965
1966 list_del(&vlan->list);
1967 kfree(vlan);
1968}
1969
1970static int qede_configure_vlan_filters(struct qede_dev *edev)
1971{
1972 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1973 struct qed_dev_eth_info *dev_info;
1974 struct qede_vlan *vlan = NULL;
1975
1976 if (list_empty(&edev->vlan_list))
1977 return 0;
1978
1979 dev_info = &edev->dev_info;
1980
1981 /* Configure non-configured vlans */
1982 list_for_each_entry(vlan, &edev->vlan_list, list) {
1983 if (vlan->configured)
1984 continue;
1985
1986 /* We have used all our credits, now enable accept_any_vlan */
1987 if ((vlan->vid != 0) &&
1988 (edev->configured_vlans == dev_info->num_vlan_filters)) {
1989 accept_any_vlan = 1;
1990 continue;
1991 }
1992
1993 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
1994
1995 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
1996 vlan->vid);
1997 if (rc) {
1998 DP_ERR(edev, "Failed to configure VLAN %u\n",
1999 vlan->vid);
2000 real_rc = rc;
2001 continue;
2002 }
2003
2004 vlan->configured = true;
2005 /* vlan0 filter doesn't consume our VLAN filter's quota */
2006 if (vlan->vid != 0) {
2007 edev->non_configured_vlans--;
2008 edev->configured_vlans++;
2009 }
2010 }
2011
2012 /* enable accept_any_vlan mode if we have more VLANs than credits,
2013 * or remove accept_any_vlan mode if we've actually removed
2014 * a non-configured vlan, and all remaining vlans are truly configured.
2015 */
2016
2017 if (accept_any_vlan)
2018 qede_config_accept_any_vlan(edev, true);
2019 else if (!edev->non_configured_vlans)
2020 qede_config_accept_any_vlan(edev, false);
2021
2022 return real_rc;
2023}
2024
2025static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
2026{
2027 struct qede_dev *edev = netdev_priv(dev);
2028 struct qede_vlan *vlan = NULL;
2029 int rc;
2030
2031 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
2032
2033 /* Find whether entry exists */
2034 list_for_each_entry(vlan, &edev->vlan_list, list)
2035 if (vlan->vid == vid)
2036 break;
2037
2038 if (!vlan || (vlan->vid != vid)) {
2039 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
2040 "Vlan isn't configured\n");
2041 return 0;
2042 }
2043
2044 if (edev->state != QEDE_STATE_OPEN) {
2045 /* As interface is already down, we don't have a VPORT
2046 * instance to remove vlan filter. So just update vlan list
2047 */
2048 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2049 "Interface is down, removing VLAN from list only\n");
2050 qede_del_vlan_from_list(edev, vlan);
2051 return 0;
2052 }
2053
2054 /* Remove vlan */
c524e2f5
YM		 2055 if (vlan->configured) {
2056 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL,
2057 vid);
2058 if (rc) {
2059 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
2060 return -EINVAL;
2061 }
7c1bfcad
SRK		 2062 }
2063
2064 qede_del_vlan_from_list(edev, vlan);
2065
2066 /* We have removed a VLAN - try to see if we can
2067 * configure non-configured VLAN from the list.
2068 */
2069 rc = qede_configure_vlan_filters(edev);
2070
2071 return rc;
2072}
2073
2074static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
2075{
2076 struct qede_vlan *vlan = NULL;
2077
2078 if (list_empty(&edev->vlan_list))
2079 return;
2080
2081 list_for_each_entry(vlan, &edev->vlan_list, list) {
2082 if (!vlan->configured)
2083 continue;
2084
2085 vlan->configured = false;
2086
2087 /* vlan0 filter isn't consuming out of our quota */
2088 if (vlan->vid != 0) {
2089 edev->non_configured_vlans++;
2090 edev->configured_vlans--;
2091 }
2092
2093 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1a635e48 2094 "marked vlan %d as non-configured\n", vlan->vid);
7c1bfcad
SRK		 2095 }
2096
2097 edev->accept_any_vlan = false;
2098}
2099
ce2b885c
YM		 2100int qede_set_features(struct net_device *dev, netdev_features_t features)
2101{
2102 struct qede_dev *edev = netdev_priv(dev);
2103 netdev_features_t changes = features ^ dev->features;
2104 bool need_reload = false;
2105
2106 /* No action needed if hardware GRO is disabled during driver load */
2107 if (changes & NETIF_F_GRO) {
2108 if (dev->features & NETIF_F_GRO)
2109 need_reload = !edev->gro_disable;
2110 else
2111 need_reload = edev->gro_disable;
2112 }
2113
2114 if (need_reload && netif_running(edev->ndev)) {
2115 dev->features = features;
2116 qede_reload(edev, NULL, NULL);
2117 return 1;
2118 }
2119
2120 return 0;
2121}
2122
f9f082a9
AD		 2123static void qede_udp_tunnel_add(struct net_device *dev,
2124 struct udp_tunnel_info *ti)
b18e170c
MC		 2125{
2126 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2127 u16 t_port = ntohs(ti->port);
b18e170c 2128
f9f082a9
AD		 2129 switch (ti->type) {
2130 case UDP_TUNNEL_TYPE_VXLAN:
2131 if (edev->vxlan_dst_port)
2132 return;
b18e170c 2133
f9f082a9 2134 edev->vxlan_dst_port = t_port;
b18e170c 2135
525ef5c0 2136 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d\n",
f9f082a9 2137 t_port);
b18e170c 2138
f9f082a9
AD		 2139 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2140 break;
2141 case UDP_TUNNEL_TYPE_GENEVE:
2142 if (edev->geneve_dst_port)
2143 return;
b18e170c 2144
f9f082a9 2145 edev->geneve_dst_port = t_port;
b18e170c 2146
525ef5c0 2147 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d\n",
f9f082a9
AD		 2148 t_port);
2149 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2150 break;
2151 default:
b18e170c 2152 return;
f9f082a9 2153 }
b18e170c 2154
b18e170c
MC		 2155 schedule_delayed_work(&edev->sp_task, 0);
2156}
b18e170c 2157
f9f082a9
AD		 2158static void qede_udp_tunnel_del(struct net_device *dev,
2159 struct udp_tunnel_info *ti)
9a109dd0
MC		 2160{
2161 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2162 u16 t_port = ntohs(ti->port);
9a109dd0 2163
f9f082a9
AD		 2164 switch (ti->type) {
2165 case UDP_TUNNEL_TYPE_VXLAN:
2166 if (t_port != edev->vxlan_dst_port)
2167 return;
9a109dd0 2168
f9f082a9 2169 edev->vxlan_dst_port = 0;
9a109dd0 2170
525ef5c0 2171 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d\n",
f9f082a9 2172 t_port);
9a109dd0 2173
f9f082a9
AD		 2174 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2175 break;
2176 case UDP_TUNNEL_TYPE_GENEVE:
2177 if (t_port != edev->geneve_dst_port)
2178 return;
9a109dd0 2179
f9f082a9 2180 edev->geneve_dst_port = 0;
9a109dd0 2181
525ef5c0 2182 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d\n",
f9f082a9
AD		 2183 t_port);
2184 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2185 break;
2186 default:
2187 return;
2188 }
9a109dd0 2189
9a109dd0
MC		 2190 schedule_delayed_work(&edev->sp_task, 0);
2191}
9a109dd0 2192
2950219d
YM		 2193static const struct net_device_ops qede_netdev_ops = {
2194 .ndo_open = qede_open,
2195 .ndo_stop = qede_close,
2196 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2197 .ndo_set_rx_mode = qede_set_rx_mode,
2198 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2199 .ndo_validate_addr = eth_validate_addr,
133fac0e 2200 .ndo_change_mtu = qede_change_mtu,
08feecd7 2201#ifdef CONFIG_QED_SRIOV
eff16960 2202 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7
YM		 2203 .ndo_set_vf_vlan = qede_set_vf_vlan,
2204#endif
7c1bfcad
SRK		 2205 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2206 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
ce2b885c 2207 .ndo_set_features = qede_set_features,
133fac0e 2208 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 2209#ifdef CONFIG_QED_SRIOV
2210 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 2211 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 2212 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 2213 .ndo_set_vf_rate = qede_set_vf_rate,
2214#endif
f9f082a9
AD		 2215 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
2216 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
2950219d
YM		 2217};
2218
e712d52b
YM		 2219/* -------------------------------------------------------------------------
2220 * START OF PROBE / REMOVE
2221 * -------------------------------------------------------------------------
2222 */
2223
2224static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2225 struct pci_dev *pdev,
2226 struct qed_dev_eth_info *info,
1a635e48 2227 u32 dp_module, u8 dp_level)
e712d52b
YM		 2228{
2229 struct net_device *ndev;
2230 struct qede_dev *edev;
2231
2232 ndev = alloc_etherdev_mqs(sizeof(*edev),
1a635e48 2233 info->num_queues, info->num_queues);
e712d52b
YM		 2234 if (!ndev) {
2235 pr_err("etherdev allocation failed\n");
2236 return NULL;
2237 }
2238
2239 edev = netdev_priv(ndev);
2240 edev->ndev = ndev;
2241 edev->cdev = cdev;
2242 edev->pdev = pdev;
2243 edev->dp_module = dp_module;
2244 edev->dp_level = dp_level;
2245 edev->ops = qed_ops;
2950219d
YM		 2246 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2247 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2248
525ef5c0
YM		 2249 DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
2250 info->num_queues, info->num_queues);
2251
e712d52b
YM		 2252 SET_NETDEV_DEV(ndev, &pdev->dev);
2253
133fac0e 2254 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2255 memcpy(&edev->dev_info, info, sizeof(*info));
2256
2257 edev->num_tc = edev->dev_info.num_tc;
2258
7c1bfcad
SRK		 2259 INIT_LIST_HEAD(&edev->vlan_list);
2260
e712d52b
YM		 2261 return edev;
2262}
2263
2264static void qede_init_ndev(struct qede_dev *edev)
2265{
2266 struct net_device *ndev = edev->ndev;
2267 struct pci_dev *pdev = edev->pdev;
2268 u32 hw_features;
2269
2270 pci_set_drvdata(pdev, ndev);
2271
2272 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2273 ndev->base_addr = ndev->mem_start;
2274 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2275 ndev->irq = edev->dev_info.common.pci_irq;
2276
2277 ndev->watchdog_timeo = TX_TIMEOUT;
2278
2950219d
YM		 2279 ndev->netdev_ops = &qede_netdev_ops;
2280
133fac0e
SK		 2281 qede_set_ethtool_ops(ndev);
2282
e712d52b
YM		 2283 /* user-changeble features */
2284 hw_features = NETIF_F_GRO | NETIF_F_SG |
2285 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2286 NETIF_F_TSO | NETIF_F_TSO6;
2287
14db81de
MC		 2288 /* Encap features*/
2289 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2290 NETIF_F_TSO_ECN;
2291 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2292 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2293 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2294 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2295
e712d52b
YM		 2296 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2297 NETIF_F_HIGHDMA;
2298 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2299 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2300 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2301
2302 ndev->hw_features = hw_features;
2303
2304 /* Set network device HW mac */
2305 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2306}
2307
2308/* This function converts from 32b param to two params of level and module
2309 * Input 32b decoding:
2310 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2311 * 'happy' flow, e.g. memory allocation failed.
2312 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2313 * and provide important parameters.
2314 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2315 * module. VERBOSE prints are for tracking the specific flow in low level.
2316 *
2317 * Notice that the level should be that of the lowest required logs.
2318 */
133fac0e 2319void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2320{
2321 *p_dp_level = QED_LEVEL_NOTICE;
2322 *p_dp_module = 0;
2323
2324 if (debug & QED_LOG_VERBOSE_MASK) {
2325 *p_dp_level = QED_LEVEL_VERBOSE;
2326 *p_dp_module = (debug & 0x3FFFFFFF);
2327 } else if (debug & QED_LOG_INFO_MASK) {
2328 *p_dp_level = QED_LEVEL_INFO;
2329 } else if (debug & QED_LOG_NOTICE_MASK) {
2330 *p_dp_level = QED_LEVEL_NOTICE;
2331 }
2332}
2333
2950219d
YM		 2334static void qede_free_fp_array(struct qede_dev *edev)
2335{
2336 if (edev->fp_array) {
2337 struct qede_fastpath *fp;
2338 int i;
2339
2340 for_each_rss(i) {
2341 fp = &edev->fp_array[i];
2342
2343 kfree(fp->sb_info);
2344 kfree(fp->rxq);
2345 kfree(fp->txqs);
2346 }
2347 kfree(edev->fp_array);
2348 }
2349 edev->num_rss = 0;
2350}
2351
2352static int qede_alloc_fp_array(struct qede_dev *edev)
2353{
2354 struct qede_fastpath *fp;
2355 int i;
2356
2357 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2358 sizeof(*edev->fp_array), GFP_KERNEL);
2359 if (!edev->fp_array) {
2360 DP_NOTICE(edev, "fp array allocation failed\n");
2361 goto err;
2362 }
2363
2364 for_each_rss(i) {
2365 fp = &edev->fp_array[i];
2366
2367 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2368 if (!fp->sb_info) {
2369 DP_NOTICE(edev, "sb info struct allocation failed\n");
2370 goto err;
2371 }
2372
2373 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2374 if (!fp->rxq) {
2375 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2376 goto err;
2377 }
2378
2379 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2380 if (!fp->txqs) {
2381 DP_NOTICE(edev, "TXQ array allocation failed\n");
2382 goto err;
2383 }
2384 }
2385
2386 return 0;
2387err:
2388 qede_free_fp_array(edev);
2389 return -ENOMEM;
2390}
2391
0d8e0aa0
SK		 2392static void qede_sp_task(struct work_struct *work)
2393{
2394 struct qede_dev *edev = container_of(work, struct qede_dev,
2395 sp_task.work);
b18e170c
MC		 2396 struct qed_dev *cdev = edev->cdev;
2397
0d8e0aa0
SK		 2398 mutex_lock(&edev->qede_lock);
2399
2400 if (edev->state == QEDE_STATE_OPEN) {
2401 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2402 qede_config_rx_mode(edev->ndev);
2403 }
2404
b18e170c
MC		 2405 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2406 struct qed_tunn_params tunn_params;
2407
2408 memset(&tunn_params, 0, sizeof(tunn_params));
2409 tunn_params.update_vxlan_port = 1;
2410 tunn_params.vxlan_port = edev->vxlan_dst_port;
2411 qed_ops->tunn_config(cdev, &tunn_params);
2412 }
2413
9a109dd0
MC		 2414 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2415 struct qed_tunn_params tunn_params;
2416
2417 memset(&tunn_params, 0, sizeof(tunn_params));
2418 tunn_params.update_geneve_port = 1;
2419 tunn_params.geneve_port = edev->geneve_dst_port;
2420 qed_ops->tunn_config(cdev, &tunn_params);
2421 }
2422
0d8e0aa0
SK		 2423 mutex_unlock(&edev->qede_lock);
2424}
2425
e712d52b
YM		 2426static void qede_update_pf_params(struct qed_dev *cdev)
2427{
2428 struct qed_pf_params pf_params;
2429
8e0ddc04 2430 /* 64 rx + 64 tx */
e712d52b 2431 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2432 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2433 qed_ops->common->update_pf_params(cdev, &pf_params);
2434}
2435
2436enum qede_probe_mode {
2437 QEDE_PROBE_NORMAL,
2438};
2439
2440static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2441 bool is_vf, enum qede_probe_mode mode)
e712d52b 2442{
1408cc1f 2443 struct qed_probe_params probe_params;
1a635e48 2444 struct qed_slowpath_params sp_params;
e712d52b
YM		 2445 struct qed_dev_eth_info dev_info;
2446 struct qede_dev *edev;
2447 struct qed_dev *cdev;
2448 int rc;
2449
2450 if (unlikely(dp_level & QED_LEVEL_INFO))
2451 pr_notice("Starting qede probe\n");
2452
1408cc1f
YM		 2453 memset(&probe_params, 0, sizeof(probe_params));
2454 probe_params.protocol = QED_PROTOCOL_ETH;
2455 probe_params.dp_module = dp_module;
2456 probe_params.dp_level = dp_level;
2457 probe_params.is_vf = is_vf;
2458 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2459 if (!cdev) {
2460 rc = -ENODEV;
2461 goto err0;
2462 }
2463
2464 qede_update_pf_params(cdev);
2465
2466 /* Start the Slowpath-process */
1a635e48
YM		 2467 memset(&sp_params, 0, sizeof(sp_params));
2468 sp_params.int_mode = QED_INT_MODE_MSIX;
2469 sp_params.drv_major = QEDE_MAJOR_VERSION;
2470 sp_params.drv_minor = QEDE_MINOR_VERSION;
2471 sp_params.drv_rev = QEDE_REVISION_VERSION;
2472 sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
2473 strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2474 rc = qed_ops->common->slowpath_start(cdev, &sp_params);
e712d52b
YM		 2475 if (rc) {
2476 pr_notice("Cannot start slowpath\n");
2477 goto err1;
2478 }
2479
2480 /* Learn information crucial for qede to progress */
2481 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2482 if (rc)
2483 goto err2;
2484
2485 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2486 dp_level);
2487 if (!edev) {
2488 rc = -ENOMEM;
2489 goto err2;
2490 }
2491
fefb0202
YM		 2492 if (is_vf)
2493 edev->flags |= QEDE_FLAG_IS_VF;
2494
e712d52b
YM		 2495 qede_init_ndev(edev);
2496
2950219d
YM		 2497 rc = register_netdev(edev->ndev);
2498 if (rc) {
2499 DP_NOTICE(edev, "Cannot register net-device\n");
2500 goto err3;
2501 }
2502
e712d52b
YM		 2503 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2504
a2ec6172
SK		 2505 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2506
489e45ae
SRK		 2507#ifdef CONFIG_DCB
2508 qede_set_dcbnl_ops(edev->ndev);
2509#endif
2510
0d8e0aa0
SK		 2511 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2512 mutex_init(&edev->qede_lock);
3d789994 2513 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
0d8e0aa0 2514
e712d52b
YM		 2515 DP_INFO(edev, "Ending successfully qede probe\n");
2516
2517 return 0;
2518
2950219d
YM		 2519err3:
2520 free_netdev(edev->ndev);
e712d52b
YM		 2521err2:
2522 qed_ops->common->slowpath_stop(cdev);
2523err1:
2524 qed_ops->common->remove(cdev);
2525err0:
2526 return rc;
2527}
2528
2529static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2530{
fefb0202 2531 bool is_vf = false;
e712d52b
YM		 2532 u32 dp_module = 0;
2533 u8 dp_level = 0;
2534
fefb0202
YM		 2535 switch ((enum qede_pci_private)id->driver_data) {
2536 case QEDE_PRIVATE_VF:
2537 if (debug & QED_LOG_VERBOSE_MASK)
2538 dev_err(&pdev->dev, "Probing a VF\n");
2539 is_vf = true;
2540 break;
2541 default:
2542 if (debug & QED_LOG_VERBOSE_MASK)
2543 dev_err(&pdev->dev, "Probing a PF\n");
2544 }
2545
e712d52b
YM		 2546 qede_config_debug(debug, &dp_module, &dp_level);
2547
fefb0202 2548 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2549 QEDE_PROBE_NORMAL);
2550}
2551
2552enum qede_remove_mode {
2553 QEDE_REMOVE_NORMAL,
2554};
2555
2556static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2557{
2558 struct net_device *ndev = pci_get_drvdata(pdev);
2559 struct qede_dev *edev = netdev_priv(ndev);
2560 struct qed_dev *cdev = edev->cdev;
2561
2562 DP_INFO(edev, "Starting qede_remove\n");
2563
0d8e0aa0 2564 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2565 unregister_netdev(ndev);
2566
e712d52b
YM		 2567 edev->ops->common->set_power_state(cdev, PCI_D0);
2568
2569 pci_set_drvdata(pdev, NULL);
2570
2571 free_netdev(ndev);
2572
2573 /* Use global ops since we've freed edev */
2574 qed_ops->common->slowpath_stop(cdev);
2575 qed_ops->common->remove(cdev);
2576
525ef5c0 2577 dev_info(&pdev->dev, "Ending qede_remove successfully\n");
e712d52b
YM		 2578}
2579
2580static void qede_remove(struct pci_dev *pdev)
2581{
2582 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2583}
2950219d
YM		 2584
2585/* -------------------------------------------------------------------------
2586 * START OF LOAD / UNLOAD
2587 * -------------------------------------------------------------------------
2588 */
2589
2590static int qede_set_num_queues(struct qede_dev *edev)
2591{
2592 int rc;
2593 u16 rss_num;
2594
2595 /* Setup queues according to possible resources*/
8edf049d
SK		 2596 if (edev->req_rss)
2597 rss_num = edev->req_rss;
2598 else
2599 rss_num = netif_get_num_default_rss_queues() *
2600 edev->dev_info.common.num_hwfns;
2950219d
YM		 2601
2602 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2603
2604 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2605 if (rc > 0) {
2606 /* Managed to request interrupts for our queues */
2607 edev->num_rss = rc;
2608 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2609 QEDE_RSS_CNT(edev), rss_num);
2610 rc = 0;
2611 }
2612 return rc;
2613}
2614
2615static void qede_free_mem_sb(struct qede_dev *edev,
2616 struct qed_sb_info *sb_info)
2617{
2618 if (sb_info->sb_virt)
2619 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2620 (void *)sb_info->sb_virt, sb_info->sb_phys);
2621}
2622
2623/* This function allocates fast-path status block memory */
2624static int qede_alloc_mem_sb(struct qede_dev *edev,
1a635e48 2625 struct qed_sb_info *sb_info, u16 sb_id)
2950219d
YM		 2626{
2627 struct status_block *sb_virt;
2628 dma_addr_t sb_phys;
2629 int rc;
2630
2631 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1a635e48 2632 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
2950219d
YM		 2633 if (!sb_virt) {
2634 DP_ERR(edev, "Status block allocation failed\n");
2635 return -ENOMEM;
2636 }
2637
2638 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2639 sb_virt, sb_phys, sb_id,
2640 QED_SB_TYPE_L2_QUEUE);
2641 if (rc) {
2642 DP_ERR(edev, "Status block initialization failed\n");
2643 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2644 sb_virt, sb_phys);
2645 return rc;
2646 }
2647
2648 return 0;
2649}
2650
2651static void qede_free_rx_buffers(struct qede_dev *edev,
2652 struct qede_rx_queue *rxq)
2653{
2654 u16 i;
2655
2656 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2657 struct sw_rx_data *rx_buf;
fc48b7a6 2658 struct page *data;
2950219d
YM		 2659
2660 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2661 data = rx_buf->data;
2662
fc48b7a6 2663 dma_unmap_page(&edev->pdev->dev,
1a635e48 2664 rx_buf->mapping, PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2665
2666 rx_buf->data = NULL;
fc48b7a6 2667 __free_page(data);
2950219d
YM		 2668 }
2669}
2670
1a635e48
YM		 2671static void qede_free_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
2672{
55482edc
MC		 2673 int i;
2674
2675 if (edev->gro_disable)
2676 return;
2677
2678 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2679 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2680 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2681
f86af2df 2682 if (replace_buf->data) {
55482edc 2683 dma_unmap_page(&edev->pdev->dev,
09ec8e7f 2684 replace_buf->mapping,
55482edc
MC		 2685 PAGE_SIZE, DMA_FROM_DEVICE);
2686 __free_page(replace_buf->data);
2687 }
2688 }
2689}
2690
1a635e48 2691static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2692{
55482edc
MC		 2693 qede_free_sge_mem(edev, rxq);
2694
2950219d
YM		 2695 /* Free rx buffers */
2696 qede_free_rx_buffers(edev, rxq);
2697
2698 /* Free the parallel SW ring */
2699 kfree(rxq->sw_rx_ring);
2700
2701 /* Free the real RQ ring used by FW */
2702 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2703 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2704}
2705
2706static int qede_alloc_rx_buffer(struct qede_dev *edev,
2707 struct qede_rx_queue *rxq)
2708{
2709 struct sw_rx_data *sw_rx_data;
2710 struct eth_rx_bd *rx_bd;
2711 dma_addr_t mapping;
fc48b7a6 2712 struct page *data;
2950219d 2713
fc48b7a6 2714 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2715 if (unlikely(!data)) {
fc48b7a6 2716 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2717 return -ENOMEM;
2718 }
2719
fc48b7a6
YM		 2720 /* Map the entire page as it would be used
2721 * for multiple RX buffer segment size mapping.
2722 */
2723 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2724 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2725 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2726 __free_page(data);
2950219d
YM		 2727 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2728 return -ENOMEM;
2729 }
2730
2731 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2732 sw_rx_data->page_offset = 0;
2950219d 2733 sw_rx_data->data = data;
fc48b7a6 2734 sw_rx_data->mapping = mapping;
2950219d
YM		 2735
2736 /* Advance PROD and get BD pointer */
2737 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2738 WARN_ON(!rx_bd);
2739 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2740 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2741
2742 rxq->sw_rx_prod++;
2743
2744 return 0;
2745}
2746
1a635e48 2747static int qede_alloc_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
55482edc
MC		 2748{
2749 dma_addr_t mapping;
2750 int i;
2751
2752 if (edev->gro_disable)
2753 return 0;
2754
2755 if (edev->ndev->mtu > PAGE_SIZE) {
2756 edev->gro_disable = 1;
2757 return 0;
2758 }
2759
2760 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2761 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2762 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2763
2764 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2765 if (unlikely(!replace_buf->data)) {
2766 DP_NOTICE(edev,
2767 "Failed to allocate TPA skb pool [replacement buffer]\n");
2768 goto err;
2769 }
2770
2771 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2772 rxq->rx_buf_size, DMA_FROM_DEVICE);
2773 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2774 DP_NOTICE(edev,
2775 "Failed to map TPA replacement buffer\n");
2776 goto err;
2777 }
2778
09ec8e7f 2779 replace_buf->mapping = mapping;
55482edc
MC		 2780 tpa_info->replace_buf.page_offset = 0;
2781
2782 tpa_info->replace_buf_mapping = mapping;
2783 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2784 }
2785
2786 return 0;
2787err:
2788 qede_free_sge_mem(edev, rxq);
2789 edev->gro_disable = 1;
2790 return -ENOMEM;
2791}
2792
2950219d 2793/* This function allocates all memory needed per Rx queue */
1a635e48 2794static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2795{
f86af2df 2796 int i, rc, size;
2950219d
YM		 2797
2798 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2799
1a635e48
YM		 2800 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
2801
fc48b7a6
YM		 2802 if (rxq->rx_buf_size > PAGE_SIZE)
2803 rxq->rx_buf_size = PAGE_SIZE;
2804
2805 /* Segment size to spilt a page in multiple equal parts */
2806 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2807
2808 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2809 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2810 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2811 if (!rxq->sw_rx_ring) {
2812 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2813 rc = -ENOMEM;
2950219d
YM		 2814 goto err;
2815 }
2816
2817 /* Allocate FW Rx ring */
2818 rc = edev->ops->common->chain_alloc(edev->cdev,
2819 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2820 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 2821 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2822 RX_RING_SIZE,
2950219d
YM		 2823 sizeof(struct eth_rx_bd),
2824 &rxq->rx_bd_ring);
2825
2826 if (rc)
2827 goto err;
2828
2829 /* Allocate FW completion ring */
2830 rc = edev->ops->common->chain_alloc(edev->cdev,
2831 QED_CHAIN_USE_TO_CONSUME,
2832 QED_CHAIN_MODE_PBL,
a91eb52a 2833 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2834 RX_RING_SIZE,
2950219d
YM		 2835 sizeof(union eth_rx_cqe),
2836 &rxq->rx_comp_ring);
2837 if (rc)
2838 goto err;
2839
2840 /* Allocate buffers for the Rx ring */
2841 for (i = 0; i < rxq->num_rx_buffers; i++) {
2842 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2843 if (rc) {
2844 DP_ERR(edev,
2845 "Rx buffers allocation failed at index %d\n", i);
2846 goto err;
2847 }
2950219d
YM		 2848 }
2849
f86af2df 2850 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2851err:
f86af2df 2852 return rc;
2950219d
YM		 2853}
2854
1a635e48 2855static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 2856{
2857 /* Free the parallel SW ring */
2858 kfree(txq->sw_tx_ring);
2859
2860 /* Free the real RQ ring used by FW */
2861 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2862}
2863
2864/* This function allocates all memory needed per Tx queue */
1a635e48 2865static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 2866{
2867 int size, rc;
2868 union eth_tx_bd_types *p_virt;
2869
2870 txq->num_tx_buffers = edev->q_num_tx_buffers;
2871
2872 /* Allocate the parallel driver ring for Tx buffers */
2873 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2874 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2875 if (!txq->sw_tx_ring) {
2876 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2877 goto err;
2878 }
2879
2880 rc = edev->ops->common->chain_alloc(edev->cdev,
2881 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2882 QED_CHAIN_MODE_PBL,
a91eb52a 2883 QED_CHAIN_CNT_TYPE_U16,
2950219d 2884 NUM_TX_BDS_MAX,
a91eb52a 2885 sizeof(*p_virt), &txq->tx_pbl);
2950219d
YM		 2886 if (rc)
2887 goto err;
2888
2889 return 0;
2890
2891err:
2892 qede_free_mem_txq(edev, txq);
2893 return -ENOMEM;
2894}
2895
2896/* This function frees all memory of a single fp */
1a635e48 2897static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d
YM		 2898{
2899 int tc;
2900
2901 qede_free_mem_sb(edev, fp->sb_info);
2902
2903 qede_free_mem_rxq(edev, fp->rxq);
2904
2905 for (tc = 0; tc < edev->num_tc; tc++)
2906 qede_free_mem_txq(edev, &fp->txqs[tc]);
2907}
2908
2909/* This function allocates all memory needed for a single fp (i.e. an entity
2910 * which contains status block, one rx queue and multiple per-TC tx queues.
2911 */
1a635e48 2912static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d
YM		 2913{
2914 int rc, tc;
2915
2916 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2917 if (rc)
2918 goto err;
2919
2920 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2921 if (rc)
2922 goto err;
2923
2924 for (tc = 0; tc < edev->num_tc; tc++) {
2925 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2926 if (rc)
2927 goto err;
2928 }
2929
2930 return 0;
2950219d 2931err:
f86af2df 2932 return rc;
2950219d
YM		 2933}
2934
2935static void qede_free_mem_load(struct qede_dev *edev)
2936{
2937 int i;
2938
2939 for_each_rss(i) {
2940 struct qede_fastpath *fp = &edev->fp_array[i];
2941
2942 qede_free_mem_fp(edev, fp);
2943 }
2944}
2945
2946/* This function allocates all qede memory at NIC load. */
2947static int qede_alloc_mem_load(struct qede_dev *edev)
2948{
2949 int rc = 0, rss_id;
2950
2951 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2952 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2953
2954 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2955 if (rc) {
2950219d 2956 DP_ERR(edev,
f86af2df
MC		 2957 "Failed to allocate memory for fastpath - rss id = %d\n",
2958 rss_id);
2959 qede_free_mem_load(edev);
2960 return rc;
2950219d 2961 }
2950219d
YM		 2962 }
2963
2964 return 0;
2965}
2966
2967/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2968static void qede_init_fp(struct qede_dev *edev)
2969{
2970 int rss_id, txq_index, tc;
2971 struct qede_fastpath *fp;
2972
2973 for_each_rss(rss_id) {
2974 fp = &edev->fp_array[rss_id];
2975
2976 fp->edev = edev;
2977 fp->rss_id = rss_id;
2978
2979 memset((void *)&fp->napi, 0, sizeof(fp->napi));
2980
2981 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
2982
2983 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
2984 fp->rxq->rxq_id = rss_id;
2985
2986 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
2987 for (tc = 0; tc < edev->num_tc; tc++) {
2988 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
2989 fp->txqs[tc].index = txq_index;
2990 }
2991
2992 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
2993 edev->ndev->name, rss_id);
2994 }
55482edc
MC		 2995
2996 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 2997}
2998
2999static int qede_set_real_num_queues(struct qede_dev *edev)
3000{
3001 int rc = 0;
3002
3003 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
3004 if (rc) {
3005 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
3006 return rc;
3007 }
3008 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
3009 if (rc) {
3010 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
3011 return rc;
3012 }
3013
3014 return 0;
3015}
3016
3017static void qede_napi_disable_remove(struct qede_dev *edev)
3018{
3019 int i;
3020
3021 for_each_rss(i) {
3022 napi_disable(&edev->fp_array[i].napi);
3023
3024 netif_napi_del(&edev->fp_array[i].napi);
3025 }
3026}
3027
3028static void qede_napi_add_enable(struct qede_dev *edev)
3029{
3030 int i;
3031
3032 /* Add NAPI objects */
3033 for_each_rss(i) {
3034 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
3035 qede_poll, NAPI_POLL_WEIGHT);
3036 napi_enable(&edev->fp_array[i].napi);
3037 }
3038}
3039
3040static void qede_sync_free_irqs(struct qede_dev *edev)
3041{
3042 int i;
3043
3044 for (i = 0; i < edev->int_info.used_cnt; i++) {
3045 if (edev->int_info.msix_cnt) {
3046 synchronize_irq(edev->int_info.msix[i].vector);
3047 free_irq(edev->int_info.msix[i].vector,
3048 &edev->fp_array[i]);
3049 } else {
3050 edev->ops->common->simd_handler_clean(edev->cdev, i);
3051 }
3052 }
3053
3054 edev->int_info.used_cnt = 0;
3055}
3056
3057static int qede_req_msix_irqs(struct qede_dev *edev)
3058{
3059 int i, rc;
3060
3061 /* Sanitize number of interrupts == number of prepared RSS queues */
3062 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
3063 DP_ERR(edev,
3064 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
3065 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
3066 return -EINVAL;
3067 }
3068
3069 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
3070 rc = request_irq(edev->int_info.msix[i].vector,
3071 qede_msix_fp_int, 0, edev->fp_array[i].name,
3072 &edev->fp_array[i]);
3073 if (rc) {
3074 DP_ERR(edev, "Request fp %d irq failed\n", i);
3075 qede_sync_free_irqs(edev);
3076 return rc;
3077 }
3078 DP_VERBOSE(edev, NETIF_MSG_INTR,
3079 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
3080 edev->fp_array[i].name, i,
3081 &edev->fp_array[i]);
3082 edev->int_info.used_cnt++;
3083 }
3084
3085 return 0;
3086}
3087
3088static void qede_simd_fp_handler(void *cookie)
3089{
3090 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
3091
3092 napi_schedule_irqoff(&fp->napi);
3093}
3094
3095static int qede_setup_irqs(struct qede_dev *edev)
3096{
3097 int i, rc = 0;
3098
3099 /* Learn Interrupt configuration */
3100 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
3101 if (rc)
3102 return rc;
3103
3104 if (edev->int_info.msix_cnt) {
3105 rc = qede_req_msix_irqs(edev);
3106 if (rc)
3107 return rc;
3108 edev->ndev->irq = edev->int_info.msix[0].vector;
3109 } else {
3110 const struct qed_common_ops *ops;
3111
3112 /* qed should learn receive the RSS ids and callbacks */
3113 ops = edev->ops->common;
3114 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
3115 ops->simd_handler_config(edev->cdev,
3116 &edev->fp_array[i], i,
3117 qede_simd_fp_handler);
3118 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
3119 }
3120 return 0;
3121}
3122
3123static int qede_drain_txq(struct qede_dev *edev,
1a635e48 3124 struct qede_tx_queue *txq, bool allow_drain)
2950219d
YM		 3125{
3126 int rc, cnt = 1000;
3127
3128 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3129 if (!cnt) {
3130 if (allow_drain) {
3131 DP_NOTICE(edev,
3132 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3133 txq->index);
3134 rc = edev->ops->common->drain(edev->cdev);
3135 if (rc)
3136 return rc;
3137 return qede_drain_txq(edev, txq, false);
3138 }
3139 DP_NOTICE(edev,
3140 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3141 txq->index, txq->sw_tx_prod,
3142 txq->sw_tx_cons);
3143 return -ENODEV;
3144 }
3145 cnt--;
3146 usleep_range(1000, 2000);
3147 barrier();
3148 }
3149
3150 /* FW finished processing, wait for HW to transmit all tx packets */
3151 usleep_range(1000, 2000);
3152
3153 return 0;
3154}
3155
3156static int qede_stop_queues(struct qede_dev *edev)
3157{
3158 struct qed_update_vport_params vport_update_params;
3159 struct qed_dev *cdev = edev->cdev;
3160 int rc, tc, i;
3161
3162 /* Disable the vport */
3163 memset(&vport_update_params, 0, sizeof(vport_update_params));
3164 vport_update_params.vport_id = 0;
3165 vport_update_params.update_vport_active_flg = 1;
3166 vport_update_params.vport_active_flg = 0;
3167 vport_update_params.update_rss_flg = 0;
3168
3169 rc = edev->ops->vport_update(cdev, &vport_update_params);
3170 if (rc) {
3171 DP_ERR(edev, "Failed to update vport\n");
3172 return rc;
3173 }
3174
3175 /* Flush Tx queues. If needed, request drain from MCP */
3176 for_each_rss(i) {
3177 struct qede_fastpath *fp = &edev->fp_array[i];
3178
3179 for (tc = 0; tc < edev->num_tc; tc++) {
3180 struct qede_tx_queue *txq = &fp->txqs[tc];
3181
3182 rc = qede_drain_txq(edev, txq, true);
3183 if (rc)
3184 return rc;
3185 }
3186 }
3187
3188 /* Stop all Queues in reverse order*/
3189 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3190 struct qed_stop_rxq_params rx_params;
3191
3192 /* Stop the Tx Queue(s)*/
3193 for (tc = 0; tc < edev->num_tc; tc++) {
3194 struct qed_stop_txq_params tx_params;
3195
3196 tx_params.rss_id = i;
3197 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3198 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3199 if (rc) {
3200 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3201 tx_params.tx_queue_id);
3202 return rc;
3203 }
3204 }
3205
3206 /* Stop the Rx Queue*/
3207 memset(&rx_params, 0, sizeof(rx_params));
3208 rx_params.rss_id = i;
3209 rx_params.rx_queue_id = i;
3210
3211 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3212 if (rc) {
3213 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3214 return rc;
3215 }
3216 }
3217
3218 /* Stop the vport */
3219 rc = edev->ops->vport_stop(cdev, 0);
3220 if (rc)
3221 DP_ERR(edev, "Failed to stop VPORT\n");
3222
3223 return rc;
3224}
3225
a0d26d5a 3226static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d
YM		 3227{
3228 int rc, tc, i;
088c8618 3229 int vlan_removal_en = 1;
2950219d 3230 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3231 struct qed_update_vport_params vport_update_params;
3232 struct qed_queue_start_common_params q_params;
fefb0202 3233 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3234 struct qed_start_vport_params start = {0};
961acdea 3235 bool reset_rss_indir = false;
2950219d
YM		 3236
3237 if (!edev->num_rss) {
3238 DP_ERR(edev,
3239 "Cannot update V-VPORT as active as there are no Rx queues\n");
3240 return -EINVAL;
3241 }
3242
55482edc 3243 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3244 start.mtu = edev->ndev->mtu;
3245 start.vport_id = 0;
3246 start.drop_ttl0 = true;
3247 start.remove_inner_vlan = vlan_removal_en;
7f7a144f 3248 start.clear_stats = clear_stats;
088c8618
MC		 3249
3250 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3251
3252 if (rc) {
3253 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3254 return rc;
3255 }
3256
3257 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3258 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3259 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3260
3261 for_each_rss(i) {
3262 struct qede_fastpath *fp = &edev->fp_array[i];
3263 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3264
3265 memset(&q_params, 0, sizeof(q_params));
3266 q_params.rss_id = i;
3267 q_params.queue_id = i;
3268 q_params.vport_id = 0;
3269 q_params.sb = fp->sb_info->igu_sb_id;
3270 q_params.sb_idx = RX_PI;
3271
3272 rc = edev->ops->q_rx_start(cdev, &q_params,
3273 fp->rxq->rx_buf_size,
3274 fp->rxq->rx_bd_ring.p_phys_addr,
3275 phys_table,
3276 fp->rxq->rx_comp_ring.page_cnt,
3277 &fp->rxq->hw_rxq_prod_addr);
3278 if (rc) {
3279 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3280 return rc;
3281 }
3282
3283 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3284
3285 qede_update_rx_prod(edev, fp->rxq);
3286
3287 for (tc = 0; tc < edev->num_tc; tc++) {
3288 struct qede_tx_queue *txq = &fp->txqs[tc];
3289 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3290
3291 memset(&q_params, 0, sizeof(q_params));
3292 q_params.rss_id = i;
3293 q_params.queue_id = txq_index;
3294 q_params.vport_id = 0;
3295 q_params.sb = fp->sb_info->igu_sb_id;
3296 q_params.sb_idx = TX_PI(tc);
3297
3298 rc = edev->ops->q_tx_start(cdev, &q_params,
3299 txq->tx_pbl.pbl.p_phys_table,
3300 txq->tx_pbl.page_cnt,
3301 &txq->doorbell_addr);
3302 if (rc) {
3303 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3304 txq_index, rc);
3305 return rc;
3306 }
3307
3308 txq->hw_cons_ptr =
3309 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3310 SET_FIELD(txq->tx_db.data.params,
3311 ETH_DB_DATA_DEST, DB_DEST_XCM);
3312 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3313 DB_AGG_CMD_SET);
3314 SET_FIELD(txq->tx_db.data.params,
3315 ETH_DB_DATA_AGG_VAL_SEL,
3316 DQ_XCM_ETH_TX_BD_PROD_CMD);
3317
3318 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3319 }
3320 }
3321
3322 /* Prepare and send the vport enable */
3323 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3324 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3325 vport_update_params.update_vport_active_flg = 1;
3326 vport_update_params.vport_active_flg = 1;
3327
831bfb0e
YM		 3328 if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
3329 qed_info->tx_switching) {
3330 vport_update_params.update_tx_switching_flg = 1;
3331 vport_update_params.tx_switching_flg = 1;
3332 }
3333
2950219d
YM		 3334 /* Fill struct with RSS params */
3335 if (QEDE_RSS_CNT(edev) > 1) {
3336 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3337
3338 /* Need to validate current RSS config uses valid entries */
3339 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3340 if (edev->rss_params.rss_ind_table[i] >=
3341 edev->num_rss) {
3342 reset_rss_indir = true;
3343 break;
3344 }
3345 }
3346
3347 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3348 reset_rss_indir) {
3349 u16 val;
3350
3351 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3352 u16 indir_val;
3353
3354 val = QEDE_RSS_CNT(edev);
3355 indir_val = ethtool_rxfh_indir_default(i, val);
3356 edev->rss_params.rss_ind_table[i] = indir_val;
3357 }
3358 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3359 }
3360
3361 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3362 netdev_rss_key_fill(edev->rss_params.rss_key,
3363 sizeof(edev->rss_params.rss_key));
3364 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3365 }
3366
3367 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3368 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3369 QED_RSS_IPV6 |
3370 QED_RSS_IPV4_TCP |
3371 QED_RSS_IPV6_TCP;
3372 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3373 }
3374
3375 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3376 sizeof(vport_update_params.rss_params));
2950219d 3377 } else {
961acdea
SRK		 3378 memset(&vport_update_params.rss_params, 0,
3379 sizeof(vport_update_params.rss_params));
2950219d 3380 }
2950219d
YM		 3381
3382 rc = edev->ops->vport_update(cdev, &vport_update_params);
3383 if (rc) {
3384 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3385 return rc;
3386 }
3387
3388 return 0;
3389}
3390
0d8e0aa0
SK		 3391static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3392 enum qed_filter_xcast_params_type opcode,
3393 unsigned char *mac, int num_macs)
3394{
3395 struct qed_filter_params filter_cmd;
3396 int i;
3397
3398 memset(&filter_cmd, 0, sizeof(filter_cmd));
3399 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3400 filter_cmd.filter.mcast.type = opcode;
3401 filter_cmd.filter.mcast.num = num_macs;
3402
3403 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3404 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3405
3406 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3407}
3408
2950219d
YM		 3409enum qede_unload_mode {
3410 QEDE_UNLOAD_NORMAL,
3411};
3412
3413static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3414{
a2ec6172 3415 struct qed_link_params link_params;
2950219d
YM		 3416 int rc;
3417
3418 DP_INFO(edev, "Starting qede unload\n");
3419
0d8e0aa0
SK		 3420 mutex_lock(&edev->qede_lock);
3421 edev->state = QEDE_STATE_CLOSED;
3422
2950219d
YM		 3423 /* Close OS Tx */
3424 netif_tx_disable(edev->ndev);
3425 netif_carrier_off(edev->ndev);
3426
a2ec6172
SK		 3427 /* Reset the link */
3428 memset(&link_params, 0, sizeof(link_params));
3429 link_params.link_up = false;
3430 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3431 rc = qede_stop_queues(edev);
3432 if (rc) {
3433 qede_sync_free_irqs(edev);
3434 goto out;
3435 }
3436
3437 DP_INFO(edev, "Stopped Queues\n");
3438
7c1bfcad 3439 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3440 edev->ops->fastpath_stop(edev->cdev);
3441
3442 /* Release the interrupts */
3443 qede_sync_free_irqs(edev);
3444 edev->ops->common->set_fp_int(edev->cdev, 0);
3445
3446 qede_napi_disable_remove(edev);
3447
3448 qede_free_mem_load(edev);
3449 qede_free_fp_array(edev);
3450
3451out:
3452 mutex_unlock(&edev->qede_lock);
3453 DP_INFO(edev, "Ending qede unload\n");
3454}
3455
3456enum qede_load_mode {
3457 QEDE_LOAD_NORMAL,
a0d26d5a 3458 QEDE_LOAD_RELOAD,
2950219d
YM		 3459};
3460
3461static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3462{
a2ec6172
SK		 3463 struct qed_link_params link_params;
3464 struct qed_link_output link_output;
2950219d
YM		 3465 int rc;
3466
3467 DP_INFO(edev, "Starting qede load\n");
3468
3469 rc = qede_set_num_queues(edev);
3470 if (rc)
3471 goto err0;
3472
3473 rc = qede_alloc_fp_array(edev);
3474 if (rc)
3475 goto err0;
3476
3477 qede_init_fp(edev);
3478
3479 rc = qede_alloc_mem_load(edev);
3480 if (rc)
3481 goto err1;
3482 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3483 QEDE_RSS_CNT(edev), edev->num_tc);
3484
3485 rc = qede_set_real_num_queues(edev);
3486 if (rc)
3487 goto err2;
3488
3489 qede_napi_add_enable(edev);
3490 DP_INFO(edev, "Napi added and enabled\n");
3491
3492 rc = qede_setup_irqs(edev);
3493 if (rc)
3494 goto err3;
3495 DP_INFO(edev, "Setup IRQs succeeded\n");
3496
a0d26d5a 3497 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 3498 if (rc)
3499 goto err4;
3500 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3501
3502 /* Add primary mac and set Rx filters */
3503 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3504
0d8e0aa0
SK		 3505 mutex_lock(&edev->qede_lock);
3506 edev->state = QEDE_STATE_OPEN;
3507 mutex_unlock(&edev->qede_lock);
a2ec6172 3508
7c1bfcad
SRK		 3509 /* Program un-configured VLANs */
3510 qede_configure_vlan_filters(edev);
3511
a2ec6172
SK		 3512 /* Ask for link-up using current configuration */
3513 memset(&link_params, 0, sizeof(link_params));
3514 link_params.link_up = true;
3515 edev->ops->common->set_link(edev->cdev, &link_params);
3516
3517 /* Query whether link is already-up */
3518 memset(&link_output, 0, sizeof(link_output));
3519 edev->ops->common->get_link(edev->cdev, &link_output);
3520 qede_link_update(edev, &link_output);
3521
2950219d
YM		 3522 DP_INFO(edev, "Ending successfully qede load\n");
3523
3524 return 0;
3525
3526err4:
3527 qede_sync_free_irqs(edev);
3528 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3529err3:
3530 qede_napi_disable_remove(edev);
3531err2:
3532 qede_free_mem_load(edev);
3533err1:
3534 edev->ops->common->set_fp_int(edev->cdev, 0);
3535 qede_free_fp_array(edev);
3536 edev->num_rss = 0;
3537err0:
3538 return rc;
3539}
3540
133fac0e
SK		 3541void qede_reload(struct qede_dev *edev,
3542 void (*func)(struct qede_dev *, union qede_reload_args *),
3543 union qede_reload_args *args)
3544{
3545 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3546 /* Call function handler to update parameters
3547 * needed for function load.
3548 */
3549 if (func)
3550 func(edev, args);
3551
a0d26d5a 3552 qede_load(edev, QEDE_LOAD_RELOAD);
133fac0e
SK		 3553
3554 mutex_lock(&edev->qede_lock);
3555 qede_config_rx_mode(edev->ndev);
3556 mutex_unlock(&edev->qede_lock);
3557}
3558
2950219d
YM		 3559/* called with rtnl_lock */
3560static int qede_open(struct net_device *ndev)
3561{
3562 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3563 int rc;
2950219d
YM		 3564
3565 netif_carrier_off(ndev);
3566
3567 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3568
b18e170c
MC		 3569 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3570
3571 if (rc)
3572 return rc;
3573
f9f082a9
AD		 3574 udp_tunnel_get_rx_info(ndev);
3575
b18e170c 3576 return 0;
2950219d
YM		 3577}
3578
3579static int qede_close(struct net_device *ndev)
3580{
3581 struct qede_dev *edev = netdev_priv(ndev);
3582
3583 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3584
3585 return 0;
3586}
0d8e0aa0 3587
a2ec6172
SK		 3588static void qede_link_update(void *dev, struct qed_link_output *link)
3589{
3590 struct qede_dev *edev = dev;
3591
3592 if (!netif_running(edev->ndev)) {
3593 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3594 return;
3595 }
3596
3597 if (link->link_up) {
8e025ae2
YM		 3598 if (!netif_carrier_ok(edev->ndev)) {
3599 DP_NOTICE(edev, "Link is up\n");
3600 netif_tx_start_all_queues(edev->ndev);
3601 netif_carrier_on(edev->ndev);
3602 }
a2ec6172 3603 } else {
8e025ae2
YM		 3604 if (netif_carrier_ok(edev->ndev)) {
3605 DP_NOTICE(edev, "Link is down\n");
3606 netif_tx_disable(edev->ndev);
3607 netif_carrier_off(edev->ndev);
3608 }
a2ec6172
SK		 3609 }
3610}
3611
0d8e0aa0
SK		 3612static int qede_set_mac_addr(struct net_device *ndev, void *p)
3613{
3614 struct qede_dev *edev = netdev_priv(ndev);
3615 struct sockaddr *addr = p;
3616 int rc;
3617
3618 ASSERT_RTNL(); /* @@@TBD To be removed */
3619
3620 DP_INFO(edev, "Set_mac_addr called\n");
3621
3622 if (!is_valid_ether_addr(addr->sa_data)) {
3623 DP_NOTICE(edev, "The MAC address is not valid\n");
3624 return -EFAULT;
3625 }
3626
eff16960
YM		 3627 if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
3628 DP_NOTICE(edev, "qed prevents setting MAC\n");
3629 return -EINVAL;
3630 }
3631
0d8e0aa0
SK		 3632 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3633
3634 if (!netif_running(ndev)) {
3635 DP_NOTICE(edev, "The device is currently down\n");
3636 return 0;
3637 }
3638
3639 /* Remove the previous primary mac */
3640 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3641 edev->primary_mac);
3642 if (rc)
3643 return rc;
3644
3645 /* Add MAC filter according to the new unicast HW MAC address */
3646 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3647 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3648 edev->primary_mac);
3649}
3650
3651static int
3652qede_configure_mcast_filtering(struct net_device *ndev,
3653 enum qed_filter_rx_mode_type *accept_flags)
3654{
3655 struct qede_dev *edev = netdev_priv(ndev);
3656 unsigned char *mc_macs, *temp;
3657 struct netdev_hw_addr *ha;
3658 int rc = 0, mc_count;
3659 size_t size;
3660
3661 size = 64 * ETH_ALEN;
3662
3663 mc_macs = kzalloc(size, GFP_KERNEL);
3664 if (!mc_macs) {
3665 DP_NOTICE(edev,
3666 "Failed to allocate memory for multicast MACs\n");
3667 rc = -ENOMEM;
3668 goto exit;
3669 }
3670
3671 temp = mc_macs;
3672
3673 /* Remove all previously configured MAC filters */
3674 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3675 mc_macs, 1);
3676 if (rc)
3677 goto exit;
3678
3679 netif_addr_lock_bh(ndev);
3680
3681 mc_count = netdev_mc_count(ndev);
3682 if (mc_count < 64) {
3683 netdev_for_each_mc_addr(ha, ndev) {
3684 ether_addr_copy(temp, ha->addr);
3685 temp += ETH_ALEN;
3686 }
3687 }
3688
3689 netif_addr_unlock_bh(ndev);
3690
3691 /* Check for all multicast @@@TBD resource allocation */
3692 if ((ndev->flags & IFF_ALLMULTI) ||
3693 (mc_count > 64)) {
3694 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3695 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3696 } else {
3697 /* Add all multicast MAC filters */
3698 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3699 mc_macs, mc_count);
3700 }
3701
3702exit:
3703 kfree(mc_macs);
3704 return rc;
3705}
3706
3707static void qede_set_rx_mode(struct net_device *ndev)
3708{
3709 struct qede_dev *edev = netdev_priv(ndev);
3710
3711 DP_INFO(edev, "qede_set_rx_mode called\n");
3712
3713 if (edev->state != QEDE_STATE_OPEN) {
3714 DP_INFO(edev,
3715 "qede_set_rx_mode called while interface is down\n");
3716 } else {
3717 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3718 schedule_delayed_work(&edev->sp_task, 0);
3719 }
3720}
3721
3722/* Must be called with qede_lock held */
3723static void qede_config_rx_mode(struct net_device *ndev)
3724{
3725 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3726 struct qede_dev *edev = netdev_priv(ndev);
3727 struct qed_filter_params rx_mode;
3728 unsigned char *uc_macs, *temp;
3729 struct netdev_hw_addr *ha;
3730 int rc, uc_count;
3731 size_t size;
3732
3733 netif_addr_lock_bh(ndev);
3734
3735 uc_count = netdev_uc_count(ndev);
3736 size = uc_count * ETH_ALEN;
3737
3738 uc_macs = kzalloc(size, GFP_ATOMIC);
3739 if (!uc_macs) {
3740 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3741 netif_addr_unlock_bh(ndev);
3742 return;
3743 }
3744
3745 temp = uc_macs;
3746 netdev_for_each_uc_addr(ha, ndev) {
3747 ether_addr_copy(temp, ha->addr);
3748 temp += ETH_ALEN;
3749 }
3750
3751 netif_addr_unlock_bh(ndev);
3752
3753 /* Configure the struct for the Rx mode */
3754 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3755 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3756
3757 /* Remove all previous unicast secondary macs and multicast macs
3758 * (configrue / leave the primary mac)
3759 */
3760 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3761 edev->primary_mac);
3762 if (rc)
3763 goto out;
3764
3765 /* Check for promiscuous */
3766 if ((ndev->flags & IFF_PROMISC) ||
3767 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3768 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3769 } else {
3770 /* Add MAC filters according to the unicast secondary macs */
3771 int i;
3772
3773 temp = uc_macs;
3774 for (i = 0; i < uc_count; i++) {
3775 rc = qede_set_ucast_rx_mac(edev,
3776 QED_FILTER_XCAST_TYPE_ADD,
3777 temp);
3778 if (rc)
3779 goto out;
3780
3781 temp += ETH_ALEN;
3782 }
3783
3784 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3785 if (rc)
3786 goto out;
3787 }
3788
7c1bfcad
SRK		 3789 /* take care of VLAN mode */
3790 if (ndev->flags & IFF_PROMISC) {
3791 qede_config_accept_any_vlan(edev, true);
3792 } else if (!edev->non_configured_vlans) {
3793 /* It's possible that accept_any_vlan mode is set due to a
3794 * previous setting of IFF_PROMISC. If vlan credits are
3795 * sufficient, disable accept_any_vlan.
3796 */
3797 qede_config_accept_any_vlan(edev, false);
3798 }
3799
0d8e0aa0
SK		 3800 rx_mode.filter.accept_flags = accept_flags;
3801 edev->ops->filter_config(edev->cdev, &rx_mode);
3802out:
3803 kfree(uc_macs);
3804}
Linux kernel - Deliverables
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