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Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
f9f082a9 27#include <net/udp_tunnel.h>
e712d52b
YM		 28#include <linux/ip.h>
29#include <net/ipv6.h>
30#include <net/tcp.h>
31#include <linux/if_ether.h>
32#include <linux/if_vlan.h>
33#include <linux/pkt_sched.h>
34#include <linux/ethtool.h>
35#include <linux/in.h>
36#include <linux/random.h>
37#include <net/ip6_checksum.h>
38#include <linux/bitops.h>
39
40#include "qede.h"
41
5abd7e92
YM		 42static char version[] =
43 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 44
5abd7e92 45MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
49static uint debug;
50module_param(debug, uint, 0);
51MODULE_PARM_DESC(debug, " Default debug msglevel");
52
53static const struct qed_eth_ops *qed_ops;
54
55#define CHIP_NUM_57980S_40 0x1634
0e7441d7 56#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 57#define CHIP_NUM_57980S_MF 0x1636
58#define CHIP_NUM_57980S_100 0x1644
59#define CHIP_NUM_57980S_50 0x1654
60#define CHIP_NUM_57980S_25 0x1656
fefb0202 61#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 62
63#ifndef PCI_DEVICE_ID_NX2_57980E
64#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
65#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
66#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
67#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
68#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
69#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 70#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 71#endif
72
fefb0202
YM		 73enum qede_pci_private {
74 QEDE_PRIVATE_PF,
75 QEDE_PRIVATE_VF
76};
77
e712d52b 78static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 79 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
80 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
81 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
82 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
83 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 85#ifdef CONFIG_QED_SRIOV
fefb0202 86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
14b84e86 87#endif
e712d52b
YM		 88 { 0 }
89};
90
91MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
92
93static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
94
95#define TX_TIMEOUT (5 * HZ)
96
97static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 98static int qede_alloc_rx_buffer(struct qede_dev *edev,
99 struct qede_rx_queue *rxq);
a2ec6172 100static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 101
fefb0202 102#ifdef CONFIG_QED_SRIOV
08feecd7
YM		 103static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
104{
105 struct qede_dev *edev = netdev_priv(ndev);
106
107 if (vlan > 4095) {
108 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
109 return -EINVAL;
110 }
111
112 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
113 vlan, vf);
114
115 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
116}
117
eff16960
YM		 118static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
119{
120 struct qede_dev *edev = netdev_priv(ndev);
121
122 DP_VERBOSE(edev, QED_MSG_IOV,
123 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
124 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
125
126 if (!is_valid_ether_addr(mac)) {
127 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
128 return -EINVAL;
129 }
130
131 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
132}
133
fefb0202
YM		 134static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
135{
136 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e
YM		 137 struct qed_dev_info *qed_info = &edev->dev_info.common;
138 int rc;
fefb0202
YM		 139
140 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
141
831bfb0e
YM		 142 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
143
144 /* Enable/Disable Tx switching for PF */
145 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
146 qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
147 struct qed_update_vport_params params;
148
149 memset(&params, 0, sizeof(params));
150 params.vport_id = 0;
151 params.update_tx_switching_flg = 1;
152 params.tx_switching_flg = num_vfs_param ? 1 : 0;
153 edev->ops->vport_update(edev->cdev, &params);
154 }
155
156 return rc;
fefb0202
YM		 157}
158#endif
159
e712d52b
YM		 160static struct pci_driver qede_pci_driver = {
161 .name = "qede",
162 .id_table = qede_pci_tbl,
163 .probe = qede_probe,
164 .remove = qede_remove,
fefb0202
YM		 165#ifdef CONFIG_QED_SRIOV
166 .sriov_configure = qede_sriov_configure,
167#endif
e712d52b
YM		 168};
169
eff16960
YM		 170static void qede_force_mac(void *dev, u8 *mac)
171{
172 struct qede_dev *edev = dev;
173
174 ether_addr_copy(edev->ndev->dev_addr, mac);
175 ether_addr_copy(edev->primary_mac, mac);
176}
177
a2ec6172
SK		 178static struct qed_eth_cb_ops qede_ll_ops = {
179 {
180 .link_update = qede_link_update,
181 },
eff16960 182 .force_mac = qede_force_mac,
a2ec6172
SK		 183};
184
2950219d
YM		 185static int qede_netdev_event(struct notifier_block *this, unsigned long event,
186 void *ptr)
187{
188 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
189 struct ethtool_drvinfo drvinfo;
190 struct qede_dev *edev;
191
192 /* Currently only support name change */
193 if (event != NETDEV_CHANGENAME)
194 goto done;
195
196 /* Check whether this is a qede device */
197 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
198 goto done;
199
200 memset(&drvinfo, 0, sizeof(drvinfo));
201 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
202 if (strcmp(drvinfo.driver, "qede"))
203 goto done;
204 edev = netdev_priv(ndev);
205
206 /* Notify qed of the name change */
207 if (!edev->ops || !edev->ops->common)
208 goto done;
209 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
210 "qede");
211
212done:
213 return NOTIFY_DONE;
214}
215
216static struct notifier_block qede_netdev_notifier = {
217 .notifier_call = qede_netdev_event,
218};
219
e712d52b
YM		 220static
221int __init qede_init(void)
222{
223 int ret;
e712d52b
YM		 224
225 pr_notice("qede_init: %s\n", version);
226
95114344 227 qed_ops = qed_get_eth_ops();
e712d52b
YM		 228 if (!qed_ops) {
229 pr_notice("Failed to get qed ethtool operations\n");
230 return -EINVAL;
231 }
232
2950219d
YM		 233 /* Must register notifier before pci ops, since we might miss
234 * interface rename after pci probe and netdev registeration.
235 */
236 ret = register_netdevice_notifier(&qede_netdev_notifier);
237 if (ret) {
238 pr_notice("Failed to register netdevice_notifier\n");
239 qed_put_eth_ops();
240 return -EINVAL;
241 }
242
e712d52b
YM		 243 ret = pci_register_driver(&qede_pci_driver);
244 if (ret) {
245 pr_notice("Failed to register driver\n");
2950219d 246 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 247 qed_put_eth_ops();
248 return -EINVAL;
249 }
250
251 return 0;
252}
253
254static void __exit qede_cleanup(void)
255{
256 pr_notice("qede_cleanup called\n");
257
2950219d 258 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 259 pci_unregister_driver(&qede_pci_driver);
260 qed_put_eth_ops();
261}
262
263module_init(qede_init);
264module_exit(qede_cleanup);
265
2950219d
YM		 266/* -------------------------------------------------------------------------
267 * START OF FAST-PATH
268 * -------------------------------------------------------------------------
269 */
270
271/* Unmap the data and free skb */
272static int qede_free_tx_pkt(struct qede_dev *edev,
273 struct qede_tx_queue *txq,
274 int *len)
275{
276 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
277 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
278 struct eth_tx_1st_bd *first_bd;
279 struct eth_tx_bd *tx_data_bd;
280 int bds_consumed = 0;
281 int nbds;
282 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
283 int i, split_bd_len = 0;
284
285 if (unlikely(!skb)) {
286 DP_ERR(edev,
287 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
288 idx, txq->sw_tx_cons, txq->sw_tx_prod);
289 return -1;
290 }
291
292 *len = skb->len;
293
294 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
295
296 bds_consumed++;
297
298 nbds = first_bd->data.nbds;
299
300 if (data_split) {
301 struct eth_tx_bd *split = (struct eth_tx_bd *)
302 qed_chain_consume(&txq->tx_pbl);
303 split_bd_len = BD_UNMAP_LEN(split);
304 bds_consumed++;
305 }
306 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
307 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
308
309 /* Unmap the data of the skb frags */
310 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
311 tx_data_bd = (struct eth_tx_bd *)
312 qed_chain_consume(&txq->tx_pbl);
313 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
314 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
315 }
316
317 while (bds_consumed++ < nbds)
318 qed_chain_consume(&txq->tx_pbl);
319
320 /* Free skb */
321 dev_kfree_skb_any(skb);
322 txq->sw_tx_ring[idx].skb = NULL;
323 txq->sw_tx_ring[idx].flags = 0;
324
325 return 0;
326}
327
328/* Unmap the data and free skb when mapping failed during start_xmit */
329static void qede_free_failed_tx_pkt(struct qede_dev *edev,
330 struct qede_tx_queue *txq,
331 struct eth_tx_1st_bd *first_bd,
332 int nbd,
333 bool data_split)
334{
335 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
336 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
337 struct eth_tx_bd *tx_data_bd;
338 int i, split_bd_len = 0;
339
340 /* Return prod to its position before this skb was handled */
341 qed_chain_set_prod(&txq->tx_pbl,
342 le16_to_cpu(txq->tx_db.data.bd_prod),
343 first_bd);
344
345 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
346
347 if (data_split) {
348 struct eth_tx_bd *split = (struct eth_tx_bd *)
349 qed_chain_produce(&txq->tx_pbl);
350 split_bd_len = BD_UNMAP_LEN(split);
351 nbd--;
352 }
353
354 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
355 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
356
357 /* Unmap the data of the skb frags */
358 for (i = 0; i < nbd; i++) {
359 tx_data_bd = (struct eth_tx_bd *)
360 qed_chain_produce(&txq->tx_pbl);
361 if (tx_data_bd->nbytes)
362 dma_unmap_page(&edev->pdev->dev,
363 BD_UNMAP_ADDR(tx_data_bd),
364 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
365 }
366
367 /* Return again prod to its position before this skb was handled */
368 qed_chain_set_prod(&txq->tx_pbl,
369 le16_to_cpu(txq->tx_db.data.bd_prod),
370 first_bd);
371
372 /* Free skb */
373 dev_kfree_skb_any(skb);
374 txq->sw_tx_ring[idx].skb = NULL;
375 txq->sw_tx_ring[idx].flags = 0;
376}
377
378static u32 qede_xmit_type(struct qede_dev *edev,
379 struct sk_buff *skb,
380 int *ipv6_ext)
381{
382 u32 rc = XMIT_L4_CSUM;
383 __be16 l3_proto;
384
385 if (skb->ip_summed != CHECKSUM_PARTIAL)
386 return XMIT_PLAIN;
387
388 l3_proto = vlan_get_protocol(skb);
389 if (l3_proto == htons(ETH_P_IPV6) &&
390 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
391 *ipv6_ext = 1;
392
14db81de
MC		 393 if (skb->encapsulation)
394 rc |= XMIT_ENC;
395
2950219d
YM		 396 if (skb_is_gso(skb))
397 rc |= XMIT_LSO;
398
399 return rc;
400}
401
402static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
403 struct eth_tx_2nd_bd *second_bd,
404 struct eth_tx_3rd_bd *third_bd)
405{
406 u8 l4_proto;
fc48b7a6 407 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 408
fc48b7a6 409 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 410
fc48b7a6 411 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 412 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
413 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
414
fc48b7a6 415 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 416 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
417
418 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
419 l4_proto = ipv6_hdr(skb)->nexthdr;
420 else
421 l4_proto = ip_hdr(skb)->protocol;
422
423 if (l4_proto == IPPROTO_UDP)
fc48b7a6 424 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 425
fc48b7a6 426 if (third_bd)
2950219d 427 third_bd->data.bitfields |=
fc48b7a6
YM		 428 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
429 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
430 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 431
fc48b7a6 432 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 433 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
434}
435
436static int map_frag_to_bd(struct qede_dev *edev,
437 skb_frag_t *frag,
438 struct eth_tx_bd *bd)
439{
440 dma_addr_t mapping;
441
442 /* Map skb non-linear frag data for DMA */
443 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
444 skb_frag_size(frag),
445 DMA_TO_DEVICE);
446 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
447 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
448 return -ENOMEM;
449 }
450
451 /* Setup the data pointer of the frag data */
452 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
453
454 return 0;
455}
456
14db81de
MC		 457static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
458{
459 if (is_encap_pkt)
460 return (skb_inner_transport_header(skb) +
461 inner_tcp_hdrlen(skb) - skb->data);
462 else
463 return (skb_transport_header(skb) +
464 tcp_hdrlen(skb) - skb->data);
465}
466
b1199b10
YM		 467/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
468#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
469static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
470 u8 xmit_type)
471{
472 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
473
474 if (xmit_type & XMIT_LSO) {
475 int hlen;
476
14db81de 477 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 478
479 /* linear payload would require its own BD */
480 if (skb_headlen(skb) > hlen)
481 allowed_frags--;
482 }
483
484 return (skb_shinfo(skb)->nr_frags > allowed_frags);
485}
486#endif
487
312e0676
MC		 488static inline void qede_update_tx_producer(struct qede_tx_queue *txq)
489{
490 /* wmb makes sure that the BDs data is updated before updating the
491 * producer, otherwise FW may read old data from the BDs.
492 */
493 wmb();
494 barrier();
495 writel(txq->tx_db.raw, txq->doorbell_addr);
496
497 /* mmiowb is needed to synchronize doorbell writes from more than one
498 * processor. It guarantees that the write arrives to the device before
499 * the queue lock is released and another start_xmit is called (possibly
500 * on another CPU). Without this barrier, the next doorbell can bypass
501 * this doorbell. This is applicable to IA64/Altix systems.
502 */
503 mmiowb();
504}
505
2950219d
YM		 506/* Main transmit function */
507static
508netdev_tx_t qede_start_xmit(struct sk_buff *skb,
509 struct net_device *ndev)
510{
511 struct qede_dev *edev = netdev_priv(ndev);
512 struct netdev_queue *netdev_txq;
513 struct qede_tx_queue *txq;
514 struct eth_tx_1st_bd *first_bd;
515 struct eth_tx_2nd_bd *second_bd = NULL;
516 struct eth_tx_3rd_bd *third_bd = NULL;
517 struct eth_tx_bd *tx_data_bd = NULL;
518 u16 txq_index;
519 u8 nbd = 0;
520 dma_addr_t mapping;
521 int rc, frag_idx = 0, ipv6_ext = 0;
522 u8 xmit_type;
523 u16 idx;
524 u16 hlen;
810810ff 525 bool data_split = false;
2950219d
YM		 526
527 /* Get tx-queue context and netdev index */
528 txq_index = skb_get_queue_mapping(skb);
529 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
530 txq = QEDE_TX_QUEUE(edev, txq_index);
531 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
532
2950219d
YM		 533 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) <
534 (MAX_SKB_FRAGS + 1));
535
536 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
537
b1199b10
YM		 538#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
539 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
540 if (skb_linearize(skb)) {
541 DP_NOTICE(edev,
542 "SKB linearization failed - silently dropping this SKB\n");
543 dev_kfree_skb_any(skb);
544 return NETDEV_TX_OK;
545 }
546 }
547#endif
548
2950219d
YM		 549 /* Fill the entry in the SW ring and the BDs in the FW ring */
550 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
551 txq->sw_tx_ring[idx].skb = skb;
552 first_bd = (struct eth_tx_1st_bd *)
553 qed_chain_produce(&txq->tx_pbl);
554 memset(first_bd, 0, sizeof(*first_bd));
555 first_bd->data.bd_flags.bitfields =
556 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
557
558 /* Map skb linear data for DMA and set in the first BD */
559 mapping = dma_map_single(&edev->pdev->dev, skb->data,
560 skb_headlen(skb), DMA_TO_DEVICE);
561 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
562 DP_NOTICE(edev, "SKB mapping failed\n");
563 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
312e0676 564 qede_update_tx_producer(txq);
2950219d
YM		 565 return NETDEV_TX_OK;
566 }
567 nbd++;
568 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
569
570 /* In case there is IPv6 with extension headers or LSO we need 2nd and
571 * 3rd BDs.
572 */
573 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
574 second_bd = (struct eth_tx_2nd_bd *)
575 qed_chain_produce(&txq->tx_pbl);
576 memset(second_bd, 0, sizeof(*second_bd));
577
578 nbd++;
579 third_bd = (struct eth_tx_3rd_bd *)
580 qed_chain_produce(&txq->tx_pbl);
581 memset(third_bd, 0, sizeof(*third_bd));
582
583 nbd++;
584 /* We need to fill in additional data in second_bd... */
585 tx_data_bd = (struct eth_tx_bd *)second_bd;
586 }
587
588 if (skb_vlan_tag_present(skb)) {
589 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
590 first_bd->data.bd_flags.bitfields |=
591 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
592 }
593
594 /* Fill the parsing flags & params according to the requested offload */
595 if (xmit_type & XMIT_L4_CSUM) {
596 /* We don't re-calculate IP checksum as it is already done by
597 * the upper stack
598 */
599 first_bd->data.bd_flags.bitfields |=
600 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
601
14db81de
MC		 602 if (xmit_type & XMIT_ENC) {
603 first_bd->data.bd_flags.bitfields |=
604 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
351a4ded
YM		 605 first_bd->data.bitfields |=
606 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
14db81de 607 }
fc48b7a6 608
2950219d
YM		 609 /* If the packet is IPv6 with extension header, indicate that
610 * to FW and pass few params, since the device cracker doesn't
611 * support parsing IPv6 with extension header/s.
612 */
613 if (unlikely(ipv6_ext))
614 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
615 }
616
617 if (xmit_type & XMIT_LSO) {
618 first_bd->data.bd_flags.bitfields |=
619 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
620 third_bd->data.lso_mss =
621 cpu_to_le16(skb_shinfo(skb)->gso_size);
622
14db81de
MC		 623 if (unlikely(xmit_type & XMIT_ENC)) {
624 first_bd->data.bd_flags.bitfields |=
625 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
626 hlen = qede_get_skb_hlen(skb, true);
627 } else {
628 first_bd->data.bd_flags.bitfields |=
629 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
630 hlen = qede_get_skb_hlen(skb, false);
631 }
2950219d
YM		 632
633 /* @@@TBD - if will not be removed need to check */
634 third_bd->data.bitfields |=
fc48b7a6 635 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 636
637 /* Make life easier for FW guys who can't deal with header and
638 * data on same BD. If we need to split, use the second bd...
639 */
640 if (unlikely(skb_headlen(skb) > hlen)) {
641 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
642 "TSO split header size is %d (%x:%x)\n",
643 first_bd->nbytes, first_bd->addr.hi,
644 first_bd->addr.lo);
645
646 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
647 le32_to_cpu(first_bd->addr.lo)) +
648 hlen;
649
650 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
651 le16_to_cpu(first_bd->nbytes) -
652 hlen);
653
654 /* this marks the BD as one that has no
655 * individual mapping
656 */
657 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
658
659 first_bd->nbytes = cpu_to_le16(hlen);
660
661 tx_data_bd = (struct eth_tx_bd *)third_bd;
662 data_split = true;
663 }
351a4ded
YM		 664 } else {
665 first_bd->data.bitfields |=
666 (skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) <<
667 ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2950219d
YM		 668 }
669
670 /* Handle fragmented skb */
671 /* special handle for frags inside 2nd and 3rd bds.. */
672 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
673 rc = map_frag_to_bd(edev,
674 &skb_shinfo(skb)->frags[frag_idx],
675 tx_data_bd);
676 if (rc) {
677 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
678 data_split);
312e0676 679 qede_update_tx_producer(txq);
2950219d
YM		 680 return NETDEV_TX_OK;
681 }
682
683 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
684 tx_data_bd = (struct eth_tx_bd *)third_bd;
685 else
686 tx_data_bd = NULL;
687
688 frag_idx++;
689 }
690
691 /* map last frags into 4th, 5th .... */
692 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
693 tx_data_bd = (struct eth_tx_bd *)
694 qed_chain_produce(&txq->tx_pbl);
695
696 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
697
698 rc = map_frag_to_bd(edev,
699 &skb_shinfo(skb)->frags[frag_idx],
700 tx_data_bd);
701 if (rc) {
702 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
703 data_split);
312e0676 704 qede_update_tx_producer(txq);
2950219d
YM		 705 return NETDEV_TX_OK;
706 }
707 }
708
709 /* update the first BD with the actual num BDs */
710 first_bd->data.nbds = nbd;
711
712 netdev_tx_sent_queue(netdev_txq, skb->len);
713
714 skb_tx_timestamp(skb);
715
716 /* Advance packet producer only before sending the packet since mapping
717 * of pages may fail.
718 */
719 txq->sw_tx_prod++;
720
721 /* 'next page' entries are counted in the producer value */
722 txq->tx_db.data.bd_prod =
723 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
724
312e0676
MC		 725 if (!skb->xmit_more || netif_tx_queue_stopped(netdev_txq))
726 qede_update_tx_producer(txq);
2950219d
YM		 727
728 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
729 < (MAX_SKB_FRAGS + 1))) {
730 netif_tx_stop_queue(netdev_txq);
731 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
732 "Stop queue was called\n");
733 /* paired memory barrier is in qede_tx_int(), we have to keep
734 * ordering of set_bit() in netif_tx_stop_queue() and read of
735 * fp->bd_tx_cons
736 */
737 smp_mb();
738
739 if (qed_chain_get_elem_left(&txq->tx_pbl)
740 >= (MAX_SKB_FRAGS + 1) &&
741 (edev->state == QEDE_STATE_OPEN)) {
742 netif_tx_wake_queue(netdev_txq);
743 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
744 "Wake queue was called\n");
745 }
746 }
747
748 return NETDEV_TX_OK;
749}
750
16f46bf0 751int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 752{
753 u16 hw_bd_cons;
754
755 /* Tell compiler that consumer and producer can change */
756 barrier();
757 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
758 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
759 return 0;
760
761 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
762}
763
764static int qede_tx_int(struct qede_dev *edev,
765 struct qede_tx_queue *txq)
766{
767 struct netdev_queue *netdev_txq;
768 u16 hw_bd_cons;
769 unsigned int pkts_compl = 0, bytes_compl = 0;
770 int rc;
771
772 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
773
774 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
775 barrier();
776
777 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
778 int len = 0;
779
780 rc = qede_free_tx_pkt(edev, txq, &len);
781 if (rc) {
782 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
783 hw_bd_cons,
784 qed_chain_get_cons_idx(&txq->tx_pbl));
785 break;
786 }
787
788 bytes_compl += len;
789 pkts_compl++;
790 txq->sw_tx_cons++;
791 }
792
793 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
794
795 /* Need to make the tx_bd_cons update visible to start_xmit()
796 * before checking for netif_tx_queue_stopped(). Without the
797 * memory barrier, there is a small possibility that
798 * start_xmit() will miss it and cause the queue to be stopped
799 * forever.
800 * On the other hand we need an rmb() here to ensure the proper
801 * ordering of bit testing in the following
802 * netif_tx_queue_stopped(txq) call.
803 */
804 smp_mb();
805
806 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
807 /* Taking tx_lock is needed to prevent reenabling the queue
808 * while it's empty. This could have happen if rx_action() gets
809 * suspended in qede_tx_int() after the condition before
810 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
811 *
812 * stops the queue->sees fresh tx_bd_cons->releases the queue->
813 * sends some packets consuming the whole queue again->
814 * stops the queue
815 */
816
817 __netif_tx_lock(netdev_txq, smp_processor_id());
818
819 if ((netif_tx_queue_stopped(netdev_txq)) &&
820 (edev->state == QEDE_STATE_OPEN) &&
821 (qed_chain_get_elem_left(&txq->tx_pbl)
822 >= (MAX_SKB_FRAGS + 1))) {
823 netif_tx_wake_queue(netdev_txq);
824 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
825 "Wake queue was called\n");
826 }
827
828 __netif_tx_unlock(netdev_txq);
829 }
830
831 return 0;
832}
833
16f46bf0 834bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 835{
836 u16 hw_comp_cons, sw_comp_cons;
837
838 /* Tell compiler that status block fields can change */
839 barrier();
840
841 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
842 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
843
844 return hw_comp_cons != sw_comp_cons;
845}
846
847static bool qede_has_tx_work(struct qede_fastpath *fp)
848{
849 u8 tc;
850
851 for (tc = 0; tc < fp->edev->num_tc; tc++)
852 if (qede_txq_has_work(&fp->txqs[tc]))
853 return true;
854 return false;
855}
856
f86af2df
MC		 857static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
858{
859 qed_chain_consume(&rxq->rx_bd_ring);
860 rxq->sw_rx_cons++;
861}
862
fc48b7a6
YM		 863/* This function reuses the buffer(from an offset) from
864 * consumer index to producer index in the bd ring
2950219d 865 */
fc48b7a6
YM		 866static inline void qede_reuse_page(struct qede_dev *edev,
867 struct qede_rx_queue *rxq,
868 struct sw_rx_data *curr_cons)
2950219d 869{
2950219d 870 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 871 struct sw_rx_data *curr_prod;
872 dma_addr_t new_mapping;
2950219d 873
fc48b7a6
YM		 874 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
875 *curr_prod = *curr_cons;
2950219d 876
fc48b7a6
YM		 877 new_mapping = curr_prod->mapping + curr_prod->page_offset;
878
879 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
880 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 881
2950219d 882 rxq->sw_rx_prod++;
fc48b7a6
YM		 883 curr_cons->data = NULL;
884}
885
f86af2df
MC		 886/* In case of allocation failures reuse buffers
887 * from consumer index to produce buffers for firmware
888 */
16f46bf0
SRK		 889void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
890 struct qede_dev *edev, u8 count)
f86af2df
MC		 891{
892 struct sw_rx_data *curr_cons;
893
894 for (; count > 0; count--) {
895 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
896 qede_reuse_page(edev, rxq, curr_cons);
897 qede_rx_bd_ring_consume(rxq);
898 }
899}
900
fc48b7a6
YM		 901static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
902 struct qede_rx_queue *rxq,
903 struct sw_rx_data *curr_cons)
904{
905 /* Move to the next segment in the page */
906 curr_cons->page_offset += rxq->rx_buf_seg_size;
907
908 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 909 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
910 /* Since we failed to allocate new buffer
911 * current buffer can be used again.
912 */
913 curr_cons->page_offset -= rxq->rx_buf_seg_size;
914
fc48b7a6 915 return -ENOMEM;
f86af2df 916 }
fc48b7a6
YM		 917
918 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
919 PAGE_SIZE, DMA_FROM_DEVICE);
920 } else {
921 /* Increment refcount of the page as we don't want
922 * network stack to take the ownership of the page
923 * which can be recycled multiple times by the driver.
924 */
6d061f9f 925 page_ref_inc(curr_cons->data);
fc48b7a6
YM		 926 qede_reuse_page(edev, rxq, curr_cons);
927 }
928
929 return 0;
2950219d
YM		 930}
931
932static inline void qede_update_rx_prod(struct qede_dev *edev,
933 struct qede_rx_queue *rxq)
934{
935 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
936 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
937 struct eth_rx_prod_data rx_prods = {0};
938
939 /* Update producers */
940 rx_prods.bd_prod = cpu_to_le16(bd_prod);
941 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
942
943 /* Make sure that the BD and SGE data is updated before updating the
944 * producers since FW might read the BD/SGE right after the producer
945 * is updated.
946 */
947 wmb();
948
949 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
950 (u32 *)&rx_prods);
951
952 /* mmiowb is needed to synchronize doorbell writes from more than one
953 * processor. It guarantees that the write arrives to the device before
954 * the napi lock is released and another qede_poll is called (possibly
955 * on another CPU). Without this barrier, the next doorbell can bypass
956 * this doorbell. This is applicable to IA64/Altix systems.
957 */
958 mmiowb();
959}
960
961static u32 qede_get_rxhash(struct qede_dev *edev,
962 u8 bitfields,
963 __le32 rss_hash,
964 enum pkt_hash_types *rxhash_type)
965{
966 enum rss_hash_type htype;
967
968 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
969
970 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
971 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
972 (htype == RSS_HASH_TYPE_IPV6)) ?
973 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
974 return le32_to_cpu(rss_hash);
975 }
976 *rxhash_type = PKT_HASH_TYPE_NONE;
977 return 0;
978}
979
980static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
981{
982 skb_checksum_none_assert(skb);
983
984 if (csum_flag & QEDE_CSUM_UNNECESSARY)
985 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 986
987 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
988 skb->csum_level = 1;
2950219d
YM		 989}
990
991static inline void qede_skb_receive(struct qede_dev *edev,
992 struct qede_fastpath *fp,
993 struct sk_buff *skb,
994 u16 vlan_tag)
995{
996 if (vlan_tag)
997 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
998 vlan_tag);
999
1000 napi_gro_receive(&fp->napi, skb);
1001}
1002
55482edc
MC		 1003static void qede_set_gro_params(struct qede_dev *edev,
1004 struct sk_buff *skb,
1005 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1006{
1007 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
1008
1009 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
1010 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
1011 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
1012 else
1013 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1014
1015 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
1016 cqe->header_len;
1017}
1018
1019static int qede_fill_frag_skb(struct qede_dev *edev,
1020 struct qede_rx_queue *rxq,
1021 u8 tpa_agg_index,
1022 u16 len_on_bd)
1023{
1024 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
1025 NUM_RX_BDS_MAX];
1026 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
1027 struct sk_buff *skb = tpa_info->skb;
1028
1029 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1030 goto out;
1031
1032 /* Add one frag and update the appropriate fields in the skb */
1033 skb_fill_page_desc(skb, tpa_info->frag_id++,
1034 current_bd->data, current_bd->page_offset,
1035 len_on_bd);
1036
1037 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 1038 /* Incr page ref count to reuse on allocation failure
1039 * so that it doesn't get freed while freeing SKB.
1040 */
0139aa7b 1041 page_ref_inc(current_bd->data);
55482edc
MC		 1042 goto out;
1043 }
1044
1045 qed_chain_consume(&rxq->rx_bd_ring);
1046 rxq->sw_rx_cons++;
1047
1048 skb->data_len += len_on_bd;
1049 skb->truesize += rxq->rx_buf_seg_size;
1050 skb->len += len_on_bd;
1051
1052 return 0;
1053
1054out:
f86af2df
MC		 1055 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1056 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1057 return -ENOMEM;
1058}
1059
1060static void qede_tpa_start(struct qede_dev *edev,
1061 struct qede_rx_queue *rxq,
1062 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1063{
1064 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1065 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1066 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
1067 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
1068 dma_addr_t mapping = tpa_info->replace_buf_mapping;
1069 struct sw_rx_data *sw_rx_data_cons;
1070 struct sw_rx_data *sw_rx_data_prod;
1071 enum pkt_hash_types rxhash_type;
1072 u32 rxhash;
1073
1074 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1075 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1076
1077 /* Use pre-allocated replacement buffer - we can't release the agg.
1078 * start until its over and we don't want to risk allocation failing
1079 * here, so re-allocate when aggregation will be over.
1080 */
09ec8e7f 1081 sw_rx_data_prod->mapping = replace_buf->mapping;
55482edc
MC		 1082
1083 sw_rx_data_prod->data = replace_buf->data;
1084 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1085 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1086 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1087
1088 rxq->sw_rx_prod++;
1089
1090 /* move partial skb from cons to pool (don't unmap yet)
1091 * save mapping, incase we drop the packet later on.
1092 */
1093 tpa_info->start_buf = *sw_rx_data_cons;
1094 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1095 le32_to_cpu(rx_bd_cons->addr.lo));
1096
1097 tpa_info->start_buf_mapping = mapping;
1098 rxq->sw_rx_cons++;
1099
1100 /* set tpa state to start only if we are able to allocate skb
1101 * for this aggregation, otherwise mark as error and aggregation will
1102 * be dropped
1103 */
1104 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1105 le16_to_cpu(cqe->len_on_first_bd));
1106 if (unlikely(!tpa_info->skb)) {
f86af2df 1107 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1108 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1109 goto cons_buf;
55482edc
MC		 1110 }
1111
1112 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1113 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1114
1115 /* Start filling in the aggregation info */
1116 tpa_info->frag_id = 0;
1117 tpa_info->agg_state = QEDE_AGG_STATE_START;
1118
1119 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1120 cqe->rss_hash, &rxhash_type);
1121 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1122 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1123 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1124 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1125 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1126 else
1127 tpa_info->vlan_tag = 0;
1128
1129 /* This is needed in order to enable forwarding support */
1130 qede_set_gro_params(edev, tpa_info->skb, cqe);
1131
f86af2df 1132cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1133 if (likely(cqe->ext_bd_len_list[0]))
1134 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1135 le16_to_cpu(cqe->ext_bd_len_list[0]));
1136
1137 if (unlikely(cqe->ext_bd_len_list[1])) {
1138 DP_ERR(edev,
1139 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1140 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1141 }
1142}
1143
88f09bd5 1144#ifdef CONFIG_INET
55482edc
MC		 1145static void qede_gro_ip_csum(struct sk_buff *skb)
1146{
1147 const struct iphdr *iph = ip_hdr(skb);
1148 struct tcphdr *th;
1149
55482edc
MC		 1150 skb_set_transport_header(skb, sizeof(struct iphdr));
1151 th = tcp_hdr(skb);
1152
1153 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1154 iph->saddr, iph->daddr, 0);
1155
1156 tcp_gro_complete(skb);
1157}
1158
1159static void qede_gro_ipv6_csum(struct sk_buff *skb)
1160{
1161 struct ipv6hdr *iph = ipv6_hdr(skb);
1162 struct tcphdr *th;
1163
55482edc
MC		 1164 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1165 th = tcp_hdr(skb);
1166
1167 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1168 &iph->saddr, &iph->daddr, 0);
1169 tcp_gro_complete(skb);
1170}
88f09bd5 1171#endif
55482edc
MC		 1172
1173static void qede_gro_receive(struct qede_dev *edev,
1174 struct qede_fastpath *fp,
1175 struct sk_buff *skb,
1176 u16 vlan_tag)
1177{
ee2fa8e6
MC		 1178 /* FW can send a single MTU sized packet from gro flow
1179 * due to aggregation timeout/last segment etc. which
1180 * is not expected to be a gro packet. If a skb has zero
1181 * frags then simply push it in the stack as non gso skb.
1182 */
1183 if (unlikely(!skb->data_len)) {
1184 skb_shinfo(skb)->gso_type = 0;
1185 skb_shinfo(skb)->gso_size = 0;
1186 goto send_skb;
1187 }
1188
88f09bd5 1189#ifdef CONFIG_INET
55482edc 1190 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1191 skb_set_network_header(skb, 0);
1192
55482edc
MC		 1193 switch (skb->protocol) {
1194 case htons(ETH_P_IP):
1195 qede_gro_ip_csum(skb);
1196 break;
1197 case htons(ETH_P_IPV6):
1198 qede_gro_ipv6_csum(skb);
1199 break;
1200 default:
1201 DP_ERR(edev,
1202 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1203 ntohs(skb->protocol));
1204 }
1205 }
88f09bd5 1206#endif
ee2fa8e6
MC		 1207
1208send_skb:
55482edc
MC		 1209 skb_record_rx_queue(skb, fp->rss_id);
1210 qede_skb_receive(edev, fp, skb, vlan_tag);
1211}
1212
1213static inline void qede_tpa_cont(struct qede_dev *edev,
1214 struct qede_rx_queue *rxq,
1215 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1216{
1217 int i;
1218
1219 for (i = 0; cqe->len_list[i]; i++)
1220 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1221 le16_to_cpu(cqe->len_list[i]));
1222
1223 if (unlikely(i > 1))
1224 DP_ERR(edev,
1225 "Strange - TPA cont with more than a single len_list entry\n");
1226}
1227
1228static void qede_tpa_end(struct qede_dev *edev,
1229 struct qede_fastpath *fp,
1230 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1231{
1232 struct qede_rx_queue *rxq = fp->rxq;
1233 struct qede_agg_info *tpa_info;
1234 struct sk_buff *skb;
1235 int i;
1236
1237 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1238 skb = tpa_info->skb;
1239
1240 for (i = 0; cqe->len_list[i]; i++)
1241 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1242 le16_to_cpu(cqe->len_list[i]));
1243 if (unlikely(i > 1))
1244 DP_ERR(edev,
1245 "Strange - TPA emd with more than a single len_list entry\n");
1246
1247 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1248 goto err;
1249
1250 /* Sanity */
1251 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1252 DP_ERR(edev,
1253 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1254 cqe->num_of_bds, tpa_info->frag_id);
1255 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1256 DP_ERR(edev,
1257 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1258 le16_to_cpu(cqe->total_packet_len), skb->len);
1259
1260 memcpy(skb->data,
1261 page_address(tpa_info->start_buf.data) +
1262 tpa_info->start_cqe.placement_offset +
1263 tpa_info->start_buf.page_offset,
1264 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1265
1266 /* Recycle [mapped] start buffer for the next replacement */
1267 tpa_info->replace_buf = tpa_info->start_buf;
1268 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1269
1270 /* Finalize the SKB */
1271 skb->protocol = eth_type_trans(skb, edev->ndev);
1272 skb->ip_summed = CHECKSUM_UNNECESSARY;
1273
1274 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1275 * to skb_shinfo(skb)->gso_segs
1276 */
1277 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1278
1279 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1280
1281 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1282
1283 return;
1284err:
1285 /* The BD starting the aggregation is still mapped; Re-use it for
1286 * future aggregations [as replacement buffer]
1287 */
1288 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1289 sizeof(struct sw_rx_data));
1290 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1291 tpa_info->start_buf.data = NULL;
1292 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1293 dev_kfree_skb_any(tpa_info->skb);
1294 tpa_info->skb = NULL;
1295}
1296
14db81de
MC		 1297static bool qede_tunn_exist(u16 flag)
1298{
1299 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1300 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1301}
1302
1303static u8 qede_check_tunn_csum(u16 flag)
1304{
1305 u16 csum_flag = 0;
1306 u8 tcsum = 0;
1307
1308 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1309 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1310 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1311 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1312
1313 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1314 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1315 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1316 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1317 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1318 }
1319
1320 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1321 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1322 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1323 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1324
1325 if (csum_flag & flag)
1326 return QEDE_CSUM_ERROR;
1327
1328 return QEDE_CSUM_UNNECESSARY | tcsum;
1329}
1330
1331static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1332{
1333 u16 csum_flag = 0;
1334 u8 csum = 0;
1335
14db81de
MC		 1336 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1337 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1338 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1339 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1340 csum = QEDE_CSUM_UNNECESSARY;
1341 }
1342
1343 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1344 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1345
1346 if (csum_flag & flag)
1347 return QEDE_CSUM_ERROR;
1348
1349 return csum;
1350}
1351
14db81de
MC		 1352static u8 qede_check_csum(u16 flag)
1353{
1354 if (!qede_tunn_exist(flag))
1355 return qede_check_notunn_csum(flag);
1356 else
1357 return qede_check_tunn_csum(flag);
1358}
1359
c72a6125
MC		 1360static bool qede_pkt_is_ip_fragmented(struct eth_fast_path_rx_reg_cqe *cqe,
1361 u16 flag)
1362{
1363 u8 tun_pars_flg = cqe->tunnel_pars_flags.flags;
1364
1365 if ((tun_pars_flg & (ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK <<
1366 ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT)) ||
1367 (flag & (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1368 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT)))
1369 return true;
1370
1371 return false;
1372}
1373
2950219d
YM		 1374static int qede_rx_int(struct qede_fastpath *fp, int budget)
1375{
1376 struct qede_dev *edev = fp->edev;
1377 struct qede_rx_queue *rxq = fp->rxq;
1378
1379 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1380 int rx_pkt = 0;
1381 u8 csum_flag;
1382
1383 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1384 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1385
1386 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1387 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1388 * read before it is written by FW, then FW writes CQE and SB, and then
1389 * the CPU reads the hw_comp_cons, it will use an old CQE.
1390 */
1391 rmb();
1392
1393 /* Loop to complete all indicated BDs */
1394 while (sw_comp_cons != hw_comp_cons) {
1395 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1396 enum pkt_hash_types rxhash_type;
1397 enum eth_rx_cqe_type cqe_type;
1398 struct sw_rx_data *sw_rx_data;
1399 union eth_rx_cqe *cqe;
1400 struct sk_buff *skb;
fc48b7a6
YM		 1401 struct page *data;
1402 __le16 flags;
2950219d
YM		 1403 u16 len, pad;
1404 u32 rx_hash;
2950219d
YM		 1405
1406 /* Get the CQE from the completion ring */
1407 cqe = (union eth_rx_cqe *)
1408 qed_chain_consume(&rxq->rx_comp_ring);
1409 cqe_type = cqe->fast_path_regular.type;
1410
1411 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1412 edev->ops->eth_cqe_completion(
1413 edev->cdev, fp->rss_id,
1414 (struct eth_slow_path_rx_cqe *)cqe);
1415 goto next_cqe;
1416 }
1417
55482edc
MC		 1418 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1419 switch (cqe_type) {
1420 case ETH_RX_CQE_TYPE_TPA_START:
1421 qede_tpa_start(edev, rxq,
1422 &cqe->fast_path_tpa_start);
1423 goto next_cqe;
1424 case ETH_RX_CQE_TYPE_TPA_CONT:
1425 qede_tpa_cont(edev, rxq,
1426 &cqe->fast_path_tpa_cont);
1427 goto next_cqe;
1428 case ETH_RX_CQE_TYPE_TPA_END:
1429 qede_tpa_end(edev, fp,
1430 &cqe->fast_path_tpa_end);
1431 goto next_rx_only;
1432 default:
1433 break;
1434 }
1435 }
1436
2950219d
YM		 1437 /* Get the data from the SW ring */
1438 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1439 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1440 data = sw_rx_data->data;
1441
1442 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1443 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1444 pad = fp_cqe->placement_offset;
fc48b7a6 1445 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1446
fc48b7a6
YM		 1447 /* If this is an error packet then drop it */
1448 parse_flag = le16_to_cpu(flags);
2950219d 1449
fc48b7a6
YM		 1450 csum_flag = qede_check_csum(parse_flag);
1451 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
c72a6125
MC		 1452 if (qede_pkt_is_ip_fragmented(&cqe->fast_path_regular,
1453 parse_flag)) {
1454 rxq->rx_ip_frags++;
1455 goto alloc_skb;
1456 }
1457
fc48b7a6
YM		 1458 DP_NOTICE(edev,
1459 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1460 sw_comp_cons, parse_flag);
1461 rxq->rx_hw_errors++;
f86af2df
MC		 1462 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1463 goto next_cqe;
fc48b7a6 1464 }
2950219d 1465
c72a6125 1466alloc_skb:
fc48b7a6
YM		 1467 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1468 if (unlikely(!skb)) {
2950219d 1469 DP_NOTICE(edev,
fc48b7a6 1470 "Build_skb failed, dropping incoming packet\n");
f86af2df 1471 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1472 rxq->rx_alloc_errors++;
f86af2df 1473 goto next_cqe;
fc48b7a6
YM		 1474 }
1475
1476 /* Copy data into SKB */
3d789994 1477 if (len + pad <= edev->rx_copybreak) {
fc48b7a6
YM		 1478 memcpy(skb_put(skb, len),
1479 page_address(data) + pad +
1480 sw_rx_data->page_offset, len);
1481 qede_reuse_page(edev, rxq, sw_rx_data);
1482 } else {
1483 struct skb_frag_struct *frag;
1484 unsigned int pull_len;
1485 unsigned char *va;
1486
1487 frag = &skb_shinfo(skb)->frags[0];
1488
1489 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1490 pad + sw_rx_data->page_offset,
1491 len, rxq->rx_buf_seg_size);
1492
1493 va = skb_frag_address(frag);
1494 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1495
1496 /* Align the pull_len to optimize memcpy */
1497 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1498
1499 skb_frag_size_sub(frag, pull_len);
1500 frag->page_offset += pull_len;
1501 skb->data_len -= pull_len;
1502 skb->tail += pull_len;
1503
1504 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1505 sw_rx_data))) {
1506 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1507 /* Incr page ref count to reuse on allocation
1508 * failure so that it doesn't get freed while
1509 * freeing SKB.
1510 */
1511
0139aa7b 1512 page_ref_inc(sw_rx_data->data);
fc48b7a6 1513 rxq->rx_alloc_errors++;
f86af2df
MC		 1514 qede_recycle_rx_bd_ring(rxq, edev,
1515 fp_cqe->bd_num);
1516 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1517 goto next_cqe;
1518 }
2950219d
YM		 1519 }
1520
f86af2df
MC		 1521 qede_rx_bd_ring_consume(rxq);
1522
fc48b7a6
YM		 1523 if (fp_cqe->bd_num != 1) {
1524 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1525 u8 num_frags;
1526
1527 pkt_len -= len;
1528
1529 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1530 num_frags--) {
1531 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1532 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1533 if (unlikely(!cur_size)) {
1534 DP_ERR(edev,
1535 "Still got %d BDs for mapping jumbo, but length became 0\n",
1536 num_frags);
1537 qede_recycle_rx_bd_ring(rxq, edev,
1538 num_frags);
1539 dev_kfree_skb_any(skb);
1540 goto next_cqe;
1541 }
fc48b7a6 1542
f86af2df
MC		 1543 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1544 qede_recycle_rx_bd_ring(rxq, edev,
1545 num_frags);
1546 dev_kfree_skb_any(skb);
fc48b7a6 1547 goto next_cqe;
f86af2df 1548 }
fc48b7a6 1549
fc48b7a6
YM		 1550 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1551 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1552 qede_rx_bd_ring_consume(rxq);
1553
fc48b7a6
YM		 1554 dma_unmap_page(&edev->pdev->dev,
1555 sw_rx_data->mapping,
1556 PAGE_SIZE, DMA_FROM_DEVICE);
1557
1558 skb_fill_page_desc(skb,
1559 skb_shinfo(skb)->nr_frags++,
1560 sw_rx_data->data, 0,
1561 cur_size);
1562
1563 skb->truesize += PAGE_SIZE;
1564 skb->data_len += cur_size;
1565 skb->len += cur_size;
1566 pkt_len -= cur_size;
1567 }
2950219d 1568
f86af2df 1569 if (unlikely(pkt_len))
fc48b7a6
YM		 1570 DP_ERR(edev,
1571 "Mapped all BDs of jumbo, but still have %d bytes\n",
1572 pkt_len);
1573 }
2950219d
YM		 1574
1575 skb->protocol = eth_type_trans(skb, edev->ndev);
1576
1577 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1578 fp_cqe->rss_hash,
1579 &rxhash_type);
1580
1581 skb_set_hash(skb, rx_hash, rxhash_type);
1582
1583 qede_set_skb_csum(skb, csum_flag);
1584
1585 skb_record_rx_queue(skb, fp->rss_id);
1586
1587 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1588next_rx_only:
2950219d
YM		 1589 rx_pkt++;
1590
1591next_cqe: /* don't consume bd rx buffer */
1592 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1593 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1594 /* CR TPA - revisit how to handle budget in TPA perhaps
1595 * increase on "end"
1596 */
1597 if (rx_pkt == budget)
1598 break;
1599 } /* repeat while sw_comp_cons != hw_comp_cons... */
1600
1601 /* Update producers */
1602 qede_update_rx_prod(edev, rxq);
1603
1604 return rx_pkt;
1605}
1606
1607static int qede_poll(struct napi_struct *napi, int budget)
1608{
2950219d 1609 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
c774169d 1610 napi);
2950219d 1611 struct qede_dev *edev = fp->edev;
c774169d
MC		 1612 int rx_work_done = 0;
1613 u8 tc;
2950219d 1614
c774169d
MC		 1615 for (tc = 0; tc < edev->num_tc; tc++)
1616 if (qede_txq_has_work(&fp->txqs[tc]))
1617 qede_tx_int(edev, &fp->txqs[tc]);
1618
1619 rx_work_done = qede_has_rx_work(fp->rxq) ?
1620 qede_rx_int(fp, budget) : 0;
1621 if (rx_work_done < budget) {
1622 qed_sb_update_sb_idx(fp->sb_info);
1623 /* *_has_*_work() reads the status block,
1624 * thus we need to ensure that status block indices
1625 * have been actually read (qed_sb_update_sb_idx)
1626 * prior to this check (*_has_*_work) so that
1627 * we won't write the "newer" value of the status block
1628 * to HW (if there was a DMA right after
1629 * qede_has_rx_work and if there is no rmb, the memory
1630 * reading (qed_sb_update_sb_idx) may be postponed
1631 * to right before *_ack_sb). In this case there
1632 * will never be another interrupt until there is
1633 * another update of the status block, while there
1634 * is still unhandled work.
1635 */
1636 rmb();
2950219d
YM		 1637
1638 /* Fall out from the NAPI loop if needed */
c774169d
MC		 1639 if (!(qede_has_rx_work(fp->rxq) ||
1640 qede_has_tx_work(fp))) {
1641 napi_complete(napi);
1642
1643 /* Update and reenable interrupts */
1644 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1645 1 /*update*/);
1646 } else {
1647 rx_work_done = budget;
2950219d
YM		 1648 }
1649 }
1650
c774169d 1651 return rx_work_done;
2950219d
YM		 1652}
1653
1654static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1655{
1656 struct qede_fastpath *fp = fp_cookie;
1657
1658 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1659
1660 napi_schedule_irqoff(&fp->napi);
1661 return IRQ_HANDLED;
1662}
1663
1664/* -------------------------------------------------------------------------
1665 * END OF FAST-PATH
1666 * -------------------------------------------------------------------------
1667 */
1668
1669static int qede_open(struct net_device *ndev);
1670static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1671static int qede_set_mac_addr(struct net_device *ndev, void *p);
1672static void qede_set_rx_mode(struct net_device *ndev);
1673static void qede_config_rx_mode(struct net_device *ndev);
1674
1675static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1676 enum qed_filter_xcast_params_type opcode,
1677 unsigned char mac[ETH_ALEN])
1678{
1679 struct qed_filter_params filter_cmd;
1680
1681 memset(&filter_cmd, 0, sizeof(filter_cmd));
1682 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1683 filter_cmd.filter.ucast.type = opcode;
1684 filter_cmd.filter.ucast.mac_valid = 1;
1685 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1686
1687 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1688}
1689
7c1bfcad
SRK		 1690static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1691 enum qed_filter_xcast_params_type opcode,
1692 u16 vid)
1693{
1694 struct qed_filter_params filter_cmd;
1695
1696 memset(&filter_cmd, 0, sizeof(filter_cmd));
1697 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1698 filter_cmd.filter.ucast.type = opcode;
1699 filter_cmd.filter.ucast.vlan_valid = 1;
1700 filter_cmd.filter.ucast.vlan = vid;
1701
1702 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1703}
1704
133fac0e
SK		 1705void qede_fill_by_demand_stats(struct qede_dev *edev)
1706{
1707 struct qed_eth_stats stats;
1708
1709 edev->ops->get_vport_stats(edev->cdev, &stats);
1710 edev->stats.no_buff_discards = stats.no_buff_discards;
1711 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1712 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1713 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1714 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1715 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1716 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1717 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1718 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1719
1720 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1721 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1722 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1723 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1724 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1725 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1726 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1727 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1728 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1729 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1730 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1731 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1732
1733 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1734 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1735 edev->stats.rx_128_to_255_byte_packets =
1736 stats.rx_128_to_255_byte_packets;
1737 edev->stats.rx_256_to_511_byte_packets =
1738 stats.rx_256_to_511_byte_packets;
1739 edev->stats.rx_512_to_1023_byte_packets =
1740 stats.rx_512_to_1023_byte_packets;
1741 edev->stats.rx_1024_to_1518_byte_packets =
1742 stats.rx_1024_to_1518_byte_packets;
1743 edev->stats.rx_1519_to_1522_byte_packets =
1744 stats.rx_1519_to_1522_byte_packets;
1745 edev->stats.rx_1519_to_2047_byte_packets =
1746 stats.rx_1519_to_2047_byte_packets;
1747 edev->stats.rx_2048_to_4095_byte_packets =
1748 stats.rx_2048_to_4095_byte_packets;
1749 edev->stats.rx_4096_to_9216_byte_packets =
1750 stats.rx_4096_to_9216_byte_packets;
1751 edev->stats.rx_9217_to_16383_byte_packets =
1752 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1753 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1754 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1755 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1756 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1757 edev->stats.rx_align_errors = stats.rx_align_errors;
1758 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1759 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1760 edev->stats.rx_jabbers = stats.rx_jabbers;
1761 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1762 edev->stats.rx_fragments = stats.rx_fragments;
1763 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1764 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1765 edev->stats.tx_128_to_255_byte_packets =
1766 stats.tx_128_to_255_byte_packets;
1767 edev->stats.tx_256_to_511_byte_packets =
1768 stats.tx_256_to_511_byte_packets;
1769 edev->stats.tx_512_to_1023_byte_packets =
1770 stats.tx_512_to_1023_byte_packets;
1771 edev->stats.tx_1024_to_1518_byte_packets =
1772 stats.tx_1024_to_1518_byte_packets;
1773 edev->stats.tx_1519_to_2047_byte_packets =
1774 stats.tx_1519_to_2047_byte_packets;
1775 edev->stats.tx_2048_to_4095_byte_packets =
1776 stats.tx_2048_to_4095_byte_packets;
1777 edev->stats.tx_4096_to_9216_byte_packets =
1778 stats.tx_4096_to_9216_byte_packets;
1779 edev->stats.tx_9217_to_16383_byte_packets =
1780 stats.tx_9217_to_16383_byte_packets;
1781 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1782 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1783 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1784 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1785 edev->stats.brb_truncates = stats.brb_truncates;
1786 edev->stats.brb_discards = stats.brb_discards;
1787 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1788}
1789
1790static struct rtnl_link_stats64 *qede_get_stats64(
1791 struct net_device *dev,
1792 struct rtnl_link_stats64 *stats)
1793{
1794 struct qede_dev *edev = netdev_priv(dev);
1795
1796 qede_fill_by_demand_stats(edev);
1797
1798 stats->rx_packets = edev->stats.rx_ucast_pkts +
1799 edev->stats.rx_mcast_pkts +
1800 edev->stats.rx_bcast_pkts;
1801 stats->tx_packets = edev->stats.tx_ucast_pkts +
1802 edev->stats.tx_mcast_pkts +
1803 edev->stats.tx_bcast_pkts;
1804
1805 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1806 edev->stats.rx_mcast_bytes +
1807 edev->stats.rx_bcast_bytes;
1808
1809 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1810 edev->stats.tx_mcast_bytes +
1811 edev->stats.tx_bcast_bytes;
1812
1813 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1814 stats->multicast = edev->stats.rx_mcast_pkts +
1815 edev->stats.rx_bcast_pkts;
1816
1817 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1818
1819 stats->collisions = edev->stats.tx_total_collisions;
1820 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1821 stats->rx_frame_errors = edev->stats.rx_align_errors;
1822
1823 return stats;
1824}
1825
733def6a 1826#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 1827static int qede_get_vf_config(struct net_device *dev, int vfidx,
1828 struct ifla_vf_info *ivi)
1829{
1830 struct qede_dev *edev = netdev_priv(dev);
1831
1832 if (!edev->ops)
1833 return -EINVAL;
1834
1835 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
1836}
1837
733def6a
YM		 1838static int qede_set_vf_rate(struct net_device *dev, int vfidx,
1839 int min_tx_rate, int max_tx_rate)
1840{
1841 struct qede_dev *edev = netdev_priv(dev);
1842
be7b6d64 1843 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 1844 max_tx_rate);
1845}
1846
6ddc7608
YM		 1847static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
1848{
1849 struct qede_dev *edev = netdev_priv(dev);
1850
1851 if (!edev->ops)
1852 return -EINVAL;
1853
1854 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
1855}
1856
733def6a
YM		 1857static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
1858 int link_state)
1859{
1860 struct qede_dev *edev = netdev_priv(dev);
1861
1862 if (!edev->ops)
1863 return -EINVAL;
1864
1865 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
1866}
1867#endif
1868
7c1bfcad
SRK		 1869static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1870{
1871 struct qed_update_vport_params params;
1872 int rc;
1873
1874 /* Proceed only if action actually needs to be performed */
1875 if (edev->accept_any_vlan == action)
1876 return;
1877
1878 memset(&params, 0, sizeof(params));
1879
1880 params.vport_id = 0;
1881 params.accept_any_vlan = action;
1882 params.update_accept_any_vlan_flg = 1;
1883
1884 rc = edev->ops->vport_update(edev->cdev, &params);
1885 if (rc) {
1886 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1887 action ? "enable" : "disable");
1888 } else {
1889 DP_INFO(edev, "%s accept-any-vlan\n",
1890 action ? "enabled" : "disabled");
1891 edev->accept_any_vlan = action;
1892 }
1893}
1894
1895static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1896{
1897 struct qede_dev *edev = netdev_priv(dev);
1898 struct qede_vlan *vlan, *tmp;
1899 int rc;
1900
1901 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1902
1903 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1904 if (!vlan) {
1905 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1906 return -ENOMEM;
1907 }
1908 INIT_LIST_HEAD(&vlan->list);
1909 vlan->vid = vid;
1910 vlan->configured = false;
1911
1912 /* Verify vlan isn't already configured */
1913 list_for_each_entry(tmp, &edev->vlan_list, list) {
1914 if (tmp->vid == vlan->vid) {
1915 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1916 "vlan already configured\n");
1917 kfree(vlan);
1918 return -EEXIST;
1919 }
1920 }
1921
1922 /* If interface is down, cache this VLAN ID and return */
1923 if (edev->state != QEDE_STATE_OPEN) {
1924 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1925 "Interface is down, VLAN %d will be configured when interface is up\n",
1926 vid);
1927 if (vid != 0)
1928 edev->non_configured_vlans++;
1929 list_add(&vlan->list, &edev->vlan_list);
1930
1931 return 0;
1932 }
1933
1934 /* Check for the filter limit.
1935 * Note - vlan0 has a reserved filter and can be added without
1936 * worrying about quota
1937 */
1938 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1939 (vlan->vid == 0)) {
1940 rc = qede_set_ucast_rx_vlan(edev,
1941 QED_FILTER_XCAST_TYPE_ADD,
1942 vlan->vid);
1943 if (rc) {
1944 DP_ERR(edev, "Failed to configure VLAN %d\n",
1945 vlan->vid);
1946 kfree(vlan);
1947 return -EINVAL;
1948 }
1949 vlan->configured = true;
1950
1951 /* vlan0 filter isn't consuming out of our quota */
1952 if (vlan->vid != 0)
1953 edev->configured_vlans++;
1954 } else {
1955 /* Out of quota; Activate accept-any-VLAN mode */
1956 if (!edev->non_configured_vlans)
1957 qede_config_accept_any_vlan(edev, true);
1958
1959 edev->non_configured_vlans++;
1960 }
1961
1962 list_add(&vlan->list, &edev->vlan_list);
1963
1964 return 0;
1965}
1966
1967static void qede_del_vlan_from_list(struct qede_dev *edev,
1968 struct qede_vlan *vlan)
1969{
1970 /* vlan0 filter isn't consuming out of our quota */
1971 if (vlan->vid != 0) {
1972 if (vlan->configured)
1973 edev->configured_vlans--;
1974 else
1975 edev->non_configured_vlans--;
1976 }
1977
1978 list_del(&vlan->list);
1979 kfree(vlan);
1980}
1981
1982static int qede_configure_vlan_filters(struct qede_dev *edev)
1983{
1984 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1985 struct qed_dev_eth_info *dev_info;
1986 struct qede_vlan *vlan = NULL;
1987
1988 if (list_empty(&edev->vlan_list))
1989 return 0;
1990
1991 dev_info = &edev->dev_info;
1992
1993 /* Configure non-configured vlans */
1994 list_for_each_entry(vlan, &edev->vlan_list, list) {
1995 if (vlan->configured)
1996 continue;
1997
1998 /* We have used all our credits, now enable accept_any_vlan */
1999 if ((vlan->vid != 0) &&
2000 (edev->configured_vlans == dev_info->num_vlan_filters)) {
2001 accept_any_vlan = 1;
2002 continue;
2003 }
2004
2005 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
2006
2007 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
2008 vlan->vid);
2009 if (rc) {
2010 DP_ERR(edev, "Failed to configure VLAN %u\n",
2011 vlan->vid);
2012 real_rc = rc;
2013 continue;
2014 }
2015
2016 vlan->configured = true;
2017 /* vlan0 filter doesn't consume our VLAN filter's quota */
2018 if (vlan->vid != 0) {
2019 edev->non_configured_vlans--;
2020 edev->configured_vlans++;
2021 }
2022 }
2023
2024 /* enable accept_any_vlan mode if we have more VLANs than credits,
2025 * or remove accept_any_vlan mode if we've actually removed
2026 * a non-configured vlan, and all remaining vlans are truly configured.
2027 */
2028
2029 if (accept_any_vlan)
2030 qede_config_accept_any_vlan(edev, true);
2031 else if (!edev->non_configured_vlans)
2032 qede_config_accept_any_vlan(edev, false);
2033
2034 return real_rc;
2035}
2036
2037static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
2038{
2039 struct qede_dev *edev = netdev_priv(dev);
2040 struct qede_vlan *vlan = NULL;
2041 int rc;
2042
2043 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
2044
2045 /* Find whether entry exists */
2046 list_for_each_entry(vlan, &edev->vlan_list, list)
2047 if (vlan->vid == vid)
2048 break;
2049
2050 if (!vlan || (vlan->vid != vid)) {
2051 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
2052 "Vlan isn't configured\n");
2053 return 0;
2054 }
2055
2056 if (edev->state != QEDE_STATE_OPEN) {
2057 /* As interface is already down, we don't have a VPORT
2058 * instance to remove vlan filter. So just update vlan list
2059 */
2060 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2061 "Interface is down, removing VLAN from list only\n");
2062 qede_del_vlan_from_list(edev, vlan);
2063 return 0;
2064 }
2065
2066 /* Remove vlan */
c524e2f5
YM		 2067 if (vlan->configured) {
2068 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL,
2069 vid);
2070 if (rc) {
2071 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
2072 return -EINVAL;
2073 }
7c1bfcad
SRK		 2074 }
2075
2076 qede_del_vlan_from_list(edev, vlan);
2077
2078 /* We have removed a VLAN - try to see if we can
2079 * configure non-configured VLAN from the list.
2080 */
2081 rc = qede_configure_vlan_filters(edev);
2082
2083 return rc;
2084}
2085
2086static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
2087{
2088 struct qede_vlan *vlan = NULL;
2089
2090 if (list_empty(&edev->vlan_list))
2091 return;
2092
2093 list_for_each_entry(vlan, &edev->vlan_list, list) {
2094 if (!vlan->configured)
2095 continue;
2096
2097 vlan->configured = false;
2098
2099 /* vlan0 filter isn't consuming out of our quota */
2100 if (vlan->vid != 0) {
2101 edev->non_configured_vlans++;
2102 edev->configured_vlans--;
2103 }
2104
2105 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2106 "marked vlan %d as non-configured\n",
2107 vlan->vid);
2108 }
2109
2110 edev->accept_any_vlan = false;
2111}
2112
ce2b885c
YM		 2113int qede_set_features(struct net_device *dev, netdev_features_t features)
2114{
2115 struct qede_dev *edev = netdev_priv(dev);
2116 netdev_features_t changes = features ^ dev->features;
2117 bool need_reload = false;
2118
2119 /* No action needed if hardware GRO is disabled during driver load */
2120 if (changes & NETIF_F_GRO) {
2121 if (dev->features & NETIF_F_GRO)
2122 need_reload = !edev->gro_disable;
2123 else
2124 need_reload = edev->gro_disable;
2125 }
2126
2127 if (need_reload && netif_running(edev->ndev)) {
2128 dev->features = features;
2129 qede_reload(edev, NULL, NULL);
2130 return 1;
2131 }
2132
2133 return 0;
2134}
2135
f9f082a9
AD		 2136static void qede_udp_tunnel_add(struct net_device *dev,
2137 struct udp_tunnel_info *ti)
b18e170c
MC		 2138{
2139 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2140 u16 t_port = ntohs(ti->port);
b18e170c 2141
f9f082a9
AD		 2142 switch (ti->type) {
2143 case UDP_TUNNEL_TYPE_VXLAN:
2144 if (edev->vxlan_dst_port)
2145 return;
b18e170c 2146
f9f082a9 2147 edev->vxlan_dst_port = t_port;
b18e170c 2148
f9f082a9
AD		 2149 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d",
2150 t_port);
b18e170c 2151
f9f082a9
AD		 2152 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2153 break;
2154 case UDP_TUNNEL_TYPE_GENEVE:
2155 if (edev->geneve_dst_port)
2156 return;
b18e170c 2157
f9f082a9 2158 edev->geneve_dst_port = t_port;
b18e170c 2159
f9f082a9
AD		 2160 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d",
2161 t_port);
2162 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2163 break;
2164 default:
b18e170c 2165 return;
f9f082a9 2166 }
b18e170c 2167
b18e170c
MC		 2168 schedule_delayed_work(&edev->sp_task, 0);
2169}
b18e170c 2170
f9f082a9
AD		 2171static void qede_udp_tunnel_del(struct net_device *dev,
2172 struct udp_tunnel_info *ti)
9a109dd0
MC		 2173{
2174 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2175 u16 t_port = ntohs(ti->port);
9a109dd0 2176
f9f082a9
AD		 2177 switch (ti->type) {
2178 case UDP_TUNNEL_TYPE_VXLAN:
2179 if (t_port != edev->vxlan_dst_port)
2180 return;
9a109dd0 2181
f9f082a9 2182 edev->vxlan_dst_port = 0;
9a109dd0 2183
f9f082a9
AD		 2184 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d",
2185 t_port);
9a109dd0 2186
f9f082a9
AD		 2187 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2188 break;
2189 case UDP_TUNNEL_TYPE_GENEVE:
2190 if (t_port != edev->geneve_dst_port)
2191 return;
9a109dd0 2192
f9f082a9 2193 edev->geneve_dst_port = 0;
9a109dd0 2194
f9f082a9
AD		 2195 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d",
2196 t_port);
2197 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2198 break;
2199 default:
2200 return;
2201 }
9a109dd0 2202
9a109dd0
MC		 2203 schedule_delayed_work(&edev->sp_task, 0);
2204}
9a109dd0 2205
2950219d
YM		 2206static const struct net_device_ops qede_netdev_ops = {
2207 .ndo_open = qede_open,
2208 .ndo_stop = qede_close,
2209 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2210 .ndo_set_rx_mode = qede_set_rx_mode,
2211 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2212 .ndo_validate_addr = eth_validate_addr,
133fac0e 2213 .ndo_change_mtu = qede_change_mtu,
08feecd7 2214#ifdef CONFIG_QED_SRIOV
eff16960 2215 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7
YM		 2216 .ndo_set_vf_vlan = qede_set_vf_vlan,
2217#endif
7c1bfcad
SRK		 2218 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2219 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
ce2b885c 2220 .ndo_set_features = qede_set_features,
133fac0e 2221 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 2222#ifdef CONFIG_QED_SRIOV
2223 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 2224 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 2225 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 2226 .ndo_set_vf_rate = qede_set_vf_rate,
2227#endif
f9f082a9
AD		 2228 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
2229 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
2950219d
YM		 2230};
2231
e712d52b
YM		 2232/* -------------------------------------------------------------------------
2233 * START OF PROBE / REMOVE
2234 * -------------------------------------------------------------------------
2235 */
2236
2237static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2238 struct pci_dev *pdev,
2239 struct qed_dev_eth_info *info,
2240 u32 dp_module,
2241 u8 dp_level)
2242{
2243 struct net_device *ndev;
2244 struct qede_dev *edev;
2245
2246 ndev = alloc_etherdev_mqs(sizeof(*edev),
2247 info->num_queues,
2248 info->num_queues);
2249 if (!ndev) {
2250 pr_err("etherdev allocation failed\n");
2251 return NULL;
2252 }
2253
2254 edev = netdev_priv(ndev);
2255 edev->ndev = ndev;
2256 edev->cdev = cdev;
2257 edev->pdev = pdev;
2258 edev->dp_module = dp_module;
2259 edev->dp_level = dp_level;
2260 edev->ops = qed_ops;
2950219d
YM		 2261 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2262 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2263
e712d52b
YM		 2264 SET_NETDEV_DEV(ndev, &pdev->dev);
2265
133fac0e 2266 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2267 memcpy(&edev->dev_info, info, sizeof(*info));
2268
2269 edev->num_tc = edev->dev_info.num_tc;
2270
7c1bfcad
SRK		 2271 INIT_LIST_HEAD(&edev->vlan_list);
2272
e712d52b
YM		 2273 return edev;
2274}
2275
2276static void qede_init_ndev(struct qede_dev *edev)
2277{
2278 struct net_device *ndev = edev->ndev;
2279 struct pci_dev *pdev = edev->pdev;
2280 u32 hw_features;
2281
2282 pci_set_drvdata(pdev, ndev);
2283
2284 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2285 ndev->base_addr = ndev->mem_start;
2286 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2287 ndev->irq = edev->dev_info.common.pci_irq;
2288
2289 ndev->watchdog_timeo = TX_TIMEOUT;
2290
2950219d
YM		 2291 ndev->netdev_ops = &qede_netdev_ops;
2292
133fac0e
SK		 2293 qede_set_ethtool_ops(ndev);
2294
e712d52b
YM		 2295 /* user-changeble features */
2296 hw_features = NETIF_F_GRO | NETIF_F_SG |
2297 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2298 NETIF_F_TSO | NETIF_F_TSO6;
2299
14db81de
MC		 2300 /* Encap features*/
2301 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2302 NETIF_F_TSO_ECN;
2303 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2304 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2305 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2306 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2307
e712d52b
YM		 2308 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2309 NETIF_F_HIGHDMA;
2310 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2311 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2312 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2313
2314 ndev->hw_features = hw_features;
2315
2316 /* Set network device HW mac */
2317 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2318}
2319
2320/* This function converts from 32b param to two params of level and module
2321 * Input 32b decoding:
2322 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2323 * 'happy' flow, e.g. memory allocation failed.
2324 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2325 * and provide important parameters.
2326 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2327 * module. VERBOSE prints are for tracking the specific flow in low level.
2328 *
2329 * Notice that the level should be that of the lowest required logs.
2330 */
133fac0e 2331void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2332{
2333 *p_dp_level = QED_LEVEL_NOTICE;
2334 *p_dp_module = 0;
2335
2336 if (debug & QED_LOG_VERBOSE_MASK) {
2337 *p_dp_level = QED_LEVEL_VERBOSE;
2338 *p_dp_module = (debug & 0x3FFFFFFF);
2339 } else if (debug & QED_LOG_INFO_MASK) {
2340 *p_dp_level = QED_LEVEL_INFO;
2341 } else if (debug & QED_LOG_NOTICE_MASK) {
2342 *p_dp_level = QED_LEVEL_NOTICE;
2343 }
2344}
2345
2950219d
YM		 2346static void qede_free_fp_array(struct qede_dev *edev)
2347{
2348 if (edev->fp_array) {
2349 struct qede_fastpath *fp;
2350 int i;
2351
2352 for_each_rss(i) {
2353 fp = &edev->fp_array[i];
2354
2355 kfree(fp->sb_info);
2356 kfree(fp->rxq);
2357 kfree(fp->txqs);
2358 }
2359 kfree(edev->fp_array);
2360 }
2361 edev->num_rss = 0;
2362}
2363
2364static int qede_alloc_fp_array(struct qede_dev *edev)
2365{
2366 struct qede_fastpath *fp;
2367 int i;
2368
2369 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2370 sizeof(*edev->fp_array), GFP_KERNEL);
2371 if (!edev->fp_array) {
2372 DP_NOTICE(edev, "fp array allocation failed\n");
2373 goto err;
2374 }
2375
2376 for_each_rss(i) {
2377 fp = &edev->fp_array[i];
2378
2379 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2380 if (!fp->sb_info) {
2381 DP_NOTICE(edev, "sb info struct allocation failed\n");
2382 goto err;
2383 }
2384
2385 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2386 if (!fp->rxq) {
2387 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2388 goto err;
2389 }
2390
2391 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2392 if (!fp->txqs) {
2393 DP_NOTICE(edev, "TXQ array allocation failed\n");
2394 goto err;
2395 }
2396 }
2397
2398 return 0;
2399err:
2400 qede_free_fp_array(edev);
2401 return -ENOMEM;
2402}
2403
0d8e0aa0
SK		 2404static void qede_sp_task(struct work_struct *work)
2405{
2406 struct qede_dev *edev = container_of(work, struct qede_dev,
2407 sp_task.work);
b18e170c
MC		 2408 struct qed_dev *cdev = edev->cdev;
2409
0d8e0aa0
SK		 2410 mutex_lock(&edev->qede_lock);
2411
2412 if (edev->state == QEDE_STATE_OPEN) {
2413 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2414 qede_config_rx_mode(edev->ndev);
2415 }
2416
b18e170c
MC		 2417 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2418 struct qed_tunn_params tunn_params;
2419
2420 memset(&tunn_params, 0, sizeof(tunn_params));
2421 tunn_params.update_vxlan_port = 1;
2422 tunn_params.vxlan_port = edev->vxlan_dst_port;
2423 qed_ops->tunn_config(cdev, &tunn_params);
2424 }
2425
9a109dd0
MC		 2426 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2427 struct qed_tunn_params tunn_params;
2428
2429 memset(&tunn_params, 0, sizeof(tunn_params));
2430 tunn_params.update_geneve_port = 1;
2431 tunn_params.geneve_port = edev->geneve_dst_port;
2432 qed_ops->tunn_config(cdev, &tunn_params);
2433 }
2434
0d8e0aa0
SK		 2435 mutex_unlock(&edev->qede_lock);
2436}
2437
e712d52b
YM		 2438static void qede_update_pf_params(struct qed_dev *cdev)
2439{
2440 struct qed_pf_params pf_params;
2441
8e0ddc04 2442 /* 64 rx + 64 tx */
e712d52b 2443 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2444 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2445 qed_ops->common->update_pf_params(cdev, &pf_params);
2446}
2447
2448enum qede_probe_mode {
2449 QEDE_PROBE_NORMAL,
2450};
2451
2452static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2453 bool is_vf, enum qede_probe_mode mode)
e712d52b 2454{
1408cc1f 2455 struct qed_probe_params probe_params;
e712d52b
YM		 2456 struct qed_slowpath_params params;
2457 struct qed_dev_eth_info dev_info;
2458 struct qede_dev *edev;
2459 struct qed_dev *cdev;
2460 int rc;
2461
2462 if (unlikely(dp_level & QED_LEVEL_INFO))
2463 pr_notice("Starting qede probe\n");
2464
1408cc1f
YM		 2465 memset(&probe_params, 0, sizeof(probe_params));
2466 probe_params.protocol = QED_PROTOCOL_ETH;
2467 probe_params.dp_module = dp_module;
2468 probe_params.dp_level = dp_level;
2469 probe_params.is_vf = is_vf;
2470 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2471 if (!cdev) {
2472 rc = -ENODEV;
2473 goto err0;
2474 }
2475
2476 qede_update_pf_params(cdev);
2477
2478 /* Start the Slowpath-process */
2479 memset(&params, 0, sizeof(struct qed_slowpath_params));
2480 params.int_mode = QED_INT_MODE_MSIX;
2481 params.drv_major = QEDE_MAJOR_VERSION;
2482 params.drv_minor = QEDE_MINOR_VERSION;
2483 params.drv_rev = QEDE_REVISION_VERSION;
2484 params.drv_eng = QEDE_ENGINEERING_VERSION;
2485 strlcpy(params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2486 rc = qed_ops->common->slowpath_start(cdev, &params);
2487 if (rc) {
2488 pr_notice("Cannot start slowpath\n");
2489 goto err1;
2490 }
2491
2492 /* Learn information crucial for qede to progress */
2493 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2494 if (rc)
2495 goto err2;
2496
2497 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2498 dp_level);
2499 if (!edev) {
2500 rc = -ENOMEM;
2501 goto err2;
2502 }
2503
fefb0202
YM		 2504 if (is_vf)
2505 edev->flags |= QEDE_FLAG_IS_VF;
2506
e712d52b
YM		 2507 qede_init_ndev(edev);
2508
2950219d
YM		 2509 rc = register_netdev(edev->ndev);
2510 if (rc) {
2511 DP_NOTICE(edev, "Cannot register net-device\n");
2512 goto err3;
2513 }
2514
e712d52b
YM		 2515 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2516
a2ec6172
SK		 2517 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2518
489e45ae
SRK		 2519#ifdef CONFIG_DCB
2520 qede_set_dcbnl_ops(edev->ndev);
2521#endif
2522
0d8e0aa0
SK		 2523 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2524 mutex_init(&edev->qede_lock);
3d789994 2525 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
0d8e0aa0 2526
e712d52b
YM		 2527 DP_INFO(edev, "Ending successfully qede probe\n");
2528
2529 return 0;
2530
2950219d
YM		 2531err3:
2532 free_netdev(edev->ndev);
e712d52b
YM		 2533err2:
2534 qed_ops->common->slowpath_stop(cdev);
2535err1:
2536 qed_ops->common->remove(cdev);
2537err0:
2538 return rc;
2539}
2540
2541static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2542{
fefb0202 2543 bool is_vf = false;
e712d52b
YM		 2544 u32 dp_module = 0;
2545 u8 dp_level = 0;
2546
fefb0202
YM		 2547 switch ((enum qede_pci_private)id->driver_data) {
2548 case QEDE_PRIVATE_VF:
2549 if (debug & QED_LOG_VERBOSE_MASK)
2550 dev_err(&pdev->dev, "Probing a VF\n");
2551 is_vf = true;
2552 break;
2553 default:
2554 if (debug & QED_LOG_VERBOSE_MASK)
2555 dev_err(&pdev->dev, "Probing a PF\n");
2556 }
2557
e712d52b
YM		 2558 qede_config_debug(debug, &dp_module, &dp_level);
2559
fefb0202 2560 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2561 QEDE_PROBE_NORMAL);
2562}
2563
2564enum qede_remove_mode {
2565 QEDE_REMOVE_NORMAL,
2566};
2567
2568static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2569{
2570 struct net_device *ndev = pci_get_drvdata(pdev);
2571 struct qede_dev *edev = netdev_priv(ndev);
2572 struct qed_dev *cdev = edev->cdev;
2573
2574 DP_INFO(edev, "Starting qede_remove\n");
2575
0d8e0aa0 2576 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2577 unregister_netdev(ndev);
2578
e712d52b
YM		 2579 edev->ops->common->set_power_state(cdev, PCI_D0);
2580
2581 pci_set_drvdata(pdev, NULL);
2582
2583 free_netdev(ndev);
2584
2585 /* Use global ops since we've freed edev */
2586 qed_ops->common->slowpath_stop(cdev);
2587 qed_ops->common->remove(cdev);
2588
2589 pr_notice("Ending successfully qede_remove\n");
2590}
2591
2592static void qede_remove(struct pci_dev *pdev)
2593{
2594 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2595}
2950219d
YM		 2596
2597/* -------------------------------------------------------------------------
2598 * START OF LOAD / UNLOAD
2599 * -------------------------------------------------------------------------
2600 */
2601
2602static int qede_set_num_queues(struct qede_dev *edev)
2603{
2604 int rc;
2605 u16 rss_num;
2606
2607 /* Setup queues according to possible resources*/
8edf049d
SK		 2608 if (edev->req_rss)
2609 rss_num = edev->req_rss;
2610 else
2611 rss_num = netif_get_num_default_rss_queues() *
2612 edev->dev_info.common.num_hwfns;
2950219d
YM		 2613
2614 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2615
2616 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2617 if (rc > 0) {
2618 /* Managed to request interrupts for our queues */
2619 edev->num_rss = rc;
2620 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2621 QEDE_RSS_CNT(edev), rss_num);
2622 rc = 0;
2623 }
2624 return rc;
2625}
2626
2627static void qede_free_mem_sb(struct qede_dev *edev,
2628 struct qed_sb_info *sb_info)
2629{
2630 if (sb_info->sb_virt)
2631 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2632 (void *)sb_info->sb_virt, sb_info->sb_phys);
2633}
2634
2635/* This function allocates fast-path status block memory */
2636static int qede_alloc_mem_sb(struct qede_dev *edev,
2637 struct qed_sb_info *sb_info,
2638 u16 sb_id)
2639{
2640 struct status_block *sb_virt;
2641 dma_addr_t sb_phys;
2642 int rc;
2643
2644 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
2645 sizeof(*sb_virt),
2646 &sb_phys, GFP_KERNEL);
2647 if (!sb_virt) {
2648 DP_ERR(edev, "Status block allocation failed\n");
2649 return -ENOMEM;
2650 }
2651
2652 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2653 sb_virt, sb_phys, sb_id,
2654 QED_SB_TYPE_L2_QUEUE);
2655 if (rc) {
2656 DP_ERR(edev, "Status block initialization failed\n");
2657 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2658 sb_virt, sb_phys);
2659 return rc;
2660 }
2661
2662 return 0;
2663}
2664
2665static void qede_free_rx_buffers(struct qede_dev *edev,
2666 struct qede_rx_queue *rxq)
2667{
2668 u16 i;
2669
2670 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2671 struct sw_rx_data *rx_buf;
fc48b7a6 2672 struct page *data;
2950219d
YM		 2673
2674 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2675 data = rx_buf->data;
2676
fc48b7a6
YM		 2677 dma_unmap_page(&edev->pdev->dev,
2678 rx_buf->mapping,
2679 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2680
2681 rx_buf->data = NULL;
fc48b7a6 2682 __free_page(data);
2950219d
YM		 2683 }
2684}
2685
55482edc
MC		 2686static void qede_free_sge_mem(struct qede_dev *edev,
2687 struct qede_rx_queue *rxq) {
2688 int i;
2689
2690 if (edev->gro_disable)
2691 return;
2692
2693 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2694 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2695 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2696
f86af2df 2697 if (replace_buf->data) {
55482edc 2698 dma_unmap_page(&edev->pdev->dev,
09ec8e7f 2699 replace_buf->mapping,
55482edc
MC		 2700 PAGE_SIZE, DMA_FROM_DEVICE);
2701 __free_page(replace_buf->data);
2702 }
2703 }
2704}
2705
2950219d
YM		 2706static void qede_free_mem_rxq(struct qede_dev *edev,
2707 struct qede_rx_queue *rxq)
2708{
55482edc
MC		 2709 qede_free_sge_mem(edev, rxq);
2710
2950219d
YM		 2711 /* Free rx buffers */
2712 qede_free_rx_buffers(edev, rxq);
2713
2714 /* Free the parallel SW ring */
2715 kfree(rxq->sw_rx_ring);
2716
2717 /* Free the real RQ ring used by FW */
2718 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2719 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2720}
2721
2722static int qede_alloc_rx_buffer(struct qede_dev *edev,
2723 struct qede_rx_queue *rxq)
2724{
2725 struct sw_rx_data *sw_rx_data;
2726 struct eth_rx_bd *rx_bd;
2727 dma_addr_t mapping;
fc48b7a6 2728 struct page *data;
2950219d 2729 u16 rx_buf_size;
2950219d
YM		 2730
2731 rx_buf_size = rxq->rx_buf_size;
2732
fc48b7a6 2733 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2734 if (unlikely(!data)) {
fc48b7a6 2735 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2736 return -ENOMEM;
2737 }
2738
fc48b7a6
YM		 2739 /* Map the entire page as it would be used
2740 * for multiple RX buffer segment size mapping.
2741 */
2742 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2743 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2744 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2745 __free_page(data);
2950219d
YM		 2746 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2747 return -ENOMEM;
2748 }
2749
2750 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2751 sw_rx_data->page_offset = 0;
2950219d 2752 sw_rx_data->data = data;
fc48b7a6 2753 sw_rx_data->mapping = mapping;
2950219d
YM		 2754
2755 /* Advance PROD and get BD pointer */
2756 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2757 WARN_ON(!rx_bd);
2758 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2759 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2760
2761 rxq->sw_rx_prod++;
2762
2763 return 0;
2764}
2765
55482edc
MC		 2766static int qede_alloc_sge_mem(struct qede_dev *edev,
2767 struct qede_rx_queue *rxq)
2768{
2769 dma_addr_t mapping;
2770 int i;
2771
2772 if (edev->gro_disable)
2773 return 0;
2774
2775 if (edev->ndev->mtu > PAGE_SIZE) {
2776 edev->gro_disable = 1;
2777 return 0;
2778 }
2779
2780 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2781 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2782 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2783
2784 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2785 if (unlikely(!replace_buf->data)) {
2786 DP_NOTICE(edev,
2787 "Failed to allocate TPA skb pool [replacement buffer]\n");
2788 goto err;
2789 }
2790
2791 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2792 rxq->rx_buf_size, DMA_FROM_DEVICE);
2793 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2794 DP_NOTICE(edev,
2795 "Failed to map TPA replacement buffer\n");
2796 goto err;
2797 }
2798
09ec8e7f 2799 replace_buf->mapping = mapping;
55482edc
MC		 2800 tpa_info->replace_buf.page_offset = 0;
2801
2802 tpa_info->replace_buf_mapping = mapping;
2803 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2804 }
2805
2806 return 0;
2807err:
2808 qede_free_sge_mem(edev, rxq);
2809 edev->gro_disable = 1;
2810 return -ENOMEM;
2811}
2812
2950219d
YM		 2813/* This function allocates all memory needed per Rx queue */
2814static int qede_alloc_mem_rxq(struct qede_dev *edev,
2815 struct qede_rx_queue *rxq)
2816{
f86af2df 2817 int i, rc, size;
2950219d
YM		 2818
2819 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2820
fc48b7a6
YM		 2821 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD +
2822 edev->ndev->mtu;
2823 if (rxq->rx_buf_size > PAGE_SIZE)
2824 rxq->rx_buf_size = PAGE_SIZE;
2825
2826 /* Segment size to spilt a page in multiple equal parts */
2827 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2828
2829 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2830 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2831 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2832 if (!rxq->sw_rx_ring) {
2833 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2834 rc = -ENOMEM;
2950219d
YM		 2835 goto err;
2836 }
2837
2838 /* Allocate FW Rx ring */
2839 rc = edev->ops->common->chain_alloc(edev->cdev,
2840 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2841 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 2842 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2843 RX_RING_SIZE,
2950219d
YM		 2844 sizeof(struct eth_rx_bd),
2845 &rxq->rx_bd_ring);
2846
2847 if (rc)
2848 goto err;
2849
2850 /* Allocate FW completion ring */
2851 rc = edev->ops->common->chain_alloc(edev->cdev,
2852 QED_CHAIN_USE_TO_CONSUME,
2853 QED_CHAIN_MODE_PBL,
a91eb52a 2854 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2855 RX_RING_SIZE,
2950219d
YM		 2856 sizeof(union eth_rx_cqe),
2857 &rxq->rx_comp_ring);
2858 if (rc)
2859 goto err;
2860
2861 /* Allocate buffers for the Rx ring */
2862 for (i = 0; i < rxq->num_rx_buffers; i++) {
2863 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2864 if (rc) {
2865 DP_ERR(edev,
2866 "Rx buffers allocation failed at index %d\n", i);
2867 goto err;
2868 }
2950219d
YM		 2869 }
2870
f86af2df 2871 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2872err:
f86af2df 2873 return rc;
2950219d
YM		 2874}
2875
2876static void qede_free_mem_txq(struct qede_dev *edev,
2877 struct qede_tx_queue *txq)
2878{
2879 /* Free the parallel SW ring */
2880 kfree(txq->sw_tx_ring);
2881
2882 /* Free the real RQ ring used by FW */
2883 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2884}
2885
2886/* This function allocates all memory needed per Tx queue */
2887static int qede_alloc_mem_txq(struct qede_dev *edev,
2888 struct qede_tx_queue *txq)
2889{
2890 int size, rc;
2891 union eth_tx_bd_types *p_virt;
2892
2893 txq->num_tx_buffers = edev->q_num_tx_buffers;
2894
2895 /* Allocate the parallel driver ring for Tx buffers */
2896 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2897 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2898 if (!txq->sw_tx_ring) {
2899 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2900 goto err;
2901 }
2902
2903 rc = edev->ops->common->chain_alloc(edev->cdev,
2904 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2905 QED_CHAIN_MODE_PBL,
a91eb52a 2906 QED_CHAIN_CNT_TYPE_U16,
2950219d 2907 NUM_TX_BDS_MAX,
a91eb52a 2908 sizeof(*p_virt), &txq->tx_pbl);
2950219d
YM		 2909 if (rc)
2910 goto err;
2911
2912 return 0;
2913
2914err:
2915 qede_free_mem_txq(edev, txq);
2916 return -ENOMEM;
2917}
2918
2919/* This function frees all memory of a single fp */
2920static void qede_free_mem_fp(struct qede_dev *edev,
2921 struct qede_fastpath *fp)
2922{
2923 int tc;
2924
2925 qede_free_mem_sb(edev, fp->sb_info);
2926
2927 qede_free_mem_rxq(edev, fp->rxq);
2928
2929 for (tc = 0; tc < edev->num_tc; tc++)
2930 qede_free_mem_txq(edev, &fp->txqs[tc]);
2931}
2932
2933/* This function allocates all memory needed for a single fp (i.e. an entity
2934 * which contains status block, one rx queue and multiple per-TC tx queues.
2935 */
2936static int qede_alloc_mem_fp(struct qede_dev *edev,
2937 struct qede_fastpath *fp)
2938{
2939 int rc, tc;
2940
2941 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2942 if (rc)
2943 goto err;
2944
2945 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2946 if (rc)
2947 goto err;
2948
2949 for (tc = 0; tc < edev->num_tc; tc++) {
2950 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2951 if (rc)
2952 goto err;
2953 }
2954
2955 return 0;
2950219d 2956err:
f86af2df 2957 return rc;
2950219d
YM		 2958}
2959
2960static void qede_free_mem_load(struct qede_dev *edev)
2961{
2962 int i;
2963
2964 for_each_rss(i) {
2965 struct qede_fastpath *fp = &edev->fp_array[i];
2966
2967 qede_free_mem_fp(edev, fp);
2968 }
2969}
2970
2971/* This function allocates all qede memory at NIC load. */
2972static int qede_alloc_mem_load(struct qede_dev *edev)
2973{
2974 int rc = 0, rss_id;
2975
2976 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2977 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2978
2979 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2980 if (rc) {
2950219d 2981 DP_ERR(edev,
f86af2df
MC		 2982 "Failed to allocate memory for fastpath - rss id = %d\n",
2983 rss_id);
2984 qede_free_mem_load(edev);
2985 return rc;
2950219d 2986 }
2950219d
YM		 2987 }
2988
2989 return 0;
2990}
2991
2992/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2993static void qede_init_fp(struct qede_dev *edev)
2994{
2995 int rss_id, txq_index, tc;
2996 struct qede_fastpath *fp;
2997
2998 for_each_rss(rss_id) {
2999 fp = &edev->fp_array[rss_id];
3000
3001 fp->edev = edev;
3002 fp->rss_id = rss_id;
3003
3004 memset((void *)&fp->napi, 0, sizeof(fp->napi));
3005
3006 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
3007
3008 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
3009 fp->rxq->rxq_id = rss_id;
3010
3011 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
3012 for (tc = 0; tc < edev->num_tc; tc++) {
3013 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
3014 fp->txqs[tc].index = txq_index;
3015 }
3016
3017 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
3018 edev->ndev->name, rss_id);
3019 }
55482edc
MC		 3020
3021 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 3022}
3023
3024static int qede_set_real_num_queues(struct qede_dev *edev)
3025{
3026 int rc = 0;
3027
3028 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
3029 if (rc) {
3030 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
3031 return rc;
3032 }
3033 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
3034 if (rc) {
3035 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
3036 return rc;
3037 }
3038
3039 return 0;
3040}
3041
3042static void qede_napi_disable_remove(struct qede_dev *edev)
3043{
3044 int i;
3045
3046 for_each_rss(i) {
3047 napi_disable(&edev->fp_array[i].napi);
3048
3049 netif_napi_del(&edev->fp_array[i].napi);
3050 }
3051}
3052
3053static void qede_napi_add_enable(struct qede_dev *edev)
3054{
3055 int i;
3056
3057 /* Add NAPI objects */
3058 for_each_rss(i) {
3059 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
3060 qede_poll, NAPI_POLL_WEIGHT);
3061 napi_enable(&edev->fp_array[i].napi);
3062 }
3063}
3064
3065static void qede_sync_free_irqs(struct qede_dev *edev)
3066{
3067 int i;
3068
3069 for (i = 0; i < edev->int_info.used_cnt; i++) {
3070 if (edev->int_info.msix_cnt) {
3071 synchronize_irq(edev->int_info.msix[i].vector);
3072 free_irq(edev->int_info.msix[i].vector,
3073 &edev->fp_array[i]);
3074 } else {
3075 edev->ops->common->simd_handler_clean(edev->cdev, i);
3076 }
3077 }
3078
3079 edev->int_info.used_cnt = 0;
3080}
3081
3082static int qede_req_msix_irqs(struct qede_dev *edev)
3083{
3084 int i, rc;
3085
3086 /* Sanitize number of interrupts == number of prepared RSS queues */
3087 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
3088 DP_ERR(edev,
3089 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
3090 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
3091 return -EINVAL;
3092 }
3093
3094 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
3095 rc = request_irq(edev->int_info.msix[i].vector,
3096 qede_msix_fp_int, 0, edev->fp_array[i].name,
3097 &edev->fp_array[i]);
3098 if (rc) {
3099 DP_ERR(edev, "Request fp %d irq failed\n", i);
3100 qede_sync_free_irqs(edev);
3101 return rc;
3102 }
3103 DP_VERBOSE(edev, NETIF_MSG_INTR,
3104 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
3105 edev->fp_array[i].name, i,
3106 &edev->fp_array[i]);
3107 edev->int_info.used_cnt++;
3108 }
3109
3110 return 0;
3111}
3112
3113static void qede_simd_fp_handler(void *cookie)
3114{
3115 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
3116
3117 napi_schedule_irqoff(&fp->napi);
3118}
3119
3120static int qede_setup_irqs(struct qede_dev *edev)
3121{
3122 int i, rc = 0;
3123
3124 /* Learn Interrupt configuration */
3125 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
3126 if (rc)
3127 return rc;
3128
3129 if (edev->int_info.msix_cnt) {
3130 rc = qede_req_msix_irqs(edev);
3131 if (rc)
3132 return rc;
3133 edev->ndev->irq = edev->int_info.msix[0].vector;
3134 } else {
3135 const struct qed_common_ops *ops;
3136
3137 /* qed should learn receive the RSS ids and callbacks */
3138 ops = edev->ops->common;
3139 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
3140 ops->simd_handler_config(edev->cdev,
3141 &edev->fp_array[i], i,
3142 qede_simd_fp_handler);
3143 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
3144 }
3145 return 0;
3146}
3147
3148static int qede_drain_txq(struct qede_dev *edev,
3149 struct qede_tx_queue *txq,
3150 bool allow_drain)
3151{
3152 int rc, cnt = 1000;
3153
3154 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3155 if (!cnt) {
3156 if (allow_drain) {
3157 DP_NOTICE(edev,
3158 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3159 txq->index);
3160 rc = edev->ops->common->drain(edev->cdev);
3161 if (rc)
3162 return rc;
3163 return qede_drain_txq(edev, txq, false);
3164 }
3165 DP_NOTICE(edev,
3166 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3167 txq->index, txq->sw_tx_prod,
3168 txq->sw_tx_cons);
3169 return -ENODEV;
3170 }
3171 cnt--;
3172 usleep_range(1000, 2000);
3173 barrier();
3174 }
3175
3176 /* FW finished processing, wait for HW to transmit all tx packets */
3177 usleep_range(1000, 2000);
3178
3179 return 0;
3180}
3181
3182static int qede_stop_queues(struct qede_dev *edev)
3183{
3184 struct qed_update_vport_params vport_update_params;
3185 struct qed_dev *cdev = edev->cdev;
3186 int rc, tc, i;
3187
3188 /* Disable the vport */
3189 memset(&vport_update_params, 0, sizeof(vport_update_params));
3190 vport_update_params.vport_id = 0;
3191 vport_update_params.update_vport_active_flg = 1;
3192 vport_update_params.vport_active_flg = 0;
3193 vport_update_params.update_rss_flg = 0;
3194
3195 rc = edev->ops->vport_update(cdev, &vport_update_params);
3196 if (rc) {
3197 DP_ERR(edev, "Failed to update vport\n");
3198 return rc;
3199 }
3200
3201 /* Flush Tx queues. If needed, request drain from MCP */
3202 for_each_rss(i) {
3203 struct qede_fastpath *fp = &edev->fp_array[i];
3204
3205 for (tc = 0; tc < edev->num_tc; tc++) {
3206 struct qede_tx_queue *txq = &fp->txqs[tc];
3207
3208 rc = qede_drain_txq(edev, txq, true);
3209 if (rc)
3210 return rc;
3211 }
3212 }
3213
3214 /* Stop all Queues in reverse order*/
3215 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3216 struct qed_stop_rxq_params rx_params;
3217
3218 /* Stop the Tx Queue(s)*/
3219 for (tc = 0; tc < edev->num_tc; tc++) {
3220 struct qed_stop_txq_params tx_params;
3221
3222 tx_params.rss_id = i;
3223 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3224 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3225 if (rc) {
3226 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3227 tx_params.tx_queue_id);
3228 return rc;
3229 }
3230 }
3231
3232 /* Stop the Rx Queue*/
3233 memset(&rx_params, 0, sizeof(rx_params));
3234 rx_params.rss_id = i;
3235 rx_params.rx_queue_id = i;
3236
3237 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3238 if (rc) {
3239 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3240 return rc;
3241 }
3242 }
3243
3244 /* Stop the vport */
3245 rc = edev->ops->vport_stop(cdev, 0);
3246 if (rc)
3247 DP_ERR(edev, "Failed to stop VPORT\n");
3248
3249 return rc;
3250}
3251
a0d26d5a 3252static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d
YM		 3253{
3254 int rc, tc, i;
088c8618 3255 int vlan_removal_en = 1;
2950219d 3256 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3257 struct qed_update_vport_params vport_update_params;
3258 struct qed_queue_start_common_params q_params;
fefb0202 3259 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3260 struct qed_start_vport_params start = {0};
961acdea 3261 bool reset_rss_indir = false;
2950219d
YM		 3262
3263 if (!edev->num_rss) {
3264 DP_ERR(edev,
3265 "Cannot update V-VPORT as active as there are no Rx queues\n");
3266 return -EINVAL;
3267 }
3268
55482edc 3269 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3270 start.mtu = edev->ndev->mtu;
3271 start.vport_id = 0;
3272 start.drop_ttl0 = true;
3273 start.remove_inner_vlan = vlan_removal_en;
7f7a144f 3274 start.clear_stats = clear_stats;
088c8618
MC		 3275
3276 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3277
3278 if (rc) {
3279 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3280 return rc;
3281 }
3282
3283 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3284 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3285 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3286
3287 for_each_rss(i) {
3288 struct qede_fastpath *fp = &edev->fp_array[i];
3289 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3290
3291 memset(&q_params, 0, sizeof(q_params));
3292 q_params.rss_id = i;
3293 q_params.queue_id = i;
3294 q_params.vport_id = 0;
3295 q_params.sb = fp->sb_info->igu_sb_id;
3296 q_params.sb_idx = RX_PI;
3297
3298 rc = edev->ops->q_rx_start(cdev, &q_params,
3299 fp->rxq->rx_buf_size,
3300 fp->rxq->rx_bd_ring.p_phys_addr,
3301 phys_table,
3302 fp->rxq->rx_comp_ring.page_cnt,
3303 &fp->rxq->hw_rxq_prod_addr);
3304 if (rc) {
3305 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3306 return rc;
3307 }
3308
3309 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3310
3311 qede_update_rx_prod(edev, fp->rxq);
3312
3313 for (tc = 0; tc < edev->num_tc; tc++) {
3314 struct qede_tx_queue *txq = &fp->txqs[tc];
3315 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3316
3317 memset(&q_params, 0, sizeof(q_params));
3318 q_params.rss_id = i;
3319 q_params.queue_id = txq_index;
3320 q_params.vport_id = 0;
3321 q_params.sb = fp->sb_info->igu_sb_id;
3322 q_params.sb_idx = TX_PI(tc);
3323
3324 rc = edev->ops->q_tx_start(cdev, &q_params,
3325 txq->tx_pbl.pbl.p_phys_table,
3326 txq->tx_pbl.page_cnt,
3327 &txq->doorbell_addr);
3328 if (rc) {
3329 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3330 txq_index, rc);
3331 return rc;
3332 }
3333
3334 txq->hw_cons_ptr =
3335 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3336 SET_FIELD(txq->tx_db.data.params,
3337 ETH_DB_DATA_DEST, DB_DEST_XCM);
3338 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3339 DB_AGG_CMD_SET);
3340 SET_FIELD(txq->tx_db.data.params,
3341 ETH_DB_DATA_AGG_VAL_SEL,
3342 DQ_XCM_ETH_TX_BD_PROD_CMD);
3343
3344 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3345 }
3346 }
3347
3348 /* Prepare and send the vport enable */
3349 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3350 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3351 vport_update_params.update_vport_active_flg = 1;
3352 vport_update_params.vport_active_flg = 1;
3353
831bfb0e
YM		 3354 if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
3355 qed_info->tx_switching) {
3356 vport_update_params.update_tx_switching_flg = 1;
3357 vport_update_params.tx_switching_flg = 1;
3358 }
3359
2950219d
YM		 3360 /* Fill struct with RSS params */
3361 if (QEDE_RSS_CNT(edev) > 1) {
3362 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3363
3364 /* Need to validate current RSS config uses valid entries */
3365 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3366 if (edev->rss_params.rss_ind_table[i] >=
3367 edev->num_rss) {
3368 reset_rss_indir = true;
3369 break;
3370 }
3371 }
3372
3373 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3374 reset_rss_indir) {
3375 u16 val;
3376
3377 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3378 u16 indir_val;
3379
3380 val = QEDE_RSS_CNT(edev);
3381 indir_val = ethtool_rxfh_indir_default(i, val);
3382 edev->rss_params.rss_ind_table[i] = indir_val;
3383 }
3384 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3385 }
3386
3387 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3388 netdev_rss_key_fill(edev->rss_params.rss_key,
3389 sizeof(edev->rss_params.rss_key));
3390 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3391 }
3392
3393 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3394 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3395 QED_RSS_IPV6 |
3396 QED_RSS_IPV4_TCP |
3397 QED_RSS_IPV6_TCP;
3398 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3399 }
3400
3401 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3402 sizeof(vport_update_params.rss_params));
2950219d 3403 } else {
961acdea
SRK		 3404 memset(&vport_update_params.rss_params, 0,
3405 sizeof(vport_update_params.rss_params));
2950219d 3406 }
2950219d
YM		 3407
3408 rc = edev->ops->vport_update(cdev, &vport_update_params);
3409 if (rc) {
3410 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3411 return rc;
3412 }
3413
3414 return 0;
3415}
3416
0d8e0aa0
SK		 3417static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3418 enum qed_filter_xcast_params_type opcode,
3419 unsigned char *mac, int num_macs)
3420{
3421 struct qed_filter_params filter_cmd;
3422 int i;
3423
3424 memset(&filter_cmd, 0, sizeof(filter_cmd));
3425 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3426 filter_cmd.filter.mcast.type = opcode;
3427 filter_cmd.filter.mcast.num = num_macs;
3428
3429 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3430 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3431
3432 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3433}
3434
2950219d
YM		 3435enum qede_unload_mode {
3436 QEDE_UNLOAD_NORMAL,
3437};
3438
3439static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3440{
a2ec6172 3441 struct qed_link_params link_params;
2950219d
YM		 3442 int rc;
3443
3444 DP_INFO(edev, "Starting qede unload\n");
3445
0d8e0aa0
SK		 3446 mutex_lock(&edev->qede_lock);
3447 edev->state = QEDE_STATE_CLOSED;
3448
2950219d
YM		 3449 /* Close OS Tx */
3450 netif_tx_disable(edev->ndev);
3451 netif_carrier_off(edev->ndev);
3452
a2ec6172
SK		 3453 /* Reset the link */
3454 memset(&link_params, 0, sizeof(link_params));
3455 link_params.link_up = false;
3456 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3457 rc = qede_stop_queues(edev);
3458 if (rc) {
3459 qede_sync_free_irqs(edev);
3460 goto out;
3461 }
3462
3463 DP_INFO(edev, "Stopped Queues\n");
3464
7c1bfcad 3465 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3466 edev->ops->fastpath_stop(edev->cdev);
3467
3468 /* Release the interrupts */
3469 qede_sync_free_irqs(edev);
3470 edev->ops->common->set_fp_int(edev->cdev, 0);
3471
3472 qede_napi_disable_remove(edev);
3473
3474 qede_free_mem_load(edev);
3475 qede_free_fp_array(edev);
3476
3477out:
3478 mutex_unlock(&edev->qede_lock);
3479 DP_INFO(edev, "Ending qede unload\n");
3480}
3481
3482enum qede_load_mode {
3483 QEDE_LOAD_NORMAL,
a0d26d5a 3484 QEDE_LOAD_RELOAD,
2950219d
YM		 3485};
3486
3487static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3488{
a2ec6172
SK		 3489 struct qed_link_params link_params;
3490 struct qed_link_output link_output;
2950219d
YM		 3491 int rc;
3492
3493 DP_INFO(edev, "Starting qede load\n");
3494
3495 rc = qede_set_num_queues(edev);
3496 if (rc)
3497 goto err0;
3498
3499 rc = qede_alloc_fp_array(edev);
3500 if (rc)
3501 goto err0;
3502
3503 qede_init_fp(edev);
3504
3505 rc = qede_alloc_mem_load(edev);
3506 if (rc)
3507 goto err1;
3508 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3509 QEDE_RSS_CNT(edev), edev->num_tc);
3510
3511 rc = qede_set_real_num_queues(edev);
3512 if (rc)
3513 goto err2;
3514
3515 qede_napi_add_enable(edev);
3516 DP_INFO(edev, "Napi added and enabled\n");
3517
3518 rc = qede_setup_irqs(edev);
3519 if (rc)
3520 goto err3;
3521 DP_INFO(edev, "Setup IRQs succeeded\n");
3522
a0d26d5a 3523 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 3524 if (rc)
3525 goto err4;
3526 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3527
3528 /* Add primary mac and set Rx filters */
3529 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3530
0d8e0aa0
SK		 3531 mutex_lock(&edev->qede_lock);
3532 edev->state = QEDE_STATE_OPEN;
3533 mutex_unlock(&edev->qede_lock);
a2ec6172 3534
7c1bfcad
SRK		 3535 /* Program un-configured VLANs */
3536 qede_configure_vlan_filters(edev);
3537
a2ec6172
SK		 3538 /* Ask for link-up using current configuration */
3539 memset(&link_params, 0, sizeof(link_params));
3540 link_params.link_up = true;
3541 edev->ops->common->set_link(edev->cdev, &link_params);
3542
3543 /* Query whether link is already-up */
3544 memset(&link_output, 0, sizeof(link_output));
3545 edev->ops->common->get_link(edev->cdev, &link_output);
3546 qede_link_update(edev, &link_output);
3547
2950219d
YM		 3548 DP_INFO(edev, "Ending successfully qede load\n");
3549
3550 return 0;
3551
3552err4:
3553 qede_sync_free_irqs(edev);
3554 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3555err3:
3556 qede_napi_disable_remove(edev);
3557err2:
3558 qede_free_mem_load(edev);
3559err1:
3560 edev->ops->common->set_fp_int(edev->cdev, 0);
3561 qede_free_fp_array(edev);
3562 edev->num_rss = 0;
3563err0:
3564 return rc;
3565}
3566
133fac0e
SK		 3567void qede_reload(struct qede_dev *edev,
3568 void (*func)(struct qede_dev *, union qede_reload_args *),
3569 union qede_reload_args *args)
3570{
3571 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3572 /* Call function handler to update parameters
3573 * needed for function load.
3574 */
3575 if (func)
3576 func(edev, args);
3577
a0d26d5a 3578 qede_load(edev, QEDE_LOAD_RELOAD);
133fac0e
SK		 3579
3580 mutex_lock(&edev->qede_lock);
3581 qede_config_rx_mode(edev->ndev);
3582 mutex_unlock(&edev->qede_lock);
3583}
3584
2950219d
YM		 3585/* called with rtnl_lock */
3586static int qede_open(struct net_device *ndev)
3587{
3588 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3589 int rc;
2950219d
YM		 3590
3591 netif_carrier_off(ndev);
3592
3593 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3594
b18e170c
MC		 3595 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3596
3597 if (rc)
3598 return rc;
3599
f9f082a9
AD		 3600 udp_tunnel_get_rx_info(ndev);
3601
b18e170c 3602 return 0;
2950219d
YM		 3603}
3604
3605static int qede_close(struct net_device *ndev)
3606{
3607 struct qede_dev *edev = netdev_priv(ndev);
3608
3609 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3610
3611 return 0;
3612}
0d8e0aa0 3613
a2ec6172
SK		 3614static void qede_link_update(void *dev, struct qed_link_output *link)
3615{
3616 struct qede_dev *edev = dev;
3617
3618 if (!netif_running(edev->ndev)) {
3619 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3620 return;
3621 }
3622
3623 if (link->link_up) {
8e025ae2
YM		 3624 if (!netif_carrier_ok(edev->ndev)) {
3625 DP_NOTICE(edev, "Link is up\n");
3626 netif_tx_start_all_queues(edev->ndev);
3627 netif_carrier_on(edev->ndev);
3628 }
a2ec6172 3629 } else {
8e025ae2
YM		 3630 if (netif_carrier_ok(edev->ndev)) {
3631 DP_NOTICE(edev, "Link is down\n");
3632 netif_tx_disable(edev->ndev);
3633 netif_carrier_off(edev->ndev);
3634 }
a2ec6172
SK		 3635 }
3636}
3637
0d8e0aa0
SK		 3638static int qede_set_mac_addr(struct net_device *ndev, void *p)
3639{
3640 struct qede_dev *edev = netdev_priv(ndev);
3641 struct sockaddr *addr = p;
3642 int rc;
3643
3644 ASSERT_RTNL(); /* @@@TBD To be removed */
3645
3646 DP_INFO(edev, "Set_mac_addr called\n");
3647
3648 if (!is_valid_ether_addr(addr->sa_data)) {
3649 DP_NOTICE(edev, "The MAC address is not valid\n");
3650 return -EFAULT;
3651 }
3652
eff16960
YM		 3653 if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
3654 DP_NOTICE(edev, "qed prevents setting MAC\n");
3655 return -EINVAL;
3656 }
3657
0d8e0aa0
SK		 3658 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3659
3660 if (!netif_running(ndev)) {
3661 DP_NOTICE(edev, "The device is currently down\n");
3662 return 0;
3663 }
3664
3665 /* Remove the previous primary mac */
3666 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3667 edev->primary_mac);
3668 if (rc)
3669 return rc;
3670
3671 /* Add MAC filter according to the new unicast HW MAC address */
3672 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3673 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3674 edev->primary_mac);
3675}
3676
3677static int
3678qede_configure_mcast_filtering(struct net_device *ndev,
3679 enum qed_filter_rx_mode_type *accept_flags)
3680{
3681 struct qede_dev *edev = netdev_priv(ndev);
3682 unsigned char *mc_macs, *temp;
3683 struct netdev_hw_addr *ha;
3684 int rc = 0, mc_count;
3685 size_t size;
3686
3687 size = 64 * ETH_ALEN;
3688
3689 mc_macs = kzalloc(size, GFP_KERNEL);
3690 if (!mc_macs) {
3691 DP_NOTICE(edev,
3692 "Failed to allocate memory for multicast MACs\n");
3693 rc = -ENOMEM;
3694 goto exit;
3695 }
3696
3697 temp = mc_macs;
3698
3699 /* Remove all previously configured MAC filters */
3700 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3701 mc_macs, 1);
3702 if (rc)
3703 goto exit;
3704
3705 netif_addr_lock_bh(ndev);
3706
3707 mc_count = netdev_mc_count(ndev);
3708 if (mc_count < 64) {
3709 netdev_for_each_mc_addr(ha, ndev) {
3710 ether_addr_copy(temp, ha->addr);
3711 temp += ETH_ALEN;
3712 }
3713 }
3714
3715 netif_addr_unlock_bh(ndev);
3716
3717 /* Check for all multicast @@@TBD resource allocation */
3718 if ((ndev->flags & IFF_ALLMULTI) ||
3719 (mc_count > 64)) {
3720 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3721 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3722 } else {
3723 /* Add all multicast MAC filters */
3724 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3725 mc_macs, mc_count);
3726 }
3727
3728exit:
3729 kfree(mc_macs);
3730 return rc;
3731}
3732
3733static void qede_set_rx_mode(struct net_device *ndev)
3734{
3735 struct qede_dev *edev = netdev_priv(ndev);
3736
3737 DP_INFO(edev, "qede_set_rx_mode called\n");
3738
3739 if (edev->state != QEDE_STATE_OPEN) {
3740 DP_INFO(edev,
3741 "qede_set_rx_mode called while interface is down\n");
3742 } else {
3743 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3744 schedule_delayed_work(&edev->sp_task, 0);
3745 }
3746}
3747
3748/* Must be called with qede_lock held */
3749static void qede_config_rx_mode(struct net_device *ndev)
3750{
3751 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3752 struct qede_dev *edev = netdev_priv(ndev);
3753 struct qed_filter_params rx_mode;
3754 unsigned char *uc_macs, *temp;
3755 struct netdev_hw_addr *ha;
3756 int rc, uc_count;
3757 size_t size;
3758
3759 netif_addr_lock_bh(ndev);
3760
3761 uc_count = netdev_uc_count(ndev);
3762 size = uc_count * ETH_ALEN;
3763
3764 uc_macs = kzalloc(size, GFP_ATOMIC);
3765 if (!uc_macs) {
3766 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3767 netif_addr_unlock_bh(ndev);
3768 return;
3769 }
3770
3771 temp = uc_macs;
3772 netdev_for_each_uc_addr(ha, ndev) {
3773 ether_addr_copy(temp, ha->addr);
3774 temp += ETH_ALEN;
3775 }
3776
3777 netif_addr_unlock_bh(ndev);
3778
3779 /* Configure the struct for the Rx mode */
3780 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3781 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3782
3783 /* Remove all previous unicast secondary macs and multicast macs
3784 * (configrue / leave the primary mac)
3785 */
3786 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3787 edev->primary_mac);
3788 if (rc)
3789 goto out;
3790
3791 /* Check for promiscuous */
3792 if ((ndev->flags & IFF_PROMISC) ||
3793 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3794 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3795 } else {
3796 /* Add MAC filters according to the unicast secondary macs */
3797 int i;
3798
3799 temp = uc_macs;
3800 for (i = 0; i < uc_count; i++) {
3801 rc = qede_set_ucast_rx_mac(edev,
3802 QED_FILTER_XCAST_TYPE_ADD,
3803 temp);
3804 if (rc)
3805 goto out;
3806
3807 temp += ETH_ALEN;
3808 }
3809
3810 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3811 if (rc)
3812 goto out;
3813 }
3814
7c1bfcad
SRK		 3815 /* take care of VLAN mode */
3816 if (ndev->flags & IFF_PROMISC) {
3817 qede_config_accept_any_vlan(edev, true);
3818 } else if (!edev->non_configured_vlans) {
3819 /* It's possible that accept_any_vlan mode is set due to a
3820 * previous setting of IFF_PROMISC. If vlan credits are
3821 * sufficient, disable accept_any_vlan.
3822 */
3823 qede_config_accept_any_vlan(edev, false);
3824 }
3825
0d8e0aa0
SK		 3826 rx_mode.filter.accept_flags = accept_flags;
3827 edev->ops->filter_config(edev->cdev, &rx_mode);
3828out:
3829 kfree(uc_macs);
3830}
Linux kernel - Deliverables
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