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qed*: support ndo_get_vf_config
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
b18e170c 27#ifdef CONFIG_QEDE_VXLAN
e712d52b 28#include <net/vxlan.h>
b18e170c 29#endif
9a109dd0
MC		 30#ifdef CONFIG_QEDE_GENEVE
31#include <net/geneve.h>
32#endif
e712d52b
YM		 33#include <linux/ip.h>
34#include <net/ipv6.h>
35#include <net/tcp.h>
36#include <linux/if_ether.h>
37#include <linux/if_vlan.h>
38#include <linux/pkt_sched.h>
39#include <linux/ethtool.h>
40#include <linux/in.h>
41#include <linux/random.h>
42#include <net/ip6_checksum.h>
43#include <linux/bitops.h>
44
45#include "qede.h"
46
5abd7e92
YM		 47static char version[] =
48 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 49
5abd7e92 50MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_MODULE_VERSION);
53
54static uint debug;
55module_param(debug, uint, 0);
56MODULE_PARM_DESC(debug, " Default debug msglevel");
57
58static const struct qed_eth_ops *qed_ops;
59
60#define CHIP_NUM_57980S_40 0x1634
0e7441d7 61#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 62#define CHIP_NUM_57980S_MF 0x1636
63#define CHIP_NUM_57980S_100 0x1644
64#define CHIP_NUM_57980S_50 0x1654
65#define CHIP_NUM_57980S_25 0x1656
fefb0202 66#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 67
68#ifndef PCI_DEVICE_ID_NX2_57980E
69#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
70#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
71#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
72#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
73#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
74#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 75#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 76#endif
77
fefb0202
YM		 78enum qede_pci_private {
79 QEDE_PRIVATE_PF,
80 QEDE_PRIVATE_VF
81};
82
e712d52b 83static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
85 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
87 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
88 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
89 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
90 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
e712d52b
YM		 91 { 0 }
92};
93
94MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
95
96static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
97
98#define TX_TIMEOUT (5 * HZ)
99
100static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 101static int qede_alloc_rx_buffer(struct qede_dev *edev,
102 struct qede_rx_queue *rxq);
a2ec6172 103static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 104
fefb0202 105#ifdef CONFIG_QED_SRIOV
08feecd7
YM		 106static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
107{
108 struct qede_dev *edev = netdev_priv(ndev);
109
110 if (vlan > 4095) {
111 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
112 return -EINVAL;
113 }
114
115 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
116 vlan, vf);
117
118 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
119}
120
eff16960
YM		 121static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
122{
123 struct qede_dev *edev = netdev_priv(ndev);
124
125 DP_VERBOSE(edev, QED_MSG_IOV,
126 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
127 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
128
129 if (!is_valid_ether_addr(mac)) {
130 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
131 return -EINVAL;
132 }
133
134 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
135}
136
fefb0202
YM		 137static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
138{
139 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
140
141 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
142
143 return edev->ops->iov->configure(edev->cdev, num_vfs_param);
144}
145#endif
146
e712d52b
YM		 147static struct pci_driver qede_pci_driver = {
148 .name = "qede",
149 .id_table = qede_pci_tbl,
150 .probe = qede_probe,
151 .remove = qede_remove,
fefb0202
YM		 152#ifdef CONFIG_QED_SRIOV
153 .sriov_configure = qede_sriov_configure,
154#endif
e712d52b
YM		 155};
156
eff16960
YM		 157static void qede_force_mac(void *dev, u8 *mac)
158{
159 struct qede_dev *edev = dev;
160
161 ether_addr_copy(edev->ndev->dev_addr, mac);
162 ether_addr_copy(edev->primary_mac, mac);
163}
164
a2ec6172
SK		 165static struct qed_eth_cb_ops qede_ll_ops = {
166 {
167 .link_update = qede_link_update,
168 },
eff16960 169 .force_mac = qede_force_mac,
a2ec6172
SK		 170};
171
2950219d
YM		 172static int qede_netdev_event(struct notifier_block *this, unsigned long event,
173 void *ptr)
174{
175 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
176 struct ethtool_drvinfo drvinfo;
177 struct qede_dev *edev;
178
179 /* Currently only support name change */
180 if (event != NETDEV_CHANGENAME)
181 goto done;
182
183 /* Check whether this is a qede device */
184 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
185 goto done;
186
187 memset(&drvinfo, 0, sizeof(drvinfo));
188 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
189 if (strcmp(drvinfo.driver, "qede"))
190 goto done;
191 edev = netdev_priv(ndev);
192
193 /* Notify qed of the name change */
194 if (!edev->ops || !edev->ops->common)
195 goto done;
196 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
197 "qede");
198
199done:
200 return NOTIFY_DONE;
201}
202
203static struct notifier_block qede_netdev_notifier = {
204 .notifier_call = qede_netdev_event,
205};
206
e712d52b
YM		 207static
208int __init qede_init(void)
209{
210 int ret;
e712d52b
YM		 211
212 pr_notice("qede_init: %s\n", version);
213
95114344 214 qed_ops = qed_get_eth_ops();
e712d52b
YM		 215 if (!qed_ops) {
216 pr_notice("Failed to get qed ethtool operations\n");
217 return -EINVAL;
218 }
219
2950219d
YM		 220 /* Must register notifier before pci ops, since we might miss
221 * interface rename after pci probe and netdev registeration.
222 */
223 ret = register_netdevice_notifier(&qede_netdev_notifier);
224 if (ret) {
225 pr_notice("Failed to register netdevice_notifier\n");
226 qed_put_eth_ops();
227 return -EINVAL;
228 }
229
e712d52b
YM		 230 ret = pci_register_driver(&qede_pci_driver);
231 if (ret) {
232 pr_notice("Failed to register driver\n");
2950219d 233 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 234 qed_put_eth_ops();
235 return -EINVAL;
236 }
237
238 return 0;
239}
240
241static void __exit qede_cleanup(void)
242{
243 pr_notice("qede_cleanup called\n");
244
2950219d 245 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 246 pci_unregister_driver(&qede_pci_driver);
247 qed_put_eth_ops();
248}
249
250module_init(qede_init);
251module_exit(qede_cleanup);
252
2950219d
YM		 253/* -------------------------------------------------------------------------
254 * START OF FAST-PATH
255 * -------------------------------------------------------------------------
256 */
257
258/* Unmap the data and free skb */
259static int qede_free_tx_pkt(struct qede_dev *edev,
260 struct qede_tx_queue *txq,
261 int *len)
262{
263 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
264 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
265 struct eth_tx_1st_bd *first_bd;
266 struct eth_tx_bd *tx_data_bd;
267 int bds_consumed = 0;
268 int nbds;
269 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
270 int i, split_bd_len = 0;
271
272 if (unlikely(!skb)) {
273 DP_ERR(edev,
274 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
275 idx, txq->sw_tx_cons, txq->sw_tx_prod);
276 return -1;
277 }
278
279 *len = skb->len;
280
281 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
282
283 bds_consumed++;
284
285 nbds = first_bd->data.nbds;
286
287 if (data_split) {
288 struct eth_tx_bd *split = (struct eth_tx_bd *)
289 qed_chain_consume(&txq->tx_pbl);
290 split_bd_len = BD_UNMAP_LEN(split);
291 bds_consumed++;
292 }
293 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
294 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
295
296 /* Unmap the data of the skb frags */
297 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
298 tx_data_bd = (struct eth_tx_bd *)
299 qed_chain_consume(&txq->tx_pbl);
300 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
301 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
302 }
303
304 while (bds_consumed++ < nbds)
305 qed_chain_consume(&txq->tx_pbl);
306
307 /* Free skb */
308 dev_kfree_skb_any(skb);
309 txq->sw_tx_ring[idx].skb = NULL;
310 txq->sw_tx_ring[idx].flags = 0;
311
312 return 0;
313}
314
315/* Unmap the data and free skb when mapping failed during start_xmit */
316static void qede_free_failed_tx_pkt(struct qede_dev *edev,
317 struct qede_tx_queue *txq,
318 struct eth_tx_1st_bd *first_bd,
319 int nbd,
320 bool data_split)
321{
322 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
323 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
324 struct eth_tx_bd *tx_data_bd;
325 int i, split_bd_len = 0;
326
327 /* Return prod to its position before this skb was handled */
328 qed_chain_set_prod(&txq->tx_pbl,
329 le16_to_cpu(txq->tx_db.data.bd_prod),
330 first_bd);
331
332 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
333
334 if (data_split) {
335 struct eth_tx_bd *split = (struct eth_tx_bd *)
336 qed_chain_produce(&txq->tx_pbl);
337 split_bd_len = BD_UNMAP_LEN(split);
338 nbd--;
339 }
340
341 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
342 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
343
344 /* Unmap the data of the skb frags */
345 for (i = 0; i < nbd; i++) {
346 tx_data_bd = (struct eth_tx_bd *)
347 qed_chain_produce(&txq->tx_pbl);
348 if (tx_data_bd->nbytes)
349 dma_unmap_page(&edev->pdev->dev,
350 BD_UNMAP_ADDR(tx_data_bd),
351 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
352 }
353
354 /* Return again prod to its position before this skb was handled */
355 qed_chain_set_prod(&txq->tx_pbl,
356 le16_to_cpu(txq->tx_db.data.bd_prod),
357 first_bd);
358
359 /* Free skb */
360 dev_kfree_skb_any(skb);
361 txq->sw_tx_ring[idx].skb = NULL;
362 txq->sw_tx_ring[idx].flags = 0;
363}
364
365static u32 qede_xmit_type(struct qede_dev *edev,
366 struct sk_buff *skb,
367 int *ipv6_ext)
368{
369 u32 rc = XMIT_L4_CSUM;
370 __be16 l3_proto;
371
372 if (skb->ip_summed != CHECKSUM_PARTIAL)
373 return XMIT_PLAIN;
374
375 l3_proto = vlan_get_protocol(skb);
376 if (l3_proto == htons(ETH_P_IPV6) &&
377 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
378 *ipv6_ext = 1;
379
14db81de
MC		 380 if (skb->encapsulation)
381 rc |= XMIT_ENC;
382
2950219d
YM		 383 if (skb_is_gso(skb))
384 rc |= XMIT_LSO;
385
386 return rc;
387}
388
389static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
390 struct eth_tx_2nd_bd *second_bd,
391 struct eth_tx_3rd_bd *third_bd)
392{
393 u8 l4_proto;
fc48b7a6 394 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 395
fc48b7a6 396 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 397
fc48b7a6 398 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 399 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
400 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
401
fc48b7a6 402 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 403 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
404
405 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
406 l4_proto = ipv6_hdr(skb)->nexthdr;
407 else
408 l4_proto = ip_hdr(skb)->protocol;
409
410 if (l4_proto == IPPROTO_UDP)
fc48b7a6 411 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 412
fc48b7a6 413 if (third_bd)
2950219d 414 third_bd->data.bitfields |=
fc48b7a6
YM		 415 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
416 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
417 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 418
fc48b7a6 419 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 420 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
421}
422
423static int map_frag_to_bd(struct qede_dev *edev,
424 skb_frag_t *frag,
425 struct eth_tx_bd *bd)
426{
427 dma_addr_t mapping;
428
429 /* Map skb non-linear frag data for DMA */
430 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
431 skb_frag_size(frag),
432 DMA_TO_DEVICE);
433 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
434 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
435 return -ENOMEM;
436 }
437
438 /* Setup the data pointer of the frag data */
439 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
440
441 return 0;
442}
443
14db81de
MC		 444static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
445{
446 if (is_encap_pkt)
447 return (skb_inner_transport_header(skb) +
448 inner_tcp_hdrlen(skb) - skb->data);
449 else
450 return (skb_transport_header(skb) +
451 tcp_hdrlen(skb) - skb->data);
452}
453
b1199b10
YM		 454/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
455#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
456static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
457 u8 xmit_type)
458{
459 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
460
461 if (xmit_type & XMIT_LSO) {
462 int hlen;
463
14db81de 464 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 465
466 /* linear payload would require its own BD */
467 if (skb_headlen(skb) > hlen)
468 allowed_frags--;
469 }
470
471 return (skb_shinfo(skb)->nr_frags > allowed_frags);
472}
473#endif
474
2950219d
YM		 475/* Main transmit function */
476static
477netdev_tx_t qede_start_xmit(struct sk_buff *skb,
478 struct net_device *ndev)
479{
480 struct qede_dev *edev = netdev_priv(ndev);
481 struct netdev_queue *netdev_txq;
482 struct qede_tx_queue *txq;
483 struct eth_tx_1st_bd *first_bd;
484 struct eth_tx_2nd_bd *second_bd = NULL;
485 struct eth_tx_3rd_bd *third_bd = NULL;
486 struct eth_tx_bd *tx_data_bd = NULL;
487 u16 txq_index;
488 u8 nbd = 0;
489 dma_addr_t mapping;
490 int rc, frag_idx = 0, ipv6_ext = 0;
491 u8 xmit_type;
492 u16 idx;
493 u16 hlen;
810810ff 494 bool data_split = false;
2950219d
YM		 495
496 /* Get tx-queue context and netdev index */
497 txq_index = skb_get_queue_mapping(skb);
498 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
499 txq = QEDE_TX_QUEUE(edev, txq_index);
500 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
501
2950219d
YM		 502 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) <
503 (MAX_SKB_FRAGS + 1));
504
505 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
506
b1199b10
YM		 507#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
508 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
509 if (skb_linearize(skb)) {
510 DP_NOTICE(edev,
511 "SKB linearization failed - silently dropping this SKB\n");
512 dev_kfree_skb_any(skb);
513 return NETDEV_TX_OK;
514 }
515 }
516#endif
517
2950219d
YM		 518 /* Fill the entry in the SW ring and the BDs in the FW ring */
519 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
520 txq->sw_tx_ring[idx].skb = skb;
521 first_bd = (struct eth_tx_1st_bd *)
522 qed_chain_produce(&txq->tx_pbl);
523 memset(first_bd, 0, sizeof(*first_bd));
524 first_bd->data.bd_flags.bitfields =
525 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
526
527 /* Map skb linear data for DMA and set in the first BD */
528 mapping = dma_map_single(&edev->pdev->dev, skb->data,
529 skb_headlen(skb), DMA_TO_DEVICE);
530 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
531 DP_NOTICE(edev, "SKB mapping failed\n");
532 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
533 return NETDEV_TX_OK;
534 }
535 nbd++;
536 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
537
538 /* In case there is IPv6 with extension headers or LSO we need 2nd and
539 * 3rd BDs.
540 */
541 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
542 second_bd = (struct eth_tx_2nd_bd *)
543 qed_chain_produce(&txq->tx_pbl);
544 memset(second_bd, 0, sizeof(*second_bd));
545
546 nbd++;
547 third_bd = (struct eth_tx_3rd_bd *)
548 qed_chain_produce(&txq->tx_pbl);
549 memset(third_bd, 0, sizeof(*third_bd));
550
551 nbd++;
552 /* We need to fill in additional data in second_bd... */
553 tx_data_bd = (struct eth_tx_bd *)second_bd;
554 }
555
556 if (skb_vlan_tag_present(skb)) {
557 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
558 first_bd->data.bd_flags.bitfields |=
559 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
560 }
561
562 /* Fill the parsing flags & params according to the requested offload */
563 if (xmit_type & XMIT_L4_CSUM) {
fc48b7a6
YM		 564 u16 temp = 1 << ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT;
565
2950219d
YM		 566 /* We don't re-calculate IP checksum as it is already done by
567 * the upper stack
568 */
569 first_bd->data.bd_flags.bitfields |=
570 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
571
14db81de
MC		 572 if (xmit_type & XMIT_ENC) {
573 first_bd->data.bd_flags.bitfields |=
574 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
575 } else {
576 /* In cases when OS doesn't indicate for inner offloads
577 * when packet is tunnelled, we need to override the HW
578 * tunnel configuration so that packets are treated as
579 * regular non tunnelled packets and no inner offloads
580 * are done by the hardware.
581 */
582 first_bd->data.bitfields |= cpu_to_le16(temp);
583 }
fc48b7a6 584
2950219d
YM		 585 /* If the packet is IPv6 with extension header, indicate that
586 * to FW and pass few params, since the device cracker doesn't
587 * support parsing IPv6 with extension header/s.
588 */
589 if (unlikely(ipv6_ext))
590 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
591 }
592
593 if (xmit_type & XMIT_LSO) {
594 first_bd->data.bd_flags.bitfields |=
595 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
596 third_bd->data.lso_mss =
597 cpu_to_le16(skb_shinfo(skb)->gso_size);
598
14db81de
MC		 599 if (unlikely(xmit_type & XMIT_ENC)) {
600 first_bd->data.bd_flags.bitfields |=
601 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
602 hlen = qede_get_skb_hlen(skb, true);
603 } else {
604 first_bd->data.bd_flags.bitfields |=
605 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
606 hlen = qede_get_skb_hlen(skb, false);
607 }
2950219d
YM		 608
609 /* @@@TBD - if will not be removed need to check */
610 third_bd->data.bitfields |=
fc48b7a6 611 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 612
613 /* Make life easier for FW guys who can't deal with header and
614 * data on same BD. If we need to split, use the second bd...
615 */
616 if (unlikely(skb_headlen(skb) > hlen)) {
617 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
618 "TSO split header size is %d (%x:%x)\n",
619 first_bd->nbytes, first_bd->addr.hi,
620 first_bd->addr.lo);
621
622 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
623 le32_to_cpu(first_bd->addr.lo)) +
624 hlen;
625
626 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
627 le16_to_cpu(first_bd->nbytes) -
628 hlen);
629
630 /* this marks the BD as one that has no
631 * individual mapping
632 */
633 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
634
635 first_bd->nbytes = cpu_to_le16(hlen);
636
637 tx_data_bd = (struct eth_tx_bd *)third_bd;
638 data_split = true;
639 }
640 }
641
642 /* Handle fragmented skb */
643 /* special handle for frags inside 2nd and 3rd bds.. */
644 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
645 rc = map_frag_to_bd(edev,
646 &skb_shinfo(skb)->frags[frag_idx],
647 tx_data_bd);
648 if (rc) {
649 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
650 data_split);
651 return NETDEV_TX_OK;
652 }
653
654 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
655 tx_data_bd = (struct eth_tx_bd *)third_bd;
656 else
657 tx_data_bd = NULL;
658
659 frag_idx++;
660 }
661
662 /* map last frags into 4th, 5th .... */
663 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
664 tx_data_bd = (struct eth_tx_bd *)
665 qed_chain_produce(&txq->tx_pbl);
666
667 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
668
669 rc = map_frag_to_bd(edev,
670 &skb_shinfo(skb)->frags[frag_idx],
671 tx_data_bd);
672 if (rc) {
673 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
674 data_split);
675 return NETDEV_TX_OK;
676 }
677 }
678
679 /* update the first BD with the actual num BDs */
680 first_bd->data.nbds = nbd;
681
682 netdev_tx_sent_queue(netdev_txq, skb->len);
683
684 skb_tx_timestamp(skb);
685
686 /* Advance packet producer only before sending the packet since mapping
687 * of pages may fail.
688 */
689 txq->sw_tx_prod++;
690
691 /* 'next page' entries are counted in the producer value */
692 txq->tx_db.data.bd_prod =
693 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
694
695 /* wmb makes sure that the BDs data is updated before updating the
696 * producer, otherwise FW may read old data from the BDs.
697 */
698 wmb();
699 barrier();
700 writel(txq->tx_db.raw, txq->doorbell_addr);
701
702 /* mmiowb is needed to synchronize doorbell writes from more than one
703 * processor. It guarantees that the write arrives to the device before
704 * the queue lock is released and another start_xmit is called (possibly
705 * on another CPU). Without this barrier, the next doorbell can bypass
706 * this doorbell. This is applicable to IA64/Altix systems.
707 */
708 mmiowb();
709
710 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
711 < (MAX_SKB_FRAGS + 1))) {
712 netif_tx_stop_queue(netdev_txq);
713 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
714 "Stop queue was called\n");
715 /* paired memory barrier is in qede_tx_int(), we have to keep
716 * ordering of set_bit() in netif_tx_stop_queue() and read of
717 * fp->bd_tx_cons
718 */
719 smp_mb();
720
721 if (qed_chain_get_elem_left(&txq->tx_pbl)
722 >= (MAX_SKB_FRAGS + 1) &&
723 (edev->state == QEDE_STATE_OPEN)) {
724 netif_tx_wake_queue(netdev_txq);
725 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
726 "Wake queue was called\n");
727 }
728 }
729
730 return NETDEV_TX_OK;
731}
732
16f46bf0 733int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 734{
735 u16 hw_bd_cons;
736
737 /* Tell compiler that consumer and producer can change */
738 barrier();
739 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
740 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
741 return 0;
742
743 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
744}
745
746static int qede_tx_int(struct qede_dev *edev,
747 struct qede_tx_queue *txq)
748{
749 struct netdev_queue *netdev_txq;
750 u16 hw_bd_cons;
751 unsigned int pkts_compl = 0, bytes_compl = 0;
752 int rc;
753
754 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
755
756 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
757 barrier();
758
759 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
760 int len = 0;
761
762 rc = qede_free_tx_pkt(edev, txq, &len);
763 if (rc) {
764 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
765 hw_bd_cons,
766 qed_chain_get_cons_idx(&txq->tx_pbl));
767 break;
768 }
769
770 bytes_compl += len;
771 pkts_compl++;
772 txq->sw_tx_cons++;
773 }
774
775 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
776
777 /* Need to make the tx_bd_cons update visible to start_xmit()
778 * before checking for netif_tx_queue_stopped(). Without the
779 * memory barrier, there is a small possibility that
780 * start_xmit() will miss it and cause the queue to be stopped
781 * forever.
782 * On the other hand we need an rmb() here to ensure the proper
783 * ordering of bit testing in the following
784 * netif_tx_queue_stopped(txq) call.
785 */
786 smp_mb();
787
788 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
789 /* Taking tx_lock is needed to prevent reenabling the queue
790 * while it's empty. This could have happen if rx_action() gets
791 * suspended in qede_tx_int() after the condition before
792 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
793 *
794 * stops the queue->sees fresh tx_bd_cons->releases the queue->
795 * sends some packets consuming the whole queue again->
796 * stops the queue
797 */
798
799 __netif_tx_lock(netdev_txq, smp_processor_id());
800
801 if ((netif_tx_queue_stopped(netdev_txq)) &&
802 (edev->state == QEDE_STATE_OPEN) &&
803 (qed_chain_get_elem_left(&txq->tx_pbl)
804 >= (MAX_SKB_FRAGS + 1))) {
805 netif_tx_wake_queue(netdev_txq);
806 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
807 "Wake queue was called\n");
808 }
809
810 __netif_tx_unlock(netdev_txq);
811 }
812
813 return 0;
814}
815
16f46bf0 816bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 817{
818 u16 hw_comp_cons, sw_comp_cons;
819
820 /* Tell compiler that status block fields can change */
821 barrier();
822
823 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
824 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
825
826 return hw_comp_cons != sw_comp_cons;
827}
828
829static bool qede_has_tx_work(struct qede_fastpath *fp)
830{
831 u8 tc;
832
833 for (tc = 0; tc < fp->edev->num_tc; tc++)
834 if (qede_txq_has_work(&fp->txqs[tc]))
835 return true;
836 return false;
837}
838
f86af2df
MC		 839static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
840{
841 qed_chain_consume(&rxq->rx_bd_ring);
842 rxq->sw_rx_cons++;
843}
844
fc48b7a6
YM		 845/* This function reuses the buffer(from an offset) from
846 * consumer index to producer index in the bd ring
2950219d 847 */
fc48b7a6
YM		 848static inline void qede_reuse_page(struct qede_dev *edev,
849 struct qede_rx_queue *rxq,
850 struct sw_rx_data *curr_cons)
2950219d 851{
2950219d 852 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 853 struct sw_rx_data *curr_prod;
854 dma_addr_t new_mapping;
2950219d 855
fc48b7a6
YM		 856 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
857 *curr_prod = *curr_cons;
2950219d 858
fc48b7a6
YM		 859 new_mapping = curr_prod->mapping + curr_prod->page_offset;
860
861 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
862 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 863
2950219d 864 rxq->sw_rx_prod++;
fc48b7a6
YM		 865 curr_cons->data = NULL;
866}
867
f86af2df
MC		 868/* In case of allocation failures reuse buffers
869 * from consumer index to produce buffers for firmware
870 */
16f46bf0
SRK		 871void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
872 struct qede_dev *edev, u8 count)
f86af2df
MC		 873{
874 struct sw_rx_data *curr_cons;
875
876 for (; count > 0; count--) {
877 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
878 qede_reuse_page(edev, rxq, curr_cons);
879 qede_rx_bd_ring_consume(rxq);
880 }
881}
882
fc48b7a6
YM		 883static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
884 struct qede_rx_queue *rxq,
885 struct sw_rx_data *curr_cons)
886{
887 /* Move to the next segment in the page */
888 curr_cons->page_offset += rxq->rx_buf_seg_size;
889
890 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 891 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
892 /* Since we failed to allocate new buffer
893 * current buffer can be used again.
894 */
895 curr_cons->page_offset -= rxq->rx_buf_seg_size;
896
fc48b7a6 897 return -ENOMEM;
f86af2df 898 }
fc48b7a6
YM		 899
900 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
901 PAGE_SIZE, DMA_FROM_DEVICE);
902 } else {
903 /* Increment refcount of the page as we don't want
904 * network stack to take the ownership of the page
905 * which can be recycled multiple times by the driver.
906 */
907 atomic_inc(&curr_cons->data->_count);
908 qede_reuse_page(edev, rxq, curr_cons);
909 }
910
911 return 0;
2950219d
YM		 912}
913
914static inline void qede_update_rx_prod(struct qede_dev *edev,
915 struct qede_rx_queue *rxq)
916{
917 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
918 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
919 struct eth_rx_prod_data rx_prods = {0};
920
921 /* Update producers */
922 rx_prods.bd_prod = cpu_to_le16(bd_prod);
923 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
924
925 /* Make sure that the BD and SGE data is updated before updating the
926 * producers since FW might read the BD/SGE right after the producer
927 * is updated.
928 */
929 wmb();
930
931 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
932 (u32 *)&rx_prods);
933
934 /* mmiowb is needed to synchronize doorbell writes from more than one
935 * processor. It guarantees that the write arrives to the device before
936 * the napi lock is released and another qede_poll is called (possibly
937 * on another CPU). Without this barrier, the next doorbell can bypass
938 * this doorbell. This is applicable to IA64/Altix systems.
939 */
940 mmiowb();
941}
942
943static u32 qede_get_rxhash(struct qede_dev *edev,
944 u8 bitfields,
945 __le32 rss_hash,
946 enum pkt_hash_types *rxhash_type)
947{
948 enum rss_hash_type htype;
949
950 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
951
952 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
953 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
954 (htype == RSS_HASH_TYPE_IPV6)) ?
955 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
956 return le32_to_cpu(rss_hash);
957 }
958 *rxhash_type = PKT_HASH_TYPE_NONE;
959 return 0;
960}
961
962static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
963{
964 skb_checksum_none_assert(skb);
965
966 if (csum_flag & QEDE_CSUM_UNNECESSARY)
967 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 968
969 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
970 skb->csum_level = 1;
2950219d
YM		 971}
972
973static inline void qede_skb_receive(struct qede_dev *edev,
974 struct qede_fastpath *fp,
975 struct sk_buff *skb,
976 u16 vlan_tag)
977{
978 if (vlan_tag)
979 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
980 vlan_tag);
981
982 napi_gro_receive(&fp->napi, skb);
983}
984
55482edc
MC		 985static void qede_set_gro_params(struct qede_dev *edev,
986 struct sk_buff *skb,
987 struct eth_fast_path_rx_tpa_start_cqe *cqe)
988{
989 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
990
991 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
992 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
993 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
994 else
995 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
996
997 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
998 cqe->header_len;
999}
1000
1001static int qede_fill_frag_skb(struct qede_dev *edev,
1002 struct qede_rx_queue *rxq,
1003 u8 tpa_agg_index,
1004 u16 len_on_bd)
1005{
1006 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
1007 NUM_RX_BDS_MAX];
1008 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
1009 struct sk_buff *skb = tpa_info->skb;
1010
1011 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1012 goto out;
1013
1014 /* Add one frag and update the appropriate fields in the skb */
1015 skb_fill_page_desc(skb, tpa_info->frag_id++,
1016 current_bd->data, current_bd->page_offset,
1017 len_on_bd);
1018
1019 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 1020 /* Incr page ref count to reuse on allocation failure
1021 * so that it doesn't get freed while freeing SKB.
1022 */
1023 atomic_inc(&current_bd->data->_count);
55482edc
MC		 1024 goto out;
1025 }
1026
1027 qed_chain_consume(&rxq->rx_bd_ring);
1028 rxq->sw_rx_cons++;
1029
1030 skb->data_len += len_on_bd;
1031 skb->truesize += rxq->rx_buf_seg_size;
1032 skb->len += len_on_bd;
1033
1034 return 0;
1035
1036out:
f86af2df
MC		 1037 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1038 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1039 return -ENOMEM;
1040}
1041
1042static void qede_tpa_start(struct qede_dev *edev,
1043 struct qede_rx_queue *rxq,
1044 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1045{
1046 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1047 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1048 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
1049 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
1050 dma_addr_t mapping = tpa_info->replace_buf_mapping;
1051 struct sw_rx_data *sw_rx_data_cons;
1052 struct sw_rx_data *sw_rx_data_prod;
1053 enum pkt_hash_types rxhash_type;
1054 u32 rxhash;
1055
1056 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1057 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1058
1059 /* Use pre-allocated replacement buffer - we can't release the agg.
1060 * start until its over and we don't want to risk allocation failing
1061 * here, so re-allocate when aggregation will be over.
1062 */
1063 dma_unmap_addr_set(sw_rx_data_prod, mapping,
1064 dma_unmap_addr(replace_buf, mapping));
1065
1066 sw_rx_data_prod->data = replace_buf->data;
1067 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1068 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1069 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1070
1071 rxq->sw_rx_prod++;
1072
1073 /* move partial skb from cons to pool (don't unmap yet)
1074 * save mapping, incase we drop the packet later on.
1075 */
1076 tpa_info->start_buf = *sw_rx_data_cons;
1077 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1078 le32_to_cpu(rx_bd_cons->addr.lo));
1079
1080 tpa_info->start_buf_mapping = mapping;
1081 rxq->sw_rx_cons++;
1082
1083 /* set tpa state to start only if we are able to allocate skb
1084 * for this aggregation, otherwise mark as error and aggregation will
1085 * be dropped
1086 */
1087 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1088 le16_to_cpu(cqe->len_on_first_bd));
1089 if (unlikely(!tpa_info->skb)) {
f86af2df 1090 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1091 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1092 goto cons_buf;
55482edc
MC		 1093 }
1094
1095 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1096 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1097
1098 /* Start filling in the aggregation info */
1099 tpa_info->frag_id = 0;
1100 tpa_info->agg_state = QEDE_AGG_STATE_START;
1101
1102 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1103 cqe->rss_hash, &rxhash_type);
1104 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1105 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1106 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1107 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1108 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1109 else
1110 tpa_info->vlan_tag = 0;
1111
1112 /* This is needed in order to enable forwarding support */
1113 qede_set_gro_params(edev, tpa_info->skb, cqe);
1114
f86af2df 1115cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1116 if (likely(cqe->ext_bd_len_list[0]))
1117 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1118 le16_to_cpu(cqe->ext_bd_len_list[0]));
1119
1120 if (unlikely(cqe->ext_bd_len_list[1])) {
1121 DP_ERR(edev,
1122 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1123 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1124 }
1125}
1126
88f09bd5 1127#ifdef CONFIG_INET
55482edc
MC		 1128static void qede_gro_ip_csum(struct sk_buff *skb)
1129{
1130 const struct iphdr *iph = ip_hdr(skb);
1131 struct tcphdr *th;
1132
55482edc
MC		 1133 skb_set_transport_header(skb, sizeof(struct iphdr));
1134 th = tcp_hdr(skb);
1135
1136 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1137 iph->saddr, iph->daddr, 0);
1138
1139 tcp_gro_complete(skb);
1140}
1141
1142static void qede_gro_ipv6_csum(struct sk_buff *skb)
1143{
1144 struct ipv6hdr *iph = ipv6_hdr(skb);
1145 struct tcphdr *th;
1146
55482edc
MC		 1147 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1148 th = tcp_hdr(skb);
1149
1150 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1151 &iph->saddr, &iph->daddr, 0);
1152 tcp_gro_complete(skb);
1153}
88f09bd5 1154#endif
55482edc
MC		 1155
1156static void qede_gro_receive(struct qede_dev *edev,
1157 struct qede_fastpath *fp,
1158 struct sk_buff *skb,
1159 u16 vlan_tag)
1160{
ee2fa8e6
MC		 1161 /* FW can send a single MTU sized packet from gro flow
1162 * due to aggregation timeout/last segment etc. which
1163 * is not expected to be a gro packet. If a skb has zero
1164 * frags then simply push it in the stack as non gso skb.
1165 */
1166 if (unlikely(!skb->data_len)) {
1167 skb_shinfo(skb)->gso_type = 0;
1168 skb_shinfo(skb)->gso_size = 0;
1169 goto send_skb;
1170 }
1171
88f09bd5 1172#ifdef CONFIG_INET
55482edc 1173 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1174 skb_set_network_header(skb, 0);
1175
55482edc
MC		 1176 switch (skb->protocol) {
1177 case htons(ETH_P_IP):
1178 qede_gro_ip_csum(skb);
1179 break;
1180 case htons(ETH_P_IPV6):
1181 qede_gro_ipv6_csum(skb);
1182 break;
1183 default:
1184 DP_ERR(edev,
1185 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1186 ntohs(skb->protocol));
1187 }
1188 }
88f09bd5 1189#endif
ee2fa8e6
MC		 1190
1191send_skb:
55482edc
MC		 1192 skb_record_rx_queue(skb, fp->rss_id);
1193 qede_skb_receive(edev, fp, skb, vlan_tag);
1194}
1195
1196static inline void qede_tpa_cont(struct qede_dev *edev,
1197 struct qede_rx_queue *rxq,
1198 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1199{
1200 int i;
1201
1202 for (i = 0; cqe->len_list[i]; i++)
1203 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1204 le16_to_cpu(cqe->len_list[i]));
1205
1206 if (unlikely(i > 1))
1207 DP_ERR(edev,
1208 "Strange - TPA cont with more than a single len_list entry\n");
1209}
1210
1211static void qede_tpa_end(struct qede_dev *edev,
1212 struct qede_fastpath *fp,
1213 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1214{
1215 struct qede_rx_queue *rxq = fp->rxq;
1216 struct qede_agg_info *tpa_info;
1217 struct sk_buff *skb;
1218 int i;
1219
1220 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1221 skb = tpa_info->skb;
1222
1223 for (i = 0; cqe->len_list[i]; i++)
1224 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1225 le16_to_cpu(cqe->len_list[i]));
1226 if (unlikely(i > 1))
1227 DP_ERR(edev,
1228 "Strange - TPA emd with more than a single len_list entry\n");
1229
1230 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1231 goto err;
1232
1233 /* Sanity */
1234 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1235 DP_ERR(edev,
1236 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1237 cqe->num_of_bds, tpa_info->frag_id);
1238 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1239 DP_ERR(edev,
1240 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1241 le16_to_cpu(cqe->total_packet_len), skb->len);
1242
1243 memcpy(skb->data,
1244 page_address(tpa_info->start_buf.data) +
1245 tpa_info->start_cqe.placement_offset +
1246 tpa_info->start_buf.page_offset,
1247 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1248
1249 /* Recycle [mapped] start buffer for the next replacement */
1250 tpa_info->replace_buf = tpa_info->start_buf;
1251 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1252
1253 /* Finalize the SKB */
1254 skb->protocol = eth_type_trans(skb, edev->ndev);
1255 skb->ip_summed = CHECKSUM_UNNECESSARY;
1256
1257 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1258 * to skb_shinfo(skb)->gso_segs
1259 */
1260 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1261
1262 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1263
1264 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1265
1266 return;
1267err:
1268 /* The BD starting the aggregation is still mapped; Re-use it for
1269 * future aggregations [as replacement buffer]
1270 */
1271 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1272 sizeof(struct sw_rx_data));
1273 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1274 tpa_info->start_buf.data = NULL;
1275 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1276 dev_kfree_skb_any(tpa_info->skb);
1277 tpa_info->skb = NULL;
1278}
1279
14db81de
MC		 1280static bool qede_tunn_exist(u16 flag)
1281{
1282 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1283 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1284}
1285
1286static u8 qede_check_tunn_csum(u16 flag)
1287{
1288 u16 csum_flag = 0;
1289 u8 tcsum = 0;
1290
1291 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1292 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1293 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1294 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1295
1296 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1297 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1298 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1299 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1300 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1301 }
1302
1303 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1304 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1305 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1306 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1307
1308 if (csum_flag & flag)
1309 return QEDE_CSUM_ERROR;
1310
1311 return QEDE_CSUM_UNNECESSARY | tcsum;
1312}
1313
1314static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1315{
1316 u16 csum_flag = 0;
1317 u8 csum = 0;
1318
14db81de
MC		 1319 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1320 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1321 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1322 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1323 csum = QEDE_CSUM_UNNECESSARY;
1324 }
1325
1326 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1327 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1328
1329 if (csum_flag & flag)
1330 return QEDE_CSUM_ERROR;
1331
1332 return csum;
1333}
1334
14db81de
MC		 1335static u8 qede_check_csum(u16 flag)
1336{
1337 if (!qede_tunn_exist(flag))
1338 return qede_check_notunn_csum(flag);
1339 else
1340 return qede_check_tunn_csum(flag);
1341}
1342
2950219d
YM		 1343static int qede_rx_int(struct qede_fastpath *fp, int budget)
1344{
1345 struct qede_dev *edev = fp->edev;
1346 struct qede_rx_queue *rxq = fp->rxq;
1347
1348 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1349 int rx_pkt = 0;
1350 u8 csum_flag;
1351
1352 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1353 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1354
1355 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1356 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1357 * read before it is written by FW, then FW writes CQE and SB, and then
1358 * the CPU reads the hw_comp_cons, it will use an old CQE.
1359 */
1360 rmb();
1361
1362 /* Loop to complete all indicated BDs */
1363 while (sw_comp_cons != hw_comp_cons) {
1364 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1365 enum pkt_hash_types rxhash_type;
1366 enum eth_rx_cqe_type cqe_type;
1367 struct sw_rx_data *sw_rx_data;
1368 union eth_rx_cqe *cqe;
1369 struct sk_buff *skb;
fc48b7a6
YM		 1370 struct page *data;
1371 __le16 flags;
2950219d
YM		 1372 u16 len, pad;
1373 u32 rx_hash;
2950219d
YM		 1374
1375 /* Get the CQE from the completion ring */
1376 cqe = (union eth_rx_cqe *)
1377 qed_chain_consume(&rxq->rx_comp_ring);
1378 cqe_type = cqe->fast_path_regular.type;
1379
1380 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1381 edev->ops->eth_cqe_completion(
1382 edev->cdev, fp->rss_id,
1383 (struct eth_slow_path_rx_cqe *)cqe);
1384 goto next_cqe;
1385 }
1386
55482edc
MC		 1387 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1388 switch (cqe_type) {
1389 case ETH_RX_CQE_TYPE_TPA_START:
1390 qede_tpa_start(edev, rxq,
1391 &cqe->fast_path_tpa_start);
1392 goto next_cqe;
1393 case ETH_RX_CQE_TYPE_TPA_CONT:
1394 qede_tpa_cont(edev, rxq,
1395 &cqe->fast_path_tpa_cont);
1396 goto next_cqe;
1397 case ETH_RX_CQE_TYPE_TPA_END:
1398 qede_tpa_end(edev, fp,
1399 &cqe->fast_path_tpa_end);
1400 goto next_rx_only;
1401 default:
1402 break;
1403 }
1404 }
1405
2950219d
YM		 1406 /* Get the data from the SW ring */
1407 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1408 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1409 data = sw_rx_data->data;
1410
1411 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1412 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1413 pad = fp_cqe->placement_offset;
fc48b7a6 1414 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1415
fc48b7a6
YM		 1416 /* If this is an error packet then drop it */
1417 parse_flag = le16_to_cpu(flags);
2950219d 1418
fc48b7a6
YM		 1419 csum_flag = qede_check_csum(parse_flag);
1420 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
1421 DP_NOTICE(edev,
1422 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1423 sw_comp_cons, parse_flag);
1424 rxq->rx_hw_errors++;
f86af2df
MC		 1425 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1426 goto next_cqe;
fc48b7a6 1427 }
2950219d 1428
fc48b7a6
YM		 1429 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1430 if (unlikely(!skb)) {
2950219d 1431 DP_NOTICE(edev,
fc48b7a6 1432 "Build_skb failed, dropping incoming packet\n");
f86af2df 1433 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1434 rxq->rx_alloc_errors++;
f86af2df 1435 goto next_cqe;
fc48b7a6
YM		 1436 }
1437
1438 /* Copy data into SKB */
1439 if (len + pad <= QEDE_RX_HDR_SIZE) {
1440 memcpy(skb_put(skb, len),
1441 page_address(data) + pad +
1442 sw_rx_data->page_offset, len);
1443 qede_reuse_page(edev, rxq, sw_rx_data);
1444 } else {
1445 struct skb_frag_struct *frag;
1446 unsigned int pull_len;
1447 unsigned char *va;
1448
1449 frag = &skb_shinfo(skb)->frags[0];
1450
1451 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1452 pad + sw_rx_data->page_offset,
1453 len, rxq->rx_buf_seg_size);
1454
1455 va = skb_frag_address(frag);
1456 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1457
1458 /* Align the pull_len to optimize memcpy */
1459 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1460
1461 skb_frag_size_sub(frag, pull_len);
1462 frag->page_offset += pull_len;
1463 skb->data_len -= pull_len;
1464 skb->tail += pull_len;
1465
1466 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1467 sw_rx_data))) {
1468 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1469 /* Incr page ref count to reuse on allocation
1470 * failure so that it doesn't get freed while
1471 * freeing SKB.
1472 */
1473
1474 atomic_inc(&sw_rx_data->data->_count);
fc48b7a6 1475 rxq->rx_alloc_errors++;
f86af2df
MC		 1476 qede_recycle_rx_bd_ring(rxq, edev,
1477 fp_cqe->bd_num);
1478 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1479 goto next_cqe;
1480 }
2950219d
YM		 1481 }
1482
f86af2df
MC		 1483 qede_rx_bd_ring_consume(rxq);
1484
fc48b7a6
YM		 1485 if (fp_cqe->bd_num != 1) {
1486 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1487 u8 num_frags;
1488
1489 pkt_len -= len;
1490
1491 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1492 num_frags--) {
1493 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1494 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1495 if (unlikely(!cur_size)) {
1496 DP_ERR(edev,
1497 "Still got %d BDs for mapping jumbo, but length became 0\n",
1498 num_frags);
1499 qede_recycle_rx_bd_ring(rxq, edev,
1500 num_frags);
1501 dev_kfree_skb_any(skb);
1502 goto next_cqe;
1503 }
fc48b7a6 1504
f86af2df
MC		 1505 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1506 qede_recycle_rx_bd_ring(rxq, edev,
1507 num_frags);
1508 dev_kfree_skb_any(skb);
fc48b7a6 1509 goto next_cqe;
f86af2df 1510 }
fc48b7a6 1511
fc48b7a6
YM		 1512 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1513 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1514 qede_rx_bd_ring_consume(rxq);
1515
fc48b7a6
YM		 1516 dma_unmap_page(&edev->pdev->dev,
1517 sw_rx_data->mapping,
1518 PAGE_SIZE, DMA_FROM_DEVICE);
1519
1520 skb_fill_page_desc(skb,
1521 skb_shinfo(skb)->nr_frags++,
1522 sw_rx_data->data, 0,
1523 cur_size);
1524
1525 skb->truesize += PAGE_SIZE;
1526 skb->data_len += cur_size;
1527 skb->len += cur_size;
1528 pkt_len -= cur_size;
1529 }
2950219d 1530
f86af2df 1531 if (unlikely(pkt_len))
fc48b7a6
YM		 1532 DP_ERR(edev,
1533 "Mapped all BDs of jumbo, but still have %d bytes\n",
1534 pkt_len);
1535 }
2950219d
YM		 1536
1537 skb->protocol = eth_type_trans(skb, edev->ndev);
1538
1539 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1540 fp_cqe->rss_hash,
1541 &rxhash_type);
1542
1543 skb_set_hash(skb, rx_hash, rxhash_type);
1544
1545 qede_set_skb_csum(skb, csum_flag);
1546
1547 skb_record_rx_queue(skb, fp->rss_id);
1548
1549 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1550next_rx_only:
2950219d
YM		 1551 rx_pkt++;
1552
1553next_cqe: /* don't consume bd rx buffer */
1554 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1555 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1556 /* CR TPA - revisit how to handle budget in TPA perhaps
1557 * increase on "end"
1558 */
1559 if (rx_pkt == budget)
1560 break;
1561 } /* repeat while sw_comp_cons != hw_comp_cons... */
1562
1563 /* Update producers */
1564 qede_update_rx_prod(edev, rxq);
1565
1566 return rx_pkt;
1567}
1568
1569static int qede_poll(struct napi_struct *napi, int budget)
1570{
1571 int work_done = 0;
1572 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
1573 napi);
1574 struct qede_dev *edev = fp->edev;
1575
1576 while (1) {
1577 u8 tc;
1578
1579 for (tc = 0; tc < edev->num_tc; tc++)
1580 if (qede_txq_has_work(&fp->txqs[tc]))
1581 qede_tx_int(edev, &fp->txqs[tc]);
1582
1583 if (qede_has_rx_work(fp->rxq)) {
1584 work_done += qede_rx_int(fp, budget - work_done);
1585
1586 /* must not complete if we consumed full budget */
1587 if (work_done >= budget)
1588 break;
1589 }
1590
1591 /* Fall out from the NAPI loop if needed */
1592 if (!(qede_has_rx_work(fp->rxq) || qede_has_tx_work(fp))) {
1593 qed_sb_update_sb_idx(fp->sb_info);
1594 /* *_has_*_work() reads the status block,
1595 * thus we need to ensure that status block indices
1596 * have been actually read (qed_sb_update_sb_idx)
1597 * prior to this check (*_has_*_work) so that
1598 * we won't write the "newer" value of the status block
1599 * to HW (if there was a DMA right after
1600 * qede_has_rx_work and if there is no rmb, the memory
1601 * reading (qed_sb_update_sb_idx) may be postponed
1602 * to right before *_ack_sb). In this case there
1603 * will never be another interrupt until there is
1604 * another update of the status block, while there
1605 * is still unhandled work.
1606 */
1607 rmb();
1608
1609 if (!(qede_has_rx_work(fp->rxq) ||
1610 qede_has_tx_work(fp))) {
1611 napi_complete(napi);
1612 /* Update and reenable interrupts */
1613 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1614 1 /*update*/);
1615 break;
1616 }
1617 }
1618 }
1619
1620 return work_done;
1621}
1622
1623static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1624{
1625 struct qede_fastpath *fp = fp_cookie;
1626
1627 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1628
1629 napi_schedule_irqoff(&fp->napi);
1630 return IRQ_HANDLED;
1631}
1632
1633/* -------------------------------------------------------------------------
1634 * END OF FAST-PATH
1635 * -------------------------------------------------------------------------
1636 */
1637
1638static int qede_open(struct net_device *ndev);
1639static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1640static int qede_set_mac_addr(struct net_device *ndev, void *p);
1641static void qede_set_rx_mode(struct net_device *ndev);
1642static void qede_config_rx_mode(struct net_device *ndev);
1643
1644static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1645 enum qed_filter_xcast_params_type opcode,
1646 unsigned char mac[ETH_ALEN])
1647{
1648 struct qed_filter_params filter_cmd;
1649
1650 memset(&filter_cmd, 0, sizeof(filter_cmd));
1651 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1652 filter_cmd.filter.ucast.type = opcode;
1653 filter_cmd.filter.ucast.mac_valid = 1;
1654 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1655
1656 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1657}
1658
7c1bfcad
SRK		 1659static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1660 enum qed_filter_xcast_params_type opcode,
1661 u16 vid)
1662{
1663 struct qed_filter_params filter_cmd;
1664
1665 memset(&filter_cmd, 0, sizeof(filter_cmd));
1666 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1667 filter_cmd.filter.ucast.type = opcode;
1668 filter_cmd.filter.ucast.vlan_valid = 1;
1669 filter_cmd.filter.ucast.vlan = vid;
1670
1671 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1672}
1673
133fac0e
SK		 1674void qede_fill_by_demand_stats(struct qede_dev *edev)
1675{
1676 struct qed_eth_stats stats;
1677
1678 edev->ops->get_vport_stats(edev->cdev, &stats);
1679 edev->stats.no_buff_discards = stats.no_buff_discards;
1680 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1681 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1682 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1683 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1684 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1685 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1686 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1687 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1688
1689 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1690 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1691 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1692 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1693 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1694 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1695 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1696 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1697 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1698 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1699 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1700 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1701
1702 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1703 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1704 edev->stats.rx_128_to_255_byte_packets =
1705 stats.rx_128_to_255_byte_packets;
1706 edev->stats.rx_256_to_511_byte_packets =
1707 stats.rx_256_to_511_byte_packets;
1708 edev->stats.rx_512_to_1023_byte_packets =
1709 stats.rx_512_to_1023_byte_packets;
1710 edev->stats.rx_1024_to_1518_byte_packets =
1711 stats.rx_1024_to_1518_byte_packets;
1712 edev->stats.rx_1519_to_1522_byte_packets =
1713 stats.rx_1519_to_1522_byte_packets;
1714 edev->stats.rx_1519_to_2047_byte_packets =
1715 stats.rx_1519_to_2047_byte_packets;
1716 edev->stats.rx_2048_to_4095_byte_packets =
1717 stats.rx_2048_to_4095_byte_packets;
1718 edev->stats.rx_4096_to_9216_byte_packets =
1719 stats.rx_4096_to_9216_byte_packets;
1720 edev->stats.rx_9217_to_16383_byte_packets =
1721 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1722 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1723 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1724 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1725 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1726 edev->stats.rx_align_errors = stats.rx_align_errors;
1727 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1728 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1729 edev->stats.rx_jabbers = stats.rx_jabbers;
1730 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1731 edev->stats.rx_fragments = stats.rx_fragments;
1732 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1733 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1734 edev->stats.tx_128_to_255_byte_packets =
1735 stats.tx_128_to_255_byte_packets;
1736 edev->stats.tx_256_to_511_byte_packets =
1737 stats.tx_256_to_511_byte_packets;
1738 edev->stats.tx_512_to_1023_byte_packets =
1739 stats.tx_512_to_1023_byte_packets;
1740 edev->stats.tx_1024_to_1518_byte_packets =
1741 stats.tx_1024_to_1518_byte_packets;
1742 edev->stats.tx_1519_to_2047_byte_packets =
1743 stats.tx_1519_to_2047_byte_packets;
1744 edev->stats.tx_2048_to_4095_byte_packets =
1745 stats.tx_2048_to_4095_byte_packets;
1746 edev->stats.tx_4096_to_9216_byte_packets =
1747 stats.tx_4096_to_9216_byte_packets;
1748 edev->stats.tx_9217_to_16383_byte_packets =
1749 stats.tx_9217_to_16383_byte_packets;
1750 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1751 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1752 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1753 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1754 edev->stats.brb_truncates = stats.brb_truncates;
1755 edev->stats.brb_discards = stats.brb_discards;
1756 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1757}
1758
1759static struct rtnl_link_stats64 *qede_get_stats64(
1760 struct net_device *dev,
1761 struct rtnl_link_stats64 *stats)
1762{
1763 struct qede_dev *edev = netdev_priv(dev);
1764
1765 qede_fill_by_demand_stats(edev);
1766
1767 stats->rx_packets = edev->stats.rx_ucast_pkts +
1768 edev->stats.rx_mcast_pkts +
1769 edev->stats.rx_bcast_pkts;
1770 stats->tx_packets = edev->stats.tx_ucast_pkts +
1771 edev->stats.tx_mcast_pkts +
1772 edev->stats.tx_bcast_pkts;
1773
1774 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1775 edev->stats.rx_mcast_bytes +
1776 edev->stats.rx_bcast_bytes;
1777
1778 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1779 edev->stats.tx_mcast_bytes +
1780 edev->stats.tx_bcast_bytes;
1781
1782 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1783 stats->multicast = edev->stats.rx_mcast_pkts +
1784 edev->stats.rx_bcast_pkts;
1785
1786 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1787
1788 stats->collisions = edev->stats.tx_total_collisions;
1789 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1790 stats->rx_frame_errors = edev->stats.rx_align_errors;
1791
1792 return stats;
1793}
1794
733def6a 1795#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 1796static int qede_get_vf_config(struct net_device *dev, int vfidx,
1797 struct ifla_vf_info *ivi)
1798{
1799 struct qede_dev *edev = netdev_priv(dev);
1800
1801 if (!edev->ops)
1802 return -EINVAL;
1803
1804 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
1805}
1806
733def6a
YM		 1807static int qede_set_vf_rate(struct net_device *dev, int vfidx,
1808 int min_tx_rate, int max_tx_rate)
1809{
1810 struct qede_dev *edev = netdev_priv(dev);
1811
1812 return edev->ops->iov->set_rate(edev->cdev, vfidx, max_tx_rate,
1813 max_tx_rate);
1814}
1815
6ddc7608
YM		 1816static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
1817{
1818 struct qede_dev *edev = netdev_priv(dev);
1819
1820 if (!edev->ops)
1821 return -EINVAL;
1822
1823 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
1824}
1825
733def6a
YM		 1826static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
1827 int link_state)
1828{
1829 struct qede_dev *edev = netdev_priv(dev);
1830
1831 if (!edev->ops)
1832 return -EINVAL;
1833
1834 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
1835}
1836#endif
1837
7c1bfcad
SRK		 1838static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1839{
1840 struct qed_update_vport_params params;
1841 int rc;
1842
1843 /* Proceed only if action actually needs to be performed */
1844 if (edev->accept_any_vlan == action)
1845 return;
1846
1847 memset(&params, 0, sizeof(params));
1848
1849 params.vport_id = 0;
1850 params.accept_any_vlan = action;
1851 params.update_accept_any_vlan_flg = 1;
1852
1853 rc = edev->ops->vport_update(edev->cdev, &params);
1854 if (rc) {
1855 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1856 action ? "enable" : "disable");
1857 } else {
1858 DP_INFO(edev, "%s accept-any-vlan\n",
1859 action ? "enabled" : "disabled");
1860 edev->accept_any_vlan = action;
1861 }
1862}
1863
1864static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1865{
1866 struct qede_dev *edev = netdev_priv(dev);
1867 struct qede_vlan *vlan, *tmp;
1868 int rc;
1869
1870 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1871
1872 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1873 if (!vlan) {
1874 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1875 return -ENOMEM;
1876 }
1877 INIT_LIST_HEAD(&vlan->list);
1878 vlan->vid = vid;
1879 vlan->configured = false;
1880
1881 /* Verify vlan isn't already configured */
1882 list_for_each_entry(tmp, &edev->vlan_list, list) {
1883 if (tmp->vid == vlan->vid) {
1884 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1885 "vlan already configured\n");
1886 kfree(vlan);
1887 return -EEXIST;
1888 }
1889 }
1890
1891 /* If interface is down, cache this VLAN ID and return */
1892 if (edev->state != QEDE_STATE_OPEN) {
1893 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1894 "Interface is down, VLAN %d will be configured when interface is up\n",
1895 vid);
1896 if (vid != 0)
1897 edev->non_configured_vlans++;
1898 list_add(&vlan->list, &edev->vlan_list);
1899
1900 return 0;
1901 }
1902
1903 /* Check for the filter limit.
1904 * Note - vlan0 has a reserved filter and can be added without
1905 * worrying about quota
1906 */
1907 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1908 (vlan->vid == 0)) {
1909 rc = qede_set_ucast_rx_vlan(edev,
1910 QED_FILTER_XCAST_TYPE_ADD,
1911 vlan->vid);
1912 if (rc) {
1913 DP_ERR(edev, "Failed to configure VLAN %d\n",
1914 vlan->vid);
1915 kfree(vlan);
1916 return -EINVAL;
1917 }
1918 vlan->configured = true;
1919
1920 /* vlan0 filter isn't consuming out of our quota */
1921 if (vlan->vid != 0)
1922 edev->configured_vlans++;
1923 } else {
1924 /* Out of quota; Activate accept-any-VLAN mode */
1925 if (!edev->non_configured_vlans)
1926 qede_config_accept_any_vlan(edev, true);
1927
1928 edev->non_configured_vlans++;
1929 }
1930
1931 list_add(&vlan->list, &edev->vlan_list);
1932
1933 return 0;
1934}
1935
1936static void qede_del_vlan_from_list(struct qede_dev *edev,
1937 struct qede_vlan *vlan)
1938{
1939 /* vlan0 filter isn't consuming out of our quota */
1940 if (vlan->vid != 0) {
1941 if (vlan->configured)
1942 edev->configured_vlans--;
1943 else
1944 edev->non_configured_vlans--;
1945 }
1946
1947 list_del(&vlan->list);
1948 kfree(vlan);
1949}
1950
1951static int qede_configure_vlan_filters(struct qede_dev *edev)
1952{
1953 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1954 struct qed_dev_eth_info *dev_info;
1955 struct qede_vlan *vlan = NULL;
1956
1957 if (list_empty(&edev->vlan_list))
1958 return 0;
1959
1960 dev_info = &edev->dev_info;
1961
1962 /* Configure non-configured vlans */
1963 list_for_each_entry(vlan, &edev->vlan_list, list) {
1964 if (vlan->configured)
1965 continue;
1966
1967 /* We have used all our credits, now enable accept_any_vlan */
1968 if ((vlan->vid != 0) &&
1969 (edev->configured_vlans == dev_info->num_vlan_filters)) {
1970 accept_any_vlan = 1;
1971 continue;
1972 }
1973
1974 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
1975
1976 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
1977 vlan->vid);
1978 if (rc) {
1979 DP_ERR(edev, "Failed to configure VLAN %u\n",
1980 vlan->vid);
1981 real_rc = rc;
1982 continue;
1983 }
1984
1985 vlan->configured = true;
1986 /* vlan0 filter doesn't consume our VLAN filter's quota */
1987 if (vlan->vid != 0) {
1988 edev->non_configured_vlans--;
1989 edev->configured_vlans++;
1990 }
1991 }
1992
1993 /* enable accept_any_vlan mode if we have more VLANs than credits,
1994 * or remove accept_any_vlan mode if we've actually removed
1995 * a non-configured vlan, and all remaining vlans are truly configured.
1996 */
1997
1998 if (accept_any_vlan)
1999 qede_config_accept_any_vlan(edev, true);
2000 else if (!edev->non_configured_vlans)
2001 qede_config_accept_any_vlan(edev, false);
2002
2003 return real_rc;
2004}
2005
2006static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
2007{
2008 struct qede_dev *edev = netdev_priv(dev);
2009 struct qede_vlan *vlan = NULL;
2010 int rc;
2011
2012 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
2013
2014 /* Find whether entry exists */
2015 list_for_each_entry(vlan, &edev->vlan_list, list)
2016 if (vlan->vid == vid)
2017 break;
2018
2019 if (!vlan || (vlan->vid != vid)) {
2020 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
2021 "Vlan isn't configured\n");
2022 return 0;
2023 }
2024
2025 if (edev->state != QEDE_STATE_OPEN) {
2026 /* As interface is already down, we don't have a VPORT
2027 * instance to remove vlan filter. So just update vlan list
2028 */
2029 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2030 "Interface is down, removing VLAN from list only\n");
2031 qede_del_vlan_from_list(edev, vlan);
2032 return 0;
2033 }
2034
2035 /* Remove vlan */
2036 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL, vid);
2037 if (rc) {
2038 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
2039 return -EINVAL;
2040 }
2041
2042 qede_del_vlan_from_list(edev, vlan);
2043
2044 /* We have removed a VLAN - try to see if we can
2045 * configure non-configured VLAN from the list.
2046 */
2047 rc = qede_configure_vlan_filters(edev);
2048
2049 return rc;
2050}
2051
2052static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
2053{
2054 struct qede_vlan *vlan = NULL;
2055
2056 if (list_empty(&edev->vlan_list))
2057 return;
2058
2059 list_for_each_entry(vlan, &edev->vlan_list, list) {
2060 if (!vlan->configured)
2061 continue;
2062
2063 vlan->configured = false;
2064
2065 /* vlan0 filter isn't consuming out of our quota */
2066 if (vlan->vid != 0) {
2067 edev->non_configured_vlans++;
2068 edev->configured_vlans--;
2069 }
2070
2071 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2072 "marked vlan %d as non-configured\n",
2073 vlan->vid);
2074 }
2075
2076 edev->accept_any_vlan = false;
2077}
2078
b18e170c
MC		 2079#ifdef CONFIG_QEDE_VXLAN
2080static void qede_add_vxlan_port(struct net_device *dev,
2081 sa_family_t sa_family, __be16 port)
2082{
2083 struct qede_dev *edev = netdev_priv(dev);
2084 u16 t_port = ntohs(port);
2085
2086 if (edev->vxlan_dst_port)
2087 return;
2088
2089 edev->vxlan_dst_port = t_port;
2090
2091 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d", t_port);
2092
2093 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2094 schedule_delayed_work(&edev->sp_task, 0);
2095}
2096
2097static void qede_del_vxlan_port(struct net_device *dev,
2098 sa_family_t sa_family, __be16 port)
2099{
2100 struct qede_dev *edev = netdev_priv(dev);
2101 u16 t_port = ntohs(port);
2102
2103 if (t_port != edev->vxlan_dst_port)
2104 return;
2105
2106 edev->vxlan_dst_port = 0;
2107
2108 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d", t_port);
2109
2110 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2111 schedule_delayed_work(&edev->sp_task, 0);
2112}
2113#endif
2114
9a109dd0
MC		 2115#ifdef CONFIG_QEDE_GENEVE
2116static void qede_add_geneve_port(struct net_device *dev,
2117 sa_family_t sa_family, __be16 port)
2118{
2119 struct qede_dev *edev = netdev_priv(dev);
2120 u16 t_port = ntohs(port);
2121
2122 if (edev->geneve_dst_port)
2123 return;
2124
2125 edev->geneve_dst_port = t_port;
2126
2127 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d", t_port);
2128 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2129 schedule_delayed_work(&edev->sp_task, 0);
2130}
2131
2132static void qede_del_geneve_port(struct net_device *dev,
2133 sa_family_t sa_family, __be16 port)
2134{
2135 struct qede_dev *edev = netdev_priv(dev);
2136 u16 t_port = ntohs(port);
2137
2138 if (t_port != edev->geneve_dst_port)
2139 return;
2140
2141 edev->geneve_dst_port = 0;
2142
2143 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d", t_port);
2144 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2145 schedule_delayed_work(&edev->sp_task, 0);
2146}
2147#endif
2148
2950219d
YM		 2149static const struct net_device_ops qede_netdev_ops = {
2150 .ndo_open = qede_open,
2151 .ndo_stop = qede_close,
2152 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2153 .ndo_set_rx_mode = qede_set_rx_mode,
2154 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2155 .ndo_validate_addr = eth_validate_addr,
133fac0e 2156 .ndo_change_mtu = qede_change_mtu,
08feecd7 2157#ifdef CONFIG_QED_SRIOV
eff16960 2158 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7
YM		 2159 .ndo_set_vf_vlan = qede_set_vf_vlan,
2160#endif
7c1bfcad
SRK		 2161 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2162 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
133fac0e 2163 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 2164#ifdef CONFIG_QED_SRIOV
2165 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 2166 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 2167 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 2168 .ndo_set_vf_rate = qede_set_vf_rate,
2169#endif
b18e170c
MC		 2170#ifdef CONFIG_QEDE_VXLAN
2171 .ndo_add_vxlan_port = qede_add_vxlan_port,
2172 .ndo_del_vxlan_port = qede_del_vxlan_port,
2173#endif
9a109dd0
MC		 2174#ifdef CONFIG_QEDE_GENEVE
2175 .ndo_add_geneve_port = qede_add_geneve_port,
2176 .ndo_del_geneve_port = qede_del_geneve_port,
2177#endif
2950219d
YM		 2178};
2179
e712d52b
YM		 2180/* -------------------------------------------------------------------------
2181 * START OF PROBE / REMOVE
2182 * -------------------------------------------------------------------------
2183 */
2184
2185static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2186 struct pci_dev *pdev,
2187 struct qed_dev_eth_info *info,
2188 u32 dp_module,
2189 u8 dp_level)
2190{
2191 struct net_device *ndev;
2192 struct qede_dev *edev;
2193
2194 ndev = alloc_etherdev_mqs(sizeof(*edev),
2195 info->num_queues,
2196 info->num_queues);
2197 if (!ndev) {
2198 pr_err("etherdev allocation failed\n");
2199 return NULL;
2200 }
2201
2202 edev = netdev_priv(ndev);
2203 edev->ndev = ndev;
2204 edev->cdev = cdev;
2205 edev->pdev = pdev;
2206 edev->dp_module = dp_module;
2207 edev->dp_level = dp_level;
2208 edev->ops = qed_ops;
2950219d
YM		 2209 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2210 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2211
e712d52b
YM		 2212 SET_NETDEV_DEV(ndev, &pdev->dev);
2213
133fac0e 2214 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2215 memcpy(&edev->dev_info, info, sizeof(*info));
2216
2217 edev->num_tc = edev->dev_info.num_tc;
2218
7c1bfcad
SRK		 2219 INIT_LIST_HEAD(&edev->vlan_list);
2220
e712d52b
YM		 2221 return edev;
2222}
2223
2224static void qede_init_ndev(struct qede_dev *edev)
2225{
2226 struct net_device *ndev = edev->ndev;
2227 struct pci_dev *pdev = edev->pdev;
2228 u32 hw_features;
2229
2230 pci_set_drvdata(pdev, ndev);
2231
2232 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2233 ndev->base_addr = ndev->mem_start;
2234 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2235 ndev->irq = edev->dev_info.common.pci_irq;
2236
2237 ndev->watchdog_timeo = TX_TIMEOUT;
2238
2950219d
YM		 2239 ndev->netdev_ops = &qede_netdev_ops;
2240
133fac0e
SK		 2241 qede_set_ethtool_ops(ndev);
2242
e712d52b
YM		 2243 /* user-changeble features */
2244 hw_features = NETIF_F_GRO | NETIF_F_SG |
2245 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2246 NETIF_F_TSO | NETIF_F_TSO6;
2247
14db81de
MC		 2248 /* Encap features*/
2249 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2250 NETIF_F_TSO_ECN;
2251 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2252 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2253 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2254 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2255
e712d52b
YM		 2256 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2257 NETIF_F_HIGHDMA;
2258 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2259 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2260 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2261
2262 ndev->hw_features = hw_features;
2263
2264 /* Set network device HW mac */
2265 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2266}
2267
2268/* This function converts from 32b param to two params of level and module
2269 * Input 32b decoding:
2270 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2271 * 'happy' flow, e.g. memory allocation failed.
2272 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2273 * and provide important parameters.
2274 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2275 * module. VERBOSE prints are for tracking the specific flow in low level.
2276 *
2277 * Notice that the level should be that of the lowest required logs.
2278 */
133fac0e 2279void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2280{
2281 *p_dp_level = QED_LEVEL_NOTICE;
2282 *p_dp_module = 0;
2283
2284 if (debug & QED_LOG_VERBOSE_MASK) {
2285 *p_dp_level = QED_LEVEL_VERBOSE;
2286 *p_dp_module = (debug & 0x3FFFFFFF);
2287 } else if (debug & QED_LOG_INFO_MASK) {
2288 *p_dp_level = QED_LEVEL_INFO;
2289 } else if (debug & QED_LOG_NOTICE_MASK) {
2290 *p_dp_level = QED_LEVEL_NOTICE;
2291 }
2292}
2293
2950219d
YM		 2294static void qede_free_fp_array(struct qede_dev *edev)
2295{
2296 if (edev->fp_array) {
2297 struct qede_fastpath *fp;
2298 int i;
2299
2300 for_each_rss(i) {
2301 fp = &edev->fp_array[i];
2302
2303 kfree(fp->sb_info);
2304 kfree(fp->rxq);
2305 kfree(fp->txqs);
2306 }
2307 kfree(edev->fp_array);
2308 }
2309 edev->num_rss = 0;
2310}
2311
2312static int qede_alloc_fp_array(struct qede_dev *edev)
2313{
2314 struct qede_fastpath *fp;
2315 int i;
2316
2317 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2318 sizeof(*edev->fp_array), GFP_KERNEL);
2319 if (!edev->fp_array) {
2320 DP_NOTICE(edev, "fp array allocation failed\n");
2321 goto err;
2322 }
2323
2324 for_each_rss(i) {
2325 fp = &edev->fp_array[i];
2326
2327 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2328 if (!fp->sb_info) {
2329 DP_NOTICE(edev, "sb info struct allocation failed\n");
2330 goto err;
2331 }
2332
2333 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2334 if (!fp->rxq) {
2335 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2336 goto err;
2337 }
2338
2339 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2340 if (!fp->txqs) {
2341 DP_NOTICE(edev, "TXQ array allocation failed\n");
2342 goto err;
2343 }
2344 }
2345
2346 return 0;
2347err:
2348 qede_free_fp_array(edev);
2349 return -ENOMEM;
2350}
2351
0d8e0aa0
SK		 2352static void qede_sp_task(struct work_struct *work)
2353{
2354 struct qede_dev *edev = container_of(work, struct qede_dev,
2355 sp_task.work);
b18e170c
MC		 2356 struct qed_dev *cdev = edev->cdev;
2357
0d8e0aa0
SK		 2358 mutex_lock(&edev->qede_lock);
2359
2360 if (edev->state == QEDE_STATE_OPEN) {
2361 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2362 qede_config_rx_mode(edev->ndev);
2363 }
2364
b18e170c
MC		 2365 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2366 struct qed_tunn_params tunn_params;
2367
2368 memset(&tunn_params, 0, sizeof(tunn_params));
2369 tunn_params.update_vxlan_port = 1;
2370 tunn_params.vxlan_port = edev->vxlan_dst_port;
2371 qed_ops->tunn_config(cdev, &tunn_params);
2372 }
2373
9a109dd0
MC		 2374 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2375 struct qed_tunn_params tunn_params;
2376
2377 memset(&tunn_params, 0, sizeof(tunn_params));
2378 tunn_params.update_geneve_port = 1;
2379 tunn_params.geneve_port = edev->geneve_dst_port;
2380 qed_ops->tunn_config(cdev, &tunn_params);
2381 }
2382
0d8e0aa0
SK		 2383 mutex_unlock(&edev->qede_lock);
2384}
2385
e712d52b
YM		 2386static void qede_update_pf_params(struct qed_dev *cdev)
2387{
2388 struct qed_pf_params pf_params;
2389
8e0ddc04 2390 /* 64 rx + 64 tx */
e712d52b 2391 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2392 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2393 qed_ops->common->update_pf_params(cdev, &pf_params);
2394}
2395
2396enum qede_probe_mode {
2397 QEDE_PROBE_NORMAL,
2398};
2399
2400static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2401 bool is_vf, enum qede_probe_mode mode)
e712d52b 2402{
1408cc1f 2403 struct qed_probe_params probe_params;
e712d52b
YM		 2404 struct qed_slowpath_params params;
2405 struct qed_dev_eth_info dev_info;
2406 struct qede_dev *edev;
2407 struct qed_dev *cdev;
2408 int rc;
2409
2410 if (unlikely(dp_level & QED_LEVEL_INFO))
2411 pr_notice("Starting qede probe\n");
2412
1408cc1f
YM		 2413 memset(&probe_params, 0, sizeof(probe_params));
2414 probe_params.protocol = QED_PROTOCOL_ETH;
2415 probe_params.dp_module = dp_module;
2416 probe_params.dp_level = dp_level;
2417 probe_params.is_vf = is_vf;
2418 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2419 if (!cdev) {
2420 rc = -ENODEV;
2421 goto err0;
2422 }
2423
2424 qede_update_pf_params(cdev);
2425
2426 /* Start the Slowpath-process */
2427 memset(&params, 0, sizeof(struct qed_slowpath_params));
2428 params.int_mode = QED_INT_MODE_MSIX;
2429 params.drv_major = QEDE_MAJOR_VERSION;
2430 params.drv_minor = QEDE_MINOR_VERSION;
2431 params.drv_rev = QEDE_REVISION_VERSION;
2432 params.drv_eng = QEDE_ENGINEERING_VERSION;
2433 strlcpy(params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2434 rc = qed_ops->common->slowpath_start(cdev, &params);
2435 if (rc) {
2436 pr_notice("Cannot start slowpath\n");
2437 goto err1;
2438 }
2439
2440 /* Learn information crucial for qede to progress */
2441 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2442 if (rc)
2443 goto err2;
2444
2445 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2446 dp_level);
2447 if (!edev) {
2448 rc = -ENOMEM;
2449 goto err2;
2450 }
2451
fefb0202
YM		 2452 if (is_vf)
2453 edev->flags |= QEDE_FLAG_IS_VF;
2454
e712d52b
YM		 2455 qede_init_ndev(edev);
2456
2950219d
YM		 2457 rc = register_netdev(edev->ndev);
2458 if (rc) {
2459 DP_NOTICE(edev, "Cannot register net-device\n");
2460 goto err3;
2461 }
2462
e712d52b
YM		 2463 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2464
a2ec6172
SK		 2465 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2466
0d8e0aa0
SK		 2467 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2468 mutex_init(&edev->qede_lock);
2469
e712d52b
YM		 2470 DP_INFO(edev, "Ending successfully qede probe\n");
2471
2472 return 0;
2473
2950219d
YM		 2474err3:
2475 free_netdev(edev->ndev);
e712d52b
YM		 2476err2:
2477 qed_ops->common->slowpath_stop(cdev);
2478err1:
2479 qed_ops->common->remove(cdev);
2480err0:
2481 return rc;
2482}
2483
2484static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2485{
fefb0202 2486 bool is_vf = false;
e712d52b
YM		 2487 u32 dp_module = 0;
2488 u8 dp_level = 0;
2489
fefb0202
YM		 2490 switch ((enum qede_pci_private)id->driver_data) {
2491 case QEDE_PRIVATE_VF:
2492 if (debug & QED_LOG_VERBOSE_MASK)
2493 dev_err(&pdev->dev, "Probing a VF\n");
2494 is_vf = true;
2495 break;
2496 default:
2497 if (debug & QED_LOG_VERBOSE_MASK)
2498 dev_err(&pdev->dev, "Probing a PF\n");
2499 }
2500
e712d52b
YM		 2501 qede_config_debug(debug, &dp_module, &dp_level);
2502
fefb0202 2503 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2504 QEDE_PROBE_NORMAL);
2505}
2506
2507enum qede_remove_mode {
2508 QEDE_REMOVE_NORMAL,
2509};
2510
2511static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2512{
2513 struct net_device *ndev = pci_get_drvdata(pdev);
2514 struct qede_dev *edev = netdev_priv(ndev);
2515 struct qed_dev *cdev = edev->cdev;
2516
2517 DP_INFO(edev, "Starting qede_remove\n");
2518
0d8e0aa0 2519 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2520 unregister_netdev(ndev);
2521
e712d52b
YM		 2522 edev->ops->common->set_power_state(cdev, PCI_D0);
2523
2524 pci_set_drvdata(pdev, NULL);
2525
2526 free_netdev(ndev);
2527
2528 /* Use global ops since we've freed edev */
2529 qed_ops->common->slowpath_stop(cdev);
2530 qed_ops->common->remove(cdev);
2531
2532 pr_notice("Ending successfully qede_remove\n");
2533}
2534
2535static void qede_remove(struct pci_dev *pdev)
2536{
2537 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2538}
2950219d
YM		 2539
2540/* -------------------------------------------------------------------------
2541 * START OF LOAD / UNLOAD
2542 * -------------------------------------------------------------------------
2543 */
2544
2545static int qede_set_num_queues(struct qede_dev *edev)
2546{
2547 int rc;
2548 u16 rss_num;
2549
2550 /* Setup queues according to possible resources*/
8edf049d
SK		 2551 if (edev->req_rss)
2552 rss_num = edev->req_rss;
2553 else
2554 rss_num = netif_get_num_default_rss_queues() *
2555 edev->dev_info.common.num_hwfns;
2950219d
YM		 2556
2557 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2558
2559 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2560 if (rc > 0) {
2561 /* Managed to request interrupts for our queues */
2562 edev->num_rss = rc;
2563 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2564 QEDE_RSS_CNT(edev), rss_num);
2565 rc = 0;
2566 }
2567 return rc;
2568}
2569
2570static void qede_free_mem_sb(struct qede_dev *edev,
2571 struct qed_sb_info *sb_info)
2572{
2573 if (sb_info->sb_virt)
2574 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2575 (void *)sb_info->sb_virt, sb_info->sb_phys);
2576}
2577
2578/* This function allocates fast-path status block memory */
2579static int qede_alloc_mem_sb(struct qede_dev *edev,
2580 struct qed_sb_info *sb_info,
2581 u16 sb_id)
2582{
2583 struct status_block *sb_virt;
2584 dma_addr_t sb_phys;
2585 int rc;
2586
2587 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
2588 sizeof(*sb_virt),
2589 &sb_phys, GFP_KERNEL);
2590 if (!sb_virt) {
2591 DP_ERR(edev, "Status block allocation failed\n");
2592 return -ENOMEM;
2593 }
2594
2595 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2596 sb_virt, sb_phys, sb_id,
2597 QED_SB_TYPE_L2_QUEUE);
2598 if (rc) {
2599 DP_ERR(edev, "Status block initialization failed\n");
2600 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2601 sb_virt, sb_phys);
2602 return rc;
2603 }
2604
2605 return 0;
2606}
2607
2608static void qede_free_rx_buffers(struct qede_dev *edev,
2609 struct qede_rx_queue *rxq)
2610{
2611 u16 i;
2612
2613 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2614 struct sw_rx_data *rx_buf;
fc48b7a6 2615 struct page *data;
2950219d
YM		 2616
2617 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2618 data = rx_buf->data;
2619
fc48b7a6
YM		 2620 dma_unmap_page(&edev->pdev->dev,
2621 rx_buf->mapping,
2622 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2623
2624 rx_buf->data = NULL;
fc48b7a6 2625 __free_page(data);
2950219d
YM		 2626 }
2627}
2628
55482edc
MC		 2629static void qede_free_sge_mem(struct qede_dev *edev,
2630 struct qede_rx_queue *rxq) {
2631 int i;
2632
2633 if (edev->gro_disable)
2634 return;
2635
2636 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2637 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2638 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2639
f86af2df 2640 if (replace_buf->data) {
55482edc
MC		 2641 dma_unmap_page(&edev->pdev->dev,
2642 dma_unmap_addr(replace_buf, mapping),
2643 PAGE_SIZE, DMA_FROM_DEVICE);
2644 __free_page(replace_buf->data);
2645 }
2646 }
2647}
2648
2950219d
YM		 2649static void qede_free_mem_rxq(struct qede_dev *edev,
2650 struct qede_rx_queue *rxq)
2651{
55482edc
MC		 2652 qede_free_sge_mem(edev, rxq);
2653
2950219d
YM		 2654 /* Free rx buffers */
2655 qede_free_rx_buffers(edev, rxq);
2656
2657 /* Free the parallel SW ring */
2658 kfree(rxq->sw_rx_ring);
2659
2660 /* Free the real RQ ring used by FW */
2661 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2662 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2663}
2664
2665static int qede_alloc_rx_buffer(struct qede_dev *edev,
2666 struct qede_rx_queue *rxq)
2667{
2668 struct sw_rx_data *sw_rx_data;
2669 struct eth_rx_bd *rx_bd;
2670 dma_addr_t mapping;
fc48b7a6 2671 struct page *data;
2950219d 2672 u16 rx_buf_size;
2950219d
YM		 2673
2674 rx_buf_size = rxq->rx_buf_size;
2675
fc48b7a6 2676 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2677 if (unlikely(!data)) {
fc48b7a6 2678 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2679 return -ENOMEM;
2680 }
2681
fc48b7a6
YM		 2682 /* Map the entire page as it would be used
2683 * for multiple RX buffer segment size mapping.
2684 */
2685 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2686 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2687 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2688 __free_page(data);
2950219d
YM		 2689 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2690 return -ENOMEM;
2691 }
2692
2693 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2694 sw_rx_data->page_offset = 0;
2950219d 2695 sw_rx_data->data = data;
fc48b7a6 2696 sw_rx_data->mapping = mapping;
2950219d
YM		 2697
2698 /* Advance PROD and get BD pointer */
2699 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2700 WARN_ON(!rx_bd);
2701 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2702 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2703
2704 rxq->sw_rx_prod++;
2705
2706 return 0;
2707}
2708
55482edc
MC		 2709static int qede_alloc_sge_mem(struct qede_dev *edev,
2710 struct qede_rx_queue *rxq)
2711{
2712 dma_addr_t mapping;
2713 int i;
2714
2715 if (edev->gro_disable)
2716 return 0;
2717
2718 if (edev->ndev->mtu > PAGE_SIZE) {
2719 edev->gro_disable = 1;
2720 return 0;
2721 }
2722
2723 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2724 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2725 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2726
2727 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2728 if (unlikely(!replace_buf->data)) {
2729 DP_NOTICE(edev,
2730 "Failed to allocate TPA skb pool [replacement buffer]\n");
2731 goto err;
2732 }
2733
2734 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2735 rxq->rx_buf_size, DMA_FROM_DEVICE);
2736 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2737 DP_NOTICE(edev,
2738 "Failed to map TPA replacement buffer\n");
2739 goto err;
2740 }
2741
2742 dma_unmap_addr_set(replace_buf, mapping, mapping);
2743 tpa_info->replace_buf.page_offset = 0;
2744
2745 tpa_info->replace_buf_mapping = mapping;
2746 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2747 }
2748
2749 return 0;
2750err:
2751 qede_free_sge_mem(edev, rxq);
2752 edev->gro_disable = 1;
2753 return -ENOMEM;
2754}
2755
2950219d
YM		 2756/* This function allocates all memory needed per Rx queue */
2757static int qede_alloc_mem_rxq(struct qede_dev *edev,
2758 struct qede_rx_queue *rxq)
2759{
f86af2df 2760 int i, rc, size;
2950219d
YM		 2761
2762 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2763
fc48b7a6
YM		 2764 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD +
2765 edev->ndev->mtu;
2766 if (rxq->rx_buf_size > PAGE_SIZE)
2767 rxq->rx_buf_size = PAGE_SIZE;
2768
2769 /* Segment size to spilt a page in multiple equal parts */
2770 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2771
2772 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2773 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2774 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2775 if (!rxq->sw_rx_ring) {
2776 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2777 rc = -ENOMEM;
2950219d
YM		 2778 goto err;
2779 }
2780
2781 /* Allocate FW Rx ring */
2782 rc = edev->ops->common->chain_alloc(edev->cdev,
2783 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2784 QED_CHAIN_MODE_NEXT_PTR,
fc48b7a6 2785 RX_RING_SIZE,
2950219d
YM		 2786 sizeof(struct eth_rx_bd),
2787 &rxq->rx_bd_ring);
2788
2789 if (rc)
2790 goto err;
2791
2792 /* Allocate FW completion ring */
2793 rc = edev->ops->common->chain_alloc(edev->cdev,
2794 QED_CHAIN_USE_TO_CONSUME,
2795 QED_CHAIN_MODE_PBL,
fc48b7a6 2796 RX_RING_SIZE,
2950219d
YM		 2797 sizeof(union eth_rx_cqe),
2798 &rxq->rx_comp_ring);
2799 if (rc)
2800 goto err;
2801
2802 /* Allocate buffers for the Rx ring */
2803 for (i = 0; i < rxq->num_rx_buffers; i++) {
2804 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2805 if (rc) {
2806 DP_ERR(edev,
2807 "Rx buffers allocation failed at index %d\n", i);
2808 goto err;
2809 }
2950219d
YM		 2810 }
2811
f86af2df 2812 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2813err:
f86af2df 2814 return rc;
2950219d
YM		 2815}
2816
2817static void qede_free_mem_txq(struct qede_dev *edev,
2818 struct qede_tx_queue *txq)
2819{
2820 /* Free the parallel SW ring */
2821 kfree(txq->sw_tx_ring);
2822
2823 /* Free the real RQ ring used by FW */
2824 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2825}
2826
2827/* This function allocates all memory needed per Tx queue */
2828static int qede_alloc_mem_txq(struct qede_dev *edev,
2829 struct qede_tx_queue *txq)
2830{
2831 int size, rc;
2832 union eth_tx_bd_types *p_virt;
2833
2834 txq->num_tx_buffers = edev->q_num_tx_buffers;
2835
2836 /* Allocate the parallel driver ring for Tx buffers */
2837 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2838 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2839 if (!txq->sw_tx_ring) {
2840 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2841 goto err;
2842 }
2843
2844 rc = edev->ops->common->chain_alloc(edev->cdev,
2845 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2846 QED_CHAIN_MODE_PBL,
2847 NUM_TX_BDS_MAX,
2848 sizeof(*p_virt),
2849 &txq->tx_pbl);
2850 if (rc)
2851 goto err;
2852
2853 return 0;
2854
2855err:
2856 qede_free_mem_txq(edev, txq);
2857 return -ENOMEM;
2858}
2859
2860/* This function frees all memory of a single fp */
2861static void qede_free_mem_fp(struct qede_dev *edev,
2862 struct qede_fastpath *fp)
2863{
2864 int tc;
2865
2866 qede_free_mem_sb(edev, fp->sb_info);
2867
2868 qede_free_mem_rxq(edev, fp->rxq);
2869
2870 for (tc = 0; tc < edev->num_tc; tc++)
2871 qede_free_mem_txq(edev, &fp->txqs[tc]);
2872}
2873
2874/* This function allocates all memory needed for a single fp (i.e. an entity
2875 * which contains status block, one rx queue and multiple per-TC tx queues.
2876 */
2877static int qede_alloc_mem_fp(struct qede_dev *edev,
2878 struct qede_fastpath *fp)
2879{
2880 int rc, tc;
2881
2882 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2883 if (rc)
2884 goto err;
2885
2886 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2887 if (rc)
2888 goto err;
2889
2890 for (tc = 0; tc < edev->num_tc; tc++) {
2891 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2892 if (rc)
2893 goto err;
2894 }
2895
2896 return 0;
2950219d 2897err:
f86af2df 2898 return rc;
2950219d
YM		 2899}
2900
2901static void qede_free_mem_load(struct qede_dev *edev)
2902{
2903 int i;
2904
2905 for_each_rss(i) {
2906 struct qede_fastpath *fp = &edev->fp_array[i];
2907
2908 qede_free_mem_fp(edev, fp);
2909 }
2910}
2911
2912/* This function allocates all qede memory at NIC load. */
2913static int qede_alloc_mem_load(struct qede_dev *edev)
2914{
2915 int rc = 0, rss_id;
2916
2917 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2918 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2919
2920 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2921 if (rc) {
2950219d 2922 DP_ERR(edev,
f86af2df
MC		 2923 "Failed to allocate memory for fastpath - rss id = %d\n",
2924 rss_id);
2925 qede_free_mem_load(edev);
2926 return rc;
2950219d 2927 }
2950219d
YM		 2928 }
2929
2930 return 0;
2931}
2932
2933/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2934static void qede_init_fp(struct qede_dev *edev)
2935{
2936 int rss_id, txq_index, tc;
2937 struct qede_fastpath *fp;
2938
2939 for_each_rss(rss_id) {
2940 fp = &edev->fp_array[rss_id];
2941
2942 fp->edev = edev;
2943 fp->rss_id = rss_id;
2944
2945 memset((void *)&fp->napi, 0, sizeof(fp->napi));
2946
2947 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
2948
2949 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
2950 fp->rxq->rxq_id = rss_id;
2951
2952 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
2953 for (tc = 0; tc < edev->num_tc; tc++) {
2954 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
2955 fp->txqs[tc].index = txq_index;
2956 }
2957
2958 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
2959 edev->ndev->name, rss_id);
2960 }
55482edc
MC		 2961
2962 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 2963}
2964
2965static int qede_set_real_num_queues(struct qede_dev *edev)
2966{
2967 int rc = 0;
2968
2969 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
2970 if (rc) {
2971 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
2972 return rc;
2973 }
2974 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
2975 if (rc) {
2976 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
2977 return rc;
2978 }
2979
2980 return 0;
2981}
2982
2983static void qede_napi_disable_remove(struct qede_dev *edev)
2984{
2985 int i;
2986
2987 for_each_rss(i) {
2988 napi_disable(&edev->fp_array[i].napi);
2989
2990 netif_napi_del(&edev->fp_array[i].napi);
2991 }
2992}
2993
2994static void qede_napi_add_enable(struct qede_dev *edev)
2995{
2996 int i;
2997
2998 /* Add NAPI objects */
2999 for_each_rss(i) {
3000 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
3001 qede_poll, NAPI_POLL_WEIGHT);
3002 napi_enable(&edev->fp_array[i].napi);
3003 }
3004}
3005
3006static void qede_sync_free_irqs(struct qede_dev *edev)
3007{
3008 int i;
3009
3010 for (i = 0; i < edev->int_info.used_cnt; i++) {
3011 if (edev->int_info.msix_cnt) {
3012 synchronize_irq(edev->int_info.msix[i].vector);
3013 free_irq(edev->int_info.msix[i].vector,
3014 &edev->fp_array[i]);
3015 } else {
3016 edev->ops->common->simd_handler_clean(edev->cdev, i);
3017 }
3018 }
3019
3020 edev->int_info.used_cnt = 0;
3021}
3022
3023static int qede_req_msix_irqs(struct qede_dev *edev)
3024{
3025 int i, rc;
3026
3027 /* Sanitize number of interrupts == number of prepared RSS queues */
3028 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
3029 DP_ERR(edev,
3030 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
3031 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
3032 return -EINVAL;
3033 }
3034
3035 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
3036 rc = request_irq(edev->int_info.msix[i].vector,
3037 qede_msix_fp_int, 0, edev->fp_array[i].name,
3038 &edev->fp_array[i]);
3039 if (rc) {
3040 DP_ERR(edev, "Request fp %d irq failed\n", i);
3041 qede_sync_free_irqs(edev);
3042 return rc;
3043 }
3044 DP_VERBOSE(edev, NETIF_MSG_INTR,
3045 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
3046 edev->fp_array[i].name, i,
3047 &edev->fp_array[i]);
3048 edev->int_info.used_cnt++;
3049 }
3050
3051 return 0;
3052}
3053
3054static void qede_simd_fp_handler(void *cookie)
3055{
3056 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
3057
3058 napi_schedule_irqoff(&fp->napi);
3059}
3060
3061static int qede_setup_irqs(struct qede_dev *edev)
3062{
3063 int i, rc = 0;
3064
3065 /* Learn Interrupt configuration */
3066 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
3067 if (rc)
3068 return rc;
3069
3070 if (edev->int_info.msix_cnt) {
3071 rc = qede_req_msix_irqs(edev);
3072 if (rc)
3073 return rc;
3074 edev->ndev->irq = edev->int_info.msix[0].vector;
3075 } else {
3076 const struct qed_common_ops *ops;
3077
3078 /* qed should learn receive the RSS ids and callbacks */
3079 ops = edev->ops->common;
3080 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
3081 ops->simd_handler_config(edev->cdev,
3082 &edev->fp_array[i], i,
3083 qede_simd_fp_handler);
3084 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
3085 }
3086 return 0;
3087}
3088
3089static int qede_drain_txq(struct qede_dev *edev,
3090 struct qede_tx_queue *txq,
3091 bool allow_drain)
3092{
3093 int rc, cnt = 1000;
3094
3095 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3096 if (!cnt) {
3097 if (allow_drain) {
3098 DP_NOTICE(edev,
3099 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3100 txq->index);
3101 rc = edev->ops->common->drain(edev->cdev);
3102 if (rc)
3103 return rc;
3104 return qede_drain_txq(edev, txq, false);
3105 }
3106 DP_NOTICE(edev,
3107 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3108 txq->index, txq->sw_tx_prod,
3109 txq->sw_tx_cons);
3110 return -ENODEV;
3111 }
3112 cnt--;
3113 usleep_range(1000, 2000);
3114 barrier();
3115 }
3116
3117 /* FW finished processing, wait for HW to transmit all tx packets */
3118 usleep_range(1000, 2000);
3119
3120 return 0;
3121}
3122
3123static int qede_stop_queues(struct qede_dev *edev)
3124{
3125 struct qed_update_vport_params vport_update_params;
3126 struct qed_dev *cdev = edev->cdev;
3127 int rc, tc, i;
3128
3129 /* Disable the vport */
3130 memset(&vport_update_params, 0, sizeof(vport_update_params));
3131 vport_update_params.vport_id = 0;
3132 vport_update_params.update_vport_active_flg = 1;
3133 vport_update_params.vport_active_flg = 0;
3134 vport_update_params.update_rss_flg = 0;
3135
3136 rc = edev->ops->vport_update(cdev, &vport_update_params);
3137 if (rc) {
3138 DP_ERR(edev, "Failed to update vport\n");
3139 return rc;
3140 }
3141
3142 /* Flush Tx queues. If needed, request drain from MCP */
3143 for_each_rss(i) {
3144 struct qede_fastpath *fp = &edev->fp_array[i];
3145
3146 for (tc = 0; tc < edev->num_tc; tc++) {
3147 struct qede_tx_queue *txq = &fp->txqs[tc];
3148
3149 rc = qede_drain_txq(edev, txq, true);
3150 if (rc)
3151 return rc;
3152 }
3153 }
3154
3155 /* Stop all Queues in reverse order*/
3156 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3157 struct qed_stop_rxq_params rx_params;
3158
3159 /* Stop the Tx Queue(s)*/
3160 for (tc = 0; tc < edev->num_tc; tc++) {
3161 struct qed_stop_txq_params tx_params;
3162
3163 tx_params.rss_id = i;
3164 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3165 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3166 if (rc) {
3167 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3168 tx_params.tx_queue_id);
3169 return rc;
3170 }
3171 }
3172
3173 /* Stop the Rx Queue*/
3174 memset(&rx_params, 0, sizeof(rx_params));
3175 rx_params.rss_id = i;
3176 rx_params.rx_queue_id = i;
3177
3178 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3179 if (rc) {
3180 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3181 return rc;
3182 }
3183 }
3184
3185 /* Stop the vport */
3186 rc = edev->ops->vport_stop(cdev, 0);
3187 if (rc)
3188 DP_ERR(edev, "Failed to stop VPORT\n");
3189
3190 return rc;
3191}
3192
3193static int qede_start_queues(struct qede_dev *edev)
3194{
3195 int rc, tc, i;
088c8618 3196 int vlan_removal_en = 1;
2950219d 3197 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3198 struct qed_update_vport_params vport_update_params;
3199 struct qed_queue_start_common_params q_params;
fefb0202 3200 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3201 struct qed_start_vport_params start = {0};
961acdea 3202 bool reset_rss_indir = false;
2950219d
YM		 3203
3204 if (!edev->num_rss) {
3205 DP_ERR(edev,
3206 "Cannot update V-VPORT as active as there are no Rx queues\n");
3207 return -EINVAL;
3208 }
3209
55482edc 3210 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3211 start.mtu = edev->ndev->mtu;
3212 start.vport_id = 0;
3213 start.drop_ttl0 = true;
3214 start.remove_inner_vlan = vlan_removal_en;
3215
3216 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3217
3218 if (rc) {
3219 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3220 return rc;
3221 }
3222
3223 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3224 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3225 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3226
3227 for_each_rss(i) {
3228 struct qede_fastpath *fp = &edev->fp_array[i];
3229 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3230
3231 memset(&q_params, 0, sizeof(q_params));
3232 q_params.rss_id = i;
3233 q_params.queue_id = i;
3234 q_params.vport_id = 0;
3235 q_params.sb = fp->sb_info->igu_sb_id;
3236 q_params.sb_idx = RX_PI;
3237
3238 rc = edev->ops->q_rx_start(cdev, &q_params,
3239 fp->rxq->rx_buf_size,
3240 fp->rxq->rx_bd_ring.p_phys_addr,
3241 phys_table,
3242 fp->rxq->rx_comp_ring.page_cnt,
3243 &fp->rxq->hw_rxq_prod_addr);
3244 if (rc) {
3245 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3246 return rc;
3247 }
3248
3249 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3250
3251 qede_update_rx_prod(edev, fp->rxq);
3252
3253 for (tc = 0; tc < edev->num_tc; tc++) {
3254 struct qede_tx_queue *txq = &fp->txqs[tc];
3255 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3256
3257 memset(&q_params, 0, sizeof(q_params));
3258 q_params.rss_id = i;
3259 q_params.queue_id = txq_index;
3260 q_params.vport_id = 0;
3261 q_params.sb = fp->sb_info->igu_sb_id;
3262 q_params.sb_idx = TX_PI(tc);
3263
3264 rc = edev->ops->q_tx_start(cdev, &q_params,
3265 txq->tx_pbl.pbl.p_phys_table,
3266 txq->tx_pbl.page_cnt,
3267 &txq->doorbell_addr);
3268 if (rc) {
3269 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3270 txq_index, rc);
3271 return rc;
3272 }
3273
3274 txq->hw_cons_ptr =
3275 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3276 SET_FIELD(txq->tx_db.data.params,
3277 ETH_DB_DATA_DEST, DB_DEST_XCM);
3278 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3279 DB_AGG_CMD_SET);
3280 SET_FIELD(txq->tx_db.data.params,
3281 ETH_DB_DATA_AGG_VAL_SEL,
3282 DQ_XCM_ETH_TX_BD_PROD_CMD);
3283
3284 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3285 }
3286 }
3287
3288 /* Prepare and send the vport enable */
3289 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3290 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3291 vport_update_params.update_vport_active_flg = 1;
3292 vport_update_params.vport_active_flg = 1;
3293
3294 /* Fill struct with RSS params */
3295 if (QEDE_RSS_CNT(edev) > 1) {
3296 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3297
3298 /* Need to validate current RSS config uses valid entries */
3299 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3300 if (edev->rss_params.rss_ind_table[i] >=
3301 edev->num_rss) {
3302 reset_rss_indir = true;
3303 break;
3304 }
3305 }
3306
3307 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3308 reset_rss_indir) {
3309 u16 val;
3310
3311 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3312 u16 indir_val;
3313
3314 val = QEDE_RSS_CNT(edev);
3315 indir_val = ethtool_rxfh_indir_default(i, val);
3316 edev->rss_params.rss_ind_table[i] = indir_val;
3317 }
3318 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3319 }
3320
3321 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3322 netdev_rss_key_fill(edev->rss_params.rss_key,
3323 sizeof(edev->rss_params.rss_key));
3324 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3325 }
3326
3327 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3328 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3329 QED_RSS_IPV6 |
3330 QED_RSS_IPV4_TCP |
3331 QED_RSS_IPV6_TCP;
3332 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3333 }
3334
3335 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3336 sizeof(vport_update_params.rss_params));
2950219d 3337 } else {
961acdea
SRK		 3338 memset(&vport_update_params.rss_params, 0,
3339 sizeof(vport_update_params.rss_params));
2950219d 3340 }
2950219d
YM		 3341
3342 rc = edev->ops->vport_update(cdev, &vport_update_params);
3343 if (rc) {
3344 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3345 return rc;
3346 }
3347
3348 return 0;
3349}
3350
0d8e0aa0
SK		 3351static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3352 enum qed_filter_xcast_params_type opcode,
3353 unsigned char *mac, int num_macs)
3354{
3355 struct qed_filter_params filter_cmd;
3356 int i;
3357
3358 memset(&filter_cmd, 0, sizeof(filter_cmd));
3359 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3360 filter_cmd.filter.mcast.type = opcode;
3361 filter_cmd.filter.mcast.num = num_macs;
3362
3363 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3364 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3365
3366 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3367}
3368
2950219d
YM		 3369enum qede_unload_mode {
3370 QEDE_UNLOAD_NORMAL,
3371};
3372
3373static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3374{
a2ec6172 3375 struct qed_link_params link_params;
2950219d
YM		 3376 int rc;
3377
3378 DP_INFO(edev, "Starting qede unload\n");
3379
0d8e0aa0
SK		 3380 mutex_lock(&edev->qede_lock);
3381 edev->state = QEDE_STATE_CLOSED;
3382
2950219d
YM		 3383 /* Close OS Tx */
3384 netif_tx_disable(edev->ndev);
3385 netif_carrier_off(edev->ndev);
3386
a2ec6172
SK		 3387 /* Reset the link */
3388 memset(&link_params, 0, sizeof(link_params));
3389 link_params.link_up = false;
3390 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3391 rc = qede_stop_queues(edev);
3392 if (rc) {
3393 qede_sync_free_irqs(edev);
3394 goto out;
3395 }
3396
3397 DP_INFO(edev, "Stopped Queues\n");
3398
7c1bfcad 3399 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3400 edev->ops->fastpath_stop(edev->cdev);
3401
3402 /* Release the interrupts */
3403 qede_sync_free_irqs(edev);
3404 edev->ops->common->set_fp_int(edev->cdev, 0);
3405
3406 qede_napi_disable_remove(edev);
3407
3408 qede_free_mem_load(edev);
3409 qede_free_fp_array(edev);
3410
3411out:
3412 mutex_unlock(&edev->qede_lock);
3413 DP_INFO(edev, "Ending qede unload\n");
3414}
3415
3416enum qede_load_mode {
3417 QEDE_LOAD_NORMAL,
3418};
3419
3420static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3421{
a2ec6172
SK		 3422 struct qed_link_params link_params;
3423 struct qed_link_output link_output;
2950219d
YM		 3424 int rc;
3425
3426 DP_INFO(edev, "Starting qede load\n");
3427
3428 rc = qede_set_num_queues(edev);
3429 if (rc)
3430 goto err0;
3431
3432 rc = qede_alloc_fp_array(edev);
3433 if (rc)
3434 goto err0;
3435
3436 qede_init_fp(edev);
3437
3438 rc = qede_alloc_mem_load(edev);
3439 if (rc)
3440 goto err1;
3441 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3442 QEDE_RSS_CNT(edev), edev->num_tc);
3443
3444 rc = qede_set_real_num_queues(edev);
3445 if (rc)
3446 goto err2;
3447
3448 qede_napi_add_enable(edev);
3449 DP_INFO(edev, "Napi added and enabled\n");
3450
3451 rc = qede_setup_irqs(edev);
3452 if (rc)
3453 goto err3;
3454 DP_INFO(edev, "Setup IRQs succeeded\n");
3455
3456 rc = qede_start_queues(edev);
3457 if (rc)
3458 goto err4;
3459 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3460
3461 /* Add primary mac and set Rx filters */
3462 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3463
0d8e0aa0
SK		 3464 mutex_lock(&edev->qede_lock);
3465 edev->state = QEDE_STATE_OPEN;
3466 mutex_unlock(&edev->qede_lock);
a2ec6172 3467
7c1bfcad
SRK		 3468 /* Program un-configured VLANs */
3469 qede_configure_vlan_filters(edev);
3470
a2ec6172
SK		 3471 /* Ask for link-up using current configuration */
3472 memset(&link_params, 0, sizeof(link_params));
3473 link_params.link_up = true;
3474 edev->ops->common->set_link(edev->cdev, &link_params);
3475
3476 /* Query whether link is already-up */
3477 memset(&link_output, 0, sizeof(link_output));
3478 edev->ops->common->get_link(edev->cdev, &link_output);
3479 qede_link_update(edev, &link_output);
3480
2950219d
YM		 3481 DP_INFO(edev, "Ending successfully qede load\n");
3482
3483 return 0;
3484
3485err4:
3486 qede_sync_free_irqs(edev);
3487 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3488err3:
3489 qede_napi_disable_remove(edev);
3490err2:
3491 qede_free_mem_load(edev);
3492err1:
3493 edev->ops->common->set_fp_int(edev->cdev, 0);
3494 qede_free_fp_array(edev);
3495 edev->num_rss = 0;
3496err0:
3497 return rc;
3498}
3499
133fac0e
SK		 3500void qede_reload(struct qede_dev *edev,
3501 void (*func)(struct qede_dev *, union qede_reload_args *),
3502 union qede_reload_args *args)
3503{
3504 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3505 /* Call function handler to update parameters
3506 * needed for function load.
3507 */
3508 if (func)
3509 func(edev, args);
3510
3511 qede_load(edev, QEDE_LOAD_NORMAL);
3512
3513 mutex_lock(&edev->qede_lock);
3514 qede_config_rx_mode(edev->ndev);
3515 mutex_unlock(&edev->qede_lock);
3516}
3517
2950219d
YM		 3518/* called with rtnl_lock */
3519static int qede_open(struct net_device *ndev)
3520{
3521 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3522 int rc;
2950219d
YM		 3523
3524 netif_carrier_off(ndev);
3525
3526 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3527
b18e170c
MC		 3528 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3529
3530 if (rc)
3531 return rc;
3532
3533#ifdef CONFIG_QEDE_VXLAN
3534 vxlan_get_rx_port(ndev);
9a109dd0
MC		 3535#endif
3536#ifdef CONFIG_QEDE_GENEVE
3537 geneve_get_rx_port(ndev);
b18e170c
MC		 3538#endif
3539 return 0;
2950219d
YM		 3540}
3541
3542static int qede_close(struct net_device *ndev)
3543{
3544 struct qede_dev *edev = netdev_priv(ndev);
3545
3546 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3547
3548 return 0;
3549}
0d8e0aa0 3550
a2ec6172
SK		 3551static void qede_link_update(void *dev, struct qed_link_output *link)
3552{
3553 struct qede_dev *edev = dev;
3554
3555 if (!netif_running(edev->ndev)) {
3556 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3557 return;
3558 }
3559
3560 if (link->link_up) {
8e025ae2
YM		 3561 if (!netif_carrier_ok(edev->ndev)) {
3562 DP_NOTICE(edev, "Link is up\n");
3563 netif_tx_start_all_queues(edev->ndev);
3564 netif_carrier_on(edev->ndev);
3565 }
a2ec6172 3566 } else {
8e025ae2
YM		 3567 if (netif_carrier_ok(edev->ndev)) {
3568 DP_NOTICE(edev, "Link is down\n");
3569 netif_tx_disable(edev->ndev);
3570 netif_carrier_off(edev->ndev);
3571 }
a2ec6172
SK		 3572 }
3573}
3574
0d8e0aa0
SK		 3575static int qede_set_mac_addr(struct net_device *ndev, void *p)
3576{
3577 struct qede_dev *edev = netdev_priv(ndev);
3578 struct sockaddr *addr = p;
3579 int rc;
3580
3581 ASSERT_RTNL(); /* @@@TBD To be removed */
3582
3583 DP_INFO(edev, "Set_mac_addr called\n");
3584
3585 if (!is_valid_ether_addr(addr->sa_data)) {
3586 DP_NOTICE(edev, "The MAC address is not valid\n");
3587 return -EFAULT;
3588 }
3589
eff16960
YM		 3590 if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
3591 DP_NOTICE(edev, "qed prevents setting MAC\n");
3592 return -EINVAL;
3593 }
3594
0d8e0aa0
SK		 3595 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3596
3597 if (!netif_running(ndev)) {
3598 DP_NOTICE(edev, "The device is currently down\n");
3599 return 0;
3600 }
3601
3602 /* Remove the previous primary mac */
3603 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3604 edev->primary_mac);
3605 if (rc)
3606 return rc;
3607
3608 /* Add MAC filter according to the new unicast HW MAC address */
3609 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3610 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3611 edev->primary_mac);
3612}
3613
3614static int
3615qede_configure_mcast_filtering(struct net_device *ndev,
3616 enum qed_filter_rx_mode_type *accept_flags)
3617{
3618 struct qede_dev *edev = netdev_priv(ndev);
3619 unsigned char *mc_macs, *temp;
3620 struct netdev_hw_addr *ha;
3621 int rc = 0, mc_count;
3622 size_t size;
3623
3624 size = 64 * ETH_ALEN;
3625
3626 mc_macs = kzalloc(size, GFP_KERNEL);
3627 if (!mc_macs) {
3628 DP_NOTICE(edev,
3629 "Failed to allocate memory for multicast MACs\n");
3630 rc = -ENOMEM;
3631 goto exit;
3632 }
3633
3634 temp = mc_macs;
3635
3636 /* Remove all previously configured MAC filters */
3637 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3638 mc_macs, 1);
3639 if (rc)
3640 goto exit;
3641
3642 netif_addr_lock_bh(ndev);
3643
3644 mc_count = netdev_mc_count(ndev);
3645 if (mc_count < 64) {
3646 netdev_for_each_mc_addr(ha, ndev) {
3647 ether_addr_copy(temp, ha->addr);
3648 temp += ETH_ALEN;
3649 }
3650 }
3651
3652 netif_addr_unlock_bh(ndev);
3653
3654 /* Check for all multicast @@@TBD resource allocation */
3655 if ((ndev->flags & IFF_ALLMULTI) ||
3656 (mc_count > 64)) {
3657 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3658 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3659 } else {
3660 /* Add all multicast MAC filters */
3661 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3662 mc_macs, mc_count);
3663 }
3664
3665exit:
3666 kfree(mc_macs);
3667 return rc;
3668}
3669
3670static void qede_set_rx_mode(struct net_device *ndev)
3671{
3672 struct qede_dev *edev = netdev_priv(ndev);
3673
3674 DP_INFO(edev, "qede_set_rx_mode called\n");
3675
3676 if (edev->state != QEDE_STATE_OPEN) {
3677 DP_INFO(edev,
3678 "qede_set_rx_mode called while interface is down\n");
3679 } else {
3680 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3681 schedule_delayed_work(&edev->sp_task, 0);
3682 }
3683}
3684
3685/* Must be called with qede_lock held */
3686static void qede_config_rx_mode(struct net_device *ndev)
3687{
3688 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3689 struct qede_dev *edev = netdev_priv(ndev);
3690 struct qed_filter_params rx_mode;
3691 unsigned char *uc_macs, *temp;
3692 struct netdev_hw_addr *ha;
3693 int rc, uc_count;
3694 size_t size;
3695
3696 netif_addr_lock_bh(ndev);
3697
3698 uc_count = netdev_uc_count(ndev);
3699 size = uc_count * ETH_ALEN;
3700
3701 uc_macs = kzalloc(size, GFP_ATOMIC);
3702 if (!uc_macs) {
3703 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3704 netif_addr_unlock_bh(ndev);
3705 return;
3706 }
3707
3708 temp = uc_macs;
3709 netdev_for_each_uc_addr(ha, ndev) {
3710 ether_addr_copy(temp, ha->addr);
3711 temp += ETH_ALEN;
3712 }
3713
3714 netif_addr_unlock_bh(ndev);
3715
3716 /* Configure the struct for the Rx mode */
3717 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3718 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3719
3720 /* Remove all previous unicast secondary macs and multicast macs
3721 * (configrue / leave the primary mac)
3722 */
3723 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3724 edev->primary_mac);
3725 if (rc)
3726 goto out;
3727
3728 /* Check for promiscuous */
3729 if ((ndev->flags & IFF_PROMISC) ||
3730 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3731 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3732 } else {
3733 /* Add MAC filters according to the unicast secondary macs */
3734 int i;
3735
3736 temp = uc_macs;
3737 for (i = 0; i < uc_count; i++) {
3738 rc = qede_set_ucast_rx_mac(edev,
3739 QED_FILTER_XCAST_TYPE_ADD,
3740 temp);
3741 if (rc)
3742 goto out;
3743
3744 temp += ETH_ALEN;
3745 }
3746
3747 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3748 if (rc)
3749 goto out;
3750 }
3751
7c1bfcad
SRK		 3752 /* take care of VLAN mode */
3753 if (ndev->flags & IFF_PROMISC) {
3754 qede_config_accept_any_vlan(edev, true);
3755 } else if (!edev->non_configured_vlans) {
3756 /* It's possible that accept_any_vlan mode is set due to a
3757 * previous setting of IFF_PROMISC. If vlan credits are
3758 * sufficient, disable accept_any_vlan.
3759 */
3760 qede_config_accept_any_vlan(edev, false);
3761 }
3762
0d8e0aa0
SK		 3763 rx_mode.filter.accept_flags = accept_flags;
3764 edev->ops->filter_config(edev->cdev, &rx_mode);
3765out:
3766 kfree(uc_macs);
3767}
Linux kernel - Deliverables
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