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qed*: Trivial modifications
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
f9f082a9 27#include <net/udp_tunnel.h>
e712d52b
YM		 28#include <linux/ip.h>
29#include <net/ipv6.h>
30#include <net/tcp.h>
31#include <linux/if_ether.h>
32#include <linux/if_vlan.h>
33#include <linux/pkt_sched.h>
34#include <linux/ethtool.h>
35#include <linux/in.h>
36#include <linux/random.h>
37#include <net/ip6_checksum.h>
38#include <linux/bitops.h>
39
40#include "qede.h"
41
5abd7e92
YM		 42static char version[] =
43 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 44
5abd7e92 45MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
49static uint debug;
50module_param(debug, uint, 0);
51MODULE_PARM_DESC(debug, " Default debug msglevel");
52
53static const struct qed_eth_ops *qed_ops;
54
55#define CHIP_NUM_57980S_40 0x1634
0e7441d7 56#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 57#define CHIP_NUM_57980S_MF 0x1636
58#define CHIP_NUM_57980S_100 0x1644
59#define CHIP_NUM_57980S_50 0x1654
60#define CHIP_NUM_57980S_25 0x1656
fefb0202 61#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 62
63#ifndef PCI_DEVICE_ID_NX2_57980E
64#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
65#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
66#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
67#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
68#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
69#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 70#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 71#endif
72
fefb0202
YM		 73enum qede_pci_private {
74 QEDE_PRIVATE_PF,
75 QEDE_PRIVATE_VF
76};
77
e712d52b 78static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 79 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
80 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
81 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
82 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
83 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 85#ifdef CONFIG_QED_SRIOV
fefb0202 86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
14b84e86 87#endif
e712d52b
YM		 88 { 0 }
89};
90
91MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
92
93static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
94
95#define TX_TIMEOUT (5 * HZ)
96
97static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 98static int qede_alloc_rx_buffer(struct qede_dev *edev,
99 struct qede_rx_queue *rxq);
a2ec6172 100static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 101
fefb0202 102#ifdef CONFIG_QED_SRIOV
08feecd7
YM		 103static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
104{
105 struct qede_dev *edev = netdev_priv(ndev);
106
107 if (vlan > 4095) {
108 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
109 return -EINVAL;
110 }
111
112 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
113 vlan, vf);
114
115 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
116}
117
eff16960
YM		 118static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
119{
120 struct qede_dev *edev = netdev_priv(ndev);
121
122 DP_VERBOSE(edev, QED_MSG_IOV,
123 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
124 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
125
126 if (!is_valid_ether_addr(mac)) {
127 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
128 return -EINVAL;
129 }
130
131 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
132}
133
fefb0202
YM		 134static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
135{
136 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e
YM		 137 struct qed_dev_info *qed_info = &edev->dev_info.common;
138 int rc;
fefb0202
YM		 139
140 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
141
831bfb0e
YM		 142 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
143
144 /* Enable/Disable Tx switching for PF */
145 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
146 qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
147 struct qed_update_vport_params params;
148
149 memset(&params, 0, sizeof(params));
150 params.vport_id = 0;
151 params.update_tx_switching_flg = 1;
152 params.tx_switching_flg = num_vfs_param ? 1 : 0;
153 edev->ops->vport_update(edev->cdev, &params);
154 }
155
156 return rc;
fefb0202
YM		 157}
158#endif
159
e712d52b
YM		 160static struct pci_driver qede_pci_driver = {
161 .name = "qede",
162 .id_table = qede_pci_tbl,
163 .probe = qede_probe,
164 .remove = qede_remove,
fefb0202
YM		 165#ifdef CONFIG_QED_SRIOV
166 .sriov_configure = qede_sriov_configure,
167#endif
e712d52b
YM		 168};
169
eff16960
YM		 170static void qede_force_mac(void *dev, u8 *mac)
171{
172 struct qede_dev *edev = dev;
173
174 ether_addr_copy(edev->ndev->dev_addr, mac);
175 ether_addr_copy(edev->primary_mac, mac);
176}
177
a2ec6172
SK		 178static struct qed_eth_cb_ops qede_ll_ops = {
179 {
180 .link_update = qede_link_update,
181 },
eff16960 182 .force_mac = qede_force_mac,
a2ec6172
SK		 183};
184
2950219d
YM		 185static int qede_netdev_event(struct notifier_block *this, unsigned long event,
186 void *ptr)
187{
188 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
189 struct ethtool_drvinfo drvinfo;
190 struct qede_dev *edev;
191
192 /* Currently only support name change */
193 if (event != NETDEV_CHANGENAME)
194 goto done;
195
196 /* Check whether this is a qede device */
197 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
198 goto done;
199
200 memset(&drvinfo, 0, sizeof(drvinfo));
201 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
202 if (strcmp(drvinfo.driver, "qede"))
203 goto done;
204 edev = netdev_priv(ndev);
205
206 /* Notify qed of the name change */
207 if (!edev->ops || !edev->ops->common)
208 goto done;
209 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
210 "qede");
211
212done:
213 return NOTIFY_DONE;
214}
215
216static struct notifier_block qede_netdev_notifier = {
217 .notifier_call = qede_netdev_event,
218};
219
e712d52b
YM		 220static
221int __init qede_init(void)
222{
223 int ret;
e712d52b
YM		 224
225 pr_notice("qede_init: %s\n", version);
226
95114344 227 qed_ops = qed_get_eth_ops();
e712d52b
YM		 228 if (!qed_ops) {
229 pr_notice("Failed to get qed ethtool operations\n");
230 return -EINVAL;
231 }
232
2950219d
YM		 233 /* Must register notifier before pci ops, since we might miss
234 * interface rename after pci probe and netdev registeration.
235 */
236 ret = register_netdevice_notifier(&qede_netdev_notifier);
237 if (ret) {
238 pr_notice("Failed to register netdevice_notifier\n");
239 qed_put_eth_ops();
240 return -EINVAL;
241 }
242
e712d52b
YM		 243 ret = pci_register_driver(&qede_pci_driver);
244 if (ret) {
245 pr_notice("Failed to register driver\n");
2950219d 246 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 247 qed_put_eth_ops();
248 return -EINVAL;
249 }
250
251 return 0;
252}
253
254static void __exit qede_cleanup(void)
255{
256 pr_notice("qede_cleanup called\n");
257
2950219d 258 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 259 pci_unregister_driver(&qede_pci_driver);
260 qed_put_eth_ops();
261}
262
263module_init(qede_init);
264module_exit(qede_cleanup);
265
2950219d
YM		 266/* -------------------------------------------------------------------------
267 * START OF FAST-PATH
268 * -------------------------------------------------------------------------
269 */
270
271/* Unmap the data and free skb */
272static int qede_free_tx_pkt(struct qede_dev *edev,
1a635e48 273 struct qede_tx_queue *txq, int *len)
2950219d
YM		 274{
275 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
276 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
277 struct eth_tx_1st_bd *first_bd;
278 struct eth_tx_bd *tx_data_bd;
279 int bds_consumed = 0;
280 int nbds;
281 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
282 int i, split_bd_len = 0;
283
284 if (unlikely(!skb)) {
285 DP_ERR(edev,
286 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
287 idx, txq->sw_tx_cons, txq->sw_tx_prod);
288 return -1;
289 }
290
291 *len = skb->len;
292
293 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
294
295 bds_consumed++;
296
297 nbds = first_bd->data.nbds;
298
299 if (data_split) {
300 struct eth_tx_bd *split = (struct eth_tx_bd *)
301 qed_chain_consume(&txq->tx_pbl);
302 split_bd_len = BD_UNMAP_LEN(split);
303 bds_consumed++;
304 }
305 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
306 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
307
308 /* Unmap the data of the skb frags */
309 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
310 tx_data_bd = (struct eth_tx_bd *)
311 qed_chain_consume(&txq->tx_pbl);
312 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
313 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
314 }
315
316 while (bds_consumed++ < nbds)
317 qed_chain_consume(&txq->tx_pbl);
318
319 /* Free skb */
320 dev_kfree_skb_any(skb);
321 txq->sw_tx_ring[idx].skb = NULL;
322 txq->sw_tx_ring[idx].flags = 0;
323
324 return 0;
325}
326
327/* Unmap the data and free skb when mapping failed during start_xmit */
328static void qede_free_failed_tx_pkt(struct qede_dev *edev,
329 struct qede_tx_queue *txq,
330 struct eth_tx_1st_bd *first_bd,
1a635e48 331 int nbd, bool data_split)
2950219d
YM		 332{
333 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
334 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
335 struct eth_tx_bd *tx_data_bd;
336 int i, split_bd_len = 0;
337
338 /* Return prod to its position before this skb was handled */
339 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 340 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 341
342 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
343
344 if (data_split) {
345 struct eth_tx_bd *split = (struct eth_tx_bd *)
346 qed_chain_produce(&txq->tx_pbl);
347 split_bd_len = BD_UNMAP_LEN(split);
348 nbd--;
349 }
350
351 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
352 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
353
354 /* Unmap the data of the skb frags */
355 for (i = 0; i < nbd; i++) {
356 tx_data_bd = (struct eth_tx_bd *)
357 qed_chain_produce(&txq->tx_pbl);
358 if (tx_data_bd->nbytes)
359 dma_unmap_page(&edev->pdev->dev,
360 BD_UNMAP_ADDR(tx_data_bd),
361 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
362 }
363
364 /* Return again prod to its position before this skb was handled */
365 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 366 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 367
368 /* Free skb */
369 dev_kfree_skb_any(skb);
370 txq->sw_tx_ring[idx].skb = NULL;
371 txq->sw_tx_ring[idx].flags = 0;
372}
373
374static u32 qede_xmit_type(struct qede_dev *edev,
1a635e48 375 struct sk_buff *skb, int *ipv6_ext)
2950219d
YM		 376{
377 u32 rc = XMIT_L4_CSUM;
378 __be16 l3_proto;
379
380 if (skb->ip_summed != CHECKSUM_PARTIAL)
381 return XMIT_PLAIN;
382
383 l3_proto = vlan_get_protocol(skb);
384 if (l3_proto == htons(ETH_P_IPV6) &&
385 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
386 *ipv6_ext = 1;
387
14db81de
MC		 388 if (skb->encapsulation)
389 rc |= XMIT_ENC;
390
2950219d
YM		 391 if (skb_is_gso(skb))
392 rc |= XMIT_LSO;
393
394 return rc;
395}
396
397static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
398 struct eth_tx_2nd_bd *second_bd,
399 struct eth_tx_3rd_bd *third_bd)
400{
401 u8 l4_proto;
fc48b7a6 402 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 403
fc48b7a6 404 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 405
fc48b7a6 406 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 407 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
408 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
409
fc48b7a6 410 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 411 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
412
413 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
414 l4_proto = ipv6_hdr(skb)->nexthdr;
415 else
416 l4_proto = ip_hdr(skb)->protocol;
417
418 if (l4_proto == IPPROTO_UDP)
fc48b7a6 419 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 420
fc48b7a6 421 if (third_bd)
2950219d 422 third_bd->data.bitfields |=
fc48b7a6
YM		 423 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
424 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
425 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 426
fc48b7a6 427 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 428 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
429}
430
431static int map_frag_to_bd(struct qede_dev *edev,
1a635e48 432 skb_frag_t *frag, struct eth_tx_bd *bd)
2950219d
YM		 433{
434 dma_addr_t mapping;
435
436 /* Map skb non-linear frag data for DMA */
437 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
1a635e48 438 skb_frag_size(frag), DMA_TO_DEVICE);
2950219d
YM		 439 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
440 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
441 return -ENOMEM;
442 }
443
444 /* Setup the data pointer of the frag data */
445 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
446
447 return 0;
448}
449
14db81de
MC		 450static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
451{
452 if (is_encap_pkt)
453 return (skb_inner_transport_header(skb) +
454 inner_tcp_hdrlen(skb) - skb->data);
455 else
456 return (skb_transport_header(skb) +
457 tcp_hdrlen(skb) - skb->data);
458}
459
b1199b10
YM		 460/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
461#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
462static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
463 u8 xmit_type)
464{
465 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
466
467 if (xmit_type & XMIT_LSO) {
468 int hlen;
469
14db81de 470 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 471
472 /* linear payload would require its own BD */
473 if (skb_headlen(skb) > hlen)
474 allowed_frags--;
475 }
476
477 return (skb_shinfo(skb)->nr_frags > allowed_frags);
478}
479#endif
480
312e0676
MC		 481static inline void qede_update_tx_producer(struct qede_tx_queue *txq)
482{
483 /* wmb makes sure that the BDs data is updated before updating the
484 * producer, otherwise FW may read old data from the BDs.
485 */
486 wmb();
487 barrier();
488 writel(txq->tx_db.raw, txq->doorbell_addr);
489
490 /* mmiowb is needed to synchronize doorbell writes from more than one
491 * processor. It guarantees that the write arrives to the device before
492 * the queue lock is released and another start_xmit is called (possibly
493 * on another CPU). Without this barrier, the next doorbell can bypass
494 * this doorbell. This is applicable to IA64/Altix systems.
495 */
496 mmiowb();
497}
498
2950219d 499/* Main transmit function */
1a635e48
YM		 500static netdev_tx_t qede_start_xmit(struct sk_buff *skb,
501 struct net_device *ndev)
2950219d
YM		 502{
503 struct qede_dev *edev = netdev_priv(ndev);
504 struct netdev_queue *netdev_txq;
505 struct qede_tx_queue *txq;
506 struct eth_tx_1st_bd *first_bd;
507 struct eth_tx_2nd_bd *second_bd = NULL;
508 struct eth_tx_3rd_bd *third_bd = NULL;
509 struct eth_tx_bd *tx_data_bd = NULL;
510 u16 txq_index;
511 u8 nbd = 0;
512 dma_addr_t mapping;
513 int rc, frag_idx = 0, ipv6_ext = 0;
514 u8 xmit_type;
515 u16 idx;
516 u16 hlen;
810810ff 517 bool data_split = false;
2950219d
YM		 518
519 /* Get tx-queue context and netdev index */
520 txq_index = skb_get_queue_mapping(skb);
521 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
522 txq = QEDE_TX_QUEUE(edev, txq_index);
523 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
524
1a635e48 525 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) < (MAX_SKB_FRAGS + 1));
2950219d
YM		 526
527 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
528
b1199b10
YM		 529#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
530 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
531 if (skb_linearize(skb)) {
532 DP_NOTICE(edev,
533 "SKB linearization failed - silently dropping this SKB\n");
534 dev_kfree_skb_any(skb);
535 return NETDEV_TX_OK;
536 }
537 }
538#endif
539
2950219d
YM		 540 /* Fill the entry in the SW ring and the BDs in the FW ring */
541 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
542 txq->sw_tx_ring[idx].skb = skb;
543 first_bd = (struct eth_tx_1st_bd *)
544 qed_chain_produce(&txq->tx_pbl);
545 memset(first_bd, 0, sizeof(*first_bd));
546 first_bd->data.bd_flags.bitfields =
547 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
548
549 /* Map skb linear data for DMA and set in the first BD */
550 mapping = dma_map_single(&edev->pdev->dev, skb->data,
551 skb_headlen(skb), DMA_TO_DEVICE);
552 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
553 DP_NOTICE(edev, "SKB mapping failed\n");
554 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
312e0676 555 qede_update_tx_producer(txq);
2950219d
YM		 556 return NETDEV_TX_OK;
557 }
558 nbd++;
559 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
560
561 /* In case there is IPv6 with extension headers or LSO we need 2nd and
562 * 3rd BDs.
563 */
564 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
565 second_bd = (struct eth_tx_2nd_bd *)
566 qed_chain_produce(&txq->tx_pbl);
567 memset(second_bd, 0, sizeof(*second_bd));
568
569 nbd++;
570 third_bd = (struct eth_tx_3rd_bd *)
571 qed_chain_produce(&txq->tx_pbl);
572 memset(third_bd, 0, sizeof(*third_bd));
573
574 nbd++;
575 /* We need to fill in additional data in second_bd... */
576 tx_data_bd = (struct eth_tx_bd *)second_bd;
577 }
578
579 if (skb_vlan_tag_present(skb)) {
580 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
581 first_bd->data.bd_flags.bitfields |=
582 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
583 }
584
585 /* Fill the parsing flags & params according to the requested offload */
586 if (xmit_type & XMIT_L4_CSUM) {
587 /* We don't re-calculate IP checksum as it is already done by
588 * the upper stack
589 */
590 first_bd->data.bd_flags.bitfields |=
591 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
592
14db81de
MC		 593 if (xmit_type & XMIT_ENC) {
594 first_bd->data.bd_flags.bitfields |=
595 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
351a4ded
YM		 596 first_bd->data.bitfields |=
597 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
14db81de 598 }
fc48b7a6 599
2950219d
YM		 600 /* If the packet is IPv6 with extension header, indicate that
601 * to FW and pass few params, since the device cracker doesn't
602 * support parsing IPv6 with extension header/s.
603 */
604 if (unlikely(ipv6_ext))
605 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
606 }
607
608 if (xmit_type & XMIT_LSO) {
609 first_bd->data.bd_flags.bitfields |=
610 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
611 third_bd->data.lso_mss =
612 cpu_to_le16(skb_shinfo(skb)->gso_size);
613
14db81de
MC		 614 if (unlikely(xmit_type & XMIT_ENC)) {
615 first_bd->data.bd_flags.bitfields |=
616 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
617 hlen = qede_get_skb_hlen(skb, true);
618 } else {
619 first_bd->data.bd_flags.bitfields |=
620 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
621 hlen = qede_get_skb_hlen(skb, false);
622 }
2950219d
YM		 623
624 /* @@@TBD - if will not be removed need to check */
625 third_bd->data.bitfields |=
fc48b7a6 626 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 627
628 /* Make life easier for FW guys who can't deal with header and
629 * data on same BD. If we need to split, use the second bd...
630 */
631 if (unlikely(skb_headlen(skb) > hlen)) {
632 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
633 "TSO split header size is %d (%x:%x)\n",
634 first_bd->nbytes, first_bd->addr.hi,
635 first_bd->addr.lo);
636
637 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
638 le32_to_cpu(first_bd->addr.lo)) +
639 hlen;
640
641 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
642 le16_to_cpu(first_bd->nbytes) -
643 hlen);
644
645 /* this marks the BD as one that has no
646 * individual mapping
647 */
648 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
649
650 first_bd->nbytes = cpu_to_le16(hlen);
651
652 tx_data_bd = (struct eth_tx_bd *)third_bd;
653 data_split = true;
654 }
351a4ded
YM		 655 } else {
656 first_bd->data.bitfields |=
657 (skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) <<
658 ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2950219d
YM		 659 }
660
661 /* Handle fragmented skb */
662 /* special handle for frags inside 2nd and 3rd bds.. */
663 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
664 rc = map_frag_to_bd(edev,
665 &skb_shinfo(skb)->frags[frag_idx],
666 tx_data_bd);
667 if (rc) {
668 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
669 data_split);
312e0676 670 qede_update_tx_producer(txq);
2950219d
YM		 671 return NETDEV_TX_OK;
672 }
673
674 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
675 tx_data_bd = (struct eth_tx_bd *)third_bd;
676 else
677 tx_data_bd = NULL;
678
679 frag_idx++;
680 }
681
682 /* map last frags into 4th, 5th .... */
683 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
684 tx_data_bd = (struct eth_tx_bd *)
685 qed_chain_produce(&txq->tx_pbl);
686
687 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
688
689 rc = map_frag_to_bd(edev,
690 &skb_shinfo(skb)->frags[frag_idx],
691 tx_data_bd);
692 if (rc) {
693 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
694 data_split);
312e0676 695 qede_update_tx_producer(txq);
2950219d
YM		 696 return NETDEV_TX_OK;
697 }
698 }
699
700 /* update the first BD with the actual num BDs */
701 first_bd->data.nbds = nbd;
702
703 netdev_tx_sent_queue(netdev_txq, skb->len);
704
705 skb_tx_timestamp(skb);
706
707 /* Advance packet producer only before sending the packet since mapping
708 * of pages may fail.
709 */
710 txq->sw_tx_prod++;
711
712 /* 'next page' entries are counted in the producer value */
713 txq->tx_db.data.bd_prod =
714 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
715
312e0676
MC		 716 if (!skb->xmit_more || netif_tx_queue_stopped(netdev_txq))
717 qede_update_tx_producer(txq);
2950219d
YM		 718
719 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
720 < (MAX_SKB_FRAGS + 1))) {
721 netif_tx_stop_queue(netdev_txq);
722 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
723 "Stop queue was called\n");
724 /* paired memory barrier is in qede_tx_int(), we have to keep
725 * ordering of set_bit() in netif_tx_stop_queue() and read of
726 * fp->bd_tx_cons
727 */
728 smp_mb();
729
730 if (qed_chain_get_elem_left(&txq->tx_pbl)
731 >= (MAX_SKB_FRAGS + 1) &&
732 (edev->state == QEDE_STATE_OPEN)) {
733 netif_tx_wake_queue(netdev_txq);
734 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
735 "Wake queue was called\n");
736 }
737 }
738
739 return NETDEV_TX_OK;
740}
741
16f46bf0 742int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 743{
744 u16 hw_bd_cons;
745
746 /* Tell compiler that consumer and producer can change */
747 barrier();
748 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
749 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
750 return 0;
751
752 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
753}
754
1a635e48 755static int qede_tx_int(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 756{
757 struct netdev_queue *netdev_txq;
758 u16 hw_bd_cons;
759 unsigned int pkts_compl = 0, bytes_compl = 0;
760 int rc;
761
762 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
763
764 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
765 barrier();
766
767 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
768 int len = 0;
769
770 rc = qede_free_tx_pkt(edev, txq, &len);
771 if (rc) {
772 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
773 hw_bd_cons,
774 qed_chain_get_cons_idx(&txq->tx_pbl));
775 break;
776 }
777
778 bytes_compl += len;
779 pkts_compl++;
780 txq->sw_tx_cons++;
781 }
782
783 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
784
785 /* Need to make the tx_bd_cons update visible to start_xmit()
786 * before checking for netif_tx_queue_stopped(). Without the
787 * memory barrier, there is a small possibility that
788 * start_xmit() will miss it and cause the queue to be stopped
789 * forever.
790 * On the other hand we need an rmb() here to ensure the proper
791 * ordering of bit testing in the following
792 * netif_tx_queue_stopped(txq) call.
793 */
794 smp_mb();
795
796 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
797 /* Taking tx_lock is needed to prevent reenabling the queue
798 * while it's empty. This could have happen if rx_action() gets
799 * suspended in qede_tx_int() after the condition before
800 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
801 *
802 * stops the queue->sees fresh tx_bd_cons->releases the queue->
803 * sends some packets consuming the whole queue again->
804 * stops the queue
805 */
806
807 __netif_tx_lock(netdev_txq, smp_processor_id());
808
809 if ((netif_tx_queue_stopped(netdev_txq)) &&
810 (edev->state == QEDE_STATE_OPEN) &&
811 (qed_chain_get_elem_left(&txq->tx_pbl)
812 >= (MAX_SKB_FRAGS + 1))) {
813 netif_tx_wake_queue(netdev_txq);
814 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
815 "Wake queue was called\n");
816 }
817
818 __netif_tx_unlock(netdev_txq);
819 }
820
821 return 0;
822}
823
16f46bf0 824bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 825{
826 u16 hw_comp_cons, sw_comp_cons;
827
828 /* Tell compiler that status block fields can change */
829 barrier();
830
831 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
832 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
833
834 return hw_comp_cons != sw_comp_cons;
835}
836
837static bool qede_has_tx_work(struct qede_fastpath *fp)
838{
839 u8 tc;
840
841 for (tc = 0; tc < fp->edev->num_tc; tc++)
842 if (qede_txq_has_work(&fp->txqs[tc]))
843 return true;
844 return false;
845}
846
f86af2df
MC		 847static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
848{
849 qed_chain_consume(&rxq->rx_bd_ring);
850 rxq->sw_rx_cons++;
851}
852
fc48b7a6
YM		 853/* This function reuses the buffer(from an offset) from
854 * consumer index to producer index in the bd ring
2950219d 855 */
fc48b7a6
YM		 856static inline void qede_reuse_page(struct qede_dev *edev,
857 struct qede_rx_queue *rxq,
858 struct sw_rx_data *curr_cons)
2950219d 859{
2950219d 860 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 861 struct sw_rx_data *curr_prod;
862 dma_addr_t new_mapping;
2950219d 863
fc48b7a6
YM		 864 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
865 *curr_prod = *curr_cons;
2950219d 866
fc48b7a6
YM		 867 new_mapping = curr_prod->mapping + curr_prod->page_offset;
868
869 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
870 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 871
2950219d 872 rxq->sw_rx_prod++;
fc48b7a6
YM		 873 curr_cons->data = NULL;
874}
875
f86af2df
MC		 876/* In case of allocation failures reuse buffers
877 * from consumer index to produce buffers for firmware
878 */
16f46bf0
SRK		 879void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
880 struct qede_dev *edev, u8 count)
f86af2df
MC		 881{
882 struct sw_rx_data *curr_cons;
883
884 for (; count > 0; count--) {
885 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
886 qede_reuse_page(edev, rxq, curr_cons);
887 qede_rx_bd_ring_consume(rxq);
888 }
889}
890
fc48b7a6
YM		 891static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
892 struct qede_rx_queue *rxq,
893 struct sw_rx_data *curr_cons)
894{
895 /* Move to the next segment in the page */
896 curr_cons->page_offset += rxq->rx_buf_seg_size;
897
898 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 899 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
900 /* Since we failed to allocate new buffer
901 * current buffer can be used again.
902 */
903 curr_cons->page_offset -= rxq->rx_buf_seg_size;
904
fc48b7a6 905 return -ENOMEM;
f86af2df 906 }
fc48b7a6
YM		 907
908 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
909 PAGE_SIZE, DMA_FROM_DEVICE);
910 } else {
911 /* Increment refcount of the page as we don't want
912 * network stack to take the ownership of the page
913 * which can be recycled multiple times by the driver.
914 */
6d061f9f 915 page_ref_inc(curr_cons->data);
fc48b7a6
YM		 916 qede_reuse_page(edev, rxq, curr_cons);
917 }
918
919 return 0;
2950219d
YM		 920}
921
922static inline void qede_update_rx_prod(struct qede_dev *edev,
923 struct qede_rx_queue *rxq)
924{
925 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
926 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
927 struct eth_rx_prod_data rx_prods = {0};
928
929 /* Update producers */
930 rx_prods.bd_prod = cpu_to_le16(bd_prod);
931 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
932
933 /* Make sure that the BD and SGE data is updated before updating the
934 * producers since FW might read the BD/SGE right after the producer
935 * is updated.
936 */
937 wmb();
938
939 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
940 (u32 *)&rx_prods);
941
942 /* mmiowb is needed to synchronize doorbell writes from more than one
943 * processor. It guarantees that the write arrives to the device before
944 * the napi lock is released and another qede_poll is called (possibly
945 * on another CPU). Without this barrier, the next doorbell can bypass
946 * this doorbell. This is applicable to IA64/Altix systems.
947 */
948 mmiowb();
949}
950
951static u32 qede_get_rxhash(struct qede_dev *edev,
952 u8 bitfields,
1a635e48 953 __le32 rss_hash, enum pkt_hash_types *rxhash_type)
2950219d
YM		 954{
955 enum rss_hash_type htype;
956
957 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
958
959 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
960 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
961 (htype == RSS_HASH_TYPE_IPV6)) ?
962 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
963 return le32_to_cpu(rss_hash);
964 }
965 *rxhash_type = PKT_HASH_TYPE_NONE;
966 return 0;
967}
968
969static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
970{
971 skb_checksum_none_assert(skb);
972
973 if (csum_flag & QEDE_CSUM_UNNECESSARY)
974 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 975
976 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
977 skb->csum_level = 1;
2950219d
YM		 978}
979
980static inline void qede_skb_receive(struct qede_dev *edev,
981 struct qede_fastpath *fp,
1a635e48 982 struct sk_buff *skb, u16 vlan_tag)
2950219d
YM		 983{
984 if (vlan_tag)
1a635e48 985 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
2950219d
YM		 986
987 napi_gro_receive(&fp->napi, skb);
988}
989
55482edc
MC		 990static void qede_set_gro_params(struct qede_dev *edev,
991 struct sk_buff *skb,
992 struct eth_fast_path_rx_tpa_start_cqe *cqe)
993{
994 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
995
996 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
997 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
998 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
999 else
1000 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1001
1002 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
1003 cqe->header_len;
1004}
1005
1006static int qede_fill_frag_skb(struct qede_dev *edev,
1007 struct qede_rx_queue *rxq,
1a635e48 1008 u8 tpa_agg_index, u16 len_on_bd)
55482edc
MC		 1009{
1010 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
1011 NUM_RX_BDS_MAX];
1012 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
1013 struct sk_buff *skb = tpa_info->skb;
1014
1015 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1016 goto out;
1017
1018 /* Add one frag and update the appropriate fields in the skb */
1019 skb_fill_page_desc(skb, tpa_info->frag_id++,
1020 current_bd->data, current_bd->page_offset,
1021 len_on_bd);
1022
1023 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 1024 /* Incr page ref count to reuse on allocation failure
1025 * so that it doesn't get freed while freeing SKB.
1026 */
0139aa7b 1027 page_ref_inc(current_bd->data);
55482edc
MC		 1028 goto out;
1029 }
1030
1031 qed_chain_consume(&rxq->rx_bd_ring);
1032 rxq->sw_rx_cons++;
1033
1034 skb->data_len += len_on_bd;
1035 skb->truesize += rxq->rx_buf_seg_size;
1036 skb->len += len_on_bd;
1037
1038 return 0;
1039
1040out:
f86af2df
MC		 1041 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1042 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1043 return -ENOMEM;
1044}
1045
1046static void qede_tpa_start(struct qede_dev *edev,
1047 struct qede_rx_queue *rxq,
1048 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1049{
1050 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1051 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1052 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
1053 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
1054 dma_addr_t mapping = tpa_info->replace_buf_mapping;
1055 struct sw_rx_data *sw_rx_data_cons;
1056 struct sw_rx_data *sw_rx_data_prod;
1057 enum pkt_hash_types rxhash_type;
1058 u32 rxhash;
1059
1060 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1061 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1062
1063 /* Use pre-allocated replacement buffer - we can't release the agg.
1064 * start until its over and we don't want to risk allocation failing
1065 * here, so re-allocate when aggregation will be over.
1066 */
09ec8e7f 1067 sw_rx_data_prod->mapping = replace_buf->mapping;
55482edc
MC		 1068
1069 sw_rx_data_prod->data = replace_buf->data;
1070 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1071 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1072 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1073
1074 rxq->sw_rx_prod++;
1075
1076 /* move partial skb from cons to pool (don't unmap yet)
1077 * save mapping, incase we drop the packet later on.
1078 */
1079 tpa_info->start_buf = *sw_rx_data_cons;
1080 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1081 le32_to_cpu(rx_bd_cons->addr.lo));
1082
1083 tpa_info->start_buf_mapping = mapping;
1084 rxq->sw_rx_cons++;
1085
1086 /* set tpa state to start only if we are able to allocate skb
1087 * for this aggregation, otherwise mark as error and aggregation will
1088 * be dropped
1089 */
1090 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1091 le16_to_cpu(cqe->len_on_first_bd));
1092 if (unlikely(!tpa_info->skb)) {
f86af2df 1093 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1094 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1095 goto cons_buf;
55482edc
MC		 1096 }
1097
1098 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1099 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1100
1101 /* Start filling in the aggregation info */
1102 tpa_info->frag_id = 0;
1103 tpa_info->agg_state = QEDE_AGG_STATE_START;
1104
1105 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1106 cqe->rss_hash, &rxhash_type);
1107 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1108 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1109 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1110 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1111 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1112 else
1113 tpa_info->vlan_tag = 0;
1114
1115 /* This is needed in order to enable forwarding support */
1116 qede_set_gro_params(edev, tpa_info->skb, cqe);
1117
f86af2df 1118cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1119 if (likely(cqe->ext_bd_len_list[0]))
1120 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1121 le16_to_cpu(cqe->ext_bd_len_list[0]));
1122
1123 if (unlikely(cqe->ext_bd_len_list[1])) {
1124 DP_ERR(edev,
1125 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1126 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1127 }
1128}
1129
88f09bd5 1130#ifdef CONFIG_INET
55482edc
MC		 1131static void qede_gro_ip_csum(struct sk_buff *skb)
1132{
1133 const struct iphdr *iph = ip_hdr(skb);
1134 struct tcphdr *th;
1135
55482edc
MC		 1136 skb_set_transport_header(skb, sizeof(struct iphdr));
1137 th = tcp_hdr(skb);
1138
1139 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1140 iph->saddr, iph->daddr, 0);
1141
1142 tcp_gro_complete(skb);
1143}
1144
1145static void qede_gro_ipv6_csum(struct sk_buff *skb)
1146{
1147 struct ipv6hdr *iph = ipv6_hdr(skb);
1148 struct tcphdr *th;
1149
55482edc
MC		 1150 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1151 th = tcp_hdr(skb);
1152
1153 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1154 &iph->saddr, &iph->daddr, 0);
1155 tcp_gro_complete(skb);
1156}
88f09bd5 1157#endif
55482edc
MC		 1158
1159static void qede_gro_receive(struct qede_dev *edev,
1160 struct qede_fastpath *fp,
1161 struct sk_buff *skb,
1162 u16 vlan_tag)
1163{
ee2fa8e6
MC		 1164 /* FW can send a single MTU sized packet from gro flow
1165 * due to aggregation timeout/last segment etc. which
1166 * is not expected to be a gro packet. If a skb has zero
1167 * frags then simply push it in the stack as non gso skb.
1168 */
1169 if (unlikely(!skb->data_len)) {
1170 skb_shinfo(skb)->gso_type = 0;
1171 skb_shinfo(skb)->gso_size = 0;
1172 goto send_skb;
1173 }
1174
88f09bd5 1175#ifdef CONFIG_INET
55482edc 1176 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1177 skb_set_network_header(skb, 0);
1178
55482edc
MC		 1179 switch (skb->protocol) {
1180 case htons(ETH_P_IP):
1181 qede_gro_ip_csum(skb);
1182 break;
1183 case htons(ETH_P_IPV6):
1184 qede_gro_ipv6_csum(skb);
1185 break;
1186 default:
1187 DP_ERR(edev,
1188 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1189 ntohs(skb->protocol));
1190 }
1191 }
88f09bd5 1192#endif
ee2fa8e6
MC		 1193
1194send_skb:
55482edc
MC		 1195 skb_record_rx_queue(skb, fp->rss_id);
1196 qede_skb_receive(edev, fp, skb, vlan_tag);
1197}
1198
1199static inline void qede_tpa_cont(struct qede_dev *edev,
1200 struct qede_rx_queue *rxq,
1201 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1202{
1203 int i;
1204
1205 for (i = 0; cqe->len_list[i]; i++)
1206 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1207 le16_to_cpu(cqe->len_list[i]));
1208
1209 if (unlikely(i > 1))
1210 DP_ERR(edev,
1211 "Strange - TPA cont with more than a single len_list entry\n");
1212}
1213
1214static void qede_tpa_end(struct qede_dev *edev,
1215 struct qede_fastpath *fp,
1216 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1217{
1218 struct qede_rx_queue *rxq = fp->rxq;
1219 struct qede_agg_info *tpa_info;
1220 struct sk_buff *skb;
1221 int i;
1222
1223 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1224 skb = tpa_info->skb;
1225
1226 for (i = 0; cqe->len_list[i]; i++)
1227 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1228 le16_to_cpu(cqe->len_list[i]));
1229 if (unlikely(i > 1))
1230 DP_ERR(edev,
1231 "Strange - TPA emd with more than a single len_list entry\n");
1232
1233 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1234 goto err;
1235
1236 /* Sanity */
1237 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1238 DP_ERR(edev,
1239 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1240 cqe->num_of_bds, tpa_info->frag_id);
1241 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1242 DP_ERR(edev,
1243 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1244 le16_to_cpu(cqe->total_packet_len), skb->len);
1245
1246 memcpy(skb->data,
1247 page_address(tpa_info->start_buf.data) +
1248 tpa_info->start_cqe.placement_offset +
1249 tpa_info->start_buf.page_offset,
1250 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1251
1252 /* Recycle [mapped] start buffer for the next replacement */
1253 tpa_info->replace_buf = tpa_info->start_buf;
1254 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1255
1256 /* Finalize the SKB */
1257 skb->protocol = eth_type_trans(skb, edev->ndev);
1258 skb->ip_summed = CHECKSUM_UNNECESSARY;
1259
1260 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1261 * to skb_shinfo(skb)->gso_segs
1262 */
1263 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1264
1265 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1266
1267 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1268
1269 return;
1270err:
1271 /* The BD starting the aggregation is still mapped; Re-use it for
1272 * future aggregations [as replacement buffer]
1273 */
1274 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1275 sizeof(struct sw_rx_data));
1276 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1277 tpa_info->start_buf.data = NULL;
1278 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1279 dev_kfree_skb_any(tpa_info->skb);
1280 tpa_info->skb = NULL;
1281}
1282
14db81de
MC		 1283static bool qede_tunn_exist(u16 flag)
1284{
1285 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1286 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1287}
1288
1289static u8 qede_check_tunn_csum(u16 flag)
1290{
1291 u16 csum_flag = 0;
1292 u8 tcsum = 0;
1293
1294 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1295 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1296 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1297 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1298
1299 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1300 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1301 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1302 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1303 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1304 }
1305
1306 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1307 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1308 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1309 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1310
1311 if (csum_flag & flag)
1312 return QEDE_CSUM_ERROR;
1313
1314 return QEDE_CSUM_UNNECESSARY | tcsum;
1315}
1316
1317static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1318{
1319 u16 csum_flag = 0;
1320 u8 csum = 0;
1321
14db81de
MC		 1322 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1323 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1324 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1325 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1326 csum = QEDE_CSUM_UNNECESSARY;
1327 }
1328
1329 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1330 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1331
1332 if (csum_flag & flag)
1333 return QEDE_CSUM_ERROR;
1334
1335 return csum;
1336}
1337
14db81de
MC		 1338static u8 qede_check_csum(u16 flag)
1339{
1340 if (!qede_tunn_exist(flag))
1341 return qede_check_notunn_csum(flag);
1342 else
1343 return qede_check_tunn_csum(flag);
1344}
1345
c72a6125
MC		 1346static bool qede_pkt_is_ip_fragmented(struct eth_fast_path_rx_reg_cqe *cqe,
1347 u16 flag)
1348{
1349 u8 tun_pars_flg = cqe->tunnel_pars_flags.flags;
1350
1351 if ((tun_pars_flg & (ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK <<
1352 ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT)) ||
1353 (flag & (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1354 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT)))
1355 return true;
1356
1357 return false;
1358}
1359
2950219d
YM		 1360static int qede_rx_int(struct qede_fastpath *fp, int budget)
1361{
1362 struct qede_dev *edev = fp->edev;
1363 struct qede_rx_queue *rxq = fp->rxq;
1364
1365 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1366 int rx_pkt = 0;
1367 u8 csum_flag;
1368
1369 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1370 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1371
1372 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1373 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1374 * read before it is written by FW, then FW writes CQE and SB, and then
1375 * the CPU reads the hw_comp_cons, it will use an old CQE.
1376 */
1377 rmb();
1378
1379 /* Loop to complete all indicated BDs */
1380 while (sw_comp_cons != hw_comp_cons) {
1381 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1382 enum pkt_hash_types rxhash_type;
1383 enum eth_rx_cqe_type cqe_type;
1384 struct sw_rx_data *sw_rx_data;
1385 union eth_rx_cqe *cqe;
1386 struct sk_buff *skb;
fc48b7a6
YM		 1387 struct page *data;
1388 __le16 flags;
2950219d
YM		 1389 u16 len, pad;
1390 u32 rx_hash;
2950219d
YM		 1391
1392 /* Get the CQE from the completion ring */
1393 cqe = (union eth_rx_cqe *)
1394 qed_chain_consume(&rxq->rx_comp_ring);
1395 cqe_type = cqe->fast_path_regular.type;
1396
1397 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1398 edev->ops->eth_cqe_completion(
1399 edev->cdev, fp->rss_id,
1400 (struct eth_slow_path_rx_cqe *)cqe);
1401 goto next_cqe;
1402 }
1403
55482edc
MC		 1404 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1405 switch (cqe_type) {
1406 case ETH_RX_CQE_TYPE_TPA_START:
1407 qede_tpa_start(edev, rxq,
1408 &cqe->fast_path_tpa_start);
1409 goto next_cqe;
1410 case ETH_RX_CQE_TYPE_TPA_CONT:
1411 qede_tpa_cont(edev, rxq,
1412 &cqe->fast_path_tpa_cont);
1413 goto next_cqe;
1414 case ETH_RX_CQE_TYPE_TPA_END:
1415 qede_tpa_end(edev, fp,
1416 &cqe->fast_path_tpa_end);
1417 goto next_rx_only;
1418 default:
1419 break;
1420 }
1421 }
1422
2950219d
YM		 1423 /* Get the data from the SW ring */
1424 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1425 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1426 data = sw_rx_data->data;
1427
1428 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1429 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1430 pad = fp_cqe->placement_offset;
fc48b7a6 1431 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1432
fc48b7a6
YM		 1433 /* If this is an error packet then drop it */
1434 parse_flag = le16_to_cpu(flags);
2950219d 1435
fc48b7a6
YM		 1436 csum_flag = qede_check_csum(parse_flag);
1437 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
c72a6125
MC		 1438 if (qede_pkt_is_ip_fragmented(&cqe->fast_path_regular,
1439 parse_flag)) {
1440 rxq->rx_ip_frags++;
1441 goto alloc_skb;
1442 }
1443
fc48b7a6
YM		 1444 DP_NOTICE(edev,
1445 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1446 sw_comp_cons, parse_flag);
1447 rxq->rx_hw_errors++;
f86af2df
MC		 1448 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1449 goto next_cqe;
fc48b7a6 1450 }
2950219d 1451
c72a6125 1452alloc_skb:
fc48b7a6
YM		 1453 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1454 if (unlikely(!skb)) {
2950219d 1455 DP_NOTICE(edev,
fc48b7a6 1456 "Build_skb failed, dropping incoming packet\n");
f86af2df 1457 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1458 rxq->rx_alloc_errors++;
f86af2df 1459 goto next_cqe;
fc48b7a6
YM		 1460 }
1461
1462 /* Copy data into SKB */
3d789994 1463 if (len + pad <= edev->rx_copybreak) {
fc48b7a6
YM		 1464 memcpy(skb_put(skb, len),
1465 page_address(data) + pad +
1466 sw_rx_data->page_offset, len);
1467 qede_reuse_page(edev, rxq, sw_rx_data);
1468 } else {
1469 struct skb_frag_struct *frag;
1470 unsigned int pull_len;
1471 unsigned char *va;
1472
1473 frag = &skb_shinfo(skb)->frags[0];
1474
1475 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1476 pad + sw_rx_data->page_offset,
1477 len, rxq->rx_buf_seg_size);
1478
1479 va = skb_frag_address(frag);
1480 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1481
1482 /* Align the pull_len to optimize memcpy */
1483 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1484
1485 skb_frag_size_sub(frag, pull_len);
1486 frag->page_offset += pull_len;
1487 skb->data_len -= pull_len;
1488 skb->tail += pull_len;
1489
1490 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1491 sw_rx_data))) {
1492 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1493 /* Incr page ref count to reuse on allocation
1494 * failure so that it doesn't get freed while
1495 * freeing SKB.
1496 */
1497
0139aa7b 1498 page_ref_inc(sw_rx_data->data);
fc48b7a6 1499 rxq->rx_alloc_errors++;
f86af2df
MC		 1500 qede_recycle_rx_bd_ring(rxq, edev,
1501 fp_cqe->bd_num);
1502 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1503 goto next_cqe;
1504 }
2950219d
YM		 1505 }
1506
f86af2df
MC		 1507 qede_rx_bd_ring_consume(rxq);
1508
fc48b7a6
YM		 1509 if (fp_cqe->bd_num != 1) {
1510 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1511 u8 num_frags;
1512
1513 pkt_len -= len;
1514
1515 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1516 num_frags--) {
1517 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1518 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1519 if (unlikely(!cur_size)) {
1520 DP_ERR(edev,
1521 "Still got %d BDs for mapping jumbo, but length became 0\n",
1522 num_frags);
1523 qede_recycle_rx_bd_ring(rxq, edev,
1524 num_frags);
1525 dev_kfree_skb_any(skb);
1526 goto next_cqe;
1527 }
fc48b7a6 1528
f86af2df
MC		 1529 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1530 qede_recycle_rx_bd_ring(rxq, edev,
1531 num_frags);
1532 dev_kfree_skb_any(skb);
fc48b7a6 1533 goto next_cqe;
f86af2df 1534 }
fc48b7a6 1535
fc48b7a6
YM		 1536 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1537 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1538 qede_rx_bd_ring_consume(rxq);
1539
fc48b7a6
YM		 1540 dma_unmap_page(&edev->pdev->dev,
1541 sw_rx_data->mapping,
1542 PAGE_SIZE, DMA_FROM_DEVICE);
1543
1544 skb_fill_page_desc(skb,
1545 skb_shinfo(skb)->nr_frags++,
1546 sw_rx_data->data, 0,
1547 cur_size);
1548
1549 skb->truesize += PAGE_SIZE;
1550 skb->data_len += cur_size;
1551 skb->len += cur_size;
1552 pkt_len -= cur_size;
1553 }
2950219d 1554
f86af2df 1555 if (unlikely(pkt_len))
fc48b7a6
YM		 1556 DP_ERR(edev,
1557 "Mapped all BDs of jumbo, but still have %d bytes\n",
1558 pkt_len);
1559 }
2950219d
YM		 1560
1561 skb->protocol = eth_type_trans(skb, edev->ndev);
1562
1563 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1a635e48 1564 fp_cqe->rss_hash, &rxhash_type);
2950219d
YM		 1565
1566 skb_set_hash(skb, rx_hash, rxhash_type);
1567
1568 qede_set_skb_csum(skb, csum_flag);
1569
1570 skb_record_rx_queue(skb, fp->rss_id);
1571
1572 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1573next_rx_only:
2950219d
YM		 1574 rx_pkt++;
1575
1576next_cqe: /* don't consume bd rx buffer */
1577 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1578 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1579 /* CR TPA - revisit how to handle budget in TPA perhaps
1580 * increase on "end"
1581 */
1582 if (rx_pkt == budget)
1583 break;
1584 } /* repeat while sw_comp_cons != hw_comp_cons... */
1585
1586 /* Update producers */
1587 qede_update_rx_prod(edev, rxq);
1588
1589 return rx_pkt;
1590}
1591
1592static int qede_poll(struct napi_struct *napi, int budget)
1593{
2950219d 1594 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
c774169d 1595 napi);
2950219d 1596 struct qede_dev *edev = fp->edev;
c774169d
MC		 1597 int rx_work_done = 0;
1598 u8 tc;
2950219d 1599
c774169d
MC		 1600 for (tc = 0; tc < edev->num_tc; tc++)
1601 if (qede_txq_has_work(&fp->txqs[tc]))
1602 qede_tx_int(edev, &fp->txqs[tc]);
1603
1604 rx_work_done = qede_has_rx_work(fp->rxq) ?
1605 qede_rx_int(fp, budget) : 0;
1606 if (rx_work_done < budget) {
1607 qed_sb_update_sb_idx(fp->sb_info);
1608 /* *_has_*_work() reads the status block,
1609 * thus we need to ensure that status block indices
1610 * have been actually read (qed_sb_update_sb_idx)
1611 * prior to this check (*_has_*_work) so that
1612 * we won't write the "newer" value of the status block
1613 * to HW (if there was a DMA right after
1614 * qede_has_rx_work and if there is no rmb, the memory
1615 * reading (qed_sb_update_sb_idx) may be postponed
1616 * to right before *_ack_sb). In this case there
1617 * will never be another interrupt until there is
1618 * another update of the status block, while there
1619 * is still unhandled work.
1620 */
1621 rmb();
2950219d
YM		 1622
1623 /* Fall out from the NAPI loop if needed */
c774169d
MC		 1624 if (!(qede_has_rx_work(fp->rxq) ||
1625 qede_has_tx_work(fp))) {
1626 napi_complete(napi);
1627
1628 /* Update and reenable interrupts */
1629 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1630 1 /*update*/);
1631 } else {
1632 rx_work_done = budget;
2950219d
YM		 1633 }
1634 }
1635
c774169d 1636 return rx_work_done;
2950219d
YM		 1637}
1638
1639static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1640{
1641 struct qede_fastpath *fp = fp_cookie;
1642
1643 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1644
1645 napi_schedule_irqoff(&fp->napi);
1646 return IRQ_HANDLED;
1647}
1648
1649/* -------------------------------------------------------------------------
1650 * END OF FAST-PATH
1651 * -------------------------------------------------------------------------
1652 */
1653
1654static int qede_open(struct net_device *ndev);
1655static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1656static int qede_set_mac_addr(struct net_device *ndev, void *p);
1657static void qede_set_rx_mode(struct net_device *ndev);
1658static void qede_config_rx_mode(struct net_device *ndev);
1659
1660static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1661 enum qed_filter_xcast_params_type opcode,
1662 unsigned char mac[ETH_ALEN])
1663{
1664 struct qed_filter_params filter_cmd;
1665
1666 memset(&filter_cmd, 0, sizeof(filter_cmd));
1667 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1668 filter_cmd.filter.ucast.type = opcode;
1669 filter_cmd.filter.ucast.mac_valid = 1;
1670 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1671
1672 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1673}
1674
7c1bfcad
SRK		 1675static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1676 enum qed_filter_xcast_params_type opcode,
1677 u16 vid)
1678{
1679 struct qed_filter_params filter_cmd;
1680
1681 memset(&filter_cmd, 0, sizeof(filter_cmd));
1682 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1683 filter_cmd.filter.ucast.type = opcode;
1684 filter_cmd.filter.ucast.vlan_valid = 1;
1685 filter_cmd.filter.ucast.vlan = vid;
1686
1687 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1688}
1689
133fac0e
SK		 1690void qede_fill_by_demand_stats(struct qede_dev *edev)
1691{
1692 struct qed_eth_stats stats;
1693
1694 edev->ops->get_vport_stats(edev->cdev, &stats);
1695 edev->stats.no_buff_discards = stats.no_buff_discards;
1696 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1697 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1698 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1699 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1700 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1701 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1702 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1703 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1704
1705 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1706 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1707 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1708 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1709 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1710 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1711 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1712 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1713 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1714 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1715 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1716 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1717
1718 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1719 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1720 edev->stats.rx_128_to_255_byte_packets =
1721 stats.rx_128_to_255_byte_packets;
1722 edev->stats.rx_256_to_511_byte_packets =
1723 stats.rx_256_to_511_byte_packets;
1724 edev->stats.rx_512_to_1023_byte_packets =
1725 stats.rx_512_to_1023_byte_packets;
1726 edev->stats.rx_1024_to_1518_byte_packets =
1727 stats.rx_1024_to_1518_byte_packets;
1728 edev->stats.rx_1519_to_1522_byte_packets =
1729 stats.rx_1519_to_1522_byte_packets;
1730 edev->stats.rx_1519_to_2047_byte_packets =
1731 stats.rx_1519_to_2047_byte_packets;
1732 edev->stats.rx_2048_to_4095_byte_packets =
1733 stats.rx_2048_to_4095_byte_packets;
1734 edev->stats.rx_4096_to_9216_byte_packets =
1735 stats.rx_4096_to_9216_byte_packets;
1736 edev->stats.rx_9217_to_16383_byte_packets =
1737 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1738 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1739 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1740 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1741 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1742 edev->stats.rx_align_errors = stats.rx_align_errors;
1743 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1744 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1745 edev->stats.rx_jabbers = stats.rx_jabbers;
1746 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1747 edev->stats.rx_fragments = stats.rx_fragments;
1748 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1749 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1750 edev->stats.tx_128_to_255_byte_packets =
1751 stats.tx_128_to_255_byte_packets;
1752 edev->stats.tx_256_to_511_byte_packets =
1753 stats.tx_256_to_511_byte_packets;
1754 edev->stats.tx_512_to_1023_byte_packets =
1755 stats.tx_512_to_1023_byte_packets;
1756 edev->stats.tx_1024_to_1518_byte_packets =
1757 stats.tx_1024_to_1518_byte_packets;
1758 edev->stats.tx_1519_to_2047_byte_packets =
1759 stats.tx_1519_to_2047_byte_packets;
1760 edev->stats.tx_2048_to_4095_byte_packets =
1761 stats.tx_2048_to_4095_byte_packets;
1762 edev->stats.tx_4096_to_9216_byte_packets =
1763 stats.tx_4096_to_9216_byte_packets;
1764 edev->stats.tx_9217_to_16383_byte_packets =
1765 stats.tx_9217_to_16383_byte_packets;
1766 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1767 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1768 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1769 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1770 edev->stats.brb_truncates = stats.brb_truncates;
1771 edev->stats.brb_discards = stats.brb_discards;
1772 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1773}
1774
1a635e48
YM		 1775static
1776struct rtnl_link_stats64 *qede_get_stats64(struct net_device *dev,
1777 struct rtnl_link_stats64 *stats)
133fac0e
SK		 1778{
1779 struct qede_dev *edev = netdev_priv(dev);
1780
1781 qede_fill_by_demand_stats(edev);
1782
1783 stats->rx_packets = edev->stats.rx_ucast_pkts +
1784 edev->stats.rx_mcast_pkts +
1785 edev->stats.rx_bcast_pkts;
1786 stats->tx_packets = edev->stats.tx_ucast_pkts +
1787 edev->stats.tx_mcast_pkts +
1788 edev->stats.tx_bcast_pkts;
1789
1790 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1791 edev->stats.rx_mcast_bytes +
1792 edev->stats.rx_bcast_bytes;
1793
1794 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1795 edev->stats.tx_mcast_bytes +
1796 edev->stats.tx_bcast_bytes;
1797
1798 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1799 stats->multicast = edev->stats.rx_mcast_pkts +
1800 edev->stats.rx_bcast_pkts;
1801
1802 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1803
1804 stats->collisions = edev->stats.tx_total_collisions;
1805 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1806 stats->rx_frame_errors = edev->stats.rx_align_errors;
1807
1808 return stats;
1809}
1810
733def6a 1811#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 1812static int qede_get_vf_config(struct net_device *dev, int vfidx,
1813 struct ifla_vf_info *ivi)
1814{
1815 struct qede_dev *edev = netdev_priv(dev);
1816
1817 if (!edev->ops)
1818 return -EINVAL;
1819
1820 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
1821}
1822
733def6a
YM		 1823static int qede_set_vf_rate(struct net_device *dev, int vfidx,
1824 int min_tx_rate, int max_tx_rate)
1825{
1826 struct qede_dev *edev = netdev_priv(dev);
1827
be7b6d64 1828 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 1829 max_tx_rate);
1830}
1831
6ddc7608
YM		 1832static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
1833{
1834 struct qede_dev *edev = netdev_priv(dev);
1835
1836 if (!edev->ops)
1837 return -EINVAL;
1838
1839 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
1840}
1841
733def6a
YM		 1842static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
1843 int link_state)
1844{
1845 struct qede_dev *edev = netdev_priv(dev);
1846
1847 if (!edev->ops)
1848 return -EINVAL;
1849
1850 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
1851}
1852#endif
1853
7c1bfcad
SRK		 1854static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1855{
1856 struct qed_update_vport_params params;
1857 int rc;
1858
1859 /* Proceed only if action actually needs to be performed */
1860 if (edev->accept_any_vlan == action)
1861 return;
1862
1863 memset(&params, 0, sizeof(params));
1864
1865 params.vport_id = 0;
1866 params.accept_any_vlan = action;
1867 params.update_accept_any_vlan_flg = 1;
1868
1869 rc = edev->ops->vport_update(edev->cdev, &params);
1870 if (rc) {
1871 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1872 action ? "enable" : "disable");
1873 } else {
1874 DP_INFO(edev, "%s accept-any-vlan\n",
1875 action ? "enabled" : "disabled");
1876 edev->accept_any_vlan = action;
1877 }
1878}
1879
1880static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1881{
1882 struct qede_dev *edev = netdev_priv(dev);
1883 struct qede_vlan *vlan, *tmp;
1884 int rc;
1885
1886 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1887
1888 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1889 if (!vlan) {
1890 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1891 return -ENOMEM;
1892 }
1893 INIT_LIST_HEAD(&vlan->list);
1894 vlan->vid = vid;
1895 vlan->configured = false;
1896
1897 /* Verify vlan isn't already configured */
1898 list_for_each_entry(tmp, &edev->vlan_list, list) {
1899 if (tmp->vid == vlan->vid) {
1900 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1901 "vlan already configured\n");
1902 kfree(vlan);
1903 return -EEXIST;
1904 }
1905 }
1906
1907 /* If interface is down, cache this VLAN ID and return */
1908 if (edev->state != QEDE_STATE_OPEN) {
1909 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1910 "Interface is down, VLAN %d will be configured when interface is up\n",
1911 vid);
1912 if (vid != 0)
1913 edev->non_configured_vlans++;
1914 list_add(&vlan->list, &edev->vlan_list);
1915
1916 return 0;
1917 }
1918
1919 /* Check for the filter limit.
1920 * Note - vlan0 has a reserved filter and can be added without
1921 * worrying about quota
1922 */
1923 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1924 (vlan->vid == 0)) {
1925 rc = qede_set_ucast_rx_vlan(edev,
1926 QED_FILTER_XCAST_TYPE_ADD,
1927 vlan->vid);
1928 if (rc) {
1929 DP_ERR(edev, "Failed to configure VLAN %d\n",
1930 vlan->vid);
1931 kfree(vlan);
1932 return -EINVAL;
1933 }
1934 vlan->configured = true;
1935
1936 /* vlan0 filter isn't consuming out of our quota */
1937 if (vlan->vid != 0)
1938 edev->configured_vlans++;
1939 } else {
1940 /* Out of quota; Activate accept-any-VLAN mode */
1941 if (!edev->non_configured_vlans)
1942 qede_config_accept_any_vlan(edev, true);
1943
1944 edev->non_configured_vlans++;
1945 }
1946
1947 list_add(&vlan->list, &edev->vlan_list);
1948
1949 return 0;
1950}
1951
1952static void qede_del_vlan_from_list(struct qede_dev *edev,
1953 struct qede_vlan *vlan)
1954{
1955 /* vlan0 filter isn't consuming out of our quota */
1956 if (vlan->vid != 0) {
1957 if (vlan->configured)
1958 edev->configured_vlans--;
1959 else
1960 edev->non_configured_vlans--;
1961 }
1962
1963 list_del(&vlan->list);
1964 kfree(vlan);
1965}
1966
1967static int qede_configure_vlan_filters(struct qede_dev *edev)
1968{
1969 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1970 struct qed_dev_eth_info *dev_info;
1971 struct qede_vlan *vlan = NULL;
1972
1973 if (list_empty(&edev->vlan_list))
1974 return 0;
1975
1976 dev_info = &edev->dev_info;
1977
1978 /* Configure non-configured vlans */
1979 list_for_each_entry(vlan, &edev->vlan_list, list) {
1980 if (vlan->configured)
1981 continue;
1982
1983 /* We have used all our credits, now enable accept_any_vlan */
1984 if ((vlan->vid != 0) &&
1985 (edev->configured_vlans == dev_info->num_vlan_filters)) {
1986 accept_any_vlan = 1;
1987 continue;
1988 }
1989
1990 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
1991
1992 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
1993 vlan->vid);
1994 if (rc) {
1995 DP_ERR(edev, "Failed to configure VLAN %u\n",
1996 vlan->vid);
1997 real_rc = rc;
1998 continue;
1999 }
2000
2001 vlan->configured = true;
2002 /* vlan0 filter doesn't consume our VLAN filter's quota */
2003 if (vlan->vid != 0) {
2004 edev->non_configured_vlans--;
2005 edev->configured_vlans++;
2006 }
2007 }
2008
2009 /* enable accept_any_vlan mode if we have more VLANs than credits,
2010 * or remove accept_any_vlan mode if we've actually removed
2011 * a non-configured vlan, and all remaining vlans are truly configured.
2012 */
2013
2014 if (accept_any_vlan)
2015 qede_config_accept_any_vlan(edev, true);
2016 else if (!edev->non_configured_vlans)
2017 qede_config_accept_any_vlan(edev, false);
2018
2019 return real_rc;
2020}
2021
2022static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
2023{
2024 struct qede_dev *edev = netdev_priv(dev);
2025 struct qede_vlan *vlan = NULL;
2026 int rc;
2027
2028 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
2029
2030 /* Find whether entry exists */
2031 list_for_each_entry(vlan, &edev->vlan_list, list)
2032 if (vlan->vid == vid)
2033 break;
2034
2035 if (!vlan || (vlan->vid != vid)) {
2036 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
2037 "Vlan isn't configured\n");
2038 return 0;
2039 }
2040
2041 if (edev->state != QEDE_STATE_OPEN) {
2042 /* As interface is already down, we don't have a VPORT
2043 * instance to remove vlan filter. So just update vlan list
2044 */
2045 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2046 "Interface is down, removing VLAN from list only\n");
2047 qede_del_vlan_from_list(edev, vlan);
2048 return 0;
2049 }
2050
2051 /* Remove vlan */
c524e2f5
YM		 2052 if (vlan->configured) {
2053 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL,
2054 vid);
2055 if (rc) {
2056 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
2057 return -EINVAL;
2058 }
7c1bfcad
SRK		 2059 }
2060
2061 qede_del_vlan_from_list(edev, vlan);
2062
2063 /* We have removed a VLAN - try to see if we can
2064 * configure non-configured VLAN from the list.
2065 */
2066 rc = qede_configure_vlan_filters(edev);
2067
2068 return rc;
2069}
2070
2071static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
2072{
2073 struct qede_vlan *vlan = NULL;
2074
2075 if (list_empty(&edev->vlan_list))
2076 return;
2077
2078 list_for_each_entry(vlan, &edev->vlan_list, list) {
2079 if (!vlan->configured)
2080 continue;
2081
2082 vlan->configured = false;
2083
2084 /* vlan0 filter isn't consuming out of our quota */
2085 if (vlan->vid != 0) {
2086 edev->non_configured_vlans++;
2087 edev->configured_vlans--;
2088 }
2089
2090 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1a635e48 2091 "marked vlan %d as non-configured\n", vlan->vid);
7c1bfcad
SRK		 2092 }
2093
2094 edev->accept_any_vlan = false;
2095}
2096
ce2b885c
YM		 2097int qede_set_features(struct net_device *dev, netdev_features_t features)
2098{
2099 struct qede_dev *edev = netdev_priv(dev);
2100 netdev_features_t changes = features ^ dev->features;
2101 bool need_reload = false;
2102
2103 /* No action needed if hardware GRO is disabled during driver load */
2104 if (changes & NETIF_F_GRO) {
2105 if (dev->features & NETIF_F_GRO)
2106 need_reload = !edev->gro_disable;
2107 else
2108 need_reload = edev->gro_disable;
2109 }
2110
2111 if (need_reload && netif_running(edev->ndev)) {
2112 dev->features = features;
2113 qede_reload(edev, NULL, NULL);
2114 return 1;
2115 }
2116
2117 return 0;
2118}
2119
f9f082a9
AD		 2120static void qede_udp_tunnel_add(struct net_device *dev,
2121 struct udp_tunnel_info *ti)
b18e170c
MC		 2122{
2123 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2124 u16 t_port = ntohs(ti->port);
b18e170c 2125
f9f082a9
AD		 2126 switch (ti->type) {
2127 case UDP_TUNNEL_TYPE_VXLAN:
2128 if (edev->vxlan_dst_port)
2129 return;
b18e170c 2130
f9f082a9 2131 edev->vxlan_dst_port = t_port;
b18e170c 2132
f9f082a9
AD		 2133 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d",
2134 t_port);
b18e170c 2135
f9f082a9
AD		 2136 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2137 break;
2138 case UDP_TUNNEL_TYPE_GENEVE:
2139 if (edev->geneve_dst_port)
2140 return;
b18e170c 2141
f9f082a9 2142 edev->geneve_dst_port = t_port;
b18e170c 2143
f9f082a9
AD		 2144 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d",
2145 t_port);
2146 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2147 break;
2148 default:
b18e170c 2149 return;
f9f082a9 2150 }
b18e170c 2151
b18e170c
MC		 2152 schedule_delayed_work(&edev->sp_task, 0);
2153}
b18e170c 2154
f9f082a9
AD		 2155static void qede_udp_tunnel_del(struct net_device *dev,
2156 struct udp_tunnel_info *ti)
9a109dd0
MC		 2157{
2158 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2159 u16 t_port = ntohs(ti->port);
9a109dd0 2160
f9f082a9
AD		 2161 switch (ti->type) {
2162 case UDP_TUNNEL_TYPE_VXLAN:
2163 if (t_port != edev->vxlan_dst_port)
2164 return;
9a109dd0 2165
f9f082a9 2166 edev->vxlan_dst_port = 0;
9a109dd0 2167
f9f082a9
AD		 2168 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d",
2169 t_port);
9a109dd0 2170
f9f082a9
AD		 2171 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2172 break;
2173 case UDP_TUNNEL_TYPE_GENEVE:
2174 if (t_port != edev->geneve_dst_port)
2175 return;
9a109dd0 2176
f9f082a9 2177 edev->geneve_dst_port = 0;
9a109dd0 2178
f9f082a9
AD		 2179 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d",
2180 t_port);
2181 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2182 break;
2183 default:
2184 return;
2185 }
9a109dd0 2186
9a109dd0
MC		 2187 schedule_delayed_work(&edev->sp_task, 0);
2188}
9a109dd0 2189
2950219d
YM		 2190static const struct net_device_ops qede_netdev_ops = {
2191 .ndo_open = qede_open,
2192 .ndo_stop = qede_close,
2193 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2194 .ndo_set_rx_mode = qede_set_rx_mode,
2195 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2196 .ndo_validate_addr = eth_validate_addr,
133fac0e 2197 .ndo_change_mtu = qede_change_mtu,
08feecd7 2198#ifdef CONFIG_QED_SRIOV
eff16960 2199 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7
YM		 2200 .ndo_set_vf_vlan = qede_set_vf_vlan,
2201#endif
7c1bfcad
SRK		 2202 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2203 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
ce2b885c 2204 .ndo_set_features = qede_set_features,
133fac0e 2205 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 2206#ifdef CONFIG_QED_SRIOV
2207 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 2208 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 2209 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 2210 .ndo_set_vf_rate = qede_set_vf_rate,
2211#endif
f9f082a9
AD		 2212 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
2213 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
2950219d
YM		 2214};
2215
e712d52b
YM		 2216/* -------------------------------------------------------------------------
2217 * START OF PROBE / REMOVE
2218 * -------------------------------------------------------------------------
2219 */
2220
2221static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2222 struct pci_dev *pdev,
2223 struct qed_dev_eth_info *info,
1a635e48 2224 u32 dp_module, u8 dp_level)
e712d52b
YM		 2225{
2226 struct net_device *ndev;
2227 struct qede_dev *edev;
2228
2229 ndev = alloc_etherdev_mqs(sizeof(*edev),
1a635e48 2230 info->num_queues, info->num_queues);
e712d52b
YM		 2231 if (!ndev) {
2232 pr_err("etherdev allocation failed\n");
2233 return NULL;
2234 }
2235
2236 edev = netdev_priv(ndev);
2237 edev->ndev = ndev;
2238 edev->cdev = cdev;
2239 edev->pdev = pdev;
2240 edev->dp_module = dp_module;
2241 edev->dp_level = dp_level;
2242 edev->ops = qed_ops;
2950219d
YM		 2243 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2244 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2245
e712d52b
YM		 2246 SET_NETDEV_DEV(ndev, &pdev->dev);
2247
133fac0e 2248 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2249 memcpy(&edev->dev_info, info, sizeof(*info));
2250
2251 edev->num_tc = edev->dev_info.num_tc;
2252
7c1bfcad
SRK		 2253 INIT_LIST_HEAD(&edev->vlan_list);
2254
e712d52b
YM		 2255 return edev;
2256}
2257
2258static void qede_init_ndev(struct qede_dev *edev)
2259{
2260 struct net_device *ndev = edev->ndev;
2261 struct pci_dev *pdev = edev->pdev;
2262 u32 hw_features;
2263
2264 pci_set_drvdata(pdev, ndev);
2265
2266 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2267 ndev->base_addr = ndev->mem_start;
2268 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2269 ndev->irq = edev->dev_info.common.pci_irq;
2270
2271 ndev->watchdog_timeo = TX_TIMEOUT;
2272
2950219d
YM		 2273 ndev->netdev_ops = &qede_netdev_ops;
2274
133fac0e
SK		 2275 qede_set_ethtool_ops(ndev);
2276
e712d52b
YM		 2277 /* user-changeble features */
2278 hw_features = NETIF_F_GRO | NETIF_F_SG |
2279 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2280 NETIF_F_TSO | NETIF_F_TSO6;
2281
14db81de
MC		 2282 /* Encap features*/
2283 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2284 NETIF_F_TSO_ECN;
2285 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2286 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2287 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2288 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2289
e712d52b
YM		 2290 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2291 NETIF_F_HIGHDMA;
2292 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2293 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2294 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2295
2296 ndev->hw_features = hw_features;
2297
2298 /* Set network device HW mac */
2299 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2300}
2301
2302/* This function converts from 32b param to two params of level and module
2303 * Input 32b decoding:
2304 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2305 * 'happy' flow, e.g. memory allocation failed.
2306 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2307 * and provide important parameters.
2308 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2309 * module. VERBOSE prints are for tracking the specific flow in low level.
2310 *
2311 * Notice that the level should be that of the lowest required logs.
2312 */
133fac0e 2313void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2314{
2315 *p_dp_level = QED_LEVEL_NOTICE;
2316 *p_dp_module = 0;
2317
2318 if (debug & QED_LOG_VERBOSE_MASK) {
2319 *p_dp_level = QED_LEVEL_VERBOSE;
2320 *p_dp_module = (debug & 0x3FFFFFFF);
2321 } else if (debug & QED_LOG_INFO_MASK) {
2322 *p_dp_level = QED_LEVEL_INFO;
2323 } else if (debug & QED_LOG_NOTICE_MASK) {
2324 *p_dp_level = QED_LEVEL_NOTICE;
2325 }
2326}
2327
2950219d
YM		 2328static void qede_free_fp_array(struct qede_dev *edev)
2329{
2330 if (edev->fp_array) {
2331 struct qede_fastpath *fp;
2332 int i;
2333
2334 for_each_rss(i) {
2335 fp = &edev->fp_array[i];
2336
2337 kfree(fp->sb_info);
2338 kfree(fp->rxq);
2339 kfree(fp->txqs);
2340 }
2341 kfree(edev->fp_array);
2342 }
2343 edev->num_rss = 0;
2344}
2345
2346static int qede_alloc_fp_array(struct qede_dev *edev)
2347{
2348 struct qede_fastpath *fp;
2349 int i;
2350
2351 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2352 sizeof(*edev->fp_array), GFP_KERNEL);
2353 if (!edev->fp_array) {
2354 DP_NOTICE(edev, "fp array allocation failed\n");
2355 goto err;
2356 }
2357
2358 for_each_rss(i) {
2359 fp = &edev->fp_array[i];
2360
2361 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2362 if (!fp->sb_info) {
2363 DP_NOTICE(edev, "sb info struct allocation failed\n");
2364 goto err;
2365 }
2366
2367 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2368 if (!fp->rxq) {
2369 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2370 goto err;
2371 }
2372
2373 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2374 if (!fp->txqs) {
2375 DP_NOTICE(edev, "TXQ array allocation failed\n");
2376 goto err;
2377 }
2378 }
2379
2380 return 0;
2381err:
2382 qede_free_fp_array(edev);
2383 return -ENOMEM;
2384}
2385
0d8e0aa0
SK		 2386static void qede_sp_task(struct work_struct *work)
2387{
2388 struct qede_dev *edev = container_of(work, struct qede_dev,
2389 sp_task.work);
b18e170c
MC		 2390 struct qed_dev *cdev = edev->cdev;
2391
0d8e0aa0
SK		 2392 mutex_lock(&edev->qede_lock);
2393
2394 if (edev->state == QEDE_STATE_OPEN) {
2395 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2396 qede_config_rx_mode(edev->ndev);
2397 }
2398
b18e170c
MC		 2399 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2400 struct qed_tunn_params tunn_params;
2401
2402 memset(&tunn_params, 0, sizeof(tunn_params));
2403 tunn_params.update_vxlan_port = 1;
2404 tunn_params.vxlan_port = edev->vxlan_dst_port;
2405 qed_ops->tunn_config(cdev, &tunn_params);
2406 }
2407
9a109dd0
MC		 2408 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2409 struct qed_tunn_params tunn_params;
2410
2411 memset(&tunn_params, 0, sizeof(tunn_params));
2412 tunn_params.update_geneve_port = 1;
2413 tunn_params.geneve_port = edev->geneve_dst_port;
2414 qed_ops->tunn_config(cdev, &tunn_params);
2415 }
2416
0d8e0aa0
SK		 2417 mutex_unlock(&edev->qede_lock);
2418}
2419
e712d52b
YM		 2420static void qede_update_pf_params(struct qed_dev *cdev)
2421{
2422 struct qed_pf_params pf_params;
2423
8e0ddc04 2424 /* 64 rx + 64 tx */
e712d52b 2425 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2426 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2427 qed_ops->common->update_pf_params(cdev, &pf_params);
2428}
2429
2430enum qede_probe_mode {
2431 QEDE_PROBE_NORMAL,
2432};
2433
2434static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2435 bool is_vf, enum qede_probe_mode mode)
e712d52b 2436{
1408cc1f 2437 struct qed_probe_params probe_params;
1a635e48 2438 struct qed_slowpath_params sp_params;
e712d52b
YM		 2439 struct qed_dev_eth_info dev_info;
2440 struct qede_dev *edev;
2441 struct qed_dev *cdev;
2442 int rc;
2443
2444 if (unlikely(dp_level & QED_LEVEL_INFO))
2445 pr_notice("Starting qede probe\n");
2446
1408cc1f
YM		 2447 memset(&probe_params, 0, sizeof(probe_params));
2448 probe_params.protocol = QED_PROTOCOL_ETH;
2449 probe_params.dp_module = dp_module;
2450 probe_params.dp_level = dp_level;
2451 probe_params.is_vf = is_vf;
2452 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2453 if (!cdev) {
2454 rc = -ENODEV;
2455 goto err0;
2456 }
2457
2458 qede_update_pf_params(cdev);
2459
2460 /* Start the Slowpath-process */
1a635e48
YM		 2461 memset(&sp_params, 0, sizeof(sp_params));
2462 sp_params.int_mode = QED_INT_MODE_MSIX;
2463 sp_params.drv_major = QEDE_MAJOR_VERSION;
2464 sp_params.drv_minor = QEDE_MINOR_VERSION;
2465 sp_params.drv_rev = QEDE_REVISION_VERSION;
2466 sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
2467 strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2468 rc = qed_ops->common->slowpath_start(cdev, &sp_params);
e712d52b
YM		 2469 if (rc) {
2470 pr_notice("Cannot start slowpath\n");
2471 goto err1;
2472 }
2473
2474 /* Learn information crucial for qede to progress */
2475 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2476 if (rc)
2477 goto err2;
2478
2479 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2480 dp_level);
2481 if (!edev) {
2482 rc = -ENOMEM;
2483 goto err2;
2484 }
2485
fefb0202
YM		 2486 if (is_vf)
2487 edev->flags |= QEDE_FLAG_IS_VF;
2488
e712d52b
YM		 2489 qede_init_ndev(edev);
2490
2950219d
YM		 2491 rc = register_netdev(edev->ndev);
2492 if (rc) {
2493 DP_NOTICE(edev, "Cannot register net-device\n");
2494 goto err3;
2495 }
2496
e712d52b
YM		 2497 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2498
a2ec6172
SK		 2499 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2500
489e45ae
SRK		 2501#ifdef CONFIG_DCB
2502 qede_set_dcbnl_ops(edev->ndev);
2503#endif
2504
0d8e0aa0
SK		 2505 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2506 mutex_init(&edev->qede_lock);
3d789994 2507 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
0d8e0aa0 2508
e712d52b
YM		 2509 DP_INFO(edev, "Ending successfully qede probe\n");
2510
2511 return 0;
2512
2950219d
YM		 2513err3:
2514 free_netdev(edev->ndev);
e712d52b
YM		 2515err2:
2516 qed_ops->common->slowpath_stop(cdev);
2517err1:
2518 qed_ops->common->remove(cdev);
2519err0:
2520 return rc;
2521}
2522
2523static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2524{
fefb0202 2525 bool is_vf = false;
e712d52b
YM		 2526 u32 dp_module = 0;
2527 u8 dp_level = 0;
2528
fefb0202
YM		 2529 switch ((enum qede_pci_private)id->driver_data) {
2530 case QEDE_PRIVATE_VF:
2531 if (debug & QED_LOG_VERBOSE_MASK)
2532 dev_err(&pdev->dev, "Probing a VF\n");
2533 is_vf = true;
2534 break;
2535 default:
2536 if (debug & QED_LOG_VERBOSE_MASK)
2537 dev_err(&pdev->dev, "Probing a PF\n");
2538 }
2539
e712d52b
YM		 2540 qede_config_debug(debug, &dp_module, &dp_level);
2541
fefb0202 2542 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2543 QEDE_PROBE_NORMAL);
2544}
2545
2546enum qede_remove_mode {
2547 QEDE_REMOVE_NORMAL,
2548};
2549
2550static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2551{
2552 struct net_device *ndev = pci_get_drvdata(pdev);
2553 struct qede_dev *edev = netdev_priv(ndev);
2554 struct qed_dev *cdev = edev->cdev;
2555
2556 DP_INFO(edev, "Starting qede_remove\n");
2557
0d8e0aa0 2558 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2559 unregister_netdev(ndev);
2560
e712d52b
YM		 2561 edev->ops->common->set_power_state(cdev, PCI_D0);
2562
2563 pci_set_drvdata(pdev, NULL);
2564
2565 free_netdev(ndev);
2566
2567 /* Use global ops since we've freed edev */
2568 qed_ops->common->slowpath_stop(cdev);
2569 qed_ops->common->remove(cdev);
2570
2571 pr_notice("Ending successfully qede_remove\n");
2572}
2573
2574static void qede_remove(struct pci_dev *pdev)
2575{
2576 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2577}
2950219d
YM		 2578
2579/* -------------------------------------------------------------------------
2580 * START OF LOAD / UNLOAD
2581 * -------------------------------------------------------------------------
2582 */
2583
2584static int qede_set_num_queues(struct qede_dev *edev)
2585{
2586 int rc;
2587 u16 rss_num;
2588
2589 /* Setup queues according to possible resources*/
8edf049d
SK		 2590 if (edev->req_rss)
2591 rss_num = edev->req_rss;
2592 else
2593 rss_num = netif_get_num_default_rss_queues() *
2594 edev->dev_info.common.num_hwfns;
2950219d
YM		 2595
2596 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2597
2598 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2599 if (rc > 0) {
2600 /* Managed to request interrupts for our queues */
2601 edev->num_rss = rc;
2602 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2603 QEDE_RSS_CNT(edev), rss_num);
2604 rc = 0;
2605 }
2606 return rc;
2607}
2608
2609static void qede_free_mem_sb(struct qede_dev *edev,
2610 struct qed_sb_info *sb_info)
2611{
2612 if (sb_info->sb_virt)
2613 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2614 (void *)sb_info->sb_virt, sb_info->sb_phys);
2615}
2616
2617/* This function allocates fast-path status block memory */
2618static int qede_alloc_mem_sb(struct qede_dev *edev,
1a635e48 2619 struct qed_sb_info *sb_info, u16 sb_id)
2950219d
YM		 2620{
2621 struct status_block *sb_virt;
2622 dma_addr_t sb_phys;
2623 int rc;
2624
2625 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1a635e48 2626 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
2950219d
YM		 2627 if (!sb_virt) {
2628 DP_ERR(edev, "Status block allocation failed\n");
2629 return -ENOMEM;
2630 }
2631
2632 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2633 sb_virt, sb_phys, sb_id,
2634 QED_SB_TYPE_L2_QUEUE);
2635 if (rc) {
2636 DP_ERR(edev, "Status block initialization failed\n");
2637 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2638 sb_virt, sb_phys);
2639 return rc;
2640 }
2641
2642 return 0;
2643}
2644
2645static void qede_free_rx_buffers(struct qede_dev *edev,
2646 struct qede_rx_queue *rxq)
2647{
2648 u16 i;
2649
2650 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2651 struct sw_rx_data *rx_buf;
fc48b7a6 2652 struct page *data;
2950219d
YM		 2653
2654 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2655 data = rx_buf->data;
2656
fc48b7a6 2657 dma_unmap_page(&edev->pdev->dev,
1a635e48 2658 rx_buf->mapping, PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2659
2660 rx_buf->data = NULL;
fc48b7a6 2661 __free_page(data);
2950219d
YM		 2662 }
2663}
2664
1a635e48
YM		 2665static void qede_free_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
2666{
55482edc
MC		 2667 int i;
2668
2669 if (edev->gro_disable)
2670 return;
2671
2672 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2673 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2674 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2675
f86af2df 2676 if (replace_buf->data) {
55482edc 2677 dma_unmap_page(&edev->pdev->dev,
09ec8e7f 2678 replace_buf->mapping,
55482edc
MC		 2679 PAGE_SIZE, DMA_FROM_DEVICE);
2680 __free_page(replace_buf->data);
2681 }
2682 }
2683}
2684
1a635e48 2685static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2686{
55482edc
MC		 2687 qede_free_sge_mem(edev, rxq);
2688
2950219d
YM		 2689 /* Free rx buffers */
2690 qede_free_rx_buffers(edev, rxq);
2691
2692 /* Free the parallel SW ring */
2693 kfree(rxq->sw_rx_ring);
2694
2695 /* Free the real RQ ring used by FW */
2696 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2697 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2698}
2699
2700static int qede_alloc_rx_buffer(struct qede_dev *edev,
2701 struct qede_rx_queue *rxq)
2702{
2703 struct sw_rx_data *sw_rx_data;
2704 struct eth_rx_bd *rx_bd;
2705 dma_addr_t mapping;
fc48b7a6 2706 struct page *data;
2950219d 2707
fc48b7a6 2708 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2709 if (unlikely(!data)) {
fc48b7a6 2710 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2711 return -ENOMEM;
2712 }
2713
fc48b7a6
YM		 2714 /* Map the entire page as it would be used
2715 * for multiple RX buffer segment size mapping.
2716 */
2717 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2718 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2719 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2720 __free_page(data);
2950219d
YM		 2721 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2722 return -ENOMEM;
2723 }
2724
2725 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2726 sw_rx_data->page_offset = 0;
2950219d 2727 sw_rx_data->data = data;
fc48b7a6 2728 sw_rx_data->mapping = mapping;
2950219d
YM		 2729
2730 /* Advance PROD and get BD pointer */
2731 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2732 WARN_ON(!rx_bd);
2733 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2734 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2735
2736 rxq->sw_rx_prod++;
2737
2738 return 0;
2739}
2740
1a635e48 2741static int qede_alloc_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
55482edc
MC		 2742{
2743 dma_addr_t mapping;
2744 int i;
2745
2746 if (edev->gro_disable)
2747 return 0;
2748
2749 if (edev->ndev->mtu > PAGE_SIZE) {
2750 edev->gro_disable = 1;
2751 return 0;
2752 }
2753
2754 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2755 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2756 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2757
2758 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2759 if (unlikely(!replace_buf->data)) {
2760 DP_NOTICE(edev,
2761 "Failed to allocate TPA skb pool [replacement buffer]\n");
2762 goto err;
2763 }
2764
2765 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2766 rxq->rx_buf_size, DMA_FROM_DEVICE);
2767 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2768 DP_NOTICE(edev,
2769 "Failed to map TPA replacement buffer\n");
2770 goto err;
2771 }
2772
09ec8e7f 2773 replace_buf->mapping = mapping;
55482edc
MC		 2774 tpa_info->replace_buf.page_offset = 0;
2775
2776 tpa_info->replace_buf_mapping = mapping;
2777 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2778 }
2779
2780 return 0;
2781err:
2782 qede_free_sge_mem(edev, rxq);
2783 edev->gro_disable = 1;
2784 return -ENOMEM;
2785}
2786
2950219d 2787/* This function allocates all memory needed per Rx queue */
1a635e48 2788static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2789{
f86af2df 2790 int i, rc, size;
2950219d
YM		 2791
2792 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2793
1a635e48
YM		 2794 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
2795
fc48b7a6
YM		 2796 if (rxq->rx_buf_size > PAGE_SIZE)
2797 rxq->rx_buf_size = PAGE_SIZE;
2798
2799 /* Segment size to spilt a page in multiple equal parts */
2800 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2801
2802 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2803 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2804 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2805 if (!rxq->sw_rx_ring) {
2806 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2807 rc = -ENOMEM;
2950219d
YM		 2808 goto err;
2809 }
2810
2811 /* Allocate FW Rx ring */
2812 rc = edev->ops->common->chain_alloc(edev->cdev,
2813 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2814 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 2815 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2816 RX_RING_SIZE,
2950219d
YM		 2817 sizeof(struct eth_rx_bd),
2818 &rxq->rx_bd_ring);
2819
2820 if (rc)
2821 goto err;
2822
2823 /* Allocate FW completion ring */
2824 rc = edev->ops->common->chain_alloc(edev->cdev,
2825 QED_CHAIN_USE_TO_CONSUME,
2826 QED_CHAIN_MODE_PBL,
a91eb52a 2827 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2828 RX_RING_SIZE,
2950219d
YM		 2829 sizeof(union eth_rx_cqe),
2830 &rxq->rx_comp_ring);
2831 if (rc)
2832 goto err;
2833
2834 /* Allocate buffers for the Rx ring */
2835 for (i = 0; i < rxq->num_rx_buffers; i++) {
2836 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2837 if (rc) {
2838 DP_ERR(edev,
2839 "Rx buffers allocation failed at index %d\n", i);
2840 goto err;
2841 }
2950219d
YM		 2842 }
2843
f86af2df 2844 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2845err:
f86af2df 2846 return rc;
2950219d
YM		 2847}
2848
1a635e48 2849static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 2850{
2851 /* Free the parallel SW ring */
2852 kfree(txq->sw_tx_ring);
2853
2854 /* Free the real RQ ring used by FW */
2855 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2856}
2857
2858/* This function allocates all memory needed per Tx queue */
1a635e48 2859static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 2860{
2861 int size, rc;
2862 union eth_tx_bd_types *p_virt;
2863
2864 txq->num_tx_buffers = edev->q_num_tx_buffers;
2865
2866 /* Allocate the parallel driver ring for Tx buffers */
2867 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2868 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2869 if (!txq->sw_tx_ring) {
2870 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2871 goto err;
2872 }
2873
2874 rc = edev->ops->common->chain_alloc(edev->cdev,
2875 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2876 QED_CHAIN_MODE_PBL,
a91eb52a 2877 QED_CHAIN_CNT_TYPE_U16,
2950219d 2878 NUM_TX_BDS_MAX,
a91eb52a 2879 sizeof(*p_virt), &txq->tx_pbl);
2950219d
YM		 2880 if (rc)
2881 goto err;
2882
2883 return 0;
2884
2885err:
2886 qede_free_mem_txq(edev, txq);
2887 return -ENOMEM;
2888}
2889
2890/* This function frees all memory of a single fp */
1a635e48 2891static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d
YM		 2892{
2893 int tc;
2894
2895 qede_free_mem_sb(edev, fp->sb_info);
2896
2897 qede_free_mem_rxq(edev, fp->rxq);
2898
2899 for (tc = 0; tc < edev->num_tc; tc++)
2900 qede_free_mem_txq(edev, &fp->txqs[tc]);
2901}
2902
2903/* This function allocates all memory needed for a single fp (i.e. an entity
2904 * which contains status block, one rx queue and multiple per-TC tx queues.
2905 */
1a635e48 2906static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d
YM		 2907{
2908 int rc, tc;
2909
2910 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2911 if (rc)
2912 goto err;
2913
2914 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2915 if (rc)
2916 goto err;
2917
2918 for (tc = 0; tc < edev->num_tc; tc++) {
2919 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2920 if (rc)
2921 goto err;
2922 }
2923
2924 return 0;
2950219d 2925err:
f86af2df 2926 return rc;
2950219d
YM		 2927}
2928
2929static void qede_free_mem_load(struct qede_dev *edev)
2930{
2931 int i;
2932
2933 for_each_rss(i) {
2934 struct qede_fastpath *fp = &edev->fp_array[i];
2935
2936 qede_free_mem_fp(edev, fp);
2937 }
2938}
2939
2940/* This function allocates all qede memory at NIC load. */
2941static int qede_alloc_mem_load(struct qede_dev *edev)
2942{
2943 int rc = 0, rss_id;
2944
2945 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2946 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2947
2948 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2949 if (rc) {
2950219d 2950 DP_ERR(edev,
f86af2df
MC		 2951 "Failed to allocate memory for fastpath - rss id = %d\n",
2952 rss_id);
2953 qede_free_mem_load(edev);
2954 return rc;
2950219d 2955 }
2950219d
YM		 2956 }
2957
2958 return 0;
2959}
2960
2961/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2962static void qede_init_fp(struct qede_dev *edev)
2963{
2964 int rss_id, txq_index, tc;
2965 struct qede_fastpath *fp;
2966
2967 for_each_rss(rss_id) {
2968 fp = &edev->fp_array[rss_id];
2969
2970 fp->edev = edev;
2971 fp->rss_id = rss_id;
2972
2973 memset((void *)&fp->napi, 0, sizeof(fp->napi));
2974
2975 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
2976
2977 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
2978 fp->rxq->rxq_id = rss_id;
2979
2980 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
2981 for (tc = 0; tc < edev->num_tc; tc++) {
2982 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
2983 fp->txqs[tc].index = txq_index;
2984 }
2985
2986 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
2987 edev->ndev->name, rss_id);
2988 }
55482edc
MC		 2989
2990 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 2991}
2992
2993static int qede_set_real_num_queues(struct qede_dev *edev)
2994{
2995 int rc = 0;
2996
2997 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
2998 if (rc) {
2999 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
3000 return rc;
3001 }
3002 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
3003 if (rc) {
3004 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
3005 return rc;
3006 }
3007
3008 return 0;
3009}
3010
3011static void qede_napi_disable_remove(struct qede_dev *edev)
3012{
3013 int i;
3014
3015 for_each_rss(i) {
3016 napi_disable(&edev->fp_array[i].napi);
3017
3018 netif_napi_del(&edev->fp_array[i].napi);
3019 }
3020}
3021
3022static void qede_napi_add_enable(struct qede_dev *edev)
3023{
3024 int i;
3025
3026 /* Add NAPI objects */
3027 for_each_rss(i) {
3028 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
3029 qede_poll, NAPI_POLL_WEIGHT);
3030 napi_enable(&edev->fp_array[i].napi);
3031 }
3032}
3033
3034static void qede_sync_free_irqs(struct qede_dev *edev)
3035{
3036 int i;
3037
3038 for (i = 0; i < edev->int_info.used_cnt; i++) {
3039 if (edev->int_info.msix_cnt) {
3040 synchronize_irq(edev->int_info.msix[i].vector);
3041 free_irq(edev->int_info.msix[i].vector,
3042 &edev->fp_array[i]);
3043 } else {
3044 edev->ops->common->simd_handler_clean(edev->cdev, i);
3045 }
3046 }
3047
3048 edev->int_info.used_cnt = 0;
3049}
3050
3051static int qede_req_msix_irqs(struct qede_dev *edev)
3052{
3053 int i, rc;
3054
3055 /* Sanitize number of interrupts == number of prepared RSS queues */
3056 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
3057 DP_ERR(edev,
3058 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
3059 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
3060 return -EINVAL;
3061 }
3062
3063 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
3064 rc = request_irq(edev->int_info.msix[i].vector,
3065 qede_msix_fp_int, 0, edev->fp_array[i].name,
3066 &edev->fp_array[i]);
3067 if (rc) {
3068 DP_ERR(edev, "Request fp %d irq failed\n", i);
3069 qede_sync_free_irqs(edev);
3070 return rc;
3071 }
3072 DP_VERBOSE(edev, NETIF_MSG_INTR,
3073 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
3074 edev->fp_array[i].name, i,
3075 &edev->fp_array[i]);
3076 edev->int_info.used_cnt++;
3077 }
3078
3079 return 0;
3080}
3081
3082static void qede_simd_fp_handler(void *cookie)
3083{
3084 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
3085
3086 napi_schedule_irqoff(&fp->napi);
3087}
3088
3089static int qede_setup_irqs(struct qede_dev *edev)
3090{
3091 int i, rc = 0;
3092
3093 /* Learn Interrupt configuration */
3094 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
3095 if (rc)
3096 return rc;
3097
3098 if (edev->int_info.msix_cnt) {
3099 rc = qede_req_msix_irqs(edev);
3100 if (rc)
3101 return rc;
3102 edev->ndev->irq = edev->int_info.msix[0].vector;
3103 } else {
3104 const struct qed_common_ops *ops;
3105
3106 /* qed should learn receive the RSS ids and callbacks */
3107 ops = edev->ops->common;
3108 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
3109 ops->simd_handler_config(edev->cdev,
3110 &edev->fp_array[i], i,
3111 qede_simd_fp_handler);
3112 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
3113 }
3114 return 0;
3115}
3116
3117static int qede_drain_txq(struct qede_dev *edev,
1a635e48 3118 struct qede_tx_queue *txq, bool allow_drain)
2950219d
YM		 3119{
3120 int rc, cnt = 1000;
3121
3122 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3123 if (!cnt) {
3124 if (allow_drain) {
3125 DP_NOTICE(edev,
3126 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3127 txq->index);
3128 rc = edev->ops->common->drain(edev->cdev);
3129 if (rc)
3130 return rc;
3131 return qede_drain_txq(edev, txq, false);
3132 }
3133 DP_NOTICE(edev,
3134 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3135 txq->index, txq->sw_tx_prod,
3136 txq->sw_tx_cons);
3137 return -ENODEV;
3138 }
3139 cnt--;
3140 usleep_range(1000, 2000);
3141 barrier();
3142 }
3143
3144 /* FW finished processing, wait for HW to transmit all tx packets */
3145 usleep_range(1000, 2000);
3146
3147 return 0;
3148}
3149
3150static int qede_stop_queues(struct qede_dev *edev)
3151{
3152 struct qed_update_vport_params vport_update_params;
3153 struct qed_dev *cdev = edev->cdev;
3154 int rc, tc, i;
3155
3156 /* Disable the vport */
3157 memset(&vport_update_params, 0, sizeof(vport_update_params));
3158 vport_update_params.vport_id = 0;
3159 vport_update_params.update_vport_active_flg = 1;
3160 vport_update_params.vport_active_flg = 0;
3161 vport_update_params.update_rss_flg = 0;
3162
3163 rc = edev->ops->vport_update(cdev, &vport_update_params);
3164 if (rc) {
3165 DP_ERR(edev, "Failed to update vport\n");
3166 return rc;
3167 }
3168
3169 /* Flush Tx queues. If needed, request drain from MCP */
3170 for_each_rss(i) {
3171 struct qede_fastpath *fp = &edev->fp_array[i];
3172
3173 for (tc = 0; tc < edev->num_tc; tc++) {
3174 struct qede_tx_queue *txq = &fp->txqs[tc];
3175
3176 rc = qede_drain_txq(edev, txq, true);
3177 if (rc)
3178 return rc;
3179 }
3180 }
3181
3182 /* Stop all Queues in reverse order*/
3183 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3184 struct qed_stop_rxq_params rx_params;
3185
3186 /* Stop the Tx Queue(s)*/
3187 for (tc = 0; tc < edev->num_tc; tc++) {
3188 struct qed_stop_txq_params tx_params;
3189
3190 tx_params.rss_id = i;
3191 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3192 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3193 if (rc) {
3194 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3195 tx_params.tx_queue_id);
3196 return rc;
3197 }
3198 }
3199
3200 /* Stop the Rx Queue*/
3201 memset(&rx_params, 0, sizeof(rx_params));
3202 rx_params.rss_id = i;
3203 rx_params.rx_queue_id = i;
3204
3205 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3206 if (rc) {
3207 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3208 return rc;
3209 }
3210 }
3211
3212 /* Stop the vport */
3213 rc = edev->ops->vport_stop(cdev, 0);
3214 if (rc)
3215 DP_ERR(edev, "Failed to stop VPORT\n");
3216
3217 return rc;
3218}
3219
a0d26d5a 3220static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d
YM		 3221{
3222 int rc, tc, i;
088c8618 3223 int vlan_removal_en = 1;
2950219d 3224 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3225 struct qed_update_vport_params vport_update_params;
3226 struct qed_queue_start_common_params q_params;
fefb0202 3227 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3228 struct qed_start_vport_params start = {0};
961acdea 3229 bool reset_rss_indir = false;
2950219d
YM		 3230
3231 if (!edev->num_rss) {
3232 DP_ERR(edev,
3233 "Cannot update V-VPORT as active as there are no Rx queues\n");
3234 return -EINVAL;
3235 }
3236
55482edc 3237 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3238 start.mtu = edev->ndev->mtu;
3239 start.vport_id = 0;
3240 start.drop_ttl0 = true;
3241 start.remove_inner_vlan = vlan_removal_en;
7f7a144f 3242 start.clear_stats = clear_stats;
088c8618
MC		 3243
3244 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3245
3246 if (rc) {
3247 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3248 return rc;
3249 }
3250
3251 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3252 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3253 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3254
3255 for_each_rss(i) {
3256 struct qede_fastpath *fp = &edev->fp_array[i];
3257 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3258
3259 memset(&q_params, 0, sizeof(q_params));
3260 q_params.rss_id = i;
3261 q_params.queue_id = i;
3262 q_params.vport_id = 0;
3263 q_params.sb = fp->sb_info->igu_sb_id;
3264 q_params.sb_idx = RX_PI;
3265
3266 rc = edev->ops->q_rx_start(cdev, &q_params,
3267 fp->rxq->rx_buf_size,
3268 fp->rxq->rx_bd_ring.p_phys_addr,
3269 phys_table,
3270 fp->rxq->rx_comp_ring.page_cnt,
3271 &fp->rxq->hw_rxq_prod_addr);
3272 if (rc) {
3273 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3274 return rc;
3275 }
3276
3277 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3278
3279 qede_update_rx_prod(edev, fp->rxq);
3280
3281 for (tc = 0; tc < edev->num_tc; tc++) {
3282 struct qede_tx_queue *txq = &fp->txqs[tc];
3283 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3284
3285 memset(&q_params, 0, sizeof(q_params));
3286 q_params.rss_id = i;
3287 q_params.queue_id = txq_index;
3288 q_params.vport_id = 0;
3289 q_params.sb = fp->sb_info->igu_sb_id;
3290 q_params.sb_idx = TX_PI(tc);
3291
3292 rc = edev->ops->q_tx_start(cdev, &q_params,
3293 txq->tx_pbl.pbl.p_phys_table,
3294 txq->tx_pbl.page_cnt,
3295 &txq->doorbell_addr);
3296 if (rc) {
3297 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3298 txq_index, rc);
3299 return rc;
3300 }
3301
3302 txq->hw_cons_ptr =
3303 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3304 SET_FIELD(txq->tx_db.data.params,
3305 ETH_DB_DATA_DEST, DB_DEST_XCM);
3306 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3307 DB_AGG_CMD_SET);
3308 SET_FIELD(txq->tx_db.data.params,
3309 ETH_DB_DATA_AGG_VAL_SEL,
3310 DQ_XCM_ETH_TX_BD_PROD_CMD);
3311
3312 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3313 }
3314 }
3315
3316 /* Prepare and send the vport enable */
3317 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3318 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3319 vport_update_params.update_vport_active_flg = 1;
3320 vport_update_params.vport_active_flg = 1;
3321
831bfb0e
YM		 3322 if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
3323 qed_info->tx_switching) {
3324 vport_update_params.update_tx_switching_flg = 1;
3325 vport_update_params.tx_switching_flg = 1;
3326 }
3327
2950219d
YM		 3328 /* Fill struct with RSS params */
3329 if (QEDE_RSS_CNT(edev) > 1) {
3330 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3331
3332 /* Need to validate current RSS config uses valid entries */
3333 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3334 if (edev->rss_params.rss_ind_table[i] >=
3335 edev->num_rss) {
3336 reset_rss_indir = true;
3337 break;
3338 }
3339 }
3340
3341 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3342 reset_rss_indir) {
3343 u16 val;
3344
3345 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3346 u16 indir_val;
3347
3348 val = QEDE_RSS_CNT(edev);
3349 indir_val = ethtool_rxfh_indir_default(i, val);
3350 edev->rss_params.rss_ind_table[i] = indir_val;
3351 }
3352 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3353 }
3354
3355 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3356 netdev_rss_key_fill(edev->rss_params.rss_key,
3357 sizeof(edev->rss_params.rss_key));
3358 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3359 }
3360
3361 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3362 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3363 QED_RSS_IPV6 |
3364 QED_RSS_IPV4_TCP |
3365 QED_RSS_IPV6_TCP;
3366 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3367 }
3368
3369 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3370 sizeof(vport_update_params.rss_params));
2950219d 3371 } else {
961acdea
SRK		 3372 memset(&vport_update_params.rss_params, 0,
3373 sizeof(vport_update_params.rss_params));
2950219d 3374 }
2950219d
YM		 3375
3376 rc = edev->ops->vport_update(cdev, &vport_update_params);
3377 if (rc) {
3378 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3379 return rc;
3380 }
3381
3382 return 0;
3383}
3384
0d8e0aa0
SK		 3385static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3386 enum qed_filter_xcast_params_type opcode,
3387 unsigned char *mac, int num_macs)
3388{
3389 struct qed_filter_params filter_cmd;
3390 int i;
3391
3392 memset(&filter_cmd, 0, sizeof(filter_cmd));
3393 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3394 filter_cmd.filter.mcast.type = opcode;
3395 filter_cmd.filter.mcast.num = num_macs;
3396
3397 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3398 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3399
3400 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3401}
3402
2950219d
YM		 3403enum qede_unload_mode {
3404 QEDE_UNLOAD_NORMAL,
3405};
3406
3407static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3408{
a2ec6172 3409 struct qed_link_params link_params;
2950219d
YM		 3410 int rc;
3411
3412 DP_INFO(edev, "Starting qede unload\n");
3413
0d8e0aa0
SK		 3414 mutex_lock(&edev->qede_lock);
3415 edev->state = QEDE_STATE_CLOSED;
3416
2950219d
YM		 3417 /* Close OS Tx */
3418 netif_tx_disable(edev->ndev);
3419 netif_carrier_off(edev->ndev);
3420
a2ec6172
SK		 3421 /* Reset the link */
3422 memset(&link_params, 0, sizeof(link_params));
3423 link_params.link_up = false;
3424 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3425 rc = qede_stop_queues(edev);
3426 if (rc) {
3427 qede_sync_free_irqs(edev);
3428 goto out;
3429 }
3430
3431 DP_INFO(edev, "Stopped Queues\n");
3432
7c1bfcad 3433 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3434 edev->ops->fastpath_stop(edev->cdev);
3435
3436 /* Release the interrupts */
3437 qede_sync_free_irqs(edev);
3438 edev->ops->common->set_fp_int(edev->cdev, 0);
3439
3440 qede_napi_disable_remove(edev);
3441
3442 qede_free_mem_load(edev);
3443 qede_free_fp_array(edev);
3444
3445out:
3446 mutex_unlock(&edev->qede_lock);
3447 DP_INFO(edev, "Ending qede unload\n");
3448}
3449
3450enum qede_load_mode {
3451 QEDE_LOAD_NORMAL,
a0d26d5a 3452 QEDE_LOAD_RELOAD,
2950219d
YM		 3453};
3454
3455static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3456{
a2ec6172
SK		 3457 struct qed_link_params link_params;
3458 struct qed_link_output link_output;
2950219d
YM		 3459 int rc;
3460
3461 DP_INFO(edev, "Starting qede load\n");
3462
3463 rc = qede_set_num_queues(edev);
3464 if (rc)
3465 goto err0;
3466
3467 rc = qede_alloc_fp_array(edev);
3468 if (rc)
3469 goto err0;
3470
3471 qede_init_fp(edev);
3472
3473 rc = qede_alloc_mem_load(edev);
3474 if (rc)
3475 goto err1;
3476 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3477 QEDE_RSS_CNT(edev), edev->num_tc);
3478
3479 rc = qede_set_real_num_queues(edev);
3480 if (rc)
3481 goto err2;
3482
3483 qede_napi_add_enable(edev);
3484 DP_INFO(edev, "Napi added and enabled\n");
3485
3486 rc = qede_setup_irqs(edev);
3487 if (rc)
3488 goto err3;
3489 DP_INFO(edev, "Setup IRQs succeeded\n");
3490
a0d26d5a 3491 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 3492 if (rc)
3493 goto err4;
3494 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3495
3496 /* Add primary mac and set Rx filters */
3497 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3498
0d8e0aa0
SK		 3499 mutex_lock(&edev->qede_lock);
3500 edev->state = QEDE_STATE_OPEN;
3501 mutex_unlock(&edev->qede_lock);
a2ec6172 3502
7c1bfcad
SRK		 3503 /* Program un-configured VLANs */
3504 qede_configure_vlan_filters(edev);
3505
a2ec6172
SK		 3506 /* Ask for link-up using current configuration */
3507 memset(&link_params, 0, sizeof(link_params));
3508 link_params.link_up = true;
3509 edev->ops->common->set_link(edev->cdev, &link_params);
3510
3511 /* Query whether link is already-up */
3512 memset(&link_output, 0, sizeof(link_output));
3513 edev->ops->common->get_link(edev->cdev, &link_output);
3514 qede_link_update(edev, &link_output);
3515
2950219d
YM		 3516 DP_INFO(edev, "Ending successfully qede load\n");
3517
3518 return 0;
3519
3520err4:
3521 qede_sync_free_irqs(edev);
3522 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3523err3:
3524 qede_napi_disable_remove(edev);
3525err2:
3526 qede_free_mem_load(edev);
3527err1:
3528 edev->ops->common->set_fp_int(edev->cdev, 0);
3529 qede_free_fp_array(edev);
3530 edev->num_rss = 0;
3531err0:
3532 return rc;
3533}
3534
133fac0e
SK		 3535void qede_reload(struct qede_dev *edev,
3536 void (*func)(struct qede_dev *, union qede_reload_args *),
3537 union qede_reload_args *args)
3538{
3539 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3540 /* Call function handler to update parameters
3541 * needed for function load.
3542 */
3543 if (func)
3544 func(edev, args);
3545
a0d26d5a 3546 qede_load(edev, QEDE_LOAD_RELOAD);
133fac0e
SK		 3547
3548 mutex_lock(&edev->qede_lock);
3549 qede_config_rx_mode(edev->ndev);
3550 mutex_unlock(&edev->qede_lock);
3551}
3552
2950219d
YM		 3553/* called with rtnl_lock */
3554static int qede_open(struct net_device *ndev)
3555{
3556 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3557 int rc;
2950219d
YM		 3558
3559 netif_carrier_off(ndev);
3560
3561 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3562
b18e170c
MC		 3563 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3564
3565 if (rc)
3566 return rc;
3567
f9f082a9
AD		 3568 udp_tunnel_get_rx_info(ndev);
3569
b18e170c 3570 return 0;
2950219d
YM		 3571}
3572
3573static int qede_close(struct net_device *ndev)
3574{
3575 struct qede_dev *edev = netdev_priv(ndev);
3576
3577 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3578
3579 return 0;
3580}
0d8e0aa0 3581
a2ec6172
SK		 3582static void qede_link_update(void *dev, struct qed_link_output *link)
3583{
3584 struct qede_dev *edev = dev;
3585
3586 if (!netif_running(edev->ndev)) {
3587 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3588 return;
3589 }
3590
3591 if (link->link_up) {
8e025ae2
YM		 3592 if (!netif_carrier_ok(edev->ndev)) {
3593 DP_NOTICE(edev, "Link is up\n");
3594 netif_tx_start_all_queues(edev->ndev);
3595 netif_carrier_on(edev->ndev);
3596 }
a2ec6172 3597 } else {
8e025ae2
YM		 3598 if (netif_carrier_ok(edev->ndev)) {
3599 DP_NOTICE(edev, "Link is down\n");
3600 netif_tx_disable(edev->ndev);
3601 netif_carrier_off(edev->ndev);
3602 }
a2ec6172
SK		 3603 }
3604}
3605
0d8e0aa0
SK		 3606static int qede_set_mac_addr(struct net_device *ndev, void *p)
3607{
3608 struct qede_dev *edev = netdev_priv(ndev);
3609 struct sockaddr *addr = p;
3610 int rc;
3611
3612 ASSERT_RTNL(); /* @@@TBD To be removed */
3613
3614 DP_INFO(edev, "Set_mac_addr called\n");
3615
3616 if (!is_valid_ether_addr(addr->sa_data)) {
3617 DP_NOTICE(edev, "The MAC address is not valid\n");
3618 return -EFAULT;
3619 }
3620
eff16960
YM		 3621 if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
3622 DP_NOTICE(edev, "qed prevents setting MAC\n");
3623 return -EINVAL;
3624 }
3625
0d8e0aa0
SK		 3626 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3627
3628 if (!netif_running(ndev)) {
3629 DP_NOTICE(edev, "The device is currently down\n");
3630 return 0;
3631 }
3632
3633 /* Remove the previous primary mac */
3634 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3635 edev->primary_mac);
3636 if (rc)
3637 return rc;
3638
3639 /* Add MAC filter according to the new unicast HW MAC address */
3640 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3641 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3642 edev->primary_mac);
3643}
3644
3645static int
3646qede_configure_mcast_filtering(struct net_device *ndev,
3647 enum qed_filter_rx_mode_type *accept_flags)
3648{
3649 struct qede_dev *edev = netdev_priv(ndev);
3650 unsigned char *mc_macs, *temp;
3651 struct netdev_hw_addr *ha;
3652 int rc = 0, mc_count;
3653 size_t size;
3654
3655 size = 64 * ETH_ALEN;
3656
3657 mc_macs = kzalloc(size, GFP_KERNEL);
3658 if (!mc_macs) {
3659 DP_NOTICE(edev,
3660 "Failed to allocate memory for multicast MACs\n");
3661 rc = -ENOMEM;
3662 goto exit;
3663 }
3664
3665 temp = mc_macs;
3666
3667 /* Remove all previously configured MAC filters */
3668 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3669 mc_macs, 1);
3670 if (rc)
3671 goto exit;
3672
3673 netif_addr_lock_bh(ndev);
3674
3675 mc_count = netdev_mc_count(ndev);
3676 if (mc_count < 64) {
3677 netdev_for_each_mc_addr(ha, ndev) {
3678 ether_addr_copy(temp, ha->addr);
3679 temp += ETH_ALEN;
3680 }
3681 }
3682
3683 netif_addr_unlock_bh(ndev);
3684
3685 /* Check for all multicast @@@TBD resource allocation */
3686 if ((ndev->flags & IFF_ALLMULTI) ||
3687 (mc_count > 64)) {
3688 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3689 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3690 } else {
3691 /* Add all multicast MAC filters */
3692 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3693 mc_macs, mc_count);
3694 }
3695
3696exit:
3697 kfree(mc_macs);
3698 return rc;
3699}
3700
3701static void qede_set_rx_mode(struct net_device *ndev)
3702{
3703 struct qede_dev *edev = netdev_priv(ndev);
3704
3705 DP_INFO(edev, "qede_set_rx_mode called\n");
3706
3707 if (edev->state != QEDE_STATE_OPEN) {
3708 DP_INFO(edev,
3709 "qede_set_rx_mode called while interface is down\n");
3710 } else {
3711 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3712 schedule_delayed_work(&edev->sp_task, 0);
3713 }
3714}
3715
3716/* Must be called with qede_lock held */
3717static void qede_config_rx_mode(struct net_device *ndev)
3718{
3719 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3720 struct qede_dev *edev = netdev_priv(ndev);
3721 struct qed_filter_params rx_mode;
3722 unsigned char *uc_macs, *temp;
3723 struct netdev_hw_addr *ha;
3724 int rc, uc_count;
3725 size_t size;
3726
3727 netif_addr_lock_bh(ndev);
3728
3729 uc_count = netdev_uc_count(ndev);
3730 size = uc_count * ETH_ALEN;
3731
3732 uc_macs = kzalloc(size, GFP_ATOMIC);
3733 if (!uc_macs) {
3734 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3735 netif_addr_unlock_bh(ndev);
3736 return;
3737 }
3738
3739 temp = uc_macs;
3740 netdev_for_each_uc_addr(ha, ndev) {
3741 ether_addr_copy(temp, ha->addr);
3742 temp += ETH_ALEN;
3743 }
3744
3745 netif_addr_unlock_bh(ndev);
3746
3747 /* Configure the struct for the Rx mode */
3748 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3749 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3750
3751 /* Remove all previous unicast secondary macs and multicast macs
3752 * (configrue / leave the primary mac)
3753 */
3754 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3755 edev->primary_mac);
3756 if (rc)
3757 goto out;
3758
3759 /* Check for promiscuous */
3760 if ((ndev->flags & IFF_PROMISC) ||
3761 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3762 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3763 } else {
3764 /* Add MAC filters according to the unicast secondary macs */
3765 int i;
3766
3767 temp = uc_macs;
3768 for (i = 0; i < uc_count; i++) {
3769 rc = qede_set_ucast_rx_mac(edev,
3770 QED_FILTER_XCAST_TYPE_ADD,
3771 temp);
3772 if (rc)
3773 goto out;
3774
3775 temp += ETH_ALEN;
3776 }
3777
3778 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3779 if (rc)
3780 goto out;
3781 }
3782
7c1bfcad
SRK		 3783 /* take care of VLAN mode */
3784 if (ndev->flags & IFF_PROMISC) {
3785 qede_config_accept_any_vlan(edev, true);
3786 } else if (!edev->non_configured_vlans) {
3787 /* It's possible that accept_any_vlan mode is set due to a
3788 * previous setting of IFF_PROMISC. If vlan credits are
3789 * sufficient, disable accept_any_vlan.
3790 */
3791 qede_config_accept_any_vlan(edev, false);
3792 }
3793
0d8e0aa0
SK		 3794 rx_mode.filter.accept_flags = accept_flags;
3795 edev->ops->filter_config(edev->cdev, &rx_mode);
3796out:
3797 kfree(uc_macs);
3798}
Linux kernel - Deliverables
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