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net: better drop monitoring in ip{6}_recv_error()
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
b18e170c 27#ifdef CONFIG_QEDE_VXLAN
e712d52b 28#include <net/vxlan.h>
b18e170c 29#endif
9a109dd0
MC		 30#ifdef CONFIG_QEDE_GENEVE
31#include <net/geneve.h>
32#endif
e712d52b
YM		 33#include <linux/ip.h>
34#include <net/ipv6.h>
35#include <net/tcp.h>
36#include <linux/if_ether.h>
37#include <linux/if_vlan.h>
38#include <linux/pkt_sched.h>
39#include <linux/ethtool.h>
40#include <linux/in.h>
41#include <linux/random.h>
42#include <net/ip6_checksum.h>
43#include <linux/bitops.h>
44
45#include "qede.h"
46
5abd7e92
YM		 47static char version[] =
48 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 49
5abd7e92 50MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_MODULE_VERSION);
53
54static uint debug;
55module_param(debug, uint, 0);
56MODULE_PARM_DESC(debug, " Default debug msglevel");
57
58static const struct qed_eth_ops *qed_ops;
59
60#define CHIP_NUM_57980S_40 0x1634
0e7441d7 61#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 62#define CHIP_NUM_57980S_MF 0x1636
63#define CHIP_NUM_57980S_100 0x1644
64#define CHIP_NUM_57980S_50 0x1654
65#define CHIP_NUM_57980S_25 0x1656
66
67#ifndef PCI_DEVICE_ID_NX2_57980E
68#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
69#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
70#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
71#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
72#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
73#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
74#endif
75
76static const struct pci_device_id qede_pci_tbl[] = {
77 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), 0 },
78 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), 0 },
79 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), 0 },
80 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), 0 },
81 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), 0 },
82 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), 0 },
83 { 0 }
84};
85
86MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
87
88static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
89
90#define TX_TIMEOUT (5 * HZ)
91
92static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 93static int qede_alloc_rx_buffer(struct qede_dev *edev,
94 struct qede_rx_queue *rxq);
a2ec6172 95static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b
YM		 96
97static struct pci_driver qede_pci_driver = {
98 .name = "qede",
99 .id_table = qede_pci_tbl,
100 .probe = qede_probe,
101 .remove = qede_remove,
102};
103
a2ec6172
SK		 104static struct qed_eth_cb_ops qede_ll_ops = {
105 {
106 .link_update = qede_link_update,
107 },
108};
109
2950219d
YM		 110static int qede_netdev_event(struct notifier_block *this, unsigned long event,
111 void *ptr)
112{
113 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
114 struct ethtool_drvinfo drvinfo;
115 struct qede_dev *edev;
116
117 /* Currently only support name change */
118 if (event != NETDEV_CHANGENAME)
119 goto done;
120
121 /* Check whether this is a qede device */
122 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
123 goto done;
124
125 memset(&drvinfo, 0, sizeof(drvinfo));
126 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
127 if (strcmp(drvinfo.driver, "qede"))
128 goto done;
129 edev = netdev_priv(ndev);
130
131 /* Notify qed of the name change */
132 if (!edev->ops || !edev->ops->common)
133 goto done;
134 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
135 "qede");
136
137done:
138 return NOTIFY_DONE;
139}
140
141static struct notifier_block qede_netdev_notifier = {
142 .notifier_call = qede_netdev_event,
143};
144
e712d52b
YM		 145static
146int __init qede_init(void)
147{
148 int ret;
e712d52b
YM		 149
150 pr_notice("qede_init: %s\n", version);
151
95114344 152 qed_ops = qed_get_eth_ops();
e712d52b
YM		 153 if (!qed_ops) {
154 pr_notice("Failed to get qed ethtool operations\n");
155 return -EINVAL;
156 }
157
2950219d
YM		 158 /* Must register notifier before pci ops, since we might miss
159 * interface rename after pci probe and netdev registeration.
160 */
161 ret = register_netdevice_notifier(&qede_netdev_notifier);
162 if (ret) {
163 pr_notice("Failed to register netdevice_notifier\n");
164 qed_put_eth_ops();
165 return -EINVAL;
166 }
167
e712d52b
YM		 168 ret = pci_register_driver(&qede_pci_driver);
169 if (ret) {
170 pr_notice("Failed to register driver\n");
2950219d 171 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 172 qed_put_eth_ops();
173 return -EINVAL;
174 }
175
176 return 0;
177}
178
179static void __exit qede_cleanup(void)
180{
181 pr_notice("qede_cleanup called\n");
182
2950219d 183 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 184 pci_unregister_driver(&qede_pci_driver);
185 qed_put_eth_ops();
186}
187
188module_init(qede_init);
189module_exit(qede_cleanup);
190
2950219d
YM		 191/* -------------------------------------------------------------------------
192 * START OF FAST-PATH
193 * -------------------------------------------------------------------------
194 */
195
196/* Unmap the data and free skb */
197static int qede_free_tx_pkt(struct qede_dev *edev,
198 struct qede_tx_queue *txq,
199 int *len)
200{
201 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
202 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
203 struct eth_tx_1st_bd *first_bd;
204 struct eth_tx_bd *tx_data_bd;
205 int bds_consumed = 0;
206 int nbds;
207 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
208 int i, split_bd_len = 0;
209
210 if (unlikely(!skb)) {
211 DP_ERR(edev,
212 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
213 idx, txq->sw_tx_cons, txq->sw_tx_prod);
214 return -1;
215 }
216
217 *len = skb->len;
218
219 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
220
221 bds_consumed++;
222
223 nbds = first_bd->data.nbds;
224
225 if (data_split) {
226 struct eth_tx_bd *split = (struct eth_tx_bd *)
227 qed_chain_consume(&txq->tx_pbl);
228 split_bd_len = BD_UNMAP_LEN(split);
229 bds_consumed++;
230 }
231 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
232 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
233
234 /* Unmap the data of the skb frags */
235 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
236 tx_data_bd = (struct eth_tx_bd *)
237 qed_chain_consume(&txq->tx_pbl);
238 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
239 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
240 }
241
242 while (bds_consumed++ < nbds)
243 qed_chain_consume(&txq->tx_pbl);
244
245 /* Free skb */
246 dev_kfree_skb_any(skb);
247 txq->sw_tx_ring[idx].skb = NULL;
248 txq->sw_tx_ring[idx].flags = 0;
249
250 return 0;
251}
252
253/* Unmap the data and free skb when mapping failed during start_xmit */
254static void qede_free_failed_tx_pkt(struct qede_dev *edev,
255 struct qede_tx_queue *txq,
256 struct eth_tx_1st_bd *first_bd,
257 int nbd,
258 bool data_split)
259{
260 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
261 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
262 struct eth_tx_bd *tx_data_bd;
263 int i, split_bd_len = 0;
264
265 /* Return prod to its position before this skb was handled */
266 qed_chain_set_prod(&txq->tx_pbl,
267 le16_to_cpu(txq->tx_db.data.bd_prod),
268 first_bd);
269
270 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
271
272 if (data_split) {
273 struct eth_tx_bd *split = (struct eth_tx_bd *)
274 qed_chain_produce(&txq->tx_pbl);
275 split_bd_len = BD_UNMAP_LEN(split);
276 nbd--;
277 }
278
279 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
280 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
281
282 /* Unmap the data of the skb frags */
283 for (i = 0; i < nbd; i++) {
284 tx_data_bd = (struct eth_tx_bd *)
285 qed_chain_produce(&txq->tx_pbl);
286 if (tx_data_bd->nbytes)
287 dma_unmap_page(&edev->pdev->dev,
288 BD_UNMAP_ADDR(tx_data_bd),
289 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
290 }
291
292 /* Return again prod to its position before this skb was handled */
293 qed_chain_set_prod(&txq->tx_pbl,
294 le16_to_cpu(txq->tx_db.data.bd_prod),
295 first_bd);
296
297 /* Free skb */
298 dev_kfree_skb_any(skb);
299 txq->sw_tx_ring[idx].skb = NULL;
300 txq->sw_tx_ring[idx].flags = 0;
301}
302
303static u32 qede_xmit_type(struct qede_dev *edev,
304 struct sk_buff *skb,
305 int *ipv6_ext)
306{
307 u32 rc = XMIT_L4_CSUM;
308 __be16 l3_proto;
309
310 if (skb->ip_summed != CHECKSUM_PARTIAL)
311 return XMIT_PLAIN;
312
313 l3_proto = vlan_get_protocol(skb);
314 if (l3_proto == htons(ETH_P_IPV6) &&
315 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
316 *ipv6_ext = 1;
317
14db81de
MC		 318 if (skb->encapsulation)
319 rc |= XMIT_ENC;
320
2950219d
YM		 321 if (skb_is_gso(skb))
322 rc |= XMIT_LSO;
323
324 return rc;
325}
326
327static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
328 struct eth_tx_2nd_bd *second_bd,
329 struct eth_tx_3rd_bd *third_bd)
330{
331 u8 l4_proto;
fc48b7a6 332 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 333
fc48b7a6 334 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 335
fc48b7a6 336 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 337 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
338 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
339
fc48b7a6 340 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 341 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
342
343 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
344 l4_proto = ipv6_hdr(skb)->nexthdr;
345 else
346 l4_proto = ip_hdr(skb)->protocol;
347
348 if (l4_proto == IPPROTO_UDP)
fc48b7a6 349 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 350
fc48b7a6 351 if (third_bd)
2950219d 352 third_bd->data.bitfields |=
fc48b7a6
YM		 353 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
354 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
355 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 356
fc48b7a6 357 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 358 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
359}
360
361static int map_frag_to_bd(struct qede_dev *edev,
362 skb_frag_t *frag,
363 struct eth_tx_bd *bd)
364{
365 dma_addr_t mapping;
366
367 /* Map skb non-linear frag data for DMA */
368 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
369 skb_frag_size(frag),
370 DMA_TO_DEVICE);
371 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
372 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
373 return -ENOMEM;
374 }
375
376 /* Setup the data pointer of the frag data */
377 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
378
379 return 0;
380}
381
14db81de
MC		 382static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
383{
384 if (is_encap_pkt)
385 return (skb_inner_transport_header(skb) +
386 inner_tcp_hdrlen(skb) - skb->data);
387 else
388 return (skb_transport_header(skb) +
389 tcp_hdrlen(skb) - skb->data);
390}
391
b1199b10
YM		 392/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
393#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
394static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
395 u8 xmit_type)
396{
397 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
398
399 if (xmit_type & XMIT_LSO) {
400 int hlen;
401
14db81de 402 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 403
404 /* linear payload would require its own BD */
405 if (skb_headlen(skb) > hlen)
406 allowed_frags--;
407 }
408
409 return (skb_shinfo(skb)->nr_frags > allowed_frags);
410}
411#endif
412
2950219d
YM		 413/* Main transmit function */
414static
415netdev_tx_t qede_start_xmit(struct sk_buff *skb,
416 struct net_device *ndev)
417{
418 struct qede_dev *edev = netdev_priv(ndev);
419 struct netdev_queue *netdev_txq;
420 struct qede_tx_queue *txq;
421 struct eth_tx_1st_bd *first_bd;
422 struct eth_tx_2nd_bd *second_bd = NULL;
423 struct eth_tx_3rd_bd *third_bd = NULL;
424 struct eth_tx_bd *tx_data_bd = NULL;
425 u16 txq_index;
426 u8 nbd = 0;
427 dma_addr_t mapping;
428 int rc, frag_idx = 0, ipv6_ext = 0;
429 u8 xmit_type;
430 u16 idx;
431 u16 hlen;
432 bool data_split;
433
434 /* Get tx-queue context and netdev index */
435 txq_index = skb_get_queue_mapping(skb);
436 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
437 txq = QEDE_TX_QUEUE(edev, txq_index);
438 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
439
2950219d
YM		 440 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) <
441 (MAX_SKB_FRAGS + 1));
442
443 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
444
b1199b10
YM		 445#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
446 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
447 if (skb_linearize(skb)) {
448 DP_NOTICE(edev,
449 "SKB linearization failed - silently dropping this SKB\n");
450 dev_kfree_skb_any(skb);
451 return NETDEV_TX_OK;
452 }
453 }
454#endif
455
2950219d
YM		 456 /* Fill the entry in the SW ring and the BDs in the FW ring */
457 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
458 txq->sw_tx_ring[idx].skb = skb;
459 first_bd = (struct eth_tx_1st_bd *)
460 qed_chain_produce(&txq->tx_pbl);
461 memset(first_bd, 0, sizeof(*first_bd));
462 first_bd->data.bd_flags.bitfields =
463 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
464
465 /* Map skb linear data for DMA and set in the first BD */
466 mapping = dma_map_single(&edev->pdev->dev, skb->data,
467 skb_headlen(skb), DMA_TO_DEVICE);
468 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
469 DP_NOTICE(edev, "SKB mapping failed\n");
470 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
471 return NETDEV_TX_OK;
472 }
473 nbd++;
474 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
475
476 /* In case there is IPv6 with extension headers or LSO we need 2nd and
477 * 3rd BDs.
478 */
479 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
480 second_bd = (struct eth_tx_2nd_bd *)
481 qed_chain_produce(&txq->tx_pbl);
482 memset(second_bd, 0, sizeof(*second_bd));
483
484 nbd++;
485 third_bd = (struct eth_tx_3rd_bd *)
486 qed_chain_produce(&txq->tx_pbl);
487 memset(third_bd, 0, sizeof(*third_bd));
488
489 nbd++;
490 /* We need to fill in additional data in second_bd... */
491 tx_data_bd = (struct eth_tx_bd *)second_bd;
492 }
493
494 if (skb_vlan_tag_present(skb)) {
495 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
496 first_bd->data.bd_flags.bitfields |=
497 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
498 }
499
500 /* Fill the parsing flags & params according to the requested offload */
501 if (xmit_type & XMIT_L4_CSUM) {
fc48b7a6
YM		 502 u16 temp = 1 << ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT;
503
2950219d
YM		 504 /* We don't re-calculate IP checksum as it is already done by
505 * the upper stack
506 */
507 first_bd->data.bd_flags.bitfields |=
508 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
509
14db81de
MC		 510 if (xmit_type & XMIT_ENC) {
511 first_bd->data.bd_flags.bitfields |=
512 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
513 } else {
514 /* In cases when OS doesn't indicate for inner offloads
515 * when packet is tunnelled, we need to override the HW
516 * tunnel configuration so that packets are treated as
517 * regular non tunnelled packets and no inner offloads
518 * are done by the hardware.
519 */
520 first_bd->data.bitfields |= cpu_to_le16(temp);
521 }
fc48b7a6 522
2950219d
YM		 523 /* If the packet is IPv6 with extension header, indicate that
524 * to FW and pass few params, since the device cracker doesn't
525 * support parsing IPv6 with extension header/s.
526 */
527 if (unlikely(ipv6_ext))
528 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
529 }
530
531 if (xmit_type & XMIT_LSO) {
532 first_bd->data.bd_flags.bitfields |=
533 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
534 third_bd->data.lso_mss =
535 cpu_to_le16(skb_shinfo(skb)->gso_size);
536
14db81de
MC		 537 if (unlikely(xmit_type & XMIT_ENC)) {
538 first_bd->data.bd_flags.bitfields |=
539 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
540 hlen = qede_get_skb_hlen(skb, true);
541 } else {
542 first_bd->data.bd_flags.bitfields |=
543 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
544 hlen = qede_get_skb_hlen(skb, false);
545 }
2950219d
YM		 546
547 /* @@@TBD - if will not be removed need to check */
548 third_bd->data.bitfields |=
fc48b7a6 549 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 550
551 /* Make life easier for FW guys who can't deal with header and
552 * data on same BD. If we need to split, use the second bd...
553 */
554 if (unlikely(skb_headlen(skb) > hlen)) {
555 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
556 "TSO split header size is %d (%x:%x)\n",
557 first_bd->nbytes, first_bd->addr.hi,
558 first_bd->addr.lo);
559
560 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
561 le32_to_cpu(first_bd->addr.lo)) +
562 hlen;
563
564 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
565 le16_to_cpu(first_bd->nbytes) -
566 hlen);
567
568 /* this marks the BD as one that has no
569 * individual mapping
570 */
571 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
572
573 first_bd->nbytes = cpu_to_le16(hlen);
574
575 tx_data_bd = (struct eth_tx_bd *)third_bd;
576 data_split = true;
577 }
578 }
579
580 /* Handle fragmented skb */
581 /* special handle for frags inside 2nd and 3rd bds.. */
582 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
583 rc = map_frag_to_bd(edev,
584 &skb_shinfo(skb)->frags[frag_idx],
585 tx_data_bd);
586 if (rc) {
587 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
588 data_split);
589 return NETDEV_TX_OK;
590 }
591
592 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
593 tx_data_bd = (struct eth_tx_bd *)third_bd;
594 else
595 tx_data_bd = NULL;
596
597 frag_idx++;
598 }
599
600 /* map last frags into 4th, 5th .... */
601 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
602 tx_data_bd = (struct eth_tx_bd *)
603 qed_chain_produce(&txq->tx_pbl);
604
605 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
606
607 rc = map_frag_to_bd(edev,
608 &skb_shinfo(skb)->frags[frag_idx],
609 tx_data_bd);
610 if (rc) {
611 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
612 data_split);
613 return NETDEV_TX_OK;
614 }
615 }
616
617 /* update the first BD with the actual num BDs */
618 first_bd->data.nbds = nbd;
619
620 netdev_tx_sent_queue(netdev_txq, skb->len);
621
622 skb_tx_timestamp(skb);
623
624 /* Advance packet producer only before sending the packet since mapping
625 * of pages may fail.
626 */
627 txq->sw_tx_prod++;
628
629 /* 'next page' entries are counted in the producer value */
630 txq->tx_db.data.bd_prod =
631 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
632
633 /* wmb makes sure that the BDs data is updated before updating the
634 * producer, otherwise FW may read old data from the BDs.
635 */
636 wmb();
637 barrier();
638 writel(txq->tx_db.raw, txq->doorbell_addr);
639
640 /* mmiowb is needed to synchronize doorbell writes from more than one
641 * processor. It guarantees that the write arrives to the device before
642 * the queue lock is released and another start_xmit is called (possibly
643 * on another CPU). Without this barrier, the next doorbell can bypass
644 * this doorbell. This is applicable to IA64/Altix systems.
645 */
646 mmiowb();
647
648 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
649 < (MAX_SKB_FRAGS + 1))) {
650 netif_tx_stop_queue(netdev_txq);
651 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
652 "Stop queue was called\n");
653 /* paired memory barrier is in qede_tx_int(), we have to keep
654 * ordering of set_bit() in netif_tx_stop_queue() and read of
655 * fp->bd_tx_cons
656 */
657 smp_mb();
658
659 if (qed_chain_get_elem_left(&txq->tx_pbl)
660 >= (MAX_SKB_FRAGS + 1) &&
661 (edev->state == QEDE_STATE_OPEN)) {
662 netif_tx_wake_queue(netdev_txq);
663 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
664 "Wake queue was called\n");
665 }
666 }
667
668 return NETDEV_TX_OK;
669}
670
671static int qede_txq_has_work(struct qede_tx_queue *txq)
672{
673 u16 hw_bd_cons;
674
675 /* Tell compiler that consumer and producer can change */
676 barrier();
677 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
678 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
679 return 0;
680
681 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
682}
683
684static int qede_tx_int(struct qede_dev *edev,
685 struct qede_tx_queue *txq)
686{
687 struct netdev_queue *netdev_txq;
688 u16 hw_bd_cons;
689 unsigned int pkts_compl = 0, bytes_compl = 0;
690 int rc;
691
692 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
693
694 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
695 barrier();
696
697 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
698 int len = 0;
699
700 rc = qede_free_tx_pkt(edev, txq, &len);
701 if (rc) {
702 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
703 hw_bd_cons,
704 qed_chain_get_cons_idx(&txq->tx_pbl));
705 break;
706 }
707
708 bytes_compl += len;
709 pkts_compl++;
710 txq->sw_tx_cons++;
711 }
712
713 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
714
715 /* Need to make the tx_bd_cons update visible to start_xmit()
716 * before checking for netif_tx_queue_stopped(). Without the
717 * memory barrier, there is a small possibility that
718 * start_xmit() will miss it and cause the queue to be stopped
719 * forever.
720 * On the other hand we need an rmb() here to ensure the proper
721 * ordering of bit testing in the following
722 * netif_tx_queue_stopped(txq) call.
723 */
724 smp_mb();
725
726 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
727 /* Taking tx_lock is needed to prevent reenabling the queue
728 * while it's empty. This could have happen if rx_action() gets
729 * suspended in qede_tx_int() after the condition before
730 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
731 *
732 * stops the queue->sees fresh tx_bd_cons->releases the queue->
733 * sends some packets consuming the whole queue again->
734 * stops the queue
735 */
736
737 __netif_tx_lock(netdev_txq, smp_processor_id());
738
739 if ((netif_tx_queue_stopped(netdev_txq)) &&
740 (edev->state == QEDE_STATE_OPEN) &&
741 (qed_chain_get_elem_left(&txq->tx_pbl)
742 >= (MAX_SKB_FRAGS + 1))) {
743 netif_tx_wake_queue(netdev_txq);
744 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
745 "Wake queue was called\n");
746 }
747
748 __netif_tx_unlock(netdev_txq);
749 }
750
751 return 0;
752}
753
754static bool qede_has_rx_work(struct qede_rx_queue *rxq)
755{
756 u16 hw_comp_cons, sw_comp_cons;
757
758 /* Tell compiler that status block fields can change */
759 barrier();
760
761 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
762 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
763
764 return hw_comp_cons != sw_comp_cons;
765}
766
767static bool qede_has_tx_work(struct qede_fastpath *fp)
768{
769 u8 tc;
770
771 for (tc = 0; tc < fp->edev->num_tc; tc++)
772 if (qede_txq_has_work(&fp->txqs[tc]))
773 return true;
774 return false;
775}
776
f86af2df
MC		 777static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
778{
779 qed_chain_consume(&rxq->rx_bd_ring);
780 rxq->sw_rx_cons++;
781}
782
fc48b7a6
YM		 783/* This function reuses the buffer(from an offset) from
784 * consumer index to producer index in the bd ring
2950219d 785 */
fc48b7a6
YM		 786static inline void qede_reuse_page(struct qede_dev *edev,
787 struct qede_rx_queue *rxq,
788 struct sw_rx_data *curr_cons)
2950219d 789{
2950219d 790 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 791 struct sw_rx_data *curr_prod;
792 dma_addr_t new_mapping;
2950219d 793
fc48b7a6
YM		 794 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
795 *curr_prod = *curr_cons;
2950219d 796
fc48b7a6
YM		 797 new_mapping = curr_prod->mapping + curr_prod->page_offset;
798
799 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
800 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 801
2950219d 802 rxq->sw_rx_prod++;
fc48b7a6
YM		 803 curr_cons->data = NULL;
804}
805
f86af2df
MC		 806/* In case of allocation failures reuse buffers
807 * from consumer index to produce buffers for firmware
808 */
809static void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
810 struct qede_dev *edev, u8 count)
811{
812 struct sw_rx_data *curr_cons;
813
814 for (; count > 0; count--) {
815 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
816 qede_reuse_page(edev, rxq, curr_cons);
817 qede_rx_bd_ring_consume(rxq);
818 }
819}
820
fc48b7a6
YM		 821static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
822 struct qede_rx_queue *rxq,
823 struct sw_rx_data *curr_cons)
824{
825 /* Move to the next segment in the page */
826 curr_cons->page_offset += rxq->rx_buf_seg_size;
827
828 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 829 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
830 /* Since we failed to allocate new buffer
831 * current buffer can be used again.
832 */
833 curr_cons->page_offset -= rxq->rx_buf_seg_size;
834
fc48b7a6 835 return -ENOMEM;
f86af2df 836 }
fc48b7a6
YM		 837
838 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
839 PAGE_SIZE, DMA_FROM_DEVICE);
840 } else {
841 /* Increment refcount of the page as we don't want
842 * network stack to take the ownership of the page
843 * which can be recycled multiple times by the driver.
844 */
845 atomic_inc(&curr_cons->data->_count);
846 qede_reuse_page(edev, rxq, curr_cons);
847 }
848
849 return 0;
2950219d
YM		 850}
851
852static inline void qede_update_rx_prod(struct qede_dev *edev,
853 struct qede_rx_queue *rxq)
854{
855 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
856 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
857 struct eth_rx_prod_data rx_prods = {0};
858
859 /* Update producers */
860 rx_prods.bd_prod = cpu_to_le16(bd_prod);
861 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
862
863 /* Make sure that the BD and SGE data is updated before updating the
864 * producers since FW might read the BD/SGE right after the producer
865 * is updated.
866 */
867 wmb();
868
869 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
870 (u32 *)&rx_prods);
871
872 /* mmiowb is needed to synchronize doorbell writes from more than one
873 * processor. It guarantees that the write arrives to the device before
874 * the napi lock is released and another qede_poll is called (possibly
875 * on another CPU). Without this barrier, the next doorbell can bypass
876 * this doorbell. This is applicable to IA64/Altix systems.
877 */
878 mmiowb();
879}
880
881static u32 qede_get_rxhash(struct qede_dev *edev,
882 u8 bitfields,
883 __le32 rss_hash,
884 enum pkt_hash_types *rxhash_type)
885{
886 enum rss_hash_type htype;
887
888 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
889
890 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
891 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
892 (htype == RSS_HASH_TYPE_IPV6)) ?
893 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
894 return le32_to_cpu(rss_hash);
895 }
896 *rxhash_type = PKT_HASH_TYPE_NONE;
897 return 0;
898}
899
900static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
901{
902 skb_checksum_none_assert(skb);
903
904 if (csum_flag & QEDE_CSUM_UNNECESSARY)
905 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 906
907 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
908 skb->csum_level = 1;
2950219d
YM		 909}
910
911static inline void qede_skb_receive(struct qede_dev *edev,
912 struct qede_fastpath *fp,
913 struct sk_buff *skb,
914 u16 vlan_tag)
915{
916 if (vlan_tag)
917 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
918 vlan_tag);
919
920 napi_gro_receive(&fp->napi, skb);
921}
922
55482edc
MC		 923static void qede_set_gro_params(struct qede_dev *edev,
924 struct sk_buff *skb,
925 struct eth_fast_path_rx_tpa_start_cqe *cqe)
926{
927 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
928
929 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
930 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
931 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
932 else
933 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
934
935 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
936 cqe->header_len;
937}
938
939static int qede_fill_frag_skb(struct qede_dev *edev,
940 struct qede_rx_queue *rxq,
941 u8 tpa_agg_index,
942 u16 len_on_bd)
943{
944 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
945 NUM_RX_BDS_MAX];
946 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
947 struct sk_buff *skb = tpa_info->skb;
948
949 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
950 goto out;
951
952 /* Add one frag and update the appropriate fields in the skb */
953 skb_fill_page_desc(skb, tpa_info->frag_id++,
954 current_bd->data, current_bd->page_offset,
955 len_on_bd);
956
957 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 958 /* Incr page ref count to reuse on allocation failure
959 * so that it doesn't get freed while freeing SKB.
960 */
961 atomic_inc(&current_bd->data->_count);
55482edc
MC		 962 goto out;
963 }
964
965 qed_chain_consume(&rxq->rx_bd_ring);
966 rxq->sw_rx_cons++;
967
968 skb->data_len += len_on_bd;
969 skb->truesize += rxq->rx_buf_seg_size;
970 skb->len += len_on_bd;
971
972 return 0;
973
974out:
f86af2df
MC		 975 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
976 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 977 return -ENOMEM;
978}
979
980static void qede_tpa_start(struct qede_dev *edev,
981 struct qede_rx_queue *rxq,
982 struct eth_fast_path_rx_tpa_start_cqe *cqe)
983{
984 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
985 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
986 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
987 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
988 dma_addr_t mapping = tpa_info->replace_buf_mapping;
989 struct sw_rx_data *sw_rx_data_cons;
990 struct sw_rx_data *sw_rx_data_prod;
991 enum pkt_hash_types rxhash_type;
992 u32 rxhash;
993
994 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
995 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
996
997 /* Use pre-allocated replacement buffer - we can't release the agg.
998 * start until its over and we don't want to risk allocation failing
999 * here, so re-allocate when aggregation will be over.
1000 */
1001 dma_unmap_addr_set(sw_rx_data_prod, mapping,
1002 dma_unmap_addr(replace_buf, mapping));
1003
1004 sw_rx_data_prod->data = replace_buf->data;
1005 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1006 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1007 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1008
1009 rxq->sw_rx_prod++;
1010
1011 /* move partial skb from cons to pool (don't unmap yet)
1012 * save mapping, incase we drop the packet later on.
1013 */
1014 tpa_info->start_buf = *sw_rx_data_cons;
1015 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1016 le32_to_cpu(rx_bd_cons->addr.lo));
1017
1018 tpa_info->start_buf_mapping = mapping;
1019 rxq->sw_rx_cons++;
1020
1021 /* set tpa state to start only if we are able to allocate skb
1022 * for this aggregation, otherwise mark as error and aggregation will
1023 * be dropped
1024 */
1025 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1026 le16_to_cpu(cqe->len_on_first_bd));
1027 if (unlikely(!tpa_info->skb)) {
f86af2df 1028 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1029 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1030 goto cons_buf;
55482edc
MC		 1031 }
1032
1033 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1034 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1035
1036 /* Start filling in the aggregation info */
1037 tpa_info->frag_id = 0;
1038 tpa_info->agg_state = QEDE_AGG_STATE_START;
1039
1040 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1041 cqe->rss_hash, &rxhash_type);
1042 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1043 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1044 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1045 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1046 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1047 else
1048 tpa_info->vlan_tag = 0;
1049
1050 /* This is needed in order to enable forwarding support */
1051 qede_set_gro_params(edev, tpa_info->skb, cqe);
1052
f86af2df 1053cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1054 if (likely(cqe->ext_bd_len_list[0]))
1055 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1056 le16_to_cpu(cqe->ext_bd_len_list[0]));
1057
1058 if (unlikely(cqe->ext_bd_len_list[1])) {
1059 DP_ERR(edev,
1060 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1061 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1062 }
1063}
1064
88f09bd5 1065#ifdef CONFIG_INET
55482edc
MC		 1066static void qede_gro_ip_csum(struct sk_buff *skb)
1067{
1068 const struct iphdr *iph = ip_hdr(skb);
1069 struct tcphdr *th;
1070
55482edc
MC		 1071 skb_set_transport_header(skb, sizeof(struct iphdr));
1072 th = tcp_hdr(skb);
1073
1074 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1075 iph->saddr, iph->daddr, 0);
1076
1077 tcp_gro_complete(skb);
1078}
1079
1080static void qede_gro_ipv6_csum(struct sk_buff *skb)
1081{
1082 struct ipv6hdr *iph = ipv6_hdr(skb);
1083 struct tcphdr *th;
1084
55482edc
MC		 1085 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1086 th = tcp_hdr(skb);
1087
1088 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1089 &iph->saddr, &iph->daddr, 0);
1090 tcp_gro_complete(skb);
1091}
88f09bd5 1092#endif
55482edc
MC		 1093
1094static void qede_gro_receive(struct qede_dev *edev,
1095 struct qede_fastpath *fp,
1096 struct sk_buff *skb,
1097 u16 vlan_tag)
1098{
ee2fa8e6
MC		 1099 /* FW can send a single MTU sized packet from gro flow
1100 * due to aggregation timeout/last segment etc. which
1101 * is not expected to be a gro packet. If a skb has zero
1102 * frags then simply push it in the stack as non gso skb.
1103 */
1104 if (unlikely(!skb->data_len)) {
1105 skb_shinfo(skb)->gso_type = 0;
1106 skb_shinfo(skb)->gso_size = 0;
1107 goto send_skb;
1108 }
1109
88f09bd5 1110#ifdef CONFIG_INET
55482edc 1111 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1112 skb_set_network_header(skb, 0);
1113
55482edc
MC		 1114 switch (skb->protocol) {
1115 case htons(ETH_P_IP):
1116 qede_gro_ip_csum(skb);
1117 break;
1118 case htons(ETH_P_IPV6):
1119 qede_gro_ipv6_csum(skb);
1120 break;
1121 default:
1122 DP_ERR(edev,
1123 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1124 ntohs(skb->protocol));
1125 }
1126 }
88f09bd5 1127#endif
ee2fa8e6
MC		 1128
1129send_skb:
55482edc
MC		 1130 skb_record_rx_queue(skb, fp->rss_id);
1131 qede_skb_receive(edev, fp, skb, vlan_tag);
1132}
1133
1134static inline void qede_tpa_cont(struct qede_dev *edev,
1135 struct qede_rx_queue *rxq,
1136 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1137{
1138 int i;
1139
1140 for (i = 0; cqe->len_list[i]; i++)
1141 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1142 le16_to_cpu(cqe->len_list[i]));
1143
1144 if (unlikely(i > 1))
1145 DP_ERR(edev,
1146 "Strange - TPA cont with more than a single len_list entry\n");
1147}
1148
1149static void qede_tpa_end(struct qede_dev *edev,
1150 struct qede_fastpath *fp,
1151 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1152{
1153 struct qede_rx_queue *rxq = fp->rxq;
1154 struct qede_agg_info *tpa_info;
1155 struct sk_buff *skb;
1156 int i;
1157
1158 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1159 skb = tpa_info->skb;
1160
1161 for (i = 0; cqe->len_list[i]; i++)
1162 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1163 le16_to_cpu(cqe->len_list[i]));
1164 if (unlikely(i > 1))
1165 DP_ERR(edev,
1166 "Strange - TPA emd with more than a single len_list entry\n");
1167
1168 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1169 goto err;
1170
1171 /* Sanity */
1172 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1173 DP_ERR(edev,
1174 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1175 cqe->num_of_bds, tpa_info->frag_id);
1176 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1177 DP_ERR(edev,
1178 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1179 le16_to_cpu(cqe->total_packet_len), skb->len);
1180
1181 memcpy(skb->data,
1182 page_address(tpa_info->start_buf.data) +
1183 tpa_info->start_cqe.placement_offset +
1184 tpa_info->start_buf.page_offset,
1185 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1186
1187 /* Recycle [mapped] start buffer for the next replacement */
1188 tpa_info->replace_buf = tpa_info->start_buf;
1189 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1190
1191 /* Finalize the SKB */
1192 skb->protocol = eth_type_trans(skb, edev->ndev);
1193 skb->ip_summed = CHECKSUM_UNNECESSARY;
1194
1195 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1196 * to skb_shinfo(skb)->gso_segs
1197 */
1198 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1199
1200 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1201
1202 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1203
1204 return;
1205err:
1206 /* The BD starting the aggregation is still mapped; Re-use it for
1207 * future aggregations [as replacement buffer]
1208 */
1209 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1210 sizeof(struct sw_rx_data));
1211 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1212 tpa_info->start_buf.data = NULL;
1213 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1214 dev_kfree_skb_any(tpa_info->skb);
1215 tpa_info->skb = NULL;
1216}
1217
14db81de
MC		 1218static bool qede_tunn_exist(u16 flag)
1219{
1220 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1221 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1222}
1223
1224static u8 qede_check_tunn_csum(u16 flag)
1225{
1226 u16 csum_flag = 0;
1227 u8 tcsum = 0;
1228
1229 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1230 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1231 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1232 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1233
1234 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1235 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1236 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1237 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1238 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1239 }
1240
1241 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1242 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1243 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1244 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1245
1246 if (csum_flag & flag)
1247 return QEDE_CSUM_ERROR;
1248
1249 return QEDE_CSUM_UNNECESSARY | tcsum;
1250}
1251
1252static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1253{
1254 u16 csum_flag = 0;
1255 u8 csum = 0;
1256
14db81de
MC		 1257 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1258 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1259 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1260 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1261 csum = QEDE_CSUM_UNNECESSARY;
1262 }
1263
1264 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1265 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1266
1267 if (csum_flag & flag)
1268 return QEDE_CSUM_ERROR;
1269
1270 return csum;
1271}
1272
14db81de
MC		 1273static u8 qede_check_csum(u16 flag)
1274{
1275 if (!qede_tunn_exist(flag))
1276 return qede_check_notunn_csum(flag);
1277 else
1278 return qede_check_tunn_csum(flag);
1279}
1280
2950219d
YM		 1281static int qede_rx_int(struct qede_fastpath *fp, int budget)
1282{
1283 struct qede_dev *edev = fp->edev;
1284 struct qede_rx_queue *rxq = fp->rxq;
1285
1286 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1287 int rx_pkt = 0;
1288 u8 csum_flag;
1289
1290 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1291 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1292
1293 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1294 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1295 * read before it is written by FW, then FW writes CQE and SB, and then
1296 * the CPU reads the hw_comp_cons, it will use an old CQE.
1297 */
1298 rmb();
1299
1300 /* Loop to complete all indicated BDs */
1301 while (sw_comp_cons != hw_comp_cons) {
1302 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1303 enum pkt_hash_types rxhash_type;
1304 enum eth_rx_cqe_type cqe_type;
1305 struct sw_rx_data *sw_rx_data;
1306 union eth_rx_cqe *cqe;
1307 struct sk_buff *skb;
fc48b7a6
YM		 1308 struct page *data;
1309 __le16 flags;
2950219d
YM		 1310 u16 len, pad;
1311 u32 rx_hash;
2950219d
YM		 1312
1313 /* Get the CQE from the completion ring */
1314 cqe = (union eth_rx_cqe *)
1315 qed_chain_consume(&rxq->rx_comp_ring);
1316 cqe_type = cqe->fast_path_regular.type;
1317
1318 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1319 edev->ops->eth_cqe_completion(
1320 edev->cdev, fp->rss_id,
1321 (struct eth_slow_path_rx_cqe *)cqe);
1322 goto next_cqe;
1323 }
1324
55482edc
MC		 1325 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1326 switch (cqe_type) {
1327 case ETH_RX_CQE_TYPE_TPA_START:
1328 qede_tpa_start(edev, rxq,
1329 &cqe->fast_path_tpa_start);
1330 goto next_cqe;
1331 case ETH_RX_CQE_TYPE_TPA_CONT:
1332 qede_tpa_cont(edev, rxq,
1333 &cqe->fast_path_tpa_cont);
1334 goto next_cqe;
1335 case ETH_RX_CQE_TYPE_TPA_END:
1336 qede_tpa_end(edev, fp,
1337 &cqe->fast_path_tpa_end);
1338 goto next_rx_only;
1339 default:
1340 break;
1341 }
1342 }
1343
2950219d
YM		 1344 /* Get the data from the SW ring */
1345 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1346 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1347 data = sw_rx_data->data;
1348
1349 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1350 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1351 pad = fp_cqe->placement_offset;
fc48b7a6 1352 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1353
fc48b7a6
YM		 1354 /* If this is an error packet then drop it */
1355 parse_flag = le16_to_cpu(flags);
2950219d 1356
fc48b7a6
YM		 1357 csum_flag = qede_check_csum(parse_flag);
1358 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
1359 DP_NOTICE(edev,
1360 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1361 sw_comp_cons, parse_flag);
1362 rxq->rx_hw_errors++;
f86af2df
MC		 1363 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1364 goto next_cqe;
fc48b7a6 1365 }
2950219d 1366
fc48b7a6
YM		 1367 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1368 if (unlikely(!skb)) {
2950219d 1369 DP_NOTICE(edev,
fc48b7a6 1370 "Build_skb failed, dropping incoming packet\n");
f86af2df 1371 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1372 rxq->rx_alloc_errors++;
f86af2df 1373 goto next_cqe;
fc48b7a6
YM		 1374 }
1375
1376 /* Copy data into SKB */
1377 if (len + pad <= QEDE_RX_HDR_SIZE) {
1378 memcpy(skb_put(skb, len),
1379 page_address(data) + pad +
1380 sw_rx_data->page_offset, len);
1381 qede_reuse_page(edev, rxq, sw_rx_data);
1382 } else {
1383 struct skb_frag_struct *frag;
1384 unsigned int pull_len;
1385 unsigned char *va;
1386
1387 frag = &skb_shinfo(skb)->frags[0];
1388
1389 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1390 pad + sw_rx_data->page_offset,
1391 len, rxq->rx_buf_seg_size);
1392
1393 va = skb_frag_address(frag);
1394 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1395
1396 /* Align the pull_len to optimize memcpy */
1397 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1398
1399 skb_frag_size_sub(frag, pull_len);
1400 frag->page_offset += pull_len;
1401 skb->data_len -= pull_len;
1402 skb->tail += pull_len;
1403
1404 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1405 sw_rx_data))) {
1406 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1407 /* Incr page ref count to reuse on allocation
1408 * failure so that it doesn't get freed while
1409 * freeing SKB.
1410 */
1411
1412 atomic_inc(&sw_rx_data->data->_count);
fc48b7a6 1413 rxq->rx_alloc_errors++;
f86af2df
MC		 1414 qede_recycle_rx_bd_ring(rxq, edev,
1415 fp_cqe->bd_num);
1416 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1417 goto next_cqe;
1418 }
2950219d
YM		 1419 }
1420
f86af2df
MC		 1421 qede_rx_bd_ring_consume(rxq);
1422
fc48b7a6
YM		 1423 if (fp_cqe->bd_num != 1) {
1424 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1425 u8 num_frags;
1426
1427 pkt_len -= len;
1428
1429 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1430 num_frags--) {
1431 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1432 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1433 if (unlikely(!cur_size)) {
1434 DP_ERR(edev,
1435 "Still got %d BDs for mapping jumbo, but length became 0\n",
1436 num_frags);
1437 qede_recycle_rx_bd_ring(rxq, edev,
1438 num_frags);
1439 dev_kfree_skb_any(skb);
1440 goto next_cqe;
1441 }
fc48b7a6 1442
f86af2df
MC		 1443 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1444 qede_recycle_rx_bd_ring(rxq, edev,
1445 num_frags);
1446 dev_kfree_skb_any(skb);
fc48b7a6 1447 goto next_cqe;
f86af2df 1448 }
fc48b7a6 1449
fc48b7a6
YM		 1450 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1451 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1452 qede_rx_bd_ring_consume(rxq);
1453
fc48b7a6
YM		 1454 dma_unmap_page(&edev->pdev->dev,
1455 sw_rx_data->mapping,
1456 PAGE_SIZE, DMA_FROM_DEVICE);
1457
1458 skb_fill_page_desc(skb,
1459 skb_shinfo(skb)->nr_frags++,
1460 sw_rx_data->data, 0,
1461 cur_size);
1462
1463 skb->truesize += PAGE_SIZE;
1464 skb->data_len += cur_size;
1465 skb->len += cur_size;
1466 pkt_len -= cur_size;
1467 }
2950219d 1468
f86af2df 1469 if (unlikely(pkt_len))
fc48b7a6
YM		 1470 DP_ERR(edev,
1471 "Mapped all BDs of jumbo, but still have %d bytes\n",
1472 pkt_len);
1473 }
2950219d
YM		 1474
1475 skb->protocol = eth_type_trans(skb, edev->ndev);
1476
1477 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1478 fp_cqe->rss_hash,
1479 &rxhash_type);
1480
1481 skb_set_hash(skb, rx_hash, rxhash_type);
1482
1483 qede_set_skb_csum(skb, csum_flag);
1484
1485 skb_record_rx_queue(skb, fp->rss_id);
1486
1487 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1488next_rx_only:
2950219d
YM		 1489 rx_pkt++;
1490
1491next_cqe: /* don't consume bd rx buffer */
1492 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1493 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1494 /* CR TPA - revisit how to handle budget in TPA perhaps
1495 * increase on "end"
1496 */
1497 if (rx_pkt == budget)
1498 break;
1499 } /* repeat while sw_comp_cons != hw_comp_cons... */
1500
1501 /* Update producers */
1502 qede_update_rx_prod(edev, rxq);
1503
1504 return rx_pkt;
1505}
1506
1507static int qede_poll(struct napi_struct *napi, int budget)
1508{
1509 int work_done = 0;
1510 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
1511 napi);
1512 struct qede_dev *edev = fp->edev;
1513
1514 while (1) {
1515 u8 tc;
1516
1517 for (tc = 0; tc < edev->num_tc; tc++)
1518 if (qede_txq_has_work(&fp->txqs[tc]))
1519 qede_tx_int(edev, &fp->txqs[tc]);
1520
1521 if (qede_has_rx_work(fp->rxq)) {
1522 work_done += qede_rx_int(fp, budget - work_done);
1523
1524 /* must not complete if we consumed full budget */
1525 if (work_done >= budget)
1526 break;
1527 }
1528
1529 /* Fall out from the NAPI loop if needed */
1530 if (!(qede_has_rx_work(fp->rxq) || qede_has_tx_work(fp))) {
1531 qed_sb_update_sb_idx(fp->sb_info);
1532 /* *_has_*_work() reads the status block,
1533 * thus we need to ensure that status block indices
1534 * have been actually read (qed_sb_update_sb_idx)
1535 * prior to this check (*_has_*_work) so that
1536 * we won't write the "newer" value of the status block
1537 * to HW (if there was a DMA right after
1538 * qede_has_rx_work and if there is no rmb, the memory
1539 * reading (qed_sb_update_sb_idx) may be postponed
1540 * to right before *_ack_sb). In this case there
1541 * will never be another interrupt until there is
1542 * another update of the status block, while there
1543 * is still unhandled work.
1544 */
1545 rmb();
1546
1547 if (!(qede_has_rx_work(fp->rxq) ||
1548 qede_has_tx_work(fp))) {
1549 napi_complete(napi);
1550 /* Update and reenable interrupts */
1551 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1552 1 /*update*/);
1553 break;
1554 }
1555 }
1556 }
1557
1558 return work_done;
1559}
1560
1561static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1562{
1563 struct qede_fastpath *fp = fp_cookie;
1564
1565 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1566
1567 napi_schedule_irqoff(&fp->napi);
1568 return IRQ_HANDLED;
1569}
1570
1571/* -------------------------------------------------------------------------
1572 * END OF FAST-PATH
1573 * -------------------------------------------------------------------------
1574 */
1575
1576static int qede_open(struct net_device *ndev);
1577static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1578static int qede_set_mac_addr(struct net_device *ndev, void *p);
1579static void qede_set_rx_mode(struct net_device *ndev);
1580static void qede_config_rx_mode(struct net_device *ndev);
1581
1582static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1583 enum qed_filter_xcast_params_type opcode,
1584 unsigned char mac[ETH_ALEN])
1585{
1586 struct qed_filter_params filter_cmd;
1587
1588 memset(&filter_cmd, 0, sizeof(filter_cmd));
1589 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1590 filter_cmd.filter.ucast.type = opcode;
1591 filter_cmd.filter.ucast.mac_valid = 1;
1592 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1593
1594 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1595}
1596
7c1bfcad
SRK		 1597static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1598 enum qed_filter_xcast_params_type opcode,
1599 u16 vid)
1600{
1601 struct qed_filter_params filter_cmd;
1602
1603 memset(&filter_cmd, 0, sizeof(filter_cmd));
1604 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1605 filter_cmd.filter.ucast.type = opcode;
1606 filter_cmd.filter.ucast.vlan_valid = 1;
1607 filter_cmd.filter.ucast.vlan = vid;
1608
1609 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1610}
1611
133fac0e
SK		 1612void qede_fill_by_demand_stats(struct qede_dev *edev)
1613{
1614 struct qed_eth_stats stats;
1615
1616 edev->ops->get_vport_stats(edev->cdev, &stats);
1617 edev->stats.no_buff_discards = stats.no_buff_discards;
1618 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1619 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1620 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1621 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1622 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1623 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1624 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1625 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1626
1627 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1628 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1629 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1630 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1631 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1632 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1633 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1634 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1635 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1636 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1637 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1638 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1639
1640 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
1641 edev->stats.rx_127_byte_packets = stats.rx_127_byte_packets;
1642 edev->stats.rx_255_byte_packets = stats.rx_255_byte_packets;
1643 edev->stats.rx_511_byte_packets = stats.rx_511_byte_packets;
1644 edev->stats.rx_1023_byte_packets = stats.rx_1023_byte_packets;
1645 edev->stats.rx_1518_byte_packets = stats.rx_1518_byte_packets;
1646 edev->stats.rx_1522_byte_packets = stats.rx_1522_byte_packets;
1647 edev->stats.rx_2047_byte_packets = stats.rx_2047_byte_packets;
1648 edev->stats.rx_4095_byte_packets = stats.rx_4095_byte_packets;
1649 edev->stats.rx_9216_byte_packets = stats.rx_9216_byte_packets;
1650 edev->stats.rx_16383_byte_packets = stats.rx_16383_byte_packets;
1651 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1652 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1653 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1654 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1655 edev->stats.rx_align_errors = stats.rx_align_errors;
1656 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1657 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1658 edev->stats.rx_jabbers = stats.rx_jabbers;
1659 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1660 edev->stats.rx_fragments = stats.rx_fragments;
1661 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1662 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1663 edev->stats.tx_128_to_255_byte_packets =
1664 stats.tx_128_to_255_byte_packets;
1665 edev->stats.tx_256_to_511_byte_packets =
1666 stats.tx_256_to_511_byte_packets;
1667 edev->stats.tx_512_to_1023_byte_packets =
1668 stats.tx_512_to_1023_byte_packets;
1669 edev->stats.tx_1024_to_1518_byte_packets =
1670 stats.tx_1024_to_1518_byte_packets;
1671 edev->stats.tx_1519_to_2047_byte_packets =
1672 stats.tx_1519_to_2047_byte_packets;
1673 edev->stats.tx_2048_to_4095_byte_packets =
1674 stats.tx_2048_to_4095_byte_packets;
1675 edev->stats.tx_4096_to_9216_byte_packets =
1676 stats.tx_4096_to_9216_byte_packets;
1677 edev->stats.tx_9217_to_16383_byte_packets =
1678 stats.tx_9217_to_16383_byte_packets;
1679 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1680 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1681 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1682 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1683 edev->stats.brb_truncates = stats.brb_truncates;
1684 edev->stats.brb_discards = stats.brb_discards;
1685 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1686}
1687
1688static struct rtnl_link_stats64 *qede_get_stats64(
1689 struct net_device *dev,
1690 struct rtnl_link_stats64 *stats)
1691{
1692 struct qede_dev *edev = netdev_priv(dev);
1693
1694 qede_fill_by_demand_stats(edev);
1695
1696 stats->rx_packets = edev->stats.rx_ucast_pkts +
1697 edev->stats.rx_mcast_pkts +
1698 edev->stats.rx_bcast_pkts;
1699 stats->tx_packets = edev->stats.tx_ucast_pkts +
1700 edev->stats.tx_mcast_pkts +
1701 edev->stats.tx_bcast_pkts;
1702
1703 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1704 edev->stats.rx_mcast_bytes +
1705 edev->stats.rx_bcast_bytes;
1706
1707 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1708 edev->stats.tx_mcast_bytes +
1709 edev->stats.tx_bcast_bytes;
1710
1711 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1712 stats->multicast = edev->stats.rx_mcast_pkts +
1713 edev->stats.rx_bcast_pkts;
1714
1715 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1716
1717 stats->collisions = edev->stats.tx_total_collisions;
1718 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1719 stats->rx_frame_errors = edev->stats.rx_align_errors;
1720
1721 return stats;
1722}
1723
7c1bfcad
SRK		 1724static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1725{
1726 struct qed_update_vport_params params;
1727 int rc;
1728
1729 /* Proceed only if action actually needs to be performed */
1730 if (edev->accept_any_vlan == action)
1731 return;
1732
1733 memset(&params, 0, sizeof(params));
1734
1735 params.vport_id = 0;
1736 params.accept_any_vlan = action;
1737 params.update_accept_any_vlan_flg = 1;
1738
1739 rc = edev->ops->vport_update(edev->cdev, &params);
1740 if (rc) {
1741 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1742 action ? "enable" : "disable");
1743 } else {
1744 DP_INFO(edev, "%s accept-any-vlan\n",
1745 action ? "enabled" : "disabled");
1746 edev->accept_any_vlan = action;
1747 }
1748}
1749
1750static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1751{
1752 struct qede_dev *edev = netdev_priv(dev);
1753 struct qede_vlan *vlan, *tmp;
1754 int rc;
1755
1756 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1757
1758 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1759 if (!vlan) {
1760 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1761 return -ENOMEM;
1762 }
1763 INIT_LIST_HEAD(&vlan->list);
1764 vlan->vid = vid;
1765 vlan->configured = false;
1766
1767 /* Verify vlan isn't already configured */
1768 list_for_each_entry(tmp, &edev->vlan_list, list) {
1769 if (tmp->vid == vlan->vid) {
1770 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1771 "vlan already configured\n");
1772 kfree(vlan);
1773 return -EEXIST;
1774 }
1775 }
1776
1777 /* If interface is down, cache this VLAN ID and return */
1778 if (edev->state != QEDE_STATE_OPEN) {
1779 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1780 "Interface is down, VLAN %d will be configured when interface is up\n",
1781 vid);
1782 if (vid != 0)
1783 edev->non_configured_vlans++;
1784 list_add(&vlan->list, &edev->vlan_list);
1785
1786 return 0;
1787 }
1788
1789 /* Check for the filter limit.
1790 * Note - vlan0 has a reserved filter and can be added without
1791 * worrying about quota
1792 */
1793 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1794 (vlan->vid == 0)) {
1795 rc = qede_set_ucast_rx_vlan(edev,
1796 QED_FILTER_XCAST_TYPE_ADD,
1797 vlan->vid);
1798 if (rc) {
1799 DP_ERR(edev, "Failed to configure VLAN %d\n",
1800 vlan->vid);
1801 kfree(vlan);
1802 return -EINVAL;
1803 }
1804 vlan->configured = true;
1805
1806 /* vlan0 filter isn't consuming out of our quota */
1807 if (vlan->vid != 0)
1808 edev->configured_vlans++;
1809 } else {
1810 /* Out of quota; Activate accept-any-VLAN mode */
1811 if (!edev->non_configured_vlans)
1812 qede_config_accept_any_vlan(edev, true);
1813
1814 edev->non_configured_vlans++;
1815 }
1816
1817 list_add(&vlan->list, &edev->vlan_list);
1818
1819 return 0;
1820}
1821
1822static void qede_del_vlan_from_list(struct qede_dev *edev,
1823 struct qede_vlan *vlan)
1824{
1825 /* vlan0 filter isn't consuming out of our quota */
1826 if (vlan->vid != 0) {
1827 if (vlan->configured)
1828 edev->configured_vlans--;
1829 else
1830 edev->non_configured_vlans--;
1831 }
1832
1833 list_del(&vlan->list);
1834 kfree(vlan);
1835}
1836
1837static int qede_configure_vlan_filters(struct qede_dev *edev)
1838{
1839 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1840 struct qed_dev_eth_info *dev_info;
1841 struct qede_vlan *vlan = NULL;
1842
1843 if (list_empty(&edev->vlan_list))
1844 return 0;
1845
1846 dev_info = &edev->dev_info;
1847
1848 /* Configure non-configured vlans */
1849 list_for_each_entry(vlan, &edev->vlan_list, list) {
1850 if (vlan->configured)
1851 continue;
1852
1853 /* We have used all our credits, now enable accept_any_vlan */
1854 if ((vlan->vid != 0) &&
1855 (edev->configured_vlans == dev_info->num_vlan_filters)) {
1856 accept_any_vlan = 1;
1857 continue;
1858 }
1859
1860 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
1861
1862 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
1863 vlan->vid);
1864 if (rc) {
1865 DP_ERR(edev, "Failed to configure VLAN %u\n",
1866 vlan->vid);
1867 real_rc = rc;
1868 continue;
1869 }
1870
1871 vlan->configured = true;
1872 /* vlan0 filter doesn't consume our VLAN filter's quota */
1873 if (vlan->vid != 0) {
1874 edev->non_configured_vlans--;
1875 edev->configured_vlans++;
1876 }
1877 }
1878
1879 /* enable accept_any_vlan mode if we have more VLANs than credits,
1880 * or remove accept_any_vlan mode if we've actually removed
1881 * a non-configured vlan, and all remaining vlans are truly configured.
1882 */
1883
1884 if (accept_any_vlan)
1885 qede_config_accept_any_vlan(edev, true);
1886 else if (!edev->non_configured_vlans)
1887 qede_config_accept_any_vlan(edev, false);
1888
1889 return real_rc;
1890}
1891
1892static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
1893{
1894 struct qede_dev *edev = netdev_priv(dev);
1895 struct qede_vlan *vlan = NULL;
1896 int rc;
1897
1898 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
1899
1900 /* Find whether entry exists */
1901 list_for_each_entry(vlan, &edev->vlan_list, list)
1902 if (vlan->vid == vid)
1903 break;
1904
1905 if (!vlan || (vlan->vid != vid)) {
1906 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1907 "Vlan isn't configured\n");
1908 return 0;
1909 }
1910
1911 if (edev->state != QEDE_STATE_OPEN) {
1912 /* As interface is already down, we don't have a VPORT
1913 * instance to remove vlan filter. So just update vlan list
1914 */
1915 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1916 "Interface is down, removing VLAN from list only\n");
1917 qede_del_vlan_from_list(edev, vlan);
1918 return 0;
1919 }
1920
1921 /* Remove vlan */
1922 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL, vid);
1923 if (rc) {
1924 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
1925 return -EINVAL;
1926 }
1927
1928 qede_del_vlan_from_list(edev, vlan);
1929
1930 /* We have removed a VLAN - try to see if we can
1931 * configure non-configured VLAN from the list.
1932 */
1933 rc = qede_configure_vlan_filters(edev);
1934
1935 return rc;
1936}
1937
1938static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
1939{
1940 struct qede_vlan *vlan = NULL;
1941
1942 if (list_empty(&edev->vlan_list))
1943 return;
1944
1945 list_for_each_entry(vlan, &edev->vlan_list, list) {
1946 if (!vlan->configured)
1947 continue;
1948
1949 vlan->configured = false;
1950
1951 /* vlan0 filter isn't consuming out of our quota */
1952 if (vlan->vid != 0) {
1953 edev->non_configured_vlans++;
1954 edev->configured_vlans--;
1955 }
1956
1957 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1958 "marked vlan %d as non-configured\n",
1959 vlan->vid);
1960 }
1961
1962 edev->accept_any_vlan = false;
1963}
1964
b18e170c
MC		 1965#ifdef CONFIG_QEDE_VXLAN
1966static void qede_add_vxlan_port(struct net_device *dev,
1967 sa_family_t sa_family, __be16 port)
1968{
1969 struct qede_dev *edev = netdev_priv(dev);
1970 u16 t_port = ntohs(port);
1971
1972 if (edev->vxlan_dst_port)
1973 return;
1974
1975 edev->vxlan_dst_port = t_port;
1976
1977 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d", t_port);
1978
1979 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
1980 schedule_delayed_work(&edev->sp_task, 0);
1981}
1982
1983static void qede_del_vxlan_port(struct net_device *dev,
1984 sa_family_t sa_family, __be16 port)
1985{
1986 struct qede_dev *edev = netdev_priv(dev);
1987 u16 t_port = ntohs(port);
1988
1989 if (t_port != edev->vxlan_dst_port)
1990 return;
1991
1992 edev->vxlan_dst_port = 0;
1993
1994 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d", t_port);
1995
1996 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
1997 schedule_delayed_work(&edev->sp_task, 0);
1998}
1999#endif
2000
9a109dd0
MC		 2001#ifdef CONFIG_QEDE_GENEVE
2002static void qede_add_geneve_port(struct net_device *dev,
2003 sa_family_t sa_family, __be16 port)
2004{
2005 struct qede_dev *edev = netdev_priv(dev);
2006 u16 t_port = ntohs(port);
2007
2008 if (edev->geneve_dst_port)
2009 return;
2010
2011 edev->geneve_dst_port = t_port;
2012
2013 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d", t_port);
2014 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2015 schedule_delayed_work(&edev->sp_task, 0);
2016}
2017
2018static void qede_del_geneve_port(struct net_device *dev,
2019 sa_family_t sa_family, __be16 port)
2020{
2021 struct qede_dev *edev = netdev_priv(dev);
2022 u16 t_port = ntohs(port);
2023
2024 if (t_port != edev->geneve_dst_port)
2025 return;
2026
2027 edev->geneve_dst_port = 0;
2028
2029 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d", t_port);
2030 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2031 schedule_delayed_work(&edev->sp_task, 0);
2032}
2033#endif
2034
2950219d
YM		 2035static const struct net_device_ops qede_netdev_ops = {
2036 .ndo_open = qede_open,
2037 .ndo_stop = qede_close,
2038 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2039 .ndo_set_rx_mode = qede_set_rx_mode,
2040 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2041 .ndo_validate_addr = eth_validate_addr,
133fac0e 2042 .ndo_change_mtu = qede_change_mtu,
7c1bfcad
SRK		 2043 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2044 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
133fac0e 2045 .ndo_get_stats64 = qede_get_stats64,
b18e170c
MC		 2046#ifdef CONFIG_QEDE_VXLAN
2047 .ndo_add_vxlan_port = qede_add_vxlan_port,
2048 .ndo_del_vxlan_port = qede_del_vxlan_port,
2049#endif
9a109dd0
MC		 2050#ifdef CONFIG_QEDE_GENEVE
2051 .ndo_add_geneve_port = qede_add_geneve_port,
2052 .ndo_del_geneve_port = qede_del_geneve_port,
2053#endif
2950219d
YM		 2054};
2055
e712d52b
YM		 2056/* -------------------------------------------------------------------------
2057 * START OF PROBE / REMOVE
2058 * -------------------------------------------------------------------------
2059 */
2060
2061static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2062 struct pci_dev *pdev,
2063 struct qed_dev_eth_info *info,
2064 u32 dp_module,
2065 u8 dp_level)
2066{
2067 struct net_device *ndev;
2068 struct qede_dev *edev;
2069
2070 ndev = alloc_etherdev_mqs(sizeof(*edev),
2071 info->num_queues,
2072 info->num_queues);
2073 if (!ndev) {
2074 pr_err("etherdev allocation failed\n");
2075 return NULL;
2076 }
2077
2078 edev = netdev_priv(ndev);
2079 edev->ndev = ndev;
2080 edev->cdev = cdev;
2081 edev->pdev = pdev;
2082 edev->dp_module = dp_module;
2083 edev->dp_level = dp_level;
2084 edev->ops = qed_ops;
2950219d
YM		 2085 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2086 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b
YM		 2087
2088 DP_INFO(edev, "Allocated netdev with 64 tx queues and 64 rx queues\n");
2089
2090 SET_NETDEV_DEV(ndev, &pdev->dev);
2091
133fac0e 2092 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2093 memcpy(&edev->dev_info, info, sizeof(*info));
2094
2095 edev->num_tc = edev->dev_info.num_tc;
2096
7c1bfcad
SRK		 2097 INIT_LIST_HEAD(&edev->vlan_list);
2098
e712d52b
YM		 2099 return edev;
2100}
2101
2102static void qede_init_ndev(struct qede_dev *edev)
2103{
2104 struct net_device *ndev = edev->ndev;
2105 struct pci_dev *pdev = edev->pdev;
2106 u32 hw_features;
2107
2108 pci_set_drvdata(pdev, ndev);
2109
2110 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2111 ndev->base_addr = ndev->mem_start;
2112 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2113 ndev->irq = edev->dev_info.common.pci_irq;
2114
2115 ndev->watchdog_timeo = TX_TIMEOUT;
2116
2950219d
YM		 2117 ndev->netdev_ops = &qede_netdev_ops;
2118
133fac0e
SK		 2119 qede_set_ethtool_ops(ndev);
2120
e712d52b
YM		 2121 /* user-changeble features */
2122 hw_features = NETIF_F_GRO | NETIF_F_SG |
2123 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2124 NETIF_F_TSO | NETIF_F_TSO6;
2125
14db81de
MC		 2126 /* Encap features*/
2127 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2128 NETIF_F_TSO_ECN;
2129 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2130 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2131 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2132 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2133
e712d52b
YM		 2134 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2135 NETIF_F_HIGHDMA;
2136 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2137 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2138 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2139
2140 ndev->hw_features = hw_features;
2141
2142 /* Set network device HW mac */
2143 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2144}
2145
2146/* This function converts from 32b param to two params of level and module
2147 * Input 32b decoding:
2148 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2149 * 'happy' flow, e.g. memory allocation failed.
2150 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2151 * and provide important parameters.
2152 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2153 * module. VERBOSE prints are for tracking the specific flow in low level.
2154 *
2155 * Notice that the level should be that of the lowest required logs.
2156 */
133fac0e 2157void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2158{
2159 *p_dp_level = QED_LEVEL_NOTICE;
2160 *p_dp_module = 0;
2161
2162 if (debug & QED_LOG_VERBOSE_MASK) {
2163 *p_dp_level = QED_LEVEL_VERBOSE;
2164 *p_dp_module = (debug & 0x3FFFFFFF);
2165 } else if (debug & QED_LOG_INFO_MASK) {
2166 *p_dp_level = QED_LEVEL_INFO;
2167 } else if (debug & QED_LOG_NOTICE_MASK) {
2168 *p_dp_level = QED_LEVEL_NOTICE;
2169 }
2170}
2171
2950219d
YM		 2172static void qede_free_fp_array(struct qede_dev *edev)
2173{
2174 if (edev->fp_array) {
2175 struct qede_fastpath *fp;
2176 int i;
2177
2178 for_each_rss(i) {
2179 fp = &edev->fp_array[i];
2180
2181 kfree(fp->sb_info);
2182 kfree(fp->rxq);
2183 kfree(fp->txqs);
2184 }
2185 kfree(edev->fp_array);
2186 }
2187 edev->num_rss = 0;
2188}
2189
2190static int qede_alloc_fp_array(struct qede_dev *edev)
2191{
2192 struct qede_fastpath *fp;
2193 int i;
2194
2195 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2196 sizeof(*edev->fp_array), GFP_KERNEL);
2197 if (!edev->fp_array) {
2198 DP_NOTICE(edev, "fp array allocation failed\n");
2199 goto err;
2200 }
2201
2202 for_each_rss(i) {
2203 fp = &edev->fp_array[i];
2204
2205 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2206 if (!fp->sb_info) {
2207 DP_NOTICE(edev, "sb info struct allocation failed\n");
2208 goto err;
2209 }
2210
2211 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2212 if (!fp->rxq) {
2213 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2214 goto err;
2215 }
2216
2217 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2218 if (!fp->txqs) {
2219 DP_NOTICE(edev, "TXQ array allocation failed\n");
2220 goto err;
2221 }
2222 }
2223
2224 return 0;
2225err:
2226 qede_free_fp_array(edev);
2227 return -ENOMEM;
2228}
2229
0d8e0aa0
SK		 2230static void qede_sp_task(struct work_struct *work)
2231{
2232 struct qede_dev *edev = container_of(work, struct qede_dev,
2233 sp_task.work);
b18e170c
MC		 2234 struct qed_dev *cdev = edev->cdev;
2235
0d8e0aa0
SK		 2236 mutex_lock(&edev->qede_lock);
2237
2238 if (edev->state == QEDE_STATE_OPEN) {
2239 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2240 qede_config_rx_mode(edev->ndev);
2241 }
2242
b18e170c
MC		 2243 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2244 struct qed_tunn_params tunn_params;
2245
2246 memset(&tunn_params, 0, sizeof(tunn_params));
2247 tunn_params.update_vxlan_port = 1;
2248 tunn_params.vxlan_port = edev->vxlan_dst_port;
2249 qed_ops->tunn_config(cdev, &tunn_params);
2250 }
2251
9a109dd0
MC		 2252 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2253 struct qed_tunn_params tunn_params;
2254
2255 memset(&tunn_params, 0, sizeof(tunn_params));
2256 tunn_params.update_geneve_port = 1;
2257 tunn_params.geneve_port = edev->geneve_dst_port;
2258 qed_ops->tunn_config(cdev, &tunn_params);
2259 }
2260
0d8e0aa0
SK		 2261 mutex_unlock(&edev->qede_lock);
2262}
2263
e712d52b
YM		 2264static void qede_update_pf_params(struct qed_dev *cdev)
2265{
2266 struct qed_pf_params pf_params;
2267
2268 /* 16 rx + 16 tx */
2269 memset(&pf_params, 0, sizeof(struct qed_pf_params));
2270 pf_params.eth_pf_params.num_cons = 32;
2271 qed_ops->common->update_pf_params(cdev, &pf_params);
2272}
2273
2274enum qede_probe_mode {
2275 QEDE_PROBE_NORMAL,
2276};
2277
2278static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
2279 enum qede_probe_mode mode)
2280{
2281 struct qed_slowpath_params params;
2282 struct qed_dev_eth_info dev_info;
2283 struct qede_dev *edev;
2284 struct qed_dev *cdev;
2285 int rc;
2286
2287 if (unlikely(dp_level & QED_LEVEL_INFO))
2288 pr_notice("Starting qede probe\n");
2289
2290 cdev = qed_ops->common->probe(pdev, QED_PROTOCOL_ETH,
2291 dp_module, dp_level);
2292 if (!cdev) {
2293 rc = -ENODEV;
2294 goto err0;
2295 }
2296
2297 qede_update_pf_params(cdev);
2298
2299 /* Start the Slowpath-process */
2300 memset(&params, 0, sizeof(struct qed_slowpath_params));
2301 params.int_mode = QED_INT_MODE_MSIX;
2302 params.drv_major = QEDE_MAJOR_VERSION;
2303 params.drv_minor = QEDE_MINOR_VERSION;
2304 params.drv_rev = QEDE_REVISION_VERSION;
2305 params.drv_eng = QEDE_ENGINEERING_VERSION;
2306 strlcpy(params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2307 rc = qed_ops->common->slowpath_start(cdev, &params);
2308 if (rc) {
2309 pr_notice("Cannot start slowpath\n");
2310 goto err1;
2311 }
2312
2313 /* Learn information crucial for qede to progress */
2314 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2315 if (rc)
2316 goto err2;
2317
2318 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2319 dp_level);
2320 if (!edev) {
2321 rc = -ENOMEM;
2322 goto err2;
2323 }
2324
2325 qede_init_ndev(edev);
2326
2950219d
YM		 2327 rc = register_netdev(edev->ndev);
2328 if (rc) {
2329 DP_NOTICE(edev, "Cannot register net-device\n");
2330 goto err3;
2331 }
2332
e712d52b
YM		 2333 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2334
a2ec6172
SK		 2335 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2336
0d8e0aa0
SK		 2337 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2338 mutex_init(&edev->qede_lock);
2339
e712d52b
YM		 2340 DP_INFO(edev, "Ending successfully qede probe\n");
2341
2342 return 0;
2343
2950219d
YM		 2344err3:
2345 free_netdev(edev->ndev);
e712d52b
YM		 2346err2:
2347 qed_ops->common->slowpath_stop(cdev);
2348err1:
2349 qed_ops->common->remove(cdev);
2350err0:
2351 return rc;
2352}
2353
2354static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2355{
2356 u32 dp_module = 0;
2357 u8 dp_level = 0;
2358
2359 qede_config_debug(debug, &dp_module, &dp_level);
2360
2361 return __qede_probe(pdev, dp_module, dp_level,
2362 QEDE_PROBE_NORMAL);
2363}
2364
2365enum qede_remove_mode {
2366 QEDE_REMOVE_NORMAL,
2367};
2368
2369static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2370{
2371 struct net_device *ndev = pci_get_drvdata(pdev);
2372 struct qede_dev *edev = netdev_priv(ndev);
2373 struct qed_dev *cdev = edev->cdev;
2374
2375 DP_INFO(edev, "Starting qede_remove\n");
2376
0d8e0aa0 2377 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2378 unregister_netdev(ndev);
2379
e712d52b
YM		 2380 edev->ops->common->set_power_state(cdev, PCI_D0);
2381
2382 pci_set_drvdata(pdev, NULL);
2383
2384 free_netdev(ndev);
2385
2386 /* Use global ops since we've freed edev */
2387 qed_ops->common->slowpath_stop(cdev);
2388 qed_ops->common->remove(cdev);
2389
2390 pr_notice("Ending successfully qede_remove\n");
2391}
2392
2393static void qede_remove(struct pci_dev *pdev)
2394{
2395 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2396}
2950219d
YM		 2397
2398/* -------------------------------------------------------------------------
2399 * START OF LOAD / UNLOAD
2400 * -------------------------------------------------------------------------
2401 */
2402
2403static int qede_set_num_queues(struct qede_dev *edev)
2404{
2405 int rc;
2406 u16 rss_num;
2407
2408 /* Setup queues according to possible resources*/
8edf049d
SK		 2409 if (edev->req_rss)
2410 rss_num = edev->req_rss;
2411 else
2412 rss_num = netif_get_num_default_rss_queues() *
2413 edev->dev_info.common.num_hwfns;
2950219d
YM		 2414
2415 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2416
2417 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2418 if (rc > 0) {
2419 /* Managed to request interrupts for our queues */
2420 edev->num_rss = rc;
2421 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2422 QEDE_RSS_CNT(edev), rss_num);
2423 rc = 0;
2424 }
2425 return rc;
2426}
2427
2428static void qede_free_mem_sb(struct qede_dev *edev,
2429 struct qed_sb_info *sb_info)
2430{
2431 if (sb_info->sb_virt)
2432 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2433 (void *)sb_info->sb_virt, sb_info->sb_phys);
2434}
2435
2436/* This function allocates fast-path status block memory */
2437static int qede_alloc_mem_sb(struct qede_dev *edev,
2438 struct qed_sb_info *sb_info,
2439 u16 sb_id)
2440{
2441 struct status_block *sb_virt;
2442 dma_addr_t sb_phys;
2443 int rc;
2444
2445 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
2446 sizeof(*sb_virt),
2447 &sb_phys, GFP_KERNEL);
2448 if (!sb_virt) {
2449 DP_ERR(edev, "Status block allocation failed\n");
2450 return -ENOMEM;
2451 }
2452
2453 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2454 sb_virt, sb_phys, sb_id,
2455 QED_SB_TYPE_L2_QUEUE);
2456 if (rc) {
2457 DP_ERR(edev, "Status block initialization failed\n");
2458 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2459 sb_virt, sb_phys);
2460 return rc;
2461 }
2462
2463 return 0;
2464}
2465
2466static void qede_free_rx_buffers(struct qede_dev *edev,
2467 struct qede_rx_queue *rxq)
2468{
2469 u16 i;
2470
2471 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2472 struct sw_rx_data *rx_buf;
fc48b7a6 2473 struct page *data;
2950219d
YM		 2474
2475 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2476 data = rx_buf->data;
2477
fc48b7a6
YM		 2478 dma_unmap_page(&edev->pdev->dev,
2479 rx_buf->mapping,
2480 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2481
2482 rx_buf->data = NULL;
fc48b7a6 2483 __free_page(data);
2950219d
YM		 2484 }
2485}
2486
55482edc
MC		 2487static void qede_free_sge_mem(struct qede_dev *edev,
2488 struct qede_rx_queue *rxq) {
2489 int i;
2490
2491 if (edev->gro_disable)
2492 return;
2493
2494 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2495 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2496 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2497
f86af2df 2498 if (replace_buf->data) {
55482edc
MC		 2499 dma_unmap_page(&edev->pdev->dev,
2500 dma_unmap_addr(replace_buf, mapping),
2501 PAGE_SIZE, DMA_FROM_DEVICE);
2502 __free_page(replace_buf->data);
2503 }
2504 }
2505}
2506
2950219d
YM		 2507static void qede_free_mem_rxq(struct qede_dev *edev,
2508 struct qede_rx_queue *rxq)
2509{
55482edc
MC		 2510 qede_free_sge_mem(edev, rxq);
2511
2950219d
YM		 2512 /* Free rx buffers */
2513 qede_free_rx_buffers(edev, rxq);
2514
2515 /* Free the parallel SW ring */
2516 kfree(rxq->sw_rx_ring);
2517
2518 /* Free the real RQ ring used by FW */
2519 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2520 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2521}
2522
2523static int qede_alloc_rx_buffer(struct qede_dev *edev,
2524 struct qede_rx_queue *rxq)
2525{
2526 struct sw_rx_data *sw_rx_data;
2527 struct eth_rx_bd *rx_bd;
2528 dma_addr_t mapping;
fc48b7a6 2529 struct page *data;
2950219d 2530 u16 rx_buf_size;
2950219d
YM		 2531
2532 rx_buf_size = rxq->rx_buf_size;
2533
fc48b7a6 2534 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2535 if (unlikely(!data)) {
fc48b7a6 2536 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2537 return -ENOMEM;
2538 }
2539
fc48b7a6
YM		 2540 /* Map the entire page as it would be used
2541 * for multiple RX buffer segment size mapping.
2542 */
2543 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2544 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2545 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2546 __free_page(data);
2950219d
YM		 2547 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2548 return -ENOMEM;
2549 }
2550
2551 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2552 sw_rx_data->page_offset = 0;
2950219d 2553 sw_rx_data->data = data;
fc48b7a6 2554 sw_rx_data->mapping = mapping;
2950219d
YM		 2555
2556 /* Advance PROD and get BD pointer */
2557 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2558 WARN_ON(!rx_bd);
2559 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2560 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2561
2562 rxq->sw_rx_prod++;
2563
2564 return 0;
2565}
2566
55482edc
MC		 2567static int qede_alloc_sge_mem(struct qede_dev *edev,
2568 struct qede_rx_queue *rxq)
2569{
2570 dma_addr_t mapping;
2571 int i;
2572
2573 if (edev->gro_disable)
2574 return 0;
2575
2576 if (edev->ndev->mtu > PAGE_SIZE) {
2577 edev->gro_disable = 1;
2578 return 0;
2579 }
2580
2581 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2582 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2583 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2584
2585 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2586 if (unlikely(!replace_buf->data)) {
2587 DP_NOTICE(edev,
2588 "Failed to allocate TPA skb pool [replacement buffer]\n");
2589 goto err;
2590 }
2591
2592 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2593 rxq->rx_buf_size, DMA_FROM_DEVICE);
2594 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2595 DP_NOTICE(edev,
2596 "Failed to map TPA replacement buffer\n");
2597 goto err;
2598 }
2599
2600 dma_unmap_addr_set(replace_buf, mapping, mapping);
2601 tpa_info->replace_buf.page_offset = 0;
2602
2603 tpa_info->replace_buf_mapping = mapping;
2604 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2605 }
2606
2607 return 0;
2608err:
2609 qede_free_sge_mem(edev, rxq);
2610 edev->gro_disable = 1;
2611 return -ENOMEM;
2612}
2613
2950219d
YM		 2614/* This function allocates all memory needed per Rx queue */
2615static int qede_alloc_mem_rxq(struct qede_dev *edev,
2616 struct qede_rx_queue *rxq)
2617{
f86af2df 2618 int i, rc, size;
2950219d
YM		 2619
2620 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2621
fc48b7a6
YM		 2622 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD +
2623 edev->ndev->mtu;
2624 if (rxq->rx_buf_size > PAGE_SIZE)
2625 rxq->rx_buf_size = PAGE_SIZE;
2626
2627 /* Segment size to spilt a page in multiple equal parts */
2628 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2629
2630 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2631 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2632 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2633 if (!rxq->sw_rx_ring) {
2634 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2635 rc = -ENOMEM;
2950219d
YM		 2636 goto err;
2637 }
2638
2639 /* Allocate FW Rx ring */
2640 rc = edev->ops->common->chain_alloc(edev->cdev,
2641 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2642 QED_CHAIN_MODE_NEXT_PTR,
fc48b7a6 2643 RX_RING_SIZE,
2950219d
YM		 2644 sizeof(struct eth_rx_bd),
2645 &rxq->rx_bd_ring);
2646
2647 if (rc)
2648 goto err;
2649
2650 /* Allocate FW completion ring */
2651 rc = edev->ops->common->chain_alloc(edev->cdev,
2652 QED_CHAIN_USE_TO_CONSUME,
2653 QED_CHAIN_MODE_PBL,
fc48b7a6 2654 RX_RING_SIZE,
2950219d
YM		 2655 sizeof(union eth_rx_cqe),
2656 &rxq->rx_comp_ring);
2657 if (rc)
2658 goto err;
2659
2660 /* Allocate buffers for the Rx ring */
2661 for (i = 0; i < rxq->num_rx_buffers; i++) {
2662 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2663 if (rc) {
2664 DP_ERR(edev,
2665 "Rx buffers allocation failed at index %d\n", i);
2666 goto err;
2667 }
2950219d
YM		 2668 }
2669
f86af2df 2670 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2671err:
f86af2df 2672 return rc;
2950219d
YM		 2673}
2674
2675static void qede_free_mem_txq(struct qede_dev *edev,
2676 struct qede_tx_queue *txq)
2677{
2678 /* Free the parallel SW ring */
2679 kfree(txq->sw_tx_ring);
2680
2681 /* Free the real RQ ring used by FW */
2682 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2683}
2684
2685/* This function allocates all memory needed per Tx queue */
2686static int qede_alloc_mem_txq(struct qede_dev *edev,
2687 struct qede_tx_queue *txq)
2688{
2689 int size, rc;
2690 union eth_tx_bd_types *p_virt;
2691
2692 txq->num_tx_buffers = edev->q_num_tx_buffers;
2693
2694 /* Allocate the parallel driver ring for Tx buffers */
2695 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2696 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2697 if (!txq->sw_tx_ring) {
2698 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2699 goto err;
2700 }
2701
2702 rc = edev->ops->common->chain_alloc(edev->cdev,
2703 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2704 QED_CHAIN_MODE_PBL,
2705 NUM_TX_BDS_MAX,
2706 sizeof(*p_virt),
2707 &txq->tx_pbl);
2708 if (rc)
2709 goto err;
2710
2711 return 0;
2712
2713err:
2714 qede_free_mem_txq(edev, txq);
2715 return -ENOMEM;
2716}
2717
2718/* This function frees all memory of a single fp */
2719static void qede_free_mem_fp(struct qede_dev *edev,
2720 struct qede_fastpath *fp)
2721{
2722 int tc;
2723
2724 qede_free_mem_sb(edev, fp->sb_info);
2725
2726 qede_free_mem_rxq(edev, fp->rxq);
2727
2728 for (tc = 0; tc < edev->num_tc; tc++)
2729 qede_free_mem_txq(edev, &fp->txqs[tc]);
2730}
2731
2732/* This function allocates all memory needed for a single fp (i.e. an entity
2733 * which contains status block, one rx queue and multiple per-TC tx queues.
2734 */
2735static int qede_alloc_mem_fp(struct qede_dev *edev,
2736 struct qede_fastpath *fp)
2737{
2738 int rc, tc;
2739
2740 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2741 if (rc)
2742 goto err;
2743
2744 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2745 if (rc)
2746 goto err;
2747
2748 for (tc = 0; tc < edev->num_tc; tc++) {
2749 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2750 if (rc)
2751 goto err;
2752 }
2753
2754 return 0;
2950219d 2755err:
f86af2df 2756 return rc;
2950219d
YM		 2757}
2758
2759static void qede_free_mem_load(struct qede_dev *edev)
2760{
2761 int i;
2762
2763 for_each_rss(i) {
2764 struct qede_fastpath *fp = &edev->fp_array[i];
2765
2766 qede_free_mem_fp(edev, fp);
2767 }
2768}
2769
2770/* This function allocates all qede memory at NIC load. */
2771static int qede_alloc_mem_load(struct qede_dev *edev)
2772{
2773 int rc = 0, rss_id;
2774
2775 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2776 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2777
2778 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2779 if (rc) {
2950219d 2780 DP_ERR(edev,
f86af2df
MC		 2781 "Failed to allocate memory for fastpath - rss id = %d\n",
2782 rss_id);
2783 qede_free_mem_load(edev);
2784 return rc;
2950219d 2785 }
2950219d
YM		 2786 }
2787
2788 return 0;
2789}
2790
2791/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2792static void qede_init_fp(struct qede_dev *edev)
2793{
2794 int rss_id, txq_index, tc;
2795 struct qede_fastpath *fp;
2796
2797 for_each_rss(rss_id) {
2798 fp = &edev->fp_array[rss_id];
2799
2800 fp->edev = edev;
2801 fp->rss_id = rss_id;
2802
2803 memset((void *)&fp->napi, 0, sizeof(fp->napi));
2804
2805 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
2806
2807 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
2808 fp->rxq->rxq_id = rss_id;
2809
2810 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
2811 for (tc = 0; tc < edev->num_tc; tc++) {
2812 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
2813 fp->txqs[tc].index = txq_index;
2814 }
2815
2816 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
2817 edev->ndev->name, rss_id);
2818 }
55482edc
MC		 2819
2820 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 2821}
2822
2823static int qede_set_real_num_queues(struct qede_dev *edev)
2824{
2825 int rc = 0;
2826
2827 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
2828 if (rc) {
2829 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
2830 return rc;
2831 }
2832 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
2833 if (rc) {
2834 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
2835 return rc;
2836 }
2837
2838 return 0;
2839}
2840
2841static void qede_napi_disable_remove(struct qede_dev *edev)
2842{
2843 int i;
2844
2845 for_each_rss(i) {
2846 napi_disable(&edev->fp_array[i].napi);
2847
2848 netif_napi_del(&edev->fp_array[i].napi);
2849 }
2850}
2851
2852static void qede_napi_add_enable(struct qede_dev *edev)
2853{
2854 int i;
2855
2856 /* Add NAPI objects */
2857 for_each_rss(i) {
2858 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
2859 qede_poll, NAPI_POLL_WEIGHT);
2860 napi_enable(&edev->fp_array[i].napi);
2861 }
2862}
2863
2864static void qede_sync_free_irqs(struct qede_dev *edev)
2865{
2866 int i;
2867
2868 for (i = 0; i < edev->int_info.used_cnt; i++) {
2869 if (edev->int_info.msix_cnt) {
2870 synchronize_irq(edev->int_info.msix[i].vector);
2871 free_irq(edev->int_info.msix[i].vector,
2872 &edev->fp_array[i]);
2873 } else {
2874 edev->ops->common->simd_handler_clean(edev->cdev, i);
2875 }
2876 }
2877
2878 edev->int_info.used_cnt = 0;
2879}
2880
2881static int qede_req_msix_irqs(struct qede_dev *edev)
2882{
2883 int i, rc;
2884
2885 /* Sanitize number of interrupts == number of prepared RSS queues */
2886 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
2887 DP_ERR(edev,
2888 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
2889 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
2890 return -EINVAL;
2891 }
2892
2893 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
2894 rc = request_irq(edev->int_info.msix[i].vector,
2895 qede_msix_fp_int, 0, edev->fp_array[i].name,
2896 &edev->fp_array[i]);
2897 if (rc) {
2898 DP_ERR(edev, "Request fp %d irq failed\n", i);
2899 qede_sync_free_irqs(edev);
2900 return rc;
2901 }
2902 DP_VERBOSE(edev, NETIF_MSG_INTR,
2903 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
2904 edev->fp_array[i].name, i,
2905 &edev->fp_array[i]);
2906 edev->int_info.used_cnt++;
2907 }
2908
2909 return 0;
2910}
2911
2912static void qede_simd_fp_handler(void *cookie)
2913{
2914 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
2915
2916 napi_schedule_irqoff(&fp->napi);
2917}
2918
2919static int qede_setup_irqs(struct qede_dev *edev)
2920{
2921 int i, rc = 0;
2922
2923 /* Learn Interrupt configuration */
2924 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
2925 if (rc)
2926 return rc;
2927
2928 if (edev->int_info.msix_cnt) {
2929 rc = qede_req_msix_irqs(edev);
2930 if (rc)
2931 return rc;
2932 edev->ndev->irq = edev->int_info.msix[0].vector;
2933 } else {
2934 const struct qed_common_ops *ops;
2935
2936 /* qed should learn receive the RSS ids and callbacks */
2937 ops = edev->ops->common;
2938 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
2939 ops->simd_handler_config(edev->cdev,
2940 &edev->fp_array[i], i,
2941 qede_simd_fp_handler);
2942 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
2943 }
2944 return 0;
2945}
2946
2947static int qede_drain_txq(struct qede_dev *edev,
2948 struct qede_tx_queue *txq,
2949 bool allow_drain)
2950{
2951 int rc, cnt = 1000;
2952
2953 while (txq->sw_tx_cons != txq->sw_tx_prod) {
2954 if (!cnt) {
2955 if (allow_drain) {
2956 DP_NOTICE(edev,
2957 "Tx queue[%d] is stuck, requesting MCP to drain\n",
2958 txq->index);
2959 rc = edev->ops->common->drain(edev->cdev);
2960 if (rc)
2961 return rc;
2962 return qede_drain_txq(edev, txq, false);
2963 }
2964 DP_NOTICE(edev,
2965 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
2966 txq->index, txq->sw_tx_prod,
2967 txq->sw_tx_cons);
2968 return -ENODEV;
2969 }
2970 cnt--;
2971 usleep_range(1000, 2000);
2972 barrier();
2973 }
2974
2975 /* FW finished processing, wait for HW to transmit all tx packets */
2976 usleep_range(1000, 2000);
2977
2978 return 0;
2979}
2980
2981static int qede_stop_queues(struct qede_dev *edev)
2982{
2983 struct qed_update_vport_params vport_update_params;
2984 struct qed_dev *cdev = edev->cdev;
2985 int rc, tc, i;
2986
2987 /* Disable the vport */
2988 memset(&vport_update_params, 0, sizeof(vport_update_params));
2989 vport_update_params.vport_id = 0;
2990 vport_update_params.update_vport_active_flg = 1;
2991 vport_update_params.vport_active_flg = 0;
2992 vport_update_params.update_rss_flg = 0;
2993
2994 rc = edev->ops->vport_update(cdev, &vport_update_params);
2995 if (rc) {
2996 DP_ERR(edev, "Failed to update vport\n");
2997 return rc;
2998 }
2999
3000 /* Flush Tx queues. If needed, request drain from MCP */
3001 for_each_rss(i) {
3002 struct qede_fastpath *fp = &edev->fp_array[i];
3003
3004 for (tc = 0; tc < edev->num_tc; tc++) {
3005 struct qede_tx_queue *txq = &fp->txqs[tc];
3006
3007 rc = qede_drain_txq(edev, txq, true);
3008 if (rc)
3009 return rc;
3010 }
3011 }
3012
3013 /* Stop all Queues in reverse order*/
3014 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3015 struct qed_stop_rxq_params rx_params;
3016
3017 /* Stop the Tx Queue(s)*/
3018 for (tc = 0; tc < edev->num_tc; tc++) {
3019 struct qed_stop_txq_params tx_params;
3020
3021 tx_params.rss_id = i;
3022 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3023 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3024 if (rc) {
3025 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3026 tx_params.tx_queue_id);
3027 return rc;
3028 }
3029 }
3030
3031 /* Stop the Rx Queue*/
3032 memset(&rx_params, 0, sizeof(rx_params));
3033 rx_params.rss_id = i;
3034 rx_params.rx_queue_id = i;
3035
3036 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3037 if (rc) {
3038 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3039 return rc;
3040 }
3041 }
3042
3043 /* Stop the vport */
3044 rc = edev->ops->vport_stop(cdev, 0);
3045 if (rc)
3046 DP_ERR(edev, "Failed to stop VPORT\n");
3047
3048 return rc;
3049}
3050
3051static int qede_start_queues(struct qede_dev *edev)
3052{
3053 int rc, tc, i;
088c8618 3054 int vlan_removal_en = 1;
2950219d 3055 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3056 struct qed_update_vport_params vport_update_params;
3057 struct qed_queue_start_common_params q_params;
088c8618 3058 struct qed_start_vport_params start = {0};
961acdea 3059 bool reset_rss_indir = false;
2950219d
YM		 3060
3061 if (!edev->num_rss) {
3062 DP_ERR(edev,
3063 "Cannot update V-VPORT as active as there are no Rx queues\n");
3064 return -EINVAL;
3065 }
3066
55482edc 3067 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3068 start.mtu = edev->ndev->mtu;
3069 start.vport_id = 0;
3070 start.drop_ttl0 = true;
3071 start.remove_inner_vlan = vlan_removal_en;
3072
3073 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3074
3075 if (rc) {
3076 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3077 return rc;
3078 }
3079
3080 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3081 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3082 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3083
3084 for_each_rss(i) {
3085 struct qede_fastpath *fp = &edev->fp_array[i];
3086 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3087
3088 memset(&q_params, 0, sizeof(q_params));
3089 q_params.rss_id = i;
3090 q_params.queue_id = i;
3091 q_params.vport_id = 0;
3092 q_params.sb = fp->sb_info->igu_sb_id;
3093 q_params.sb_idx = RX_PI;
3094
3095 rc = edev->ops->q_rx_start(cdev, &q_params,
3096 fp->rxq->rx_buf_size,
3097 fp->rxq->rx_bd_ring.p_phys_addr,
3098 phys_table,
3099 fp->rxq->rx_comp_ring.page_cnt,
3100 &fp->rxq->hw_rxq_prod_addr);
3101 if (rc) {
3102 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3103 return rc;
3104 }
3105
3106 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3107
3108 qede_update_rx_prod(edev, fp->rxq);
3109
3110 for (tc = 0; tc < edev->num_tc; tc++) {
3111 struct qede_tx_queue *txq = &fp->txqs[tc];
3112 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3113
3114 memset(&q_params, 0, sizeof(q_params));
3115 q_params.rss_id = i;
3116 q_params.queue_id = txq_index;
3117 q_params.vport_id = 0;
3118 q_params.sb = fp->sb_info->igu_sb_id;
3119 q_params.sb_idx = TX_PI(tc);
3120
3121 rc = edev->ops->q_tx_start(cdev, &q_params,
3122 txq->tx_pbl.pbl.p_phys_table,
3123 txq->tx_pbl.page_cnt,
3124 &txq->doorbell_addr);
3125 if (rc) {
3126 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3127 txq_index, rc);
3128 return rc;
3129 }
3130
3131 txq->hw_cons_ptr =
3132 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3133 SET_FIELD(txq->tx_db.data.params,
3134 ETH_DB_DATA_DEST, DB_DEST_XCM);
3135 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3136 DB_AGG_CMD_SET);
3137 SET_FIELD(txq->tx_db.data.params,
3138 ETH_DB_DATA_AGG_VAL_SEL,
3139 DQ_XCM_ETH_TX_BD_PROD_CMD);
3140
3141 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3142 }
3143 }
3144
3145 /* Prepare and send the vport enable */
3146 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3147 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3148 vport_update_params.update_vport_active_flg = 1;
3149 vport_update_params.vport_active_flg = 1;
3150
3151 /* Fill struct with RSS params */
3152 if (QEDE_RSS_CNT(edev) > 1) {
3153 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3154
3155 /* Need to validate current RSS config uses valid entries */
3156 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3157 if (edev->rss_params.rss_ind_table[i] >=
3158 edev->num_rss) {
3159 reset_rss_indir = true;
3160 break;
3161 }
3162 }
3163
3164 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3165 reset_rss_indir) {
3166 u16 val;
3167
3168 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3169 u16 indir_val;
3170
3171 val = QEDE_RSS_CNT(edev);
3172 indir_val = ethtool_rxfh_indir_default(i, val);
3173 edev->rss_params.rss_ind_table[i] = indir_val;
3174 }
3175 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3176 }
3177
3178 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3179 netdev_rss_key_fill(edev->rss_params.rss_key,
3180 sizeof(edev->rss_params.rss_key));
3181 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3182 }
3183
3184 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3185 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3186 QED_RSS_IPV6 |
3187 QED_RSS_IPV4_TCP |
3188 QED_RSS_IPV6_TCP;
3189 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3190 }
3191
3192 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3193 sizeof(vport_update_params.rss_params));
2950219d 3194 } else {
961acdea
SRK		 3195 memset(&vport_update_params.rss_params, 0,
3196 sizeof(vport_update_params.rss_params));
2950219d 3197 }
2950219d
YM		 3198
3199 rc = edev->ops->vport_update(cdev, &vport_update_params);
3200 if (rc) {
3201 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3202 return rc;
3203 }
3204
3205 return 0;
3206}
3207
0d8e0aa0
SK		 3208static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3209 enum qed_filter_xcast_params_type opcode,
3210 unsigned char *mac, int num_macs)
3211{
3212 struct qed_filter_params filter_cmd;
3213 int i;
3214
3215 memset(&filter_cmd, 0, sizeof(filter_cmd));
3216 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3217 filter_cmd.filter.mcast.type = opcode;
3218 filter_cmd.filter.mcast.num = num_macs;
3219
3220 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3221 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3222
3223 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3224}
3225
2950219d
YM		 3226enum qede_unload_mode {
3227 QEDE_UNLOAD_NORMAL,
3228};
3229
3230static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3231{
a2ec6172 3232 struct qed_link_params link_params;
2950219d
YM		 3233 int rc;
3234
3235 DP_INFO(edev, "Starting qede unload\n");
3236
0d8e0aa0
SK		 3237 mutex_lock(&edev->qede_lock);
3238 edev->state = QEDE_STATE_CLOSED;
3239
2950219d
YM		 3240 /* Close OS Tx */
3241 netif_tx_disable(edev->ndev);
3242 netif_carrier_off(edev->ndev);
3243
a2ec6172
SK		 3244 /* Reset the link */
3245 memset(&link_params, 0, sizeof(link_params));
3246 link_params.link_up = false;
3247 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3248 rc = qede_stop_queues(edev);
3249 if (rc) {
3250 qede_sync_free_irqs(edev);
3251 goto out;
3252 }
3253
3254 DP_INFO(edev, "Stopped Queues\n");
3255
7c1bfcad 3256 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3257 edev->ops->fastpath_stop(edev->cdev);
3258
3259 /* Release the interrupts */
3260 qede_sync_free_irqs(edev);
3261 edev->ops->common->set_fp_int(edev->cdev, 0);
3262
3263 qede_napi_disable_remove(edev);
3264
3265 qede_free_mem_load(edev);
3266 qede_free_fp_array(edev);
3267
3268out:
3269 mutex_unlock(&edev->qede_lock);
3270 DP_INFO(edev, "Ending qede unload\n");
3271}
3272
3273enum qede_load_mode {
3274 QEDE_LOAD_NORMAL,
3275};
3276
3277static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3278{
a2ec6172
SK		 3279 struct qed_link_params link_params;
3280 struct qed_link_output link_output;
2950219d
YM		 3281 int rc;
3282
3283 DP_INFO(edev, "Starting qede load\n");
3284
3285 rc = qede_set_num_queues(edev);
3286 if (rc)
3287 goto err0;
3288
3289 rc = qede_alloc_fp_array(edev);
3290 if (rc)
3291 goto err0;
3292
3293 qede_init_fp(edev);
3294
3295 rc = qede_alloc_mem_load(edev);
3296 if (rc)
3297 goto err1;
3298 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3299 QEDE_RSS_CNT(edev), edev->num_tc);
3300
3301 rc = qede_set_real_num_queues(edev);
3302 if (rc)
3303 goto err2;
3304
3305 qede_napi_add_enable(edev);
3306 DP_INFO(edev, "Napi added and enabled\n");
3307
3308 rc = qede_setup_irqs(edev);
3309 if (rc)
3310 goto err3;
3311 DP_INFO(edev, "Setup IRQs succeeded\n");
3312
3313 rc = qede_start_queues(edev);
3314 if (rc)
3315 goto err4;
3316 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3317
3318 /* Add primary mac and set Rx filters */
3319 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3320
0d8e0aa0
SK		 3321 mutex_lock(&edev->qede_lock);
3322 edev->state = QEDE_STATE_OPEN;
3323 mutex_unlock(&edev->qede_lock);
a2ec6172 3324
7c1bfcad
SRK		 3325 /* Program un-configured VLANs */
3326 qede_configure_vlan_filters(edev);
3327
a2ec6172
SK		 3328 /* Ask for link-up using current configuration */
3329 memset(&link_params, 0, sizeof(link_params));
3330 link_params.link_up = true;
3331 edev->ops->common->set_link(edev->cdev, &link_params);
3332
3333 /* Query whether link is already-up */
3334 memset(&link_output, 0, sizeof(link_output));
3335 edev->ops->common->get_link(edev->cdev, &link_output);
3336 qede_link_update(edev, &link_output);
3337
2950219d
YM		 3338 DP_INFO(edev, "Ending successfully qede load\n");
3339
3340 return 0;
3341
3342err4:
3343 qede_sync_free_irqs(edev);
3344 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3345err3:
3346 qede_napi_disable_remove(edev);
3347err2:
3348 qede_free_mem_load(edev);
3349err1:
3350 edev->ops->common->set_fp_int(edev->cdev, 0);
3351 qede_free_fp_array(edev);
3352 edev->num_rss = 0;
3353err0:
3354 return rc;
3355}
3356
133fac0e
SK		 3357void qede_reload(struct qede_dev *edev,
3358 void (*func)(struct qede_dev *, union qede_reload_args *),
3359 union qede_reload_args *args)
3360{
3361 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3362 /* Call function handler to update parameters
3363 * needed for function load.
3364 */
3365 if (func)
3366 func(edev, args);
3367
3368 qede_load(edev, QEDE_LOAD_NORMAL);
3369
3370 mutex_lock(&edev->qede_lock);
3371 qede_config_rx_mode(edev->ndev);
3372 mutex_unlock(&edev->qede_lock);
3373}
3374
2950219d
YM		 3375/* called with rtnl_lock */
3376static int qede_open(struct net_device *ndev)
3377{
3378 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3379 int rc;
2950219d
YM		 3380
3381 netif_carrier_off(ndev);
3382
3383 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3384
b18e170c
MC		 3385 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3386
3387 if (rc)
3388 return rc;
3389
3390#ifdef CONFIG_QEDE_VXLAN
3391 vxlan_get_rx_port(ndev);
9a109dd0
MC		 3392#endif
3393#ifdef CONFIG_QEDE_GENEVE
3394 geneve_get_rx_port(ndev);
b18e170c
MC		 3395#endif
3396 return 0;
2950219d
YM		 3397}
3398
3399static int qede_close(struct net_device *ndev)
3400{
3401 struct qede_dev *edev = netdev_priv(ndev);
3402
3403 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3404
3405 return 0;
3406}
0d8e0aa0 3407
a2ec6172
SK		 3408static void qede_link_update(void *dev, struct qed_link_output *link)
3409{
3410 struct qede_dev *edev = dev;
3411
3412 if (!netif_running(edev->ndev)) {
3413 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3414 return;
3415 }
3416
3417 if (link->link_up) {
8e025ae2
YM		 3418 if (!netif_carrier_ok(edev->ndev)) {
3419 DP_NOTICE(edev, "Link is up\n");
3420 netif_tx_start_all_queues(edev->ndev);
3421 netif_carrier_on(edev->ndev);
3422 }
a2ec6172 3423 } else {
8e025ae2
YM		 3424 if (netif_carrier_ok(edev->ndev)) {
3425 DP_NOTICE(edev, "Link is down\n");
3426 netif_tx_disable(edev->ndev);
3427 netif_carrier_off(edev->ndev);
3428 }
a2ec6172
SK		 3429 }
3430}
3431
0d8e0aa0
SK		 3432static int qede_set_mac_addr(struct net_device *ndev, void *p)
3433{
3434 struct qede_dev *edev = netdev_priv(ndev);
3435 struct sockaddr *addr = p;
3436 int rc;
3437
3438 ASSERT_RTNL(); /* @@@TBD To be removed */
3439
3440 DP_INFO(edev, "Set_mac_addr called\n");
3441
3442 if (!is_valid_ether_addr(addr->sa_data)) {
3443 DP_NOTICE(edev, "The MAC address is not valid\n");
3444 return -EFAULT;
3445 }
3446
3447 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3448
3449 if (!netif_running(ndev)) {
3450 DP_NOTICE(edev, "The device is currently down\n");
3451 return 0;
3452 }
3453
3454 /* Remove the previous primary mac */
3455 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3456 edev->primary_mac);
3457 if (rc)
3458 return rc;
3459
3460 /* Add MAC filter according to the new unicast HW MAC address */
3461 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3462 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3463 edev->primary_mac);
3464}
3465
3466static int
3467qede_configure_mcast_filtering(struct net_device *ndev,
3468 enum qed_filter_rx_mode_type *accept_flags)
3469{
3470 struct qede_dev *edev = netdev_priv(ndev);
3471 unsigned char *mc_macs, *temp;
3472 struct netdev_hw_addr *ha;
3473 int rc = 0, mc_count;
3474 size_t size;
3475
3476 size = 64 * ETH_ALEN;
3477
3478 mc_macs = kzalloc(size, GFP_KERNEL);
3479 if (!mc_macs) {
3480 DP_NOTICE(edev,
3481 "Failed to allocate memory for multicast MACs\n");
3482 rc = -ENOMEM;
3483 goto exit;
3484 }
3485
3486 temp = mc_macs;
3487
3488 /* Remove all previously configured MAC filters */
3489 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3490 mc_macs, 1);
3491 if (rc)
3492 goto exit;
3493
3494 netif_addr_lock_bh(ndev);
3495
3496 mc_count = netdev_mc_count(ndev);
3497 if (mc_count < 64) {
3498 netdev_for_each_mc_addr(ha, ndev) {
3499 ether_addr_copy(temp, ha->addr);
3500 temp += ETH_ALEN;
3501 }
3502 }
3503
3504 netif_addr_unlock_bh(ndev);
3505
3506 /* Check for all multicast @@@TBD resource allocation */
3507 if ((ndev->flags & IFF_ALLMULTI) ||
3508 (mc_count > 64)) {
3509 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3510 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3511 } else {
3512 /* Add all multicast MAC filters */
3513 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3514 mc_macs, mc_count);
3515 }
3516
3517exit:
3518 kfree(mc_macs);
3519 return rc;
3520}
3521
3522static void qede_set_rx_mode(struct net_device *ndev)
3523{
3524 struct qede_dev *edev = netdev_priv(ndev);
3525
3526 DP_INFO(edev, "qede_set_rx_mode called\n");
3527
3528 if (edev->state != QEDE_STATE_OPEN) {
3529 DP_INFO(edev,
3530 "qede_set_rx_mode called while interface is down\n");
3531 } else {
3532 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3533 schedule_delayed_work(&edev->sp_task, 0);
3534 }
3535}
3536
3537/* Must be called with qede_lock held */
3538static void qede_config_rx_mode(struct net_device *ndev)
3539{
3540 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3541 struct qede_dev *edev = netdev_priv(ndev);
3542 struct qed_filter_params rx_mode;
3543 unsigned char *uc_macs, *temp;
3544 struct netdev_hw_addr *ha;
3545 int rc, uc_count;
3546 size_t size;
3547
3548 netif_addr_lock_bh(ndev);
3549
3550 uc_count = netdev_uc_count(ndev);
3551 size = uc_count * ETH_ALEN;
3552
3553 uc_macs = kzalloc(size, GFP_ATOMIC);
3554 if (!uc_macs) {
3555 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3556 netif_addr_unlock_bh(ndev);
3557 return;
3558 }
3559
3560 temp = uc_macs;
3561 netdev_for_each_uc_addr(ha, ndev) {
3562 ether_addr_copy(temp, ha->addr);
3563 temp += ETH_ALEN;
3564 }
3565
3566 netif_addr_unlock_bh(ndev);
3567
3568 /* Configure the struct for the Rx mode */
3569 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3570 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3571
3572 /* Remove all previous unicast secondary macs and multicast macs
3573 * (configrue / leave the primary mac)
3574 */
3575 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3576 edev->primary_mac);
3577 if (rc)
3578 goto out;
3579
3580 /* Check for promiscuous */
3581 if ((ndev->flags & IFF_PROMISC) ||
3582 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3583 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3584 } else {
3585 /* Add MAC filters according to the unicast secondary macs */
3586 int i;
3587
3588 temp = uc_macs;
3589 for (i = 0; i < uc_count; i++) {
3590 rc = qede_set_ucast_rx_mac(edev,
3591 QED_FILTER_XCAST_TYPE_ADD,
3592 temp);
3593 if (rc)
3594 goto out;
3595
3596 temp += ETH_ALEN;
3597 }
3598
3599 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3600 if (rc)
3601 goto out;
3602 }
3603
7c1bfcad
SRK		 3604 /* take care of VLAN mode */
3605 if (ndev->flags & IFF_PROMISC) {
3606 qede_config_accept_any_vlan(edev, true);
3607 } else if (!edev->non_configured_vlans) {
3608 /* It's possible that accept_any_vlan mode is set due to a
3609 * previous setting of IFF_PROMISC. If vlan credits are
3610 * sufficient, disable accept_any_vlan.
3611 */
3612 qede_config_accept_any_vlan(edev, false);
3613 }
3614
0d8e0aa0
SK		 3615 rx_mode.filter.accept_flags = accept_flags;
3616 edev->ops->filter_config(edev->cdev, &rx_mode);
3617out:
3618 kfree(uc_macs);
3619}
Linux kernel - Deliverables
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