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qede: Add support for handling IP fragmented packets.
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
f9f082a9 27#include <net/udp_tunnel.h>
e712d52b
YM		 28#include <linux/ip.h>
29#include <net/ipv6.h>
30#include <net/tcp.h>
31#include <linux/if_ether.h>
32#include <linux/if_vlan.h>
33#include <linux/pkt_sched.h>
34#include <linux/ethtool.h>
35#include <linux/in.h>
36#include <linux/random.h>
37#include <net/ip6_checksum.h>
38#include <linux/bitops.h>
39
40#include "qede.h"
41
5abd7e92
YM		 42static char version[] =
43 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 44
5abd7e92 45MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
49static uint debug;
50module_param(debug, uint, 0);
51MODULE_PARM_DESC(debug, " Default debug msglevel");
52
53static const struct qed_eth_ops *qed_ops;
54
55#define CHIP_NUM_57980S_40 0x1634
0e7441d7 56#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 57#define CHIP_NUM_57980S_MF 0x1636
58#define CHIP_NUM_57980S_100 0x1644
59#define CHIP_NUM_57980S_50 0x1654
60#define CHIP_NUM_57980S_25 0x1656
fefb0202 61#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 62
63#ifndef PCI_DEVICE_ID_NX2_57980E
64#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
65#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
66#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
67#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
68#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
69#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 70#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 71#endif
72
fefb0202
YM		 73enum qede_pci_private {
74 QEDE_PRIVATE_PF,
75 QEDE_PRIVATE_VF
76};
77
e712d52b 78static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 79 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
80 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
81 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
82 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
83 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 85#ifdef CONFIG_QED_SRIOV
fefb0202 86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
14b84e86 87#endif
e712d52b
YM		 88 { 0 }
89};
90
91MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
92
93static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
94
95#define TX_TIMEOUT (5 * HZ)
96
97static void qede_remove(struct pci_dev *pdev);
2950219d
YM		 98static int qede_alloc_rx_buffer(struct qede_dev *edev,
99 struct qede_rx_queue *rxq);
a2ec6172 100static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 101
fefb0202 102#ifdef CONFIG_QED_SRIOV
08feecd7
YM		 103static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
104{
105 struct qede_dev *edev = netdev_priv(ndev);
106
107 if (vlan > 4095) {
108 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
109 return -EINVAL;
110 }
111
112 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
113 vlan, vf);
114
115 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
116}
117
eff16960
YM		 118static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
119{
120 struct qede_dev *edev = netdev_priv(ndev);
121
122 DP_VERBOSE(edev, QED_MSG_IOV,
123 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
124 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
125
126 if (!is_valid_ether_addr(mac)) {
127 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
128 return -EINVAL;
129 }
130
131 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
132}
133
fefb0202
YM		 134static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
135{
136 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e
YM		 137 struct qed_dev_info *qed_info = &edev->dev_info.common;
138 int rc;
fefb0202
YM		 139
140 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
141
831bfb0e
YM		 142 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
143
144 /* Enable/Disable Tx switching for PF */
145 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
146 qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
147 struct qed_update_vport_params params;
148
149 memset(&params, 0, sizeof(params));
150 params.vport_id = 0;
151 params.update_tx_switching_flg = 1;
152 params.tx_switching_flg = num_vfs_param ? 1 : 0;
153 edev->ops->vport_update(edev->cdev, &params);
154 }
155
156 return rc;
fefb0202
YM		 157}
158#endif
159
e712d52b
YM		 160static struct pci_driver qede_pci_driver = {
161 .name = "qede",
162 .id_table = qede_pci_tbl,
163 .probe = qede_probe,
164 .remove = qede_remove,
fefb0202
YM		 165#ifdef CONFIG_QED_SRIOV
166 .sriov_configure = qede_sriov_configure,
167#endif
e712d52b
YM		 168};
169
eff16960
YM		 170static void qede_force_mac(void *dev, u8 *mac)
171{
172 struct qede_dev *edev = dev;
173
174 ether_addr_copy(edev->ndev->dev_addr, mac);
175 ether_addr_copy(edev->primary_mac, mac);
176}
177
a2ec6172
SK		 178static struct qed_eth_cb_ops qede_ll_ops = {
179 {
180 .link_update = qede_link_update,
181 },
eff16960 182 .force_mac = qede_force_mac,
a2ec6172
SK		 183};
184
2950219d
YM		 185static int qede_netdev_event(struct notifier_block *this, unsigned long event,
186 void *ptr)
187{
188 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
189 struct ethtool_drvinfo drvinfo;
190 struct qede_dev *edev;
191
192 /* Currently only support name change */
193 if (event != NETDEV_CHANGENAME)
194 goto done;
195
196 /* Check whether this is a qede device */
197 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
198 goto done;
199
200 memset(&drvinfo, 0, sizeof(drvinfo));
201 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
202 if (strcmp(drvinfo.driver, "qede"))
203 goto done;
204 edev = netdev_priv(ndev);
205
206 /* Notify qed of the name change */
207 if (!edev->ops || !edev->ops->common)
208 goto done;
209 edev->ops->common->set_id(edev->cdev, edev->ndev->name,
210 "qede");
211
212done:
213 return NOTIFY_DONE;
214}
215
216static struct notifier_block qede_netdev_notifier = {
217 .notifier_call = qede_netdev_event,
218};
219
e712d52b
YM		 220static
221int __init qede_init(void)
222{
223 int ret;
e712d52b
YM		 224
225 pr_notice("qede_init: %s\n", version);
226
95114344 227 qed_ops = qed_get_eth_ops();
e712d52b
YM		 228 if (!qed_ops) {
229 pr_notice("Failed to get qed ethtool operations\n");
230 return -EINVAL;
231 }
232
2950219d
YM		 233 /* Must register notifier before pci ops, since we might miss
234 * interface rename after pci probe and netdev registeration.
235 */
236 ret = register_netdevice_notifier(&qede_netdev_notifier);
237 if (ret) {
238 pr_notice("Failed to register netdevice_notifier\n");
239 qed_put_eth_ops();
240 return -EINVAL;
241 }
242
e712d52b
YM		 243 ret = pci_register_driver(&qede_pci_driver);
244 if (ret) {
245 pr_notice("Failed to register driver\n");
2950219d 246 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 247 qed_put_eth_ops();
248 return -EINVAL;
249 }
250
251 return 0;
252}
253
254static void __exit qede_cleanup(void)
255{
256 pr_notice("qede_cleanup called\n");
257
2950219d 258 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 259 pci_unregister_driver(&qede_pci_driver);
260 qed_put_eth_ops();
261}
262
263module_init(qede_init);
264module_exit(qede_cleanup);
265
2950219d
YM		 266/* -------------------------------------------------------------------------
267 * START OF FAST-PATH
268 * -------------------------------------------------------------------------
269 */
270
271/* Unmap the data and free skb */
272static int qede_free_tx_pkt(struct qede_dev *edev,
273 struct qede_tx_queue *txq,
274 int *len)
275{
276 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
277 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
278 struct eth_tx_1st_bd *first_bd;
279 struct eth_tx_bd *tx_data_bd;
280 int bds_consumed = 0;
281 int nbds;
282 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
283 int i, split_bd_len = 0;
284
285 if (unlikely(!skb)) {
286 DP_ERR(edev,
287 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
288 idx, txq->sw_tx_cons, txq->sw_tx_prod);
289 return -1;
290 }
291
292 *len = skb->len;
293
294 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
295
296 bds_consumed++;
297
298 nbds = first_bd->data.nbds;
299
300 if (data_split) {
301 struct eth_tx_bd *split = (struct eth_tx_bd *)
302 qed_chain_consume(&txq->tx_pbl);
303 split_bd_len = BD_UNMAP_LEN(split);
304 bds_consumed++;
305 }
306 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
307 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
308
309 /* Unmap the data of the skb frags */
310 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
311 tx_data_bd = (struct eth_tx_bd *)
312 qed_chain_consume(&txq->tx_pbl);
313 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
314 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
315 }
316
317 while (bds_consumed++ < nbds)
318 qed_chain_consume(&txq->tx_pbl);
319
320 /* Free skb */
321 dev_kfree_skb_any(skb);
322 txq->sw_tx_ring[idx].skb = NULL;
323 txq->sw_tx_ring[idx].flags = 0;
324
325 return 0;
326}
327
328/* Unmap the data and free skb when mapping failed during start_xmit */
329static void qede_free_failed_tx_pkt(struct qede_dev *edev,
330 struct qede_tx_queue *txq,
331 struct eth_tx_1st_bd *first_bd,
332 int nbd,
333 bool data_split)
334{
335 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
336 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
337 struct eth_tx_bd *tx_data_bd;
338 int i, split_bd_len = 0;
339
340 /* Return prod to its position before this skb was handled */
341 qed_chain_set_prod(&txq->tx_pbl,
342 le16_to_cpu(txq->tx_db.data.bd_prod),
343 first_bd);
344
345 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
346
347 if (data_split) {
348 struct eth_tx_bd *split = (struct eth_tx_bd *)
349 qed_chain_produce(&txq->tx_pbl);
350 split_bd_len = BD_UNMAP_LEN(split);
351 nbd--;
352 }
353
354 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
355 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
356
357 /* Unmap the data of the skb frags */
358 for (i = 0; i < nbd; i++) {
359 tx_data_bd = (struct eth_tx_bd *)
360 qed_chain_produce(&txq->tx_pbl);
361 if (tx_data_bd->nbytes)
362 dma_unmap_page(&edev->pdev->dev,
363 BD_UNMAP_ADDR(tx_data_bd),
364 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
365 }
366
367 /* Return again prod to its position before this skb was handled */
368 qed_chain_set_prod(&txq->tx_pbl,
369 le16_to_cpu(txq->tx_db.data.bd_prod),
370 first_bd);
371
372 /* Free skb */
373 dev_kfree_skb_any(skb);
374 txq->sw_tx_ring[idx].skb = NULL;
375 txq->sw_tx_ring[idx].flags = 0;
376}
377
378static u32 qede_xmit_type(struct qede_dev *edev,
379 struct sk_buff *skb,
380 int *ipv6_ext)
381{
382 u32 rc = XMIT_L4_CSUM;
383 __be16 l3_proto;
384
385 if (skb->ip_summed != CHECKSUM_PARTIAL)
386 return XMIT_PLAIN;
387
388 l3_proto = vlan_get_protocol(skb);
389 if (l3_proto == htons(ETH_P_IPV6) &&
390 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
391 *ipv6_ext = 1;
392
14db81de
MC		 393 if (skb->encapsulation)
394 rc |= XMIT_ENC;
395
2950219d
YM		 396 if (skb_is_gso(skb))
397 rc |= XMIT_LSO;
398
399 return rc;
400}
401
402static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
403 struct eth_tx_2nd_bd *second_bd,
404 struct eth_tx_3rd_bd *third_bd)
405{
406 u8 l4_proto;
fc48b7a6 407 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 408
fc48b7a6 409 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 410
fc48b7a6 411 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 412 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
413 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
414
fc48b7a6 415 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 416 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
417
418 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
419 l4_proto = ipv6_hdr(skb)->nexthdr;
420 else
421 l4_proto = ip_hdr(skb)->protocol;
422
423 if (l4_proto == IPPROTO_UDP)
fc48b7a6 424 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 425
fc48b7a6 426 if (third_bd)
2950219d 427 third_bd->data.bitfields |=
fc48b7a6
YM		 428 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
429 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
430 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 431
fc48b7a6 432 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 433 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
434}
435
436static int map_frag_to_bd(struct qede_dev *edev,
437 skb_frag_t *frag,
438 struct eth_tx_bd *bd)
439{
440 dma_addr_t mapping;
441
442 /* Map skb non-linear frag data for DMA */
443 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
444 skb_frag_size(frag),
445 DMA_TO_DEVICE);
446 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
447 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
448 return -ENOMEM;
449 }
450
451 /* Setup the data pointer of the frag data */
452 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
453
454 return 0;
455}
456
14db81de
MC		 457static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
458{
459 if (is_encap_pkt)
460 return (skb_inner_transport_header(skb) +
461 inner_tcp_hdrlen(skb) - skb->data);
462 else
463 return (skb_transport_header(skb) +
464 tcp_hdrlen(skb) - skb->data);
465}
466
b1199b10
YM		 467/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
468#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
469static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
470 u8 xmit_type)
471{
472 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
473
474 if (xmit_type & XMIT_LSO) {
475 int hlen;
476
14db81de 477 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 478
479 /* linear payload would require its own BD */
480 if (skb_headlen(skb) > hlen)
481 allowed_frags--;
482 }
483
484 return (skb_shinfo(skb)->nr_frags > allowed_frags);
485}
486#endif
487
2950219d
YM		 488/* Main transmit function */
489static
490netdev_tx_t qede_start_xmit(struct sk_buff *skb,
491 struct net_device *ndev)
492{
493 struct qede_dev *edev = netdev_priv(ndev);
494 struct netdev_queue *netdev_txq;
495 struct qede_tx_queue *txq;
496 struct eth_tx_1st_bd *first_bd;
497 struct eth_tx_2nd_bd *second_bd = NULL;
498 struct eth_tx_3rd_bd *third_bd = NULL;
499 struct eth_tx_bd *tx_data_bd = NULL;
500 u16 txq_index;
501 u8 nbd = 0;
502 dma_addr_t mapping;
503 int rc, frag_idx = 0, ipv6_ext = 0;
504 u8 xmit_type;
505 u16 idx;
506 u16 hlen;
810810ff 507 bool data_split = false;
2950219d
YM		 508
509 /* Get tx-queue context and netdev index */
510 txq_index = skb_get_queue_mapping(skb);
511 WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
512 txq = QEDE_TX_QUEUE(edev, txq_index);
513 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
514
2950219d
YM		 515 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) <
516 (MAX_SKB_FRAGS + 1));
517
518 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
519
b1199b10
YM		 520#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
521 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
522 if (skb_linearize(skb)) {
523 DP_NOTICE(edev,
524 "SKB linearization failed - silently dropping this SKB\n");
525 dev_kfree_skb_any(skb);
526 return NETDEV_TX_OK;
527 }
528 }
529#endif
530
2950219d
YM		 531 /* Fill the entry in the SW ring and the BDs in the FW ring */
532 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
533 txq->sw_tx_ring[idx].skb = skb;
534 first_bd = (struct eth_tx_1st_bd *)
535 qed_chain_produce(&txq->tx_pbl);
536 memset(first_bd, 0, sizeof(*first_bd));
537 first_bd->data.bd_flags.bitfields =
538 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
539
540 /* Map skb linear data for DMA and set in the first BD */
541 mapping = dma_map_single(&edev->pdev->dev, skb->data,
542 skb_headlen(skb), DMA_TO_DEVICE);
543 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
544 DP_NOTICE(edev, "SKB mapping failed\n");
545 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
546 return NETDEV_TX_OK;
547 }
548 nbd++;
549 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
550
551 /* In case there is IPv6 with extension headers or LSO we need 2nd and
552 * 3rd BDs.
553 */
554 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
555 second_bd = (struct eth_tx_2nd_bd *)
556 qed_chain_produce(&txq->tx_pbl);
557 memset(second_bd, 0, sizeof(*second_bd));
558
559 nbd++;
560 third_bd = (struct eth_tx_3rd_bd *)
561 qed_chain_produce(&txq->tx_pbl);
562 memset(third_bd, 0, sizeof(*third_bd));
563
564 nbd++;
565 /* We need to fill in additional data in second_bd... */
566 tx_data_bd = (struct eth_tx_bd *)second_bd;
567 }
568
569 if (skb_vlan_tag_present(skb)) {
570 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
571 first_bd->data.bd_flags.bitfields |=
572 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
573 }
574
575 /* Fill the parsing flags & params according to the requested offload */
576 if (xmit_type & XMIT_L4_CSUM) {
577 /* We don't re-calculate IP checksum as it is already done by
578 * the upper stack
579 */
580 first_bd->data.bd_flags.bitfields |=
581 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
582
14db81de
MC		 583 if (xmit_type & XMIT_ENC) {
584 first_bd->data.bd_flags.bitfields |=
585 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
351a4ded
YM		 586 first_bd->data.bitfields |=
587 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
14db81de 588 }
fc48b7a6 589
2950219d
YM		 590 /* If the packet is IPv6 with extension header, indicate that
591 * to FW and pass few params, since the device cracker doesn't
592 * support parsing IPv6 with extension header/s.
593 */
594 if (unlikely(ipv6_ext))
595 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
596 }
597
598 if (xmit_type & XMIT_LSO) {
599 first_bd->data.bd_flags.bitfields |=
600 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
601 third_bd->data.lso_mss =
602 cpu_to_le16(skb_shinfo(skb)->gso_size);
603
14db81de
MC		 604 if (unlikely(xmit_type & XMIT_ENC)) {
605 first_bd->data.bd_flags.bitfields |=
606 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
607 hlen = qede_get_skb_hlen(skb, true);
608 } else {
609 first_bd->data.bd_flags.bitfields |=
610 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
611 hlen = qede_get_skb_hlen(skb, false);
612 }
2950219d
YM		 613
614 /* @@@TBD - if will not be removed need to check */
615 third_bd->data.bitfields |=
fc48b7a6 616 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 617
618 /* Make life easier for FW guys who can't deal with header and
619 * data on same BD. If we need to split, use the second bd...
620 */
621 if (unlikely(skb_headlen(skb) > hlen)) {
622 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
623 "TSO split header size is %d (%x:%x)\n",
624 first_bd->nbytes, first_bd->addr.hi,
625 first_bd->addr.lo);
626
627 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
628 le32_to_cpu(first_bd->addr.lo)) +
629 hlen;
630
631 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
632 le16_to_cpu(first_bd->nbytes) -
633 hlen);
634
635 /* this marks the BD as one that has no
636 * individual mapping
637 */
638 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
639
640 first_bd->nbytes = cpu_to_le16(hlen);
641
642 tx_data_bd = (struct eth_tx_bd *)third_bd;
643 data_split = true;
644 }
351a4ded
YM		 645 } else {
646 first_bd->data.bitfields |=
647 (skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) <<
648 ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2950219d
YM		 649 }
650
651 /* Handle fragmented skb */
652 /* special handle for frags inside 2nd and 3rd bds.. */
653 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
654 rc = map_frag_to_bd(edev,
655 &skb_shinfo(skb)->frags[frag_idx],
656 tx_data_bd);
657 if (rc) {
658 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
659 data_split);
660 return NETDEV_TX_OK;
661 }
662
663 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
664 tx_data_bd = (struct eth_tx_bd *)third_bd;
665 else
666 tx_data_bd = NULL;
667
668 frag_idx++;
669 }
670
671 /* map last frags into 4th, 5th .... */
672 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
673 tx_data_bd = (struct eth_tx_bd *)
674 qed_chain_produce(&txq->tx_pbl);
675
676 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
677
678 rc = map_frag_to_bd(edev,
679 &skb_shinfo(skb)->frags[frag_idx],
680 tx_data_bd);
681 if (rc) {
682 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
683 data_split);
684 return NETDEV_TX_OK;
685 }
686 }
687
688 /* update the first BD with the actual num BDs */
689 first_bd->data.nbds = nbd;
690
691 netdev_tx_sent_queue(netdev_txq, skb->len);
692
693 skb_tx_timestamp(skb);
694
695 /* Advance packet producer only before sending the packet since mapping
696 * of pages may fail.
697 */
698 txq->sw_tx_prod++;
699
700 /* 'next page' entries are counted in the producer value */
701 txq->tx_db.data.bd_prod =
702 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
703
704 /* wmb makes sure that the BDs data is updated before updating the
705 * producer, otherwise FW may read old data from the BDs.
706 */
707 wmb();
708 barrier();
709 writel(txq->tx_db.raw, txq->doorbell_addr);
710
711 /* mmiowb is needed to synchronize doorbell writes from more than one
712 * processor. It guarantees that the write arrives to the device before
713 * the queue lock is released and another start_xmit is called (possibly
714 * on another CPU). Without this barrier, the next doorbell can bypass
715 * this doorbell. This is applicable to IA64/Altix systems.
716 */
717 mmiowb();
718
719 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
720 < (MAX_SKB_FRAGS + 1))) {
721 netif_tx_stop_queue(netdev_txq);
722 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
723 "Stop queue was called\n");
724 /* paired memory barrier is in qede_tx_int(), we have to keep
725 * ordering of set_bit() in netif_tx_stop_queue() and read of
726 * fp->bd_tx_cons
727 */
728 smp_mb();
729
730 if (qed_chain_get_elem_left(&txq->tx_pbl)
731 >= (MAX_SKB_FRAGS + 1) &&
732 (edev->state == QEDE_STATE_OPEN)) {
733 netif_tx_wake_queue(netdev_txq);
734 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
735 "Wake queue was called\n");
736 }
737 }
738
739 return NETDEV_TX_OK;
740}
741
16f46bf0 742int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 743{
744 u16 hw_bd_cons;
745
746 /* Tell compiler that consumer and producer can change */
747 barrier();
748 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
749 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
750 return 0;
751
752 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
753}
754
755static int qede_tx_int(struct qede_dev *edev,
756 struct qede_tx_queue *txq)
757{
758 struct netdev_queue *netdev_txq;
759 u16 hw_bd_cons;
760 unsigned int pkts_compl = 0, bytes_compl = 0;
761 int rc;
762
763 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
764
765 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
766 barrier();
767
768 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
769 int len = 0;
770
771 rc = qede_free_tx_pkt(edev, txq, &len);
772 if (rc) {
773 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
774 hw_bd_cons,
775 qed_chain_get_cons_idx(&txq->tx_pbl));
776 break;
777 }
778
779 bytes_compl += len;
780 pkts_compl++;
781 txq->sw_tx_cons++;
782 }
783
784 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
785
786 /* Need to make the tx_bd_cons update visible to start_xmit()
787 * before checking for netif_tx_queue_stopped(). Without the
788 * memory barrier, there is a small possibility that
789 * start_xmit() will miss it and cause the queue to be stopped
790 * forever.
791 * On the other hand we need an rmb() here to ensure the proper
792 * ordering of bit testing in the following
793 * netif_tx_queue_stopped(txq) call.
794 */
795 smp_mb();
796
797 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
798 /* Taking tx_lock is needed to prevent reenabling the queue
799 * while it's empty. This could have happen if rx_action() gets
800 * suspended in qede_tx_int() after the condition before
801 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
802 *
803 * stops the queue->sees fresh tx_bd_cons->releases the queue->
804 * sends some packets consuming the whole queue again->
805 * stops the queue
806 */
807
808 __netif_tx_lock(netdev_txq, smp_processor_id());
809
810 if ((netif_tx_queue_stopped(netdev_txq)) &&
811 (edev->state == QEDE_STATE_OPEN) &&
812 (qed_chain_get_elem_left(&txq->tx_pbl)
813 >= (MAX_SKB_FRAGS + 1))) {
814 netif_tx_wake_queue(netdev_txq);
815 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
816 "Wake queue was called\n");
817 }
818
819 __netif_tx_unlock(netdev_txq);
820 }
821
822 return 0;
823}
824
16f46bf0 825bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 826{
827 u16 hw_comp_cons, sw_comp_cons;
828
829 /* Tell compiler that status block fields can change */
830 barrier();
831
832 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
833 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
834
835 return hw_comp_cons != sw_comp_cons;
836}
837
838static bool qede_has_tx_work(struct qede_fastpath *fp)
839{
840 u8 tc;
841
842 for (tc = 0; tc < fp->edev->num_tc; tc++)
843 if (qede_txq_has_work(&fp->txqs[tc]))
844 return true;
845 return false;
846}
847
f86af2df
MC		 848static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
849{
850 qed_chain_consume(&rxq->rx_bd_ring);
851 rxq->sw_rx_cons++;
852}
853
fc48b7a6
YM		 854/* This function reuses the buffer(from an offset) from
855 * consumer index to producer index in the bd ring
2950219d 856 */
fc48b7a6
YM		 857static inline void qede_reuse_page(struct qede_dev *edev,
858 struct qede_rx_queue *rxq,
859 struct sw_rx_data *curr_cons)
2950219d 860{
2950219d 861 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 862 struct sw_rx_data *curr_prod;
863 dma_addr_t new_mapping;
2950219d 864
fc48b7a6
YM		 865 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
866 *curr_prod = *curr_cons;
2950219d 867
fc48b7a6
YM		 868 new_mapping = curr_prod->mapping + curr_prod->page_offset;
869
870 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
871 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 872
2950219d 873 rxq->sw_rx_prod++;
fc48b7a6
YM		 874 curr_cons->data = NULL;
875}
876
f86af2df
MC		 877/* In case of allocation failures reuse buffers
878 * from consumer index to produce buffers for firmware
879 */
16f46bf0
SRK		 880void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
881 struct qede_dev *edev, u8 count)
f86af2df
MC		 882{
883 struct sw_rx_data *curr_cons;
884
885 for (; count > 0; count--) {
886 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
887 qede_reuse_page(edev, rxq, curr_cons);
888 qede_rx_bd_ring_consume(rxq);
889 }
890}
891
fc48b7a6
YM		 892static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
893 struct qede_rx_queue *rxq,
894 struct sw_rx_data *curr_cons)
895{
896 /* Move to the next segment in the page */
897 curr_cons->page_offset += rxq->rx_buf_seg_size;
898
899 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 900 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
901 /* Since we failed to allocate new buffer
902 * current buffer can be used again.
903 */
904 curr_cons->page_offset -= rxq->rx_buf_seg_size;
905
fc48b7a6 906 return -ENOMEM;
f86af2df 907 }
fc48b7a6
YM		 908
909 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
910 PAGE_SIZE, DMA_FROM_DEVICE);
911 } else {
912 /* Increment refcount of the page as we don't want
913 * network stack to take the ownership of the page
914 * which can be recycled multiple times by the driver.
915 */
6d061f9f 916 page_ref_inc(curr_cons->data);
fc48b7a6
YM		 917 qede_reuse_page(edev, rxq, curr_cons);
918 }
919
920 return 0;
2950219d
YM		 921}
922
923static inline void qede_update_rx_prod(struct qede_dev *edev,
924 struct qede_rx_queue *rxq)
925{
926 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
927 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
928 struct eth_rx_prod_data rx_prods = {0};
929
930 /* Update producers */
931 rx_prods.bd_prod = cpu_to_le16(bd_prod);
932 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
933
934 /* Make sure that the BD and SGE data is updated before updating the
935 * producers since FW might read the BD/SGE right after the producer
936 * is updated.
937 */
938 wmb();
939
940 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
941 (u32 *)&rx_prods);
942
943 /* mmiowb is needed to synchronize doorbell writes from more than one
944 * processor. It guarantees that the write arrives to the device before
945 * the napi lock is released and another qede_poll is called (possibly
946 * on another CPU). Without this barrier, the next doorbell can bypass
947 * this doorbell. This is applicable to IA64/Altix systems.
948 */
949 mmiowb();
950}
951
952static u32 qede_get_rxhash(struct qede_dev *edev,
953 u8 bitfields,
954 __le32 rss_hash,
955 enum pkt_hash_types *rxhash_type)
956{
957 enum rss_hash_type htype;
958
959 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
960
961 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
962 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
963 (htype == RSS_HASH_TYPE_IPV6)) ?
964 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
965 return le32_to_cpu(rss_hash);
966 }
967 *rxhash_type = PKT_HASH_TYPE_NONE;
968 return 0;
969}
970
971static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
972{
973 skb_checksum_none_assert(skb);
974
975 if (csum_flag & QEDE_CSUM_UNNECESSARY)
976 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 977
978 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
979 skb->csum_level = 1;
2950219d
YM		 980}
981
982static inline void qede_skb_receive(struct qede_dev *edev,
983 struct qede_fastpath *fp,
984 struct sk_buff *skb,
985 u16 vlan_tag)
986{
987 if (vlan_tag)
988 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
989 vlan_tag);
990
991 napi_gro_receive(&fp->napi, skb);
992}
993
55482edc
MC		 994static void qede_set_gro_params(struct qede_dev *edev,
995 struct sk_buff *skb,
996 struct eth_fast_path_rx_tpa_start_cqe *cqe)
997{
998 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
999
1000 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
1001 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
1002 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
1003 else
1004 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1005
1006 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
1007 cqe->header_len;
1008}
1009
1010static int qede_fill_frag_skb(struct qede_dev *edev,
1011 struct qede_rx_queue *rxq,
1012 u8 tpa_agg_index,
1013 u16 len_on_bd)
1014{
1015 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
1016 NUM_RX_BDS_MAX];
1017 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
1018 struct sk_buff *skb = tpa_info->skb;
1019
1020 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1021 goto out;
1022
1023 /* Add one frag and update the appropriate fields in the skb */
1024 skb_fill_page_desc(skb, tpa_info->frag_id++,
1025 current_bd->data, current_bd->page_offset,
1026 len_on_bd);
1027
1028 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 1029 /* Incr page ref count to reuse on allocation failure
1030 * so that it doesn't get freed while freeing SKB.
1031 */
0139aa7b 1032 page_ref_inc(current_bd->data);
55482edc
MC		 1033 goto out;
1034 }
1035
1036 qed_chain_consume(&rxq->rx_bd_ring);
1037 rxq->sw_rx_cons++;
1038
1039 skb->data_len += len_on_bd;
1040 skb->truesize += rxq->rx_buf_seg_size;
1041 skb->len += len_on_bd;
1042
1043 return 0;
1044
1045out:
f86af2df
MC		 1046 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1047 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1048 return -ENOMEM;
1049}
1050
1051static void qede_tpa_start(struct qede_dev *edev,
1052 struct qede_rx_queue *rxq,
1053 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1054{
1055 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1056 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1057 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
1058 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
1059 dma_addr_t mapping = tpa_info->replace_buf_mapping;
1060 struct sw_rx_data *sw_rx_data_cons;
1061 struct sw_rx_data *sw_rx_data_prod;
1062 enum pkt_hash_types rxhash_type;
1063 u32 rxhash;
1064
1065 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1066 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1067
1068 /* Use pre-allocated replacement buffer - we can't release the agg.
1069 * start until its over and we don't want to risk allocation failing
1070 * here, so re-allocate when aggregation will be over.
1071 */
09ec8e7f 1072 sw_rx_data_prod->mapping = replace_buf->mapping;
55482edc
MC		 1073
1074 sw_rx_data_prod->data = replace_buf->data;
1075 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1076 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1077 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1078
1079 rxq->sw_rx_prod++;
1080
1081 /* move partial skb from cons to pool (don't unmap yet)
1082 * save mapping, incase we drop the packet later on.
1083 */
1084 tpa_info->start_buf = *sw_rx_data_cons;
1085 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1086 le32_to_cpu(rx_bd_cons->addr.lo));
1087
1088 tpa_info->start_buf_mapping = mapping;
1089 rxq->sw_rx_cons++;
1090
1091 /* set tpa state to start only if we are able to allocate skb
1092 * for this aggregation, otherwise mark as error and aggregation will
1093 * be dropped
1094 */
1095 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1096 le16_to_cpu(cqe->len_on_first_bd));
1097 if (unlikely(!tpa_info->skb)) {
f86af2df 1098 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
55482edc 1099 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
f86af2df 1100 goto cons_buf;
55482edc
MC		 1101 }
1102
1103 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
1104 memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
1105
1106 /* Start filling in the aggregation info */
1107 tpa_info->frag_id = 0;
1108 tpa_info->agg_state = QEDE_AGG_STATE_START;
1109
1110 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1111 cqe->rss_hash, &rxhash_type);
1112 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
1113 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1114 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
1115 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
1116 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1117 else
1118 tpa_info->vlan_tag = 0;
1119
1120 /* This is needed in order to enable forwarding support */
1121 qede_set_gro_params(edev, tpa_info->skb, cqe);
1122
f86af2df 1123cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1124 if (likely(cqe->ext_bd_len_list[0]))
1125 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1126 le16_to_cpu(cqe->ext_bd_len_list[0]));
1127
1128 if (unlikely(cqe->ext_bd_len_list[1])) {
1129 DP_ERR(edev,
1130 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
1131 tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
1132 }
1133}
1134
88f09bd5 1135#ifdef CONFIG_INET
55482edc
MC		 1136static void qede_gro_ip_csum(struct sk_buff *skb)
1137{
1138 const struct iphdr *iph = ip_hdr(skb);
1139 struct tcphdr *th;
1140
55482edc
MC		 1141 skb_set_transport_header(skb, sizeof(struct iphdr));
1142 th = tcp_hdr(skb);
1143
1144 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1145 iph->saddr, iph->daddr, 0);
1146
1147 tcp_gro_complete(skb);
1148}
1149
1150static void qede_gro_ipv6_csum(struct sk_buff *skb)
1151{
1152 struct ipv6hdr *iph = ipv6_hdr(skb);
1153 struct tcphdr *th;
1154
55482edc
MC		 1155 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1156 th = tcp_hdr(skb);
1157
1158 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1159 &iph->saddr, &iph->daddr, 0);
1160 tcp_gro_complete(skb);
1161}
88f09bd5 1162#endif
55482edc
MC		 1163
1164static void qede_gro_receive(struct qede_dev *edev,
1165 struct qede_fastpath *fp,
1166 struct sk_buff *skb,
1167 u16 vlan_tag)
1168{
ee2fa8e6
MC		 1169 /* FW can send a single MTU sized packet from gro flow
1170 * due to aggregation timeout/last segment etc. which
1171 * is not expected to be a gro packet. If a skb has zero
1172 * frags then simply push it in the stack as non gso skb.
1173 */
1174 if (unlikely(!skb->data_len)) {
1175 skb_shinfo(skb)->gso_type = 0;
1176 skb_shinfo(skb)->gso_size = 0;
1177 goto send_skb;
1178 }
1179
88f09bd5 1180#ifdef CONFIG_INET
55482edc 1181 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1182 skb_set_network_header(skb, 0);
1183
55482edc
MC		 1184 switch (skb->protocol) {
1185 case htons(ETH_P_IP):
1186 qede_gro_ip_csum(skb);
1187 break;
1188 case htons(ETH_P_IPV6):
1189 qede_gro_ipv6_csum(skb);
1190 break;
1191 default:
1192 DP_ERR(edev,
1193 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1194 ntohs(skb->protocol));
1195 }
1196 }
88f09bd5 1197#endif
ee2fa8e6
MC		 1198
1199send_skb:
55482edc
MC		 1200 skb_record_rx_queue(skb, fp->rss_id);
1201 qede_skb_receive(edev, fp, skb, vlan_tag);
1202}
1203
1204static inline void qede_tpa_cont(struct qede_dev *edev,
1205 struct qede_rx_queue *rxq,
1206 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1207{
1208 int i;
1209
1210 for (i = 0; cqe->len_list[i]; i++)
1211 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1212 le16_to_cpu(cqe->len_list[i]));
1213
1214 if (unlikely(i > 1))
1215 DP_ERR(edev,
1216 "Strange - TPA cont with more than a single len_list entry\n");
1217}
1218
1219static void qede_tpa_end(struct qede_dev *edev,
1220 struct qede_fastpath *fp,
1221 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1222{
1223 struct qede_rx_queue *rxq = fp->rxq;
1224 struct qede_agg_info *tpa_info;
1225 struct sk_buff *skb;
1226 int i;
1227
1228 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1229 skb = tpa_info->skb;
1230
1231 for (i = 0; cqe->len_list[i]; i++)
1232 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1233 le16_to_cpu(cqe->len_list[i]));
1234 if (unlikely(i > 1))
1235 DP_ERR(edev,
1236 "Strange - TPA emd with more than a single len_list entry\n");
1237
1238 if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
1239 goto err;
1240
1241 /* Sanity */
1242 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1243 DP_ERR(edev,
1244 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1245 cqe->num_of_bds, tpa_info->frag_id);
1246 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1247 DP_ERR(edev,
1248 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1249 le16_to_cpu(cqe->total_packet_len), skb->len);
1250
1251 memcpy(skb->data,
1252 page_address(tpa_info->start_buf.data) +
1253 tpa_info->start_cqe.placement_offset +
1254 tpa_info->start_buf.page_offset,
1255 le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
1256
1257 /* Recycle [mapped] start buffer for the next replacement */
1258 tpa_info->replace_buf = tpa_info->start_buf;
1259 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1260
1261 /* Finalize the SKB */
1262 skb->protocol = eth_type_trans(skb, edev->ndev);
1263 skb->ip_summed = CHECKSUM_UNNECESSARY;
1264
1265 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1266 * to skb_shinfo(skb)->gso_segs
1267 */
1268 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1269
1270 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1271
1272 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1273
1274 return;
1275err:
1276 /* The BD starting the aggregation is still mapped; Re-use it for
1277 * future aggregations [as replacement buffer]
1278 */
1279 memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
1280 sizeof(struct sw_rx_data));
1281 tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
1282 tpa_info->start_buf.data = NULL;
1283 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
1284 dev_kfree_skb_any(tpa_info->skb);
1285 tpa_info->skb = NULL;
1286}
1287
14db81de
MC		 1288static bool qede_tunn_exist(u16 flag)
1289{
1290 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1291 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1292}
1293
1294static u8 qede_check_tunn_csum(u16 flag)
1295{
1296 u16 csum_flag = 0;
1297 u8 tcsum = 0;
1298
1299 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1300 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1301 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1302 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1303
1304 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1305 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1306 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1307 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1308 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1309 }
1310
1311 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1312 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1313 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1314 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1315
1316 if (csum_flag & flag)
1317 return QEDE_CSUM_ERROR;
1318
1319 return QEDE_CSUM_UNNECESSARY | tcsum;
1320}
1321
1322static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1323{
1324 u16 csum_flag = 0;
1325 u8 csum = 0;
1326
14db81de
MC		 1327 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1328 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1329 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1330 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1331 csum = QEDE_CSUM_UNNECESSARY;
1332 }
1333
1334 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1335 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1336
1337 if (csum_flag & flag)
1338 return QEDE_CSUM_ERROR;
1339
1340 return csum;
1341}
1342
14db81de
MC		 1343static u8 qede_check_csum(u16 flag)
1344{
1345 if (!qede_tunn_exist(flag))
1346 return qede_check_notunn_csum(flag);
1347 else
1348 return qede_check_tunn_csum(flag);
1349}
1350
c72a6125
MC		 1351static bool qede_pkt_is_ip_fragmented(struct eth_fast_path_rx_reg_cqe *cqe,
1352 u16 flag)
1353{
1354 u8 tun_pars_flg = cqe->tunnel_pars_flags.flags;
1355
1356 if ((tun_pars_flg & (ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK <<
1357 ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT)) ||
1358 (flag & (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1359 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT)))
1360 return true;
1361
1362 return false;
1363}
1364
2950219d
YM		 1365static int qede_rx_int(struct qede_fastpath *fp, int budget)
1366{
1367 struct qede_dev *edev = fp->edev;
1368 struct qede_rx_queue *rxq = fp->rxq;
1369
1370 u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
1371 int rx_pkt = 0;
1372 u8 csum_flag;
1373
1374 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1375 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1376
1377 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1378 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1379 * read before it is written by FW, then FW writes CQE and SB, and then
1380 * the CPU reads the hw_comp_cons, it will use an old CQE.
1381 */
1382 rmb();
1383
1384 /* Loop to complete all indicated BDs */
1385 while (sw_comp_cons != hw_comp_cons) {
1386 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1387 enum pkt_hash_types rxhash_type;
1388 enum eth_rx_cqe_type cqe_type;
1389 struct sw_rx_data *sw_rx_data;
1390 union eth_rx_cqe *cqe;
1391 struct sk_buff *skb;
fc48b7a6
YM		 1392 struct page *data;
1393 __le16 flags;
2950219d
YM		 1394 u16 len, pad;
1395 u32 rx_hash;
2950219d
YM		 1396
1397 /* Get the CQE from the completion ring */
1398 cqe = (union eth_rx_cqe *)
1399 qed_chain_consume(&rxq->rx_comp_ring);
1400 cqe_type = cqe->fast_path_regular.type;
1401
1402 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1403 edev->ops->eth_cqe_completion(
1404 edev->cdev, fp->rss_id,
1405 (struct eth_slow_path_rx_cqe *)cqe);
1406 goto next_cqe;
1407 }
1408
55482edc
MC		 1409 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
1410 switch (cqe_type) {
1411 case ETH_RX_CQE_TYPE_TPA_START:
1412 qede_tpa_start(edev, rxq,
1413 &cqe->fast_path_tpa_start);
1414 goto next_cqe;
1415 case ETH_RX_CQE_TYPE_TPA_CONT:
1416 qede_tpa_cont(edev, rxq,
1417 &cqe->fast_path_tpa_cont);
1418 goto next_cqe;
1419 case ETH_RX_CQE_TYPE_TPA_END:
1420 qede_tpa_end(edev, fp,
1421 &cqe->fast_path_tpa_end);
1422 goto next_rx_only;
1423 default:
1424 break;
1425 }
1426 }
1427
2950219d
YM		 1428 /* Get the data from the SW ring */
1429 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1430 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
1431 data = sw_rx_data->data;
1432
1433 fp_cqe = &cqe->fast_path_regular;
fc48b7a6 1434 len = le16_to_cpu(fp_cqe->len_on_first_bd);
2950219d 1435 pad = fp_cqe->placement_offset;
fc48b7a6 1436 flags = cqe->fast_path_regular.pars_flags.flags;
2950219d 1437
fc48b7a6
YM		 1438 /* If this is an error packet then drop it */
1439 parse_flag = le16_to_cpu(flags);
2950219d 1440
fc48b7a6
YM		 1441 csum_flag = qede_check_csum(parse_flag);
1442 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
c72a6125
MC		 1443 if (qede_pkt_is_ip_fragmented(&cqe->fast_path_regular,
1444 parse_flag)) {
1445 rxq->rx_ip_frags++;
1446 goto alloc_skb;
1447 }
1448
fc48b7a6
YM		 1449 DP_NOTICE(edev,
1450 "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
1451 sw_comp_cons, parse_flag);
1452 rxq->rx_hw_errors++;
f86af2df
MC		 1453 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1454 goto next_cqe;
fc48b7a6 1455 }
2950219d 1456
c72a6125 1457alloc_skb:
fc48b7a6
YM		 1458 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1459 if (unlikely(!skb)) {
2950219d 1460 DP_NOTICE(edev,
fc48b7a6 1461 "Build_skb failed, dropping incoming packet\n");
f86af2df 1462 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
2950219d 1463 rxq->rx_alloc_errors++;
f86af2df 1464 goto next_cqe;
fc48b7a6
YM		 1465 }
1466
1467 /* Copy data into SKB */
1468 if (len + pad <= QEDE_RX_HDR_SIZE) {
1469 memcpy(skb_put(skb, len),
1470 page_address(data) + pad +
1471 sw_rx_data->page_offset, len);
1472 qede_reuse_page(edev, rxq, sw_rx_data);
1473 } else {
1474 struct skb_frag_struct *frag;
1475 unsigned int pull_len;
1476 unsigned char *va;
1477
1478 frag = &skb_shinfo(skb)->frags[0];
1479
1480 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
1481 pad + sw_rx_data->page_offset,
1482 len, rxq->rx_buf_seg_size);
1483
1484 va = skb_frag_address(frag);
1485 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
1486
1487 /* Align the pull_len to optimize memcpy */
1488 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
1489
1490 skb_frag_size_sub(frag, pull_len);
1491 frag->page_offset += pull_len;
1492 skb->data_len -= pull_len;
1493 skb->tail += pull_len;
1494
1495 if (unlikely(qede_realloc_rx_buffer(edev, rxq,
1496 sw_rx_data))) {
1497 DP_ERR(edev, "Failed to allocate rx buffer\n");
f86af2df
MC		 1498 /* Incr page ref count to reuse on allocation
1499 * failure so that it doesn't get freed while
1500 * freeing SKB.
1501 */
1502
0139aa7b 1503 page_ref_inc(sw_rx_data->data);
fc48b7a6 1504 rxq->rx_alloc_errors++;
f86af2df
MC		 1505 qede_recycle_rx_bd_ring(rxq, edev,
1506 fp_cqe->bd_num);
1507 dev_kfree_skb_any(skb);
fc48b7a6
YM		 1508 goto next_cqe;
1509 }
2950219d
YM		 1510 }
1511
f86af2df
MC		 1512 qede_rx_bd_ring_consume(rxq);
1513
fc48b7a6
YM		 1514 if (fp_cqe->bd_num != 1) {
1515 u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
1516 u8 num_frags;
1517
1518 pkt_len -= len;
1519
1520 for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
1521 num_frags--) {
1522 u16 cur_size = pkt_len > rxq->rx_buf_size ?
1523 rxq->rx_buf_size : pkt_len;
f86af2df
MC		 1524 if (unlikely(!cur_size)) {
1525 DP_ERR(edev,
1526 "Still got %d BDs for mapping jumbo, but length became 0\n",
1527 num_frags);
1528 qede_recycle_rx_bd_ring(rxq, edev,
1529 num_frags);
1530 dev_kfree_skb_any(skb);
1531 goto next_cqe;
1532 }
fc48b7a6 1533
f86af2df
MC		 1534 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
1535 qede_recycle_rx_bd_ring(rxq, edev,
1536 num_frags);
1537 dev_kfree_skb_any(skb);
fc48b7a6 1538 goto next_cqe;
f86af2df 1539 }
fc48b7a6 1540
fc48b7a6
YM		 1541 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1542 sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
f86af2df
MC		 1543 qede_rx_bd_ring_consume(rxq);
1544
fc48b7a6
YM		 1545 dma_unmap_page(&edev->pdev->dev,
1546 sw_rx_data->mapping,
1547 PAGE_SIZE, DMA_FROM_DEVICE);
1548
1549 skb_fill_page_desc(skb,
1550 skb_shinfo(skb)->nr_frags++,
1551 sw_rx_data->data, 0,
1552 cur_size);
1553
1554 skb->truesize += PAGE_SIZE;
1555 skb->data_len += cur_size;
1556 skb->len += cur_size;
1557 pkt_len -= cur_size;
1558 }
2950219d 1559
f86af2df 1560 if (unlikely(pkt_len))
fc48b7a6
YM		 1561 DP_ERR(edev,
1562 "Mapped all BDs of jumbo, but still have %d bytes\n",
1563 pkt_len);
1564 }
2950219d
YM		 1565
1566 skb->protocol = eth_type_trans(skb, edev->ndev);
1567
1568 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1569 fp_cqe->rss_hash,
1570 &rxhash_type);
1571
1572 skb_set_hash(skb, rx_hash, rxhash_type);
1573
1574 qede_set_skb_csum(skb, csum_flag);
1575
1576 skb_record_rx_queue(skb, fp->rss_id);
1577
1578 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
55482edc 1579next_rx_only:
2950219d
YM		 1580 rx_pkt++;
1581
1582next_cqe: /* don't consume bd rx buffer */
1583 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1584 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
1585 /* CR TPA - revisit how to handle budget in TPA perhaps
1586 * increase on "end"
1587 */
1588 if (rx_pkt == budget)
1589 break;
1590 } /* repeat while sw_comp_cons != hw_comp_cons... */
1591
1592 /* Update producers */
1593 qede_update_rx_prod(edev, rxq);
1594
1595 return rx_pkt;
1596}
1597
1598static int qede_poll(struct napi_struct *napi, int budget)
1599{
1600 int work_done = 0;
1601 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
1602 napi);
1603 struct qede_dev *edev = fp->edev;
1604
1605 while (1) {
1606 u8 tc;
1607
1608 for (tc = 0; tc < edev->num_tc; tc++)
1609 if (qede_txq_has_work(&fp->txqs[tc]))
1610 qede_tx_int(edev, &fp->txqs[tc]);
1611
1612 if (qede_has_rx_work(fp->rxq)) {
1613 work_done += qede_rx_int(fp, budget - work_done);
1614
1615 /* must not complete if we consumed full budget */
1616 if (work_done >= budget)
1617 break;
1618 }
1619
1620 /* Fall out from the NAPI loop if needed */
1621 if (!(qede_has_rx_work(fp->rxq) || qede_has_tx_work(fp))) {
1622 qed_sb_update_sb_idx(fp->sb_info);
1623 /* *_has_*_work() reads the status block,
1624 * thus we need to ensure that status block indices
1625 * have been actually read (qed_sb_update_sb_idx)
1626 * prior to this check (*_has_*_work) so that
1627 * we won't write the "newer" value of the status block
1628 * to HW (if there was a DMA right after
1629 * qede_has_rx_work and if there is no rmb, the memory
1630 * reading (qed_sb_update_sb_idx) may be postponed
1631 * to right before *_ack_sb). In this case there
1632 * will never be another interrupt until there is
1633 * another update of the status block, while there
1634 * is still unhandled work.
1635 */
1636 rmb();
1637
1638 if (!(qede_has_rx_work(fp->rxq) ||
1639 qede_has_tx_work(fp))) {
1640 napi_complete(napi);
1641 /* Update and reenable interrupts */
1642 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
1643 1 /*update*/);
1644 break;
1645 }
1646 }
1647 }
1648
1649 return work_done;
1650}
1651
1652static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1653{
1654 struct qede_fastpath *fp = fp_cookie;
1655
1656 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1657
1658 napi_schedule_irqoff(&fp->napi);
1659 return IRQ_HANDLED;
1660}
1661
1662/* -------------------------------------------------------------------------
1663 * END OF FAST-PATH
1664 * -------------------------------------------------------------------------
1665 */
1666
1667static int qede_open(struct net_device *ndev);
1668static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1669static int qede_set_mac_addr(struct net_device *ndev, void *p);
1670static void qede_set_rx_mode(struct net_device *ndev);
1671static void qede_config_rx_mode(struct net_device *ndev);
1672
1673static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1674 enum qed_filter_xcast_params_type opcode,
1675 unsigned char mac[ETH_ALEN])
1676{
1677 struct qed_filter_params filter_cmd;
1678
1679 memset(&filter_cmd, 0, sizeof(filter_cmd));
1680 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1681 filter_cmd.filter.ucast.type = opcode;
1682 filter_cmd.filter.ucast.mac_valid = 1;
1683 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1684
1685 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1686}
1687
7c1bfcad
SRK		 1688static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1689 enum qed_filter_xcast_params_type opcode,
1690 u16 vid)
1691{
1692 struct qed_filter_params filter_cmd;
1693
1694 memset(&filter_cmd, 0, sizeof(filter_cmd));
1695 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1696 filter_cmd.filter.ucast.type = opcode;
1697 filter_cmd.filter.ucast.vlan_valid = 1;
1698 filter_cmd.filter.ucast.vlan = vid;
1699
1700 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1701}
1702
133fac0e
SK		 1703void qede_fill_by_demand_stats(struct qede_dev *edev)
1704{
1705 struct qed_eth_stats stats;
1706
1707 edev->ops->get_vport_stats(edev->cdev, &stats);
1708 edev->stats.no_buff_discards = stats.no_buff_discards;
1709 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1710 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1711 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1712 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1713 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1714 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1715 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1716 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1717
1718 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1719 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1720 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1721 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1722 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1723 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1724 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1725 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1726 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1727 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1728 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1729 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1730
1731 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1732 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1733 edev->stats.rx_128_to_255_byte_packets =
1734 stats.rx_128_to_255_byte_packets;
1735 edev->stats.rx_256_to_511_byte_packets =
1736 stats.rx_256_to_511_byte_packets;
1737 edev->stats.rx_512_to_1023_byte_packets =
1738 stats.rx_512_to_1023_byte_packets;
1739 edev->stats.rx_1024_to_1518_byte_packets =
1740 stats.rx_1024_to_1518_byte_packets;
1741 edev->stats.rx_1519_to_1522_byte_packets =
1742 stats.rx_1519_to_1522_byte_packets;
1743 edev->stats.rx_1519_to_2047_byte_packets =
1744 stats.rx_1519_to_2047_byte_packets;
1745 edev->stats.rx_2048_to_4095_byte_packets =
1746 stats.rx_2048_to_4095_byte_packets;
1747 edev->stats.rx_4096_to_9216_byte_packets =
1748 stats.rx_4096_to_9216_byte_packets;
1749 edev->stats.rx_9217_to_16383_byte_packets =
1750 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1751 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1752 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1753 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1754 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1755 edev->stats.rx_align_errors = stats.rx_align_errors;
1756 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1757 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1758 edev->stats.rx_jabbers = stats.rx_jabbers;
1759 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1760 edev->stats.rx_fragments = stats.rx_fragments;
1761 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1762 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1763 edev->stats.tx_128_to_255_byte_packets =
1764 stats.tx_128_to_255_byte_packets;
1765 edev->stats.tx_256_to_511_byte_packets =
1766 stats.tx_256_to_511_byte_packets;
1767 edev->stats.tx_512_to_1023_byte_packets =
1768 stats.tx_512_to_1023_byte_packets;
1769 edev->stats.tx_1024_to_1518_byte_packets =
1770 stats.tx_1024_to_1518_byte_packets;
1771 edev->stats.tx_1519_to_2047_byte_packets =
1772 stats.tx_1519_to_2047_byte_packets;
1773 edev->stats.tx_2048_to_4095_byte_packets =
1774 stats.tx_2048_to_4095_byte_packets;
1775 edev->stats.tx_4096_to_9216_byte_packets =
1776 stats.tx_4096_to_9216_byte_packets;
1777 edev->stats.tx_9217_to_16383_byte_packets =
1778 stats.tx_9217_to_16383_byte_packets;
1779 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1780 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1781 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1782 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1783 edev->stats.brb_truncates = stats.brb_truncates;
1784 edev->stats.brb_discards = stats.brb_discards;
1785 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1786}
1787
1788static struct rtnl_link_stats64 *qede_get_stats64(
1789 struct net_device *dev,
1790 struct rtnl_link_stats64 *stats)
1791{
1792 struct qede_dev *edev = netdev_priv(dev);
1793
1794 qede_fill_by_demand_stats(edev);
1795
1796 stats->rx_packets = edev->stats.rx_ucast_pkts +
1797 edev->stats.rx_mcast_pkts +
1798 edev->stats.rx_bcast_pkts;
1799 stats->tx_packets = edev->stats.tx_ucast_pkts +
1800 edev->stats.tx_mcast_pkts +
1801 edev->stats.tx_bcast_pkts;
1802
1803 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1804 edev->stats.rx_mcast_bytes +
1805 edev->stats.rx_bcast_bytes;
1806
1807 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1808 edev->stats.tx_mcast_bytes +
1809 edev->stats.tx_bcast_bytes;
1810
1811 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1812 stats->multicast = edev->stats.rx_mcast_pkts +
1813 edev->stats.rx_bcast_pkts;
1814
1815 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1816
1817 stats->collisions = edev->stats.tx_total_collisions;
1818 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1819 stats->rx_frame_errors = edev->stats.rx_align_errors;
1820
1821 return stats;
1822}
1823
733def6a 1824#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 1825static int qede_get_vf_config(struct net_device *dev, int vfidx,
1826 struct ifla_vf_info *ivi)
1827{
1828 struct qede_dev *edev = netdev_priv(dev);
1829
1830 if (!edev->ops)
1831 return -EINVAL;
1832
1833 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
1834}
1835
733def6a
YM		 1836static int qede_set_vf_rate(struct net_device *dev, int vfidx,
1837 int min_tx_rate, int max_tx_rate)
1838{
1839 struct qede_dev *edev = netdev_priv(dev);
1840
be7b6d64 1841 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 1842 max_tx_rate);
1843}
1844
6ddc7608
YM		 1845static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
1846{
1847 struct qede_dev *edev = netdev_priv(dev);
1848
1849 if (!edev->ops)
1850 return -EINVAL;
1851
1852 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
1853}
1854
733def6a
YM		 1855static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
1856 int link_state)
1857{
1858 struct qede_dev *edev = netdev_priv(dev);
1859
1860 if (!edev->ops)
1861 return -EINVAL;
1862
1863 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
1864}
1865#endif
1866
7c1bfcad
SRK		 1867static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1868{
1869 struct qed_update_vport_params params;
1870 int rc;
1871
1872 /* Proceed only if action actually needs to be performed */
1873 if (edev->accept_any_vlan == action)
1874 return;
1875
1876 memset(&params, 0, sizeof(params));
1877
1878 params.vport_id = 0;
1879 params.accept_any_vlan = action;
1880 params.update_accept_any_vlan_flg = 1;
1881
1882 rc = edev->ops->vport_update(edev->cdev, &params);
1883 if (rc) {
1884 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1885 action ? "enable" : "disable");
1886 } else {
1887 DP_INFO(edev, "%s accept-any-vlan\n",
1888 action ? "enabled" : "disabled");
1889 edev->accept_any_vlan = action;
1890 }
1891}
1892
1893static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1894{
1895 struct qede_dev *edev = netdev_priv(dev);
1896 struct qede_vlan *vlan, *tmp;
1897 int rc;
1898
1899 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1900
1901 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1902 if (!vlan) {
1903 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1904 return -ENOMEM;
1905 }
1906 INIT_LIST_HEAD(&vlan->list);
1907 vlan->vid = vid;
1908 vlan->configured = false;
1909
1910 /* Verify vlan isn't already configured */
1911 list_for_each_entry(tmp, &edev->vlan_list, list) {
1912 if (tmp->vid == vlan->vid) {
1913 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1914 "vlan already configured\n");
1915 kfree(vlan);
1916 return -EEXIST;
1917 }
1918 }
1919
1920 /* If interface is down, cache this VLAN ID and return */
1921 if (edev->state != QEDE_STATE_OPEN) {
1922 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1923 "Interface is down, VLAN %d will be configured when interface is up\n",
1924 vid);
1925 if (vid != 0)
1926 edev->non_configured_vlans++;
1927 list_add(&vlan->list, &edev->vlan_list);
1928
1929 return 0;
1930 }
1931
1932 /* Check for the filter limit.
1933 * Note - vlan0 has a reserved filter and can be added without
1934 * worrying about quota
1935 */
1936 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1937 (vlan->vid == 0)) {
1938 rc = qede_set_ucast_rx_vlan(edev,
1939 QED_FILTER_XCAST_TYPE_ADD,
1940 vlan->vid);
1941 if (rc) {
1942 DP_ERR(edev, "Failed to configure VLAN %d\n",
1943 vlan->vid);
1944 kfree(vlan);
1945 return -EINVAL;
1946 }
1947 vlan->configured = true;
1948
1949 /* vlan0 filter isn't consuming out of our quota */
1950 if (vlan->vid != 0)
1951 edev->configured_vlans++;
1952 } else {
1953 /* Out of quota; Activate accept-any-VLAN mode */
1954 if (!edev->non_configured_vlans)
1955 qede_config_accept_any_vlan(edev, true);
1956
1957 edev->non_configured_vlans++;
1958 }
1959
1960 list_add(&vlan->list, &edev->vlan_list);
1961
1962 return 0;
1963}
1964
1965static void qede_del_vlan_from_list(struct qede_dev *edev,
1966 struct qede_vlan *vlan)
1967{
1968 /* vlan0 filter isn't consuming out of our quota */
1969 if (vlan->vid != 0) {
1970 if (vlan->configured)
1971 edev->configured_vlans--;
1972 else
1973 edev->non_configured_vlans--;
1974 }
1975
1976 list_del(&vlan->list);
1977 kfree(vlan);
1978}
1979
1980static int qede_configure_vlan_filters(struct qede_dev *edev)
1981{
1982 int rc = 0, real_rc = 0, accept_any_vlan = 0;
1983 struct qed_dev_eth_info *dev_info;
1984 struct qede_vlan *vlan = NULL;
1985
1986 if (list_empty(&edev->vlan_list))
1987 return 0;
1988
1989 dev_info = &edev->dev_info;
1990
1991 /* Configure non-configured vlans */
1992 list_for_each_entry(vlan, &edev->vlan_list, list) {
1993 if (vlan->configured)
1994 continue;
1995
1996 /* We have used all our credits, now enable accept_any_vlan */
1997 if ((vlan->vid != 0) &&
1998 (edev->configured_vlans == dev_info->num_vlan_filters)) {
1999 accept_any_vlan = 1;
2000 continue;
2001 }
2002
2003 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
2004
2005 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
2006 vlan->vid);
2007 if (rc) {
2008 DP_ERR(edev, "Failed to configure VLAN %u\n",
2009 vlan->vid);
2010 real_rc = rc;
2011 continue;
2012 }
2013
2014 vlan->configured = true;
2015 /* vlan0 filter doesn't consume our VLAN filter's quota */
2016 if (vlan->vid != 0) {
2017 edev->non_configured_vlans--;
2018 edev->configured_vlans++;
2019 }
2020 }
2021
2022 /* enable accept_any_vlan mode if we have more VLANs than credits,
2023 * or remove accept_any_vlan mode if we've actually removed
2024 * a non-configured vlan, and all remaining vlans are truly configured.
2025 */
2026
2027 if (accept_any_vlan)
2028 qede_config_accept_any_vlan(edev, true);
2029 else if (!edev->non_configured_vlans)
2030 qede_config_accept_any_vlan(edev, false);
2031
2032 return real_rc;
2033}
2034
2035static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
2036{
2037 struct qede_dev *edev = netdev_priv(dev);
2038 struct qede_vlan *vlan = NULL;
2039 int rc;
2040
2041 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
2042
2043 /* Find whether entry exists */
2044 list_for_each_entry(vlan, &edev->vlan_list, list)
2045 if (vlan->vid == vid)
2046 break;
2047
2048 if (!vlan || (vlan->vid != vid)) {
2049 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
2050 "Vlan isn't configured\n");
2051 return 0;
2052 }
2053
2054 if (edev->state != QEDE_STATE_OPEN) {
2055 /* As interface is already down, we don't have a VPORT
2056 * instance to remove vlan filter. So just update vlan list
2057 */
2058 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2059 "Interface is down, removing VLAN from list only\n");
2060 qede_del_vlan_from_list(edev, vlan);
2061 return 0;
2062 }
2063
2064 /* Remove vlan */
2065 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL, vid);
2066 if (rc) {
2067 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
2068 return -EINVAL;
2069 }
2070
2071 qede_del_vlan_from_list(edev, vlan);
2072
2073 /* We have removed a VLAN - try to see if we can
2074 * configure non-configured VLAN from the list.
2075 */
2076 rc = qede_configure_vlan_filters(edev);
2077
2078 return rc;
2079}
2080
2081static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
2082{
2083 struct qede_vlan *vlan = NULL;
2084
2085 if (list_empty(&edev->vlan_list))
2086 return;
2087
2088 list_for_each_entry(vlan, &edev->vlan_list, list) {
2089 if (!vlan->configured)
2090 continue;
2091
2092 vlan->configured = false;
2093
2094 /* vlan0 filter isn't consuming out of our quota */
2095 if (vlan->vid != 0) {
2096 edev->non_configured_vlans++;
2097 edev->configured_vlans--;
2098 }
2099
2100 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2101 "marked vlan %d as non-configured\n",
2102 vlan->vid);
2103 }
2104
2105 edev->accept_any_vlan = false;
2106}
2107
ce2b885c
YM		 2108int qede_set_features(struct net_device *dev, netdev_features_t features)
2109{
2110 struct qede_dev *edev = netdev_priv(dev);
2111 netdev_features_t changes = features ^ dev->features;
2112 bool need_reload = false;
2113
2114 /* No action needed if hardware GRO is disabled during driver load */
2115 if (changes & NETIF_F_GRO) {
2116 if (dev->features & NETIF_F_GRO)
2117 need_reload = !edev->gro_disable;
2118 else
2119 need_reload = edev->gro_disable;
2120 }
2121
2122 if (need_reload && netif_running(edev->ndev)) {
2123 dev->features = features;
2124 qede_reload(edev, NULL, NULL);
2125 return 1;
2126 }
2127
2128 return 0;
2129}
2130
f9f082a9
AD		 2131static void qede_udp_tunnel_add(struct net_device *dev,
2132 struct udp_tunnel_info *ti)
b18e170c
MC		 2133{
2134 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2135 u16 t_port = ntohs(ti->port);
b18e170c 2136
f9f082a9
AD		 2137 switch (ti->type) {
2138 case UDP_TUNNEL_TYPE_VXLAN:
2139 if (edev->vxlan_dst_port)
2140 return;
b18e170c 2141
f9f082a9 2142 edev->vxlan_dst_port = t_port;
b18e170c 2143
f9f082a9
AD		 2144 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d",
2145 t_port);
b18e170c 2146
f9f082a9
AD		 2147 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2148 break;
2149 case UDP_TUNNEL_TYPE_GENEVE:
2150 if (edev->geneve_dst_port)
2151 return;
b18e170c 2152
f9f082a9 2153 edev->geneve_dst_port = t_port;
b18e170c 2154
f9f082a9
AD		 2155 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d",
2156 t_port);
2157 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2158 break;
2159 default:
b18e170c 2160 return;
f9f082a9 2161 }
b18e170c 2162
b18e170c
MC		 2163 schedule_delayed_work(&edev->sp_task, 0);
2164}
b18e170c 2165
f9f082a9
AD		 2166static void qede_udp_tunnel_del(struct net_device *dev,
2167 struct udp_tunnel_info *ti)
9a109dd0
MC		 2168{
2169 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2170 u16 t_port = ntohs(ti->port);
9a109dd0 2171
f9f082a9
AD		 2172 switch (ti->type) {
2173 case UDP_TUNNEL_TYPE_VXLAN:
2174 if (t_port != edev->vxlan_dst_port)
2175 return;
9a109dd0 2176
f9f082a9 2177 edev->vxlan_dst_port = 0;
9a109dd0 2178
f9f082a9
AD		 2179 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d",
2180 t_port);
9a109dd0 2181
f9f082a9
AD		 2182 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2183 break;
2184 case UDP_TUNNEL_TYPE_GENEVE:
2185 if (t_port != edev->geneve_dst_port)
2186 return;
9a109dd0 2187
f9f082a9 2188 edev->geneve_dst_port = 0;
9a109dd0 2189
f9f082a9
AD		 2190 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d",
2191 t_port);
2192 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2193 break;
2194 default:
2195 return;
2196 }
9a109dd0 2197
9a109dd0
MC		 2198 schedule_delayed_work(&edev->sp_task, 0);
2199}
9a109dd0 2200
2950219d
YM		 2201static const struct net_device_ops qede_netdev_ops = {
2202 .ndo_open = qede_open,
2203 .ndo_stop = qede_close,
2204 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2205 .ndo_set_rx_mode = qede_set_rx_mode,
2206 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2207 .ndo_validate_addr = eth_validate_addr,
133fac0e 2208 .ndo_change_mtu = qede_change_mtu,
08feecd7 2209#ifdef CONFIG_QED_SRIOV
eff16960 2210 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7
YM		 2211 .ndo_set_vf_vlan = qede_set_vf_vlan,
2212#endif
7c1bfcad
SRK		 2213 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2214 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
ce2b885c 2215 .ndo_set_features = qede_set_features,
133fac0e 2216 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 2217#ifdef CONFIG_QED_SRIOV
2218 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 2219 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 2220 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 2221 .ndo_set_vf_rate = qede_set_vf_rate,
2222#endif
f9f082a9
AD		 2223 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
2224 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
2950219d
YM		 2225};
2226
e712d52b
YM		 2227/* -------------------------------------------------------------------------
2228 * START OF PROBE / REMOVE
2229 * -------------------------------------------------------------------------
2230 */
2231
2232static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2233 struct pci_dev *pdev,
2234 struct qed_dev_eth_info *info,
2235 u32 dp_module,
2236 u8 dp_level)
2237{
2238 struct net_device *ndev;
2239 struct qede_dev *edev;
2240
2241 ndev = alloc_etherdev_mqs(sizeof(*edev),
2242 info->num_queues,
2243 info->num_queues);
2244 if (!ndev) {
2245 pr_err("etherdev allocation failed\n");
2246 return NULL;
2247 }
2248
2249 edev = netdev_priv(ndev);
2250 edev->ndev = ndev;
2251 edev->cdev = cdev;
2252 edev->pdev = pdev;
2253 edev->dp_module = dp_module;
2254 edev->dp_level = dp_level;
2255 edev->ops = qed_ops;
2950219d
YM		 2256 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2257 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2258
e712d52b
YM		 2259 SET_NETDEV_DEV(ndev, &pdev->dev);
2260
133fac0e 2261 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2262 memcpy(&edev->dev_info, info, sizeof(*info));
2263
2264 edev->num_tc = edev->dev_info.num_tc;
2265
7c1bfcad
SRK		 2266 INIT_LIST_HEAD(&edev->vlan_list);
2267
e712d52b
YM		 2268 return edev;
2269}
2270
2271static void qede_init_ndev(struct qede_dev *edev)
2272{
2273 struct net_device *ndev = edev->ndev;
2274 struct pci_dev *pdev = edev->pdev;
2275 u32 hw_features;
2276
2277 pci_set_drvdata(pdev, ndev);
2278
2279 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2280 ndev->base_addr = ndev->mem_start;
2281 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2282 ndev->irq = edev->dev_info.common.pci_irq;
2283
2284 ndev->watchdog_timeo = TX_TIMEOUT;
2285
2950219d
YM		 2286 ndev->netdev_ops = &qede_netdev_ops;
2287
133fac0e
SK		 2288 qede_set_ethtool_ops(ndev);
2289
e712d52b
YM		 2290 /* user-changeble features */
2291 hw_features = NETIF_F_GRO | NETIF_F_SG |
2292 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2293 NETIF_F_TSO | NETIF_F_TSO6;
2294
14db81de
MC		 2295 /* Encap features*/
2296 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2297 NETIF_F_TSO_ECN;
2298 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2299 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2300 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2301 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
2302
e712d52b
YM		 2303 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2304 NETIF_F_HIGHDMA;
2305 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2306 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2307 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2308
2309 ndev->hw_features = hw_features;
2310
2311 /* Set network device HW mac */
2312 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
2313}
2314
2315/* This function converts from 32b param to two params of level and module
2316 * Input 32b decoding:
2317 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2318 * 'happy' flow, e.g. memory allocation failed.
2319 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2320 * and provide important parameters.
2321 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2322 * module. VERBOSE prints are for tracking the specific flow in low level.
2323 *
2324 * Notice that the level should be that of the lowest required logs.
2325 */
133fac0e 2326void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2327{
2328 *p_dp_level = QED_LEVEL_NOTICE;
2329 *p_dp_module = 0;
2330
2331 if (debug & QED_LOG_VERBOSE_MASK) {
2332 *p_dp_level = QED_LEVEL_VERBOSE;
2333 *p_dp_module = (debug & 0x3FFFFFFF);
2334 } else if (debug & QED_LOG_INFO_MASK) {
2335 *p_dp_level = QED_LEVEL_INFO;
2336 } else if (debug & QED_LOG_NOTICE_MASK) {
2337 *p_dp_level = QED_LEVEL_NOTICE;
2338 }
2339}
2340
2950219d
YM		 2341static void qede_free_fp_array(struct qede_dev *edev)
2342{
2343 if (edev->fp_array) {
2344 struct qede_fastpath *fp;
2345 int i;
2346
2347 for_each_rss(i) {
2348 fp = &edev->fp_array[i];
2349
2350 kfree(fp->sb_info);
2351 kfree(fp->rxq);
2352 kfree(fp->txqs);
2353 }
2354 kfree(edev->fp_array);
2355 }
2356 edev->num_rss = 0;
2357}
2358
2359static int qede_alloc_fp_array(struct qede_dev *edev)
2360{
2361 struct qede_fastpath *fp;
2362 int i;
2363
2364 edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
2365 sizeof(*edev->fp_array), GFP_KERNEL);
2366 if (!edev->fp_array) {
2367 DP_NOTICE(edev, "fp array allocation failed\n");
2368 goto err;
2369 }
2370
2371 for_each_rss(i) {
2372 fp = &edev->fp_array[i];
2373
2374 fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
2375 if (!fp->sb_info) {
2376 DP_NOTICE(edev, "sb info struct allocation failed\n");
2377 goto err;
2378 }
2379
2380 fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
2381 if (!fp->rxq) {
2382 DP_NOTICE(edev, "RXQ struct allocation failed\n");
2383 goto err;
2384 }
2385
2386 fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
2387 if (!fp->txqs) {
2388 DP_NOTICE(edev, "TXQ array allocation failed\n");
2389 goto err;
2390 }
2391 }
2392
2393 return 0;
2394err:
2395 qede_free_fp_array(edev);
2396 return -ENOMEM;
2397}
2398
0d8e0aa0
SK		 2399static void qede_sp_task(struct work_struct *work)
2400{
2401 struct qede_dev *edev = container_of(work, struct qede_dev,
2402 sp_task.work);
b18e170c
MC		 2403 struct qed_dev *cdev = edev->cdev;
2404
0d8e0aa0
SK		 2405 mutex_lock(&edev->qede_lock);
2406
2407 if (edev->state == QEDE_STATE_OPEN) {
2408 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2409 qede_config_rx_mode(edev->ndev);
2410 }
2411
b18e170c
MC		 2412 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2413 struct qed_tunn_params tunn_params;
2414
2415 memset(&tunn_params, 0, sizeof(tunn_params));
2416 tunn_params.update_vxlan_port = 1;
2417 tunn_params.vxlan_port = edev->vxlan_dst_port;
2418 qed_ops->tunn_config(cdev, &tunn_params);
2419 }
2420
9a109dd0
MC		 2421 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2422 struct qed_tunn_params tunn_params;
2423
2424 memset(&tunn_params, 0, sizeof(tunn_params));
2425 tunn_params.update_geneve_port = 1;
2426 tunn_params.geneve_port = edev->geneve_dst_port;
2427 qed_ops->tunn_config(cdev, &tunn_params);
2428 }
2429
0d8e0aa0
SK		 2430 mutex_unlock(&edev->qede_lock);
2431}
2432
e712d52b
YM		 2433static void qede_update_pf_params(struct qed_dev *cdev)
2434{
2435 struct qed_pf_params pf_params;
2436
8e0ddc04 2437 /* 64 rx + 64 tx */
e712d52b 2438 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2439 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2440 qed_ops->common->update_pf_params(cdev, &pf_params);
2441}
2442
2443enum qede_probe_mode {
2444 QEDE_PROBE_NORMAL,
2445};
2446
2447static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2448 bool is_vf, enum qede_probe_mode mode)
e712d52b 2449{
1408cc1f 2450 struct qed_probe_params probe_params;
e712d52b
YM		 2451 struct qed_slowpath_params params;
2452 struct qed_dev_eth_info dev_info;
2453 struct qede_dev *edev;
2454 struct qed_dev *cdev;
2455 int rc;
2456
2457 if (unlikely(dp_level & QED_LEVEL_INFO))
2458 pr_notice("Starting qede probe\n");
2459
1408cc1f
YM		 2460 memset(&probe_params, 0, sizeof(probe_params));
2461 probe_params.protocol = QED_PROTOCOL_ETH;
2462 probe_params.dp_module = dp_module;
2463 probe_params.dp_level = dp_level;
2464 probe_params.is_vf = is_vf;
2465 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2466 if (!cdev) {
2467 rc = -ENODEV;
2468 goto err0;
2469 }
2470
2471 qede_update_pf_params(cdev);
2472
2473 /* Start the Slowpath-process */
2474 memset(&params, 0, sizeof(struct qed_slowpath_params));
2475 params.int_mode = QED_INT_MODE_MSIX;
2476 params.drv_major = QEDE_MAJOR_VERSION;
2477 params.drv_minor = QEDE_MINOR_VERSION;
2478 params.drv_rev = QEDE_REVISION_VERSION;
2479 params.drv_eng = QEDE_ENGINEERING_VERSION;
2480 strlcpy(params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2481 rc = qed_ops->common->slowpath_start(cdev, &params);
2482 if (rc) {
2483 pr_notice("Cannot start slowpath\n");
2484 goto err1;
2485 }
2486
2487 /* Learn information crucial for qede to progress */
2488 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2489 if (rc)
2490 goto err2;
2491
2492 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2493 dp_level);
2494 if (!edev) {
2495 rc = -ENOMEM;
2496 goto err2;
2497 }
2498
fefb0202
YM		 2499 if (is_vf)
2500 edev->flags |= QEDE_FLAG_IS_VF;
2501
e712d52b
YM		 2502 qede_init_ndev(edev);
2503
2950219d
YM		 2504 rc = register_netdev(edev->ndev);
2505 if (rc) {
2506 DP_NOTICE(edev, "Cannot register net-device\n");
2507 goto err3;
2508 }
2509
e712d52b
YM		 2510 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2511
a2ec6172
SK		 2512 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2513
489e45ae
SRK		 2514#ifdef CONFIG_DCB
2515 qede_set_dcbnl_ops(edev->ndev);
2516#endif
2517
0d8e0aa0
SK		 2518 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2519 mutex_init(&edev->qede_lock);
2520
e712d52b
YM		 2521 DP_INFO(edev, "Ending successfully qede probe\n");
2522
2523 return 0;
2524
2950219d
YM		 2525err3:
2526 free_netdev(edev->ndev);
e712d52b
YM		 2527err2:
2528 qed_ops->common->slowpath_stop(cdev);
2529err1:
2530 qed_ops->common->remove(cdev);
2531err0:
2532 return rc;
2533}
2534
2535static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2536{
fefb0202 2537 bool is_vf = false;
e712d52b
YM		 2538 u32 dp_module = 0;
2539 u8 dp_level = 0;
2540
fefb0202
YM		 2541 switch ((enum qede_pci_private)id->driver_data) {
2542 case QEDE_PRIVATE_VF:
2543 if (debug & QED_LOG_VERBOSE_MASK)
2544 dev_err(&pdev->dev, "Probing a VF\n");
2545 is_vf = true;
2546 break;
2547 default:
2548 if (debug & QED_LOG_VERBOSE_MASK)
2549 dev_err(&pdev->dev, "Probing a PF\n");
2550 }
2551
e712d52b
YM		 2552 qede_config_debug(debug, &dp_module, &dp_level);
2553
fefb0202 2554 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2555 QEDE_PROBE_NORMAL);
2556}
2557
2558enum qede_remove_mode {
2559 QEDE_REMOVE_NORMAL,
2560};
2561
2562static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2563{
2564 struct net_device *ndev = pci_get_drvdata(pdev);
2565 struct qede_dev *edev = netdev_priv(ndev);
2566 struct qed_dev *cdev = edev->cdev;
2567
2568 DP_INFO(edev, "Starting qede_remove\n");
2569
0d8e0aa0 2570 cancel_delayed_work_sync(&edev->sp_task);
2950219d
YM		 2571 unregister_netdev(ndev);
2572
e712d52b
YM		 2573 edev->ops->common->set_power_state(cdev, PCI_D0);
2574
2575 pci_set_drvdata(pdev, NULL);
2576
2577 free_netdev(ndev);
2578
2579 /* Use global ops since we've freed edev */
2580 qed_ops->common->slowpath_stop(cdev);
2581 qed_ops->common->remove(cdev);
2582
2583 pr_notice("Ending successfully qede_remove\n");
2584}
2585
2586static void qede_remove(struct pci_dev *pdev)
2587{
2588 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2589}
2950219d
YM		 2590
2591/* -------------------------------------------------------------------------
2592 * START OF LOAD / UNLOAD
2593 * -------------------------------------------------------------------------
2594 */
2595
2596static int qede_set_num_queues(struct qede_dev *edev)
2597{
2598 int rc;
2599 u16 rss_num;
2600
2601 /* Setup queues according to possible resources*/
8edf049d
SK		 2602 if (edev->req_rss)
2603 rss_num = edev->req_rss;
2604 else
2605 rss_num = netif_get_num_default_rss_queues() *
2606 edev->dev_info.common.num_hwfns;
2950219d
YM		 2607
2608 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2609
2610 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2611 if (rc > 0) {
2612 /* Managed to request interrupts for our queues */
2613 edev->num_rss = rc;
2614 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
2615 QEDE_RSS_CNT(edev), rss_num);
2616 rc = 0;
2617 }
2618 return rc;
2619}
2620
2621static void qede_free_mem_sb(struct qede_dev *edev,
2622 struct qed_sb_info *sb_info)
2623{
2624 if (sb_info->sb_virt)
2625 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2626 (void *)sb_info->sb_virt, sb_info->sb_phys);
2627}
2628
2629/* This function allocates fast-path status block memory */
2630static int qede_alloc_mem_sb(struct qede_dev *edev,
2631 struct qed_sb_info *sb_info,
2632 u16 sb_id)
2633{
2634 struct status_block *sb_virt;
2635 dma_addr_t sb_phys;
2636 int rc;
2637
2638 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
2639 sizeof(*sb_virt),
2640 &sb_phys, GFP_KERNEL);
2641 if (!sb_virt) {
2642 DP_ERR(edev, "Status block allocation failed\n");
2643 return -ENOMEM;
2644 }
2645
2646 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2647 sb_virt, sb_phys, sb_id,
2648 QED_SB_TYPE_L2_QUEUE);
2649 if (rc) {
2650 DP_ERR(edev, "Status block initialization failed\n");
2651 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2652 sb_virt, sb_phys);
2653 return rc;
2654 }
2655
2656 return 0;
2657}
2658
2659static void qede_free_rx_buffers(struct qede_dev *edev,
2660 struct qede_rx_queue *rxq)
2661{
2662 u16 i;
2663
2664 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2665 struct sw_rx_data *rx_buf;
fc48b7a6 2666 struct page *data;
2950219d
YM		 2667
2668 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2669 data = rx_buf->data;
2670
fc48b7a6
YM		 2671 dma_unmap_page(&edev->pdev->dev,
2672 rx_buf->mapping,
2673 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2674
2675 rx_buf->data = NULL;
fc48b7a6 2676 __free_page(data);
2950219d
YM		 2677 }
2678}
2679
55482edc
MC		 2680static void qede_free_sge_mem(struct qede_dev *edev,
2681 struct qede_rx_queue *rxq) {
2682 int i;
2683
2684 if (edev->gro_disable)
2685 return;
2686
2687 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2688 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2689 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2690
f86af2df 2691 if (replace_buf->data) {
55482edc 2692 dma_unmap_page(&edev->pdev->dev,
09ec8e7f 2693 replace_buf->mapping,
55482edc
MC		 2694 PAGE_SIZE, DMA_FROM_DEVICE);
2695 __free_page(replace_buf->data);
2696 }
2697 }
2698}
2699
2950219d
YM		 2700static void qede_free_mem_rxq(struct qede_dev *edev,
2701 struct qede_rx_queue *rxq)
2702{
55482edc
MC		 2703 qede_free_sge_mem(edev, rxq);
2704
2950219d
YM		 2705 /* Free rx buffers */
2706 qede_free_rx_buffers(edev, rxq);
2707
2708 /* Free the parallel SW ring */
2709 kfree(rxq->sw_rx_ring);
2710
2711 /* Free the real RQ ring used by FW */
2712 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2713 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2714}
2715
2716static int qede_alloc_rx_buffer(struct qede_dev *edev,
2717 struct qede_rx_queue *rxq)
2718{
2719 struct sw_rx_data *sw_rx_data;
2720 struct eth_rx_bd *rx_bd;
2721 dma_addr_t mapping;
fc48b7a6 2722 struct page *data;
2950219d 2723 u16 rx_buf_size;
2950219d
YM		 2724
2725 rx_buf_size = rxq->rx_buf_size;
2726
fc48b7a6 2727 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2728 if (unlikely(!data)) {
fc48b7a6 2729 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2730 return -ENOMEM;
2731 }
2732
fc48b7a6
YM		 2733 /* Map the entire page as it would be used
2734 * for multiple RX buffer segment size mapping.
2735 */
2736 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2737 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2738 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2739 __free_page(data);
2950219d
YM		 2740 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2741 return -ENOMEM;
2742 }
2743
2744 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2745 sw_rx_data->page_offset = 0;
2950219d 2746 sw_rx_data->data = data;
fc48b7a6 2747 sw_rx_data->mapping = mapping;
2950219d
YM		 2748
2749 /* Advance PROD and get BD pointer */
2750 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2751 WARN_ON(!rx_bd);
2752 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2753 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2754
2755 rxq->sw_rx_prod++;
2756
2757 return 0;
2758}
2759
55482edc
MC		 2760static int qede_alloc_sge_mem(struct qede_dev *edev,
2761 struct qede_rx_queue *rxq)
2762{
2763 dma_addr_t mapping;
2764 int i;
2765
2766 if (edev->gro_disable)
2767 return 0;
2768
2769 if (edev->ndev->mtu > PAGE_SIZE) {
2770 edev->gro_disable = 1;
2771 return 0;
2772 }
2773
2774 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2775 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
2776 struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
2777
2778 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2779 if (unlikely(!replace_buf->data)) {
2780 DP_NOTICE(edev,
2781 "Failed to allocate TPA skb pool [replacement buffer]\n");
2782 goto err;
2783 }
2784
2785 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
2786 rxq->rx_buf_size, DMA_FROM_DEVICE);
2787 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2788 DP_NOTICE(edev,
2789 "Failed to map TPA replacement buffer\n");
2790 goto err;
2791 }
2792
09ec8e7f 2793 replace_buf->mapping = mapping;
55482edc
MC		 2794 tpa_info->replace_buf.page_offset = 0;
2795
2796 tpa_info->replace_buf_mapping = mapping;
2797 tpa_info->agg_state = QEDE_AGG_STATE_NONE;
2798 }
2799
2800 return 0;
2801err:
2802 qede_free_sge_mem(edev, rxq);
2803 edev->gro_disable = 1;
2804 return -ENOMEM;
2805}
2806
2950219d
YM		 2807/* This function allocates all memory needed per Rx queue */
2808static int qede_alloc_mem_rxq(struct qede_dev *edev,
2809 struct qede_rx_queue *rxq)
2810{
f86af2df 2811 int i, rc, size;
2950219d
YM		 2812
2813 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2814
fc48b7a6
YM		 2815 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD +
2816 edev->ndev->mtu;
2817 if (rxq->rx_buf_size > PAGE_SIZE)
2818 rxq->rx_buf_size = PAGE_SIZE;
2819
2820 /* Segment size to spilt a page in multiple equal parts */
2821 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2822
2823 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2824 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2825 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2826 if (!rxq->sw_rx_ring) {
2827 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2828 rc = -ENOMEM;
2950219d
YM		 2829 goto err;
2830 }
2831
2832 /* Allocate FW Rx ring */
2833 rc = edev->ops->common->chain_alloc(edev->cdev,
2834 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2835 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 2836 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2837 RX_RING_SIZE,
2950219d
YM		 2838 sizeof(struct eth_rx_bd),
2839 &rxq->rx_bd_ring);
2840
2841 if (rc)
2842 goto err;
2843
2844 /* Allocate FW completion ring */
2845 rc = edev->ops->common->chain_alloc(edev->cdev,
2846 QED_CHAIN_USE_TO_CONSUME,
2847 QED_CHAIN_MODE_PBL,
a91eb52a 2848 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2849 RX_RING_SIZE,
2950219d
YM		 2850 sizeof(union eth_rx_cqe),
2851 &rxq->rx_comp_ring);
2852 if (rc)
2853 goto err;
2854
2855 /* Allocate buffers for the Rx ring */
2856 for (i = 0; i < rxq->num_rx_buffers; i++) {
2857 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2858 if (rc) {
2859 DP_ERR(edev,
2860 "Rx buffers allocation failed at index %d\n", i);
2861 goto err;
2862 }
2950219d
YM		 2863 }
2864
f86af2df 2865 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 2866err:
f86af2df 2867 return rc;
2950219d
YM		 2868}
2869
2870static void qede_free_mem_txq(struct qede_dev *edev,
2871 struct qede_tx_queue *txq)
2872{
2873 /* Free the parallel SW ring */
2874 kfree(txq->sw_tx_ring);
2875
2876 /* Free the real RQ ring used by FW */
2877 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
2878}
2879
2880/* This function allocates all memory needed per Tx queue */
2881static int qede_alloc_mem_txq(struct qede_dev *edev,
2882 struct qede_tx_queue *txq)
2883{
2884 int size, rc;
2885 union eth_tx_bd_types *p_virt;
2886
2887 txq->num_tx_buffers = edev->q_num_tx_buffers;
2888
2889 /* Allocate the parallel driver ring for Tx buffers */
2890 size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
2891 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
2892 if (!txq->sw_tx_ring) {
2893 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
2894 goto err;
2895 }
2896
2897 rc = edev->ops->common->chain_alloc(edev->cdev,
2898 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2899 QED_CHAIN_MODE_PBL,
a91eb52a 2900 QED_CHAIN_CNT_TYPE_U16,
2950219d 2901 NUM_TX_BDS_MAX,
a91eb52a 2902 sizeof(*p_virt), &txq->tx_pbl);
2950219d
YM		 2903 if (rc)
2904 goto err;
2905
2906 return 0;
2907
2908err:
2909 qede_free_mem_txq(edev, txq);
2910 return -ENOMEM;
2911}
2912
2913/* This function frees all memory of a single fp */
2914static void qede_free_mem_fp(struct qede_dev *edev,
2915 struct qede_fastpath *fp)
2916{
2917 int tc;
2918
2919 qede_free_mem_sb(edev, fp->sb_info);
2920
2921 qede_free_mem_rxq(edev, fp->rxq);
2922
2923 for (tc = 0; tc < edev->num_tc; tc++)
2924 qede_free_mem_txq(edev, &fp->txqs[tc]);
2925}
2926
2927/* This function allocates all memory needed for a single fp (i.e. an entity
2928 * which contains status block, one rx queue and multiple per-TC tx queues.
2929 */
2930static int qede_alloc_mem_fp(struct qede_dev *edev,
2931 struct qede_fastpath *fp)
2932{
2933 int rc, tc;
2934
2935 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
2936 if (rc)
2937 goto err;
2938
2939 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2940 if (rc)
2941 goto err;
2942
2943 for (tc = 0; tc < edev->num_tc; tc++) {
2944 rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
2945 if (rc)
2946 goto err;
2947 }
2948
2949 return 0;
2950219d 2950err:
f86af2df 2951 return rc;
2950219d
YM		 2952}
2953
2954static void qede_free_mem_load(struct qede_dev *edev)
2955{
2956 int i;
2957
2958 for_each_rss(i) {
2959 struct qede_fastpath *fp = &edev->fp_array[i];
2960
2961 qede_free_mem_fp(edev, fp);
2962 }
2963}
2964
2965/* This function allocates all qede memory at NIC load. */
2966static int qede_alloc_mem_load(struct qede_dev *edev)
2967{
2968 int rc = 0, rss_id;
2969
2970 for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
2971 struct qede_fastpath *fp = &edev->fp_array[rss_id];
2972
2973 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 2974 if (rc) {
2950219d 2975 DP_ERR(edev,
f86af2df
MC		 2976 "Failed to allocate memory for fastpath - rss id = %d\n",
2977 rss_id);
2978 qede_free_mem_load(edev);
2979 return rc;
2950219d 2980 }
2950219d
YM		 2981 }
2982
2983 return 0;
2984}
2985
2986/* This function inits fp content and resets the SB, RXQ and TXQ structures */
2987static void qede_init_fp(struct qede_dev *edev)
2988{
2989 int rss_id, txq_index, tc;
2990 struct qede_fastpath *fp;
2991
2992 for_each_rss(rss_id) {
2993 fp = &edev->fp_array[rss_id];
2994
2995 fp->edev = edev;
2996 fp->rss_id = rss_id;
2997
2998 memset((void *)&fp->napi, 0, sizeof(fp->napi));
2999
3000 memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
3001
3002 memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
3003 fp->rxq->rxq_id = rss_id;
3004
3005 memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
3006 for (tc = 0; tc < edev->num_tc; tc++) {
3007 txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
3008 fp->txqs[tc].index = txq_index;
3009 }
3010
3011 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
3012 edev->ndev->name, rss_id);
3013 }
55482edc
MC		 3014
3015 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 3016}
3017
3018static int qede_set_real_num_queues(struct qede_dev *edev)
3019{
3020 int rc = 0;
3021
3022 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
3023 if (rc) {
3024 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
3025 return rc;
3026 }
3027 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
3028 if (rc) {
3029 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
3030 return rc;
3031 }
3032
3033 return 0;
3034}
3035
3036static void qede_napi_disable_remove(struct qede_dev *edev)
3037{
3038 int i;
3039
3040 for_each_rss(i) {
3041 napi_disable(&edev->fp_array[i].napi);
3042
3043 netif_napi_del(&edev->fp_array[i].napi);
3044 }
3045}
3046
3047static void qede_napi_add_enable(struct qede_dev *edev)
3048{
3049 int i;
3050
3051 /* Add NAPI objects */
3052 for_each_rss(i) {
3053 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
3054 qede_poll, NAPI_POLL_WEIGHT);
3055 napi_enable(&edev->fp_array[i].napi);
3056 }
3057}
3058
3059static void qede_sync_free_irqs(struct qede_dev *edev)
3060{
3061 int i;
3062
3063 for (i = 0; i < edev->int_info.used_cnt; i++) {
3064 if (edev->int_info.msix_cnt) {
3065 synchronize_irq(edev->int_info.msix[i].vector);
3066 free_irq(edev->int_info.msix[i].vector,
3067 &edev->fp_array[i]);
3068 } else {
3069 edev->ops->common->simd_handler_clean(edev->cdev, i);
3070 }
3071 }
3072
3073 edev->int_info.used_cnt = 0;
3074}
3075
3076static int qede_req_msix_irqs(struct qede_dev *edev)
3077{
3078 int i, rc;
3079
3080 /* Sanitize number of interrupts == number of prepared RSS queues */
3081 if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
3082 DP_ERR(edev,
3083 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
3084 QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
3085 return -EINVAL;
3086 }
3087
3088 for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
3089 rc = request_irq(edev->int_info.msix[i].vector,
3090 qede_msix_fp_int, 0, edev->fp_array[i].name,
3091 &edev->fp_array[i]);
3092 if (rc) {
3093 DP_ERR(edev, "Request fp %d irq failed\n", i);
3094 qede_sync_free_irqs(edev);
3095 return rc;
3096 }
3097 DP_VERBOSE(edev, NETIF_MSG_INTR,
3098 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
3099 edev->fp_array[i].name, i,
3100 &edev->fp_array[i]);
3101 edev->int_info.used_cnt++;
3102 }
3103
3104 return 0;
3105}
3106
3107static void qede_simd_fp_handler(void *cookie)
3108{
3109 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
3110
3111 napi_schedule_irqoff(&fp->napi);
3112}
3113
3114static int qede_setup_irqs(struct qede_dev *edev)
3115{
3116 int i, rc = 0;
3117
3118 /* Learn Interrupt configuration */
3119 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
3120 if (rc)
3121 return rc;
3122
3123 if (edev->int_info.msix_cnt) {
3124 rc = qede_req_msix_irqs(edev);
3125 if (rc)
3126 return rc;
3127 edev->ndev->irq = edev->int_info.msix[0].vector;
3128 } else {
3129 const struct qed_common_ops *ops;
3130
3131 /* qed should learn receive the RSS ids and callbacks */
3132 ops = edev->ops->common;
3133 for (i = 0; i < QEDE_RSS_CNT(edev); i++)
3134 ops->simd_handler_config(edev->cdev,
3135 &edev->fp_array[i], i,
3136 qede_simd_fp_handler);
3137 edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
3138 }
3139 return 0;
3140}
3141
3142static int qede_drain_txq(struct qede_dev *edev,
3143 struct qede_tx_queue *txq,
3144 bool allow_drain)
3145{
3146 int rc, cnt = 1000;
3147
3148 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3149 if (!cnt) {
3150 if (allow_drain) {
3151 DP_NOTICE(edev,
3152 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3153 txq->index);
3154 rc = edev->ops->common->drain(edev->cdev);
3155 if (rc)
3156 return rc;
3157 return qede_drain_txq(edev, txq, false);
3158 }
3159 DP_NOTICE(edev,
3160 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3161 txq->index, txq->sw_tx_prod,
3162 txq->sw_tx_cons);
3163 return -ENODEV;
3164 }
3165 cnt--;
3166 usleep_range(1000, 2000);
3167 barrier();
3168 }
3169
3170 /* FW finished processing, wait for HW to transmit all tx packets */
3171 usleep_range(1000, 2000);
3172
3173 return 0;
3174}
3175
3176static int qede_stop_queues(struct qede_dev *edev)
3177{
3178 struct qed_update_vport_params vport_update_params;
3179 struct qed_dev *cdev = edev->cdev;
3180 int rc, tc, i;
3181
3182 /* Disable the vport */
3183 memset(&vport_update_params, 0, sizeof(vport_update_params));
3184 vport_update_params.vport_id = 0;
3185 vport_update_params.update_vport_active_flg = 1;
3186 vport_update_params.vport_active_flg = 0;
3187 vport_update_params.update_rss_flg = 0;
3188
3189 rc = edev->ops->vport_update(cdev, &vport_update_params);
3190 if (rc) {
3191 DP_ERR(edev, "Failed to update vport\n");
3192 return rc;
3193 }
3194
3195 /* Flush Tx queues. If needed, request drain from MCP */
3196 for_each_rss(i) {
3197 struct qede_fastpath *fp = &edev->fp_array[i];
3198
3199 for (tc = 0; tc < edev->num_tc; tc++) {
3200 struct qede_tx_queue *txq = &fp->txqs[tc];
3201
3202 rc = qede_drain_txq(edev, txq, true);
3203 if (rc)
3204 return rc;
3205 }
3206 }
3207
3208 /* Stop all Queues in reverse order*/
3209 for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
3210 struct qed_stop_rxq_params rx_params;
3211
3212 /* Stop the Tx Queue(s)*/
3213 for (tc = 0; tc < edev->num_tc; tc++) {
3214 struct qed_stop_txq_params tx_params;
3215
3216 tx_params.rss_id = i;
3217 tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
3218 rc = edev->ops->q_tx_stop(cdev, &tx_params);
3219 if (rc) {
3220 DP_ERR(edev, "Failed to stop TXQ #%d\n",
3221 tx_params.tx_queue_id);
3222 return rc;
3223 }
3224 }
3225
3226 /* Stop the Rx Queue*/
3227 memset(&rx_params, 0, sizeof(rx_params));
3228 rx_params.rss_id = i;
3229 rx_params.rx_queue_id = i;
3230
3231 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3232 if (rc) {
3233 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3234 return rc;
3235 }
3236 }
3237
3238 /* Stop the vport */
3239 rc = edev->ops->vport_stop(cdev, 0);
3240 if (rc)
3241 DP_ERR(edev, "Failed to stop VPORT\n");
3242
3243 return rc;
3244}
3245
a0d26d5a 3246static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d
YM		 3247{
3248 int rc, tc, i;
088c8618 3249 int vlan_removal_en = 1;
2950219d 3250 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3251 struct qed_update_vport_params vport_update_params;
3252 struct qed_queue_start_common_params q_params;
fefb0202 3253 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3254 struct qed_start_vport_params start = {0};
961acdea 3255 bool reset_rss_indir = false;
2950219d
YM		 3256
3257 if (!edev->num_rss) {
3258 DP_ERR(edev,
3259 "Cannot update V-VPORT as active as there are no Rx queues\n");
3260 return -EINVAL;
3261 }
3262
55482edc 3263 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3264 start.mtu = edev->ndev->mtu;
3265 start.vport_id = 0;
3266 start.drop_ttl0 = true;
3267 start.remove_inner_vlan = vlan_removal_en;
3268
3269 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3270
3271 if (rc) {
3272 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3273 return rc;
3274 }
3275
3276 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3277 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3278 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d
YM		 3279
3280 for_each_rss(i) {
3281 struct qede_fastpath *fp = &edev->fp_array[i];
3282 dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
3283
3284 memset(&q_params, 0, sizeof(q_params));
3285 q_params.rss_id = i;
3286 q_params.queue_id = i;
3287 q_params.vport_id = 0;
3288 q_params.sb = fp->sb_info->igu_sb_id;
3289 q_params.sb_idx = RX_PI;
3290
3291 rc = edev->ops->q_rx_start(cdev, &q_params,
3292 fp->rxq->rx_buf_size,
3293 fp->rxq->rx_bd_ring.p_phys_addr,
3294 phys_table,
3295 fp->rxq->rx_comp_ring.page_cnt,
3296 &fp->rxq->hw_rxq_prod_addr);
3297 if (rc) {
3298 DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
3299 return rc;
3300 }
3301
3302 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
3303
3304 qede_update_rx_prod(edev, fp->rxq);
3305
3306 for (tc = 0; tc < edev->num_tc; tc++) {
3307 struct qede_tx_queue *txq = &fp->txqs[tc];
3308 int txq_index = tc * QEDE_RSS_CNT(edev) + i;
3309
3310 memset(&q_params, 0, sizeof(q_params));
3311 q_params.rss_id = i;
3312 q_params.queue_id = txq_index;
3313 q_params.vport_id = 0;
3314 q_params.sb = fp->sb_info->igu_sb_id;
3315 q_params.sb_idx = TX_PI(tc);
3316
3317 rc = edev->ops->q_tx_start(cdev, &q_params,
3318 txq->tx_pbl.pbl.p_phys_table,
3319 txq->tx_pbl.page_cnt,
3320 &txq->doorbell_addr);
3321 if (rc) {
3322 DP_ERR(edev, "Start TXQ #%d failed %d\n",
3323 txq_index, rc);
3324 return rc;
3325 }
3326
3327 txq->hw_cons_ptr =
3328 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
3329 SET_FIELD(txq->tx_db.data.params,
3330 ETH_DB_DATA_DEST, DB_DEST_XCM);
3331 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3332 DB_AGG_CMD_SET);
3333 SET_FIELD(txq->tx_db.data.params,
3334 ETH_DB_DATA_AGG_VAL_SEL,
3335 DQ_XCM_ETH_TX_BD_PROD_CMD);
3336
3337 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3338 }
3339 }
3340
3341 /* Prepare and send the vport enable */
3342 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3343 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3344 vport_update_params.update_vport_active_flg = 1;
3345 vport_update_params.vport_active_flg = 1;
3346
831bfb0e
YM		 3347 if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
3348 qed_info->tx_switching) {
3349 vport_update_params.update_tx_switching_flg = 1;
3350 vport_update_params.tx_switching_flg = 1;
3351 }
3352
2950219d
YM		 3353 /* Fill struct with RSS params */
3354 if (QEDE_RSS_CNT(edev) > 1) {
3355 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3356
3357 /* Need to validate current RSS config uses valid entries */
3358 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3359 if (edev->rss_params.rss_ind_table[i] >=
3360 edev->num_rss) {
3361 reset_rss_indir = true;
3362 break;
3363 }
3364 }
3365
3366 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3367 reset_rss_indir) {
3368 u16 val;
3369
3370 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3371 u16 indir_val;
3372
3373 val = QEDE_RSS_CNT(edev);
3374 indir_val = ethtool_rxfh_indir_default(i, val);
3375 edev->rss_params.rss_ind_table[i] = indir_val;
3376 }
3377 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3378 }
3379
3380 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3381 netdev_rss_key_fill(edev->rss_params.rss_key,
3382 sizeof(edev->rss_params.rss_key));
3383 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3384 }
3385
3386 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3387 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3388 QED_RSS_IPV6 |
3389 QED_RSS_IPV4_TCP |
3390 QED_RSS_IPV6_TCP;
3391 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3392 }
3393
3394 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3395 sizeof(vport_update_params.rss_params));
2950219d 3396 } else {
961acdea
SRK		 3397 memset(&vport_update_params.rss_params, 0,
3398 sizeof(vport_update_params.rss_params));
2950219d 3399 }
2950219d
YM		 3400
3401 rc = edev->ops->vport_update(cdev, &vport_update_params);
3402 if (rc) {
3403 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3404 return rc;
3405 }
3406
3407 return 0;
3408}
3409
0d8e0aa0
SK		 3410static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3411 enum qed_filter_xcast_params_type opcode,
3412 unsigned char *mac, int num_macs)
3413{
3414 struct qed_filter_params filter_cmd;
3415 int i;
3416
3417 memset(&filter_cmd, 0, sizeof(filter_cmd));
3418 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3419 filter_cmd.filter.mcast.type = opcode;
3420 filter_cmd.filter.mcast.num = num_macs;
3421
3422 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3423 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3424
3425 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3426}
3427
2950219d
YM		 3428enum qede_unload_mode {
3429 QEDE_UNLOAD_NORMAL,
3430};
3431
3432static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3433{
a2ec6172 3434 struct qed_link_params link_params;
2950219d
YM		 3435 int rc;
3436
3437 DP_INFO(edev, "Starting qede unload\n");
3438
0d8e0aa0
SK		 3439 mutex_lock(&edev->qede_lock);
3440 edev->state = QEDE_STATE_CLOSED;
3441
2950219d
YM		 3442 /* Close OS Tx */
3443 netif_tx_disable(edev->ndev);
3444 netif_carrier_off(edev->ndev);
3445
a2ec6172
SK		 3446 /* Reset the link */
3447 memset(&link_params, 0, sizeof(link_params));
3448 link_params.link_up = false;
3449 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3450 rc = qede_stop_queues(edev);
3451 if (rc) {
3452 qede_sync_free_irqs(edev);
3453 goto out;
3454 }
3455
3456 DP_INFO(edev, "Stopped Queues\n");
3457
7c1bfcad 3458 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3459 edev->ops->fastpath_stop(edev->cdev);
3460
3461 /* Release the interrupts */
3462 qede_sync_free_irqs(edev);
3463 edev->ops->common->set_fp_int(edev->cdev, 0);
3464
3465 qede_napi_disable_remove(edev);
3466
3467 qede_free_mem_load(edev);
3468 qede_free_fp_array(edev);
3469
3470out:
3471 mutex_unlock(&edev->qede_lock);
3472 DP_INFO(edev, "Ending qede unload\n");
3473}
3474
3475enum qede_load_mode {
3476 QEDE_LOAD_NORMAL,
a0d26d5a 3477 QEDE_LOAD_RELOAD,
2950219d
YM		 3478};
3479
3480static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3481{
a2ec6172
SK		 3482 struct qed_link_params link_params;
3483 struct qed_link_output link_output;
2950219d
YM		 3484 int rc;
3485
3486 DP_INFO(edev, "Starting qede load\n");
3487
3488 rc = qede_set_num_queues(edev);
3489 if (rc)
3490 goto err0;
3491
3492 rc = qede_alloc_fp_array(edev);
3493 if (rc)
3494 goto err0;
3495
3496 qede_init_fp(edev);
3497
3498 rc = qede_alloc_mem_load(edev);
3499 if (rc)
3500 goto err1;
3501 DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
3502 QEDE_RSS_CNT(edev), edev->num_tc);
3503
3504 rc = qede_set_real_num_queues(edev);
3505 if (rc)
3506 goto err2;
3507
3508 qede_napi_add_enable(edev);
3509 DP_INFO(edev, "Napi added and enabled\n");
3510
3511 rc = qede_setup_irqs(edev);
3512 if (rc)
3513 goto err3;
3514 DP_INFO(edev, "Setup IRQs succeeded\n");
3515
a0d26d5a 3516 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 3517 if (rc)
3518 goto err4;
3519 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3520
3521 /* Add primary mac and set Rx filters */
3522 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3523
0d8e0aa0
SK		 3524 mutex_lock(&edev->qede_lock);
3525 edev->state = QEDE_STATE_OPEN;
3526 mutex_unlock(&edev->qede_lock);
a2ec6172 3527
7c1bfcad
SRK		 3528 /* Program un-configured VLANs */
3529 qede_configure_vlan_filters(edev);
3530
a2ec6172
SK		 3531 /* Ask for link-up using current configuration */
3532 memset(&link_params, 0, sizeof(link_params));
3533 link_params.link_up = true;
3534 edev->ops->common->set_link(edev->cdev, &link_params);
3535
3536 /* Query whether link is already-up */
3537 memset(&link_output, 0, sizeof(link_output));
3538 edev->ops->common->get_link(edev->cdev, &link_output);
3539 qede_link_update(edev, &link_output);
3540
2950219d
YM		 3541 DP_INFO(edev, "Ending successfully qede load\n");
3542
3543 return 0;
3544
3545err4:
3546 qede_sync_free_irqs(edev);
3547 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3548err3:
3549 qede_napi_disable_remove(edev);
3550err2:
3551 qede_free_mem_load(edev);
3552err1:
3553 edev->ops->common->set_fp_int(edev->cdev, 0);
3554 qede_free_fp_array(edev);
3555 edev->num_rss = 0;
3556err0:
3557 return rc;
3558}
3559
133fac0e
SK		 3560void qede_reload(struct qede_dev *edev,
3561 void (*func)(struct qede_dev *, union qede_reload_args *),
3562 union qede_reload_args *args)
3563{
3564 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3565 /* Call function handler to update parameters
3566 * needed for function load.
3567 */
3568 if (func)
3569 func(edev, args);
3570
a0d26d5a 3571 qede_load(edev, QEDE_LOAD_RELOAD);
133fac0e
SK		 3572
3573 mutex_lock(&edev->qede_lock);
3574 qede_config_rx_mode(edev->ndev);
3575 mutex_unlock(&edev->qede_lock);
3576}
3577
2950219d
YM		 3578/* called with rtnl_lock */
3579static int qede_open(struct net_device *ndev)
3580{
3581 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3582 int rc;
2950219d
YM		 3583
3584 netif_carrier_off(ndev);
3585
3586 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3587
b18e170c
MC		 3588 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3589
3590 if (rc)
3591 return rc;
3592
f9f082a9
AD		 3593 udp_tunnel_get_rx_info(ndev);
3594
b18e170c 3595 return 0;
2950219d
YM		 3596}
3597
3598static int qede_close(struct net_device *ndev)
3599{
3600 struct qede_dev *edev = netdev_priv(ndev);
3601
3602 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3603
3604 return 0;
3605}
0d8e0aa0 3606
a2ec6172
SK		 3607static void qede_link_update(void *dev, struct qed_link_output *link)
3608{
3609 struct qede_dev *edev = dev;
3610
3611 if (!netif_running(edev->ndev)) {
3612 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3613 return;
3614 }
3615
3616 if (link->link_up) {
8e025ae2
YM		 3617 if (!netif_carrier_ok(edev->ndev)) {
3618 DP_NOTICE(edev, "Link is up\n");
3619 netif_tx_start_all_queues(edev->ndev);
3620 netif_carrier_on(edev->ndev);
3621 }
a2ec6172 3622 } else {
8e025ae2
YM		 3623 if (netif_carrier_ok(edev->ndev)) {
3624 DP_NOTICE(edev, "Link is down\n");
3625 netif_tx_disable(edev->ndev);
3626 netif_carrier_off(edev->ndev);
3627 }
a2ec6172
SK		 3628 }
3629}
3630
0d8e0aa0
SK		 3631static int qede_set_mac_addr(struct net_device *ndev, void *p)
3632{
3633 struct qede_dev *edev = netdev_priv(ndev);
3634 struct sockaddr *addr = p;
3635 int rc;
3636
3637 ASSERT_RTNL(); /* @@@TBD To be removed */
3638
3639 DP_INFO(edev, "Set_mac_addr called\n");
3640
3641 if (!is_valid_ether_addr(addr->sa_data)) {
3642 DP_NOTICE(edev, "The MAC address is not valid\n");
3643 return -EFAULT;
3644 }
3645
eff16960
YM		 3646 if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
3647 DP_NOTICE(edev, "qed prevents setting MAC\n");
3648 return -EINVAL;
3649 }
3650
0d8e0aa0
SK		 3651 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3652
3653 if (!netif_running(ndev)) {
3654 DP_NOTICE(edev, "The device is currently down\n");
3655 return 0;
3656 }
3657
3658 /* Remove the previous primary mac */
3659 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3660 edev->primary_mac);
3661 if (rc)
3662 return rc;
3663
3664 /* Add MAC filter according to the new unicast HW MAC address */
3665 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3666 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3667 edev->primary_mac);
3668}
3669
3670static int
3671qede_configure_mcast_filtering(struct net_device *ndev,
3672 enum qed_filter_rx_mode_type *accept_flags)
3673{
3674 struct qede_dev *edev = netdev_priv(ndev);
3675 unsigned char *mc_macs, *temp;
3676 struct netdev_hw_addr *ha;
3677 int rc = 0, mc_count;
3678 size_t size;
3679
3680 size = 64 * ETH_ALEN;
3681
3682 mc_macs = kzalloc(size, GFP_KERNEL);
3683 if (!mc_macs) {
3684 DP_NOTICE(edev,
3685 "Failed to allocate memory for multicast MACs\n");
3686 rc = -ENOMEM;
3687 goto exit;
3688 }
3689
3690 temp = mc_macs;
3691
3692 /* Remove all previously configured MAC filters */
3693 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3694 mc_macs, 1);
3695 if (rc)
3696 goto exit;
3697
3698 netif_addr_lock_bh(ndev);
3699
3700 mc_count = netdev_mc_count(ndev);
3701 if (mc_count < 64) {
3702 netdev_for_each_mc_addr(ha, ndev) {
3703 ether_addr_copy(temp, ha->addr);
3704 temp += ETH_ALEN;
3705 }
3706 }
3707
3708 netif_addr_unlock_bh(ndev);
3709
3710 /* Check for all multicast @@@TBD resource allocation */
3711 if ((ndev->flags & IFF_ALLMULTI) ||
3712 (mc_count > 64)) {
3713 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3714 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3715 } else {
3716 /* Add all multicast MAC filters */
3717 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3718 mc_macs, mc_count);
3719 }
3720
3721exit:
3722 kfree(mc_macs);
3723 return rc;
3724}
3725
3726static void qede_set_rx_mode(struct net_device *ndev)
3727{
3728 struct qede_dev *edev = netdev_priv(ndev);
3729
3730 DP_INFO(edev, "qede_set_rx_mode called\n");
3731
3732 if (edev->state != QEDE_STATE_OPEN) {
3733 DP_INFO(edev,
3734 "qede_set_rx_mode called while interface is down\n");
3735 } else {
3736 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3737 schedule_delayed_work(&edev->sp_task, 0);
3738 }
3739}
3740
3741/* Must be called with qede_lock held */
3742static void qede_config_rx_mode(struct net_device *ndev)
3743{
3744 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3745 struct qede_dev *edev = netdev_priv(ndev);
3746 struct qed_filter_params rx_mode;
3747 unsigned char *uc_macs, *temp;
3748 struct netdev_hw_addr *ha;
3749 int rc, uc_count;
3750 size_t size;
3751
3752 netif_addr_lock_bh(ndev);
3753
3754 uc_count = netdev_uc_count(ndev);
3755 size = uc_count * ETH_ALEN;
3756
3757 uc_macs = kzalloc(size, GFP_ATOMIC);
3758 if (!uc_macs) {
3759 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3760 netif_addr_unlock_bh(ndev);
3761 return;
3762 }
3763
3764 temp = uc_macs;
3765 netdev_for_each_uc_addr(ha, ndev) {
3766 ether_addr_copy(temp, ha->addr);
3767 temp += ETH_ALEN;
3768 }
3769
3770 netif_addr_unlock_bh(ndev);
3771
3772 /* Configure the struct for the Rx mode */
3773 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3774 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3775
3776 /* Remove all previous unicast secondary macs and multicast macs
3777 * (configrue / leave the primary mac)
3778 */
3779 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3780 edev->primary_mac);
3781 if (rc)
3782 goto out;
3783
3784 /* Check for promiscuous */
3785 if ((ndev->flags & IFF_PROMISC) ||
3786 (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
3787 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3788 } else {
3789 /* Add MAC filters according to the unicast secondary macs */
3790 int i;
3791
3792 temp = uc_macs;
3793 for (i = 0; i < uc_count; i++) {
3794 rc = qede_set_ucast_rx_mac(edev,
3795 QED_FILTER_XCAST_TYPE_ADD,
3796 temp);
3797 if (rc)
3798 goto out;
3799
3800 temp += ETH_ALEN;
3801 }
3802
3803 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3804 if (rc)
3805 goto out;
3806 }
3807
7c1bfcad
SRK		 3808 /* take care of VLAN mode */
3809 if (ndev->flags & IFF_PROMISC) {
3810 qede_config_accept_any_vlan(edev, true);
3811 } else if (!edev->non_configured_vlans) {
3812 /* It's possible that accept_any_vlan mode is set due to a
3813 * previous setting of IFF_PROMISC. If vlan credits are
3814 * sufficient, disable accept_any_vlan.
3815 */
3816 qede_config_accept_any_vlan(edev, false);
3817 }
3818
0d8e0aa0
SK		 3819 rx_mode.filter.accept_flags = accept_flags;
3820 edev->ops->filter_config(edev->cdev, &rx_mode);
3821out:
3822 kfree(uc_macs);
3823}
Linux kernel - Deliverables
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