Commit | Line | Data |
---|---|---|
af19b491 | 1 | /* |
40839129 SV |
2 | * QLogic qlcnic NIC Driver |
3 | * Copyright (c) 2009-2010 QLogic Corporation | |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
23 | ||
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mii.h> | |
26 | #include <linux/timer.h> | |
27 | ||
28 | #include <linux/vmalloc.h> | |
29 | ||
30 | #include <linux/io.h> | |
31 | #include <asm/byteorder.h> | |
b9796a14 AC |
32 | #include <linux/bitops.h> |
33 | #include <linux/if_vlan.h> | |
af19b491 AKS |
34 | |
35 | #include "qlcnic_hdr.h" | |
7f966452 SC |
36 | #include "qlcnic_hw.h" |
37 | #include "qlcnic_83xx_hw.h" | |
af19b491 AKS |
38 | |
39 | #define _QLCNIC_LINUX_MAJOR 5 | |
40 | #define _QLCNIC_LINUX_MINOR 0 | |
341abdbe SSC |
41 | #define _QLCNIC_LINUX_SUBVERSION 30 |
42 | #define QLCNIC_LINUX_VERSIONID "5.0.30" | |
96f8118c | 43 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
44 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
45 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
46 | |
47 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
48 | #define _major(v) (((v) >> 24) & 0xff) | |
49 | #define _minor(v) (((v) >> 16) & 0xff) | |
50 | #define _build(v) ((v) & 0xffff) | |
51 | ||
52 | /* version in image has weird encoding: | |
53 | * 7:0 - major | |
54 | * 15:8 - minor | |
55 | * 31:16 - build (little endian) | |
56 | */ | |
57 | #define QLCNIC_DECODE_VERSION(v) \ | |
58 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
59 | ||
8f891387 | 60 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
61 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
62 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
63 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
64 | * QLCNIC_FLASH_SECTOR_SIZE) | |
65 | ||
66 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
67 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
68 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
69 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
70 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
71 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
72 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
73 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
74 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
75 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
76 | ||
77 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 78 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
79 | |
80 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
81 | ||
82 | #define FIRST_PAGE_GROUP_START 0 | |
83 | #define FIRST_PAGE_GROUP_END 0x100000 | |
84 | ||
ff1b1bf8 SV |
85 | #define P3P_MAX_MTU (9600) |
86 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
87 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
88 | ||
ff1b1bf8 SV |
89 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
90 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
91 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
92 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
93 | ||
af19b491 | 94 | /* Tx defines */ |
91a403ca | 95 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
96 | #define MAX_TSO_HEADER_DESC 2 |
97 | #define MGMT_CMD_DESC_RESV 4 | |
98 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
99 | + MGMT_CMD_DESC_RESV) | |
af19b491 | 100 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
af19b491 AKS |
101 | /* |
102 | * Following are the states of the Phantom. Phantom will set them and | |
103 | * Host will read to check if the fields are correct. | |
104 | */ | |
105 | #define PHAN_INITIALIZE_FAILED 0xffff | |
106 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
107 | ||
108 | /* Host writes the following to notify that it has done the init-handshake */ | |
109 | #define PHAN_INITIALIZE_ACK 0xf00f | |
110 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
111 | ||
112 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
113 | |
114 | #define RCV_RING_NORMAL 0 | |
115 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
116 | |
117 | #define MIN_CMD_DESCRIPTORS 64 | |
118 | #define MIN_RCV_DESCRIPTORS 64 | |
119 | #define MIN_JUMBO_DESCRIPTORS 32 | |
120 | ||
121 | #define MAX_CMD_DESCRIPTORS 1024 | |
122 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
123 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 124 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
125 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
126 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
127 | |
128 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
129 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 130 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 131 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
132 | |
133 | #define get_next_index(index, length) \ | |
134 | (((index) + 1) & ((length) - 1)) | |
135 | ||
af19b491 AKS |
136 | /* |
137 | * Following data structures describe the descriptors that will be used. | |
138 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
139 | * we are doing LSO (above the 1500 size packet) only. | |
140 | */ | |
af19b491 AKS |
141 | struct cmd_desc_type0 { |
142 | u8 tcp_hdr_offset; /* For LSO only */ | |
143 | u8 ip_hdr_offset; /* For LSO only */ | |
144 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
145 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
146 | ||
147 | __le64 addr_buffer2; | |
148 | ||
149 | __le16 reference_handle; | |
150 | __le16 mss; | |
151 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
152 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
153 | __le16 conn_id; /* IPSec offoad only */ | |
154 | ||
155 | __le64 addr_buffer3; | |
156 | __le64 addr_buffer1; | |
157 | ||
158 | __le16 buffer_length[4]; | |
159 | ||
160 | __le64 addr_buffer4; | |
161 | ||
2e9d722d | 162 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
163 | __le16 vlan_TCI; |
164 | ||
165 | } __attribute__ ((aligned(64))); | |
166 | ||
167 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
168 | struct rcv_desc { | |
169 | __le16 reference_handle; | |
170 | __le16 reserved; | |
171 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
172 | __le64 addr_buffer; | |
b1fc6d3c | 173 | } __packed; |
af19b491 | 174 | |
af19b491 AKS |
175 | struct status_desc { |
176 | __le64 status_desc_data[2]; | |
177 | } __attribute__ ((aligned(16))); | |
178 | ||
179 | /* UNIFIED ROMIMAGE */ | |
180 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
181 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
182 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
183 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
184 | ||
185 | /*Offsets */ | |
186 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
187 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
188 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
189 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
190 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
191 | ||
192 | struct uni_table_desc{ | |
63507592 SS |
193 | __le32 findex; |
194 | __le32 num_entries; | |
195 | __le32 entry_size; | |
196 | __le32 reserved[5]; | |
af19b491 AKS |
197 | }; |
198 | ||
199 | struct uni_data_desc{ | |
63507592 SS |
200 | __le32 findex; |
201 | __le32 size; | |
202 | __le32 reserved[5]; | |
af19b491 AKS |
203 | }; |
204 | ||
0e5f20b6 | 205 | /* Flash Defines and Structures */ |
206 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
a2050c7e SV |
207 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
208 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 209 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 210 | struct qlcnic_flt_header { |
211 | u16 version; | |
212 | u16 len; | |
213 | u16 checksum; | |
214 | u16 reserved; | |
215 | }; | |
216 | ||
217 | struct qlcnic_flt_entry { | |
218 | u8 region; | |
219 | u8 reserved0; | |
220 | u8 attrib; | |
221 | u8 reserved1; | |
222 | u32 size; | |
223 | u32 start_addr; | |
f8d54811 | 224 | u32 end_addr; |
0e5f20b6 | 225 | }; |
226 | ||
af19b491 AKS |
227 | /* Magic number to let user know flash is programmed */ |
228 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
229 | ||
ff1b1bf8 SV |
230 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
231 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
232 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
233 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
234 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
235 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
236 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
237 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
238 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
239 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
240 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
241 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
242 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
243 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 244 | |
2e9d722d AC |
245 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
246 | ||
af19b491 AKS |
247 | /* Flash memory map */ |
248 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
249 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
250 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
251 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
252 | ||
253 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
254 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
255 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
256 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
257 | ||
258 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
259 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
260 | ||
261 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
262 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
263 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
264 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
265 | ||
266 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
267 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
268 | ||
269 | extern char qlcnic_driver_name[]; | |
270 | ||
271 | /* Number of status descriptors to handle per interrupt */ | |
272 | #define MAX_STATUS_HANDLE (64) | |
273 | ||
274 | /* | |
275 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
276 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
277 | */ | |
278 | struct qlcnic_skb_frag { | |
279 | u64 dma; | |
280 | u64 length; | |
281 | }; | |
282 | ||
af19b491 AKS |
283 | /* Following defines are for the state of the buffers */ |
284 | #define QLCNIC_BUFFER_FREE 0 | |
285 | #define QLCNIC_BUFFER_BUSY 1 | |
286 | ||
287 | /* | |
288 | * There will be one qlcnic_buffer per skb packet. These will be | |
289 | * used to save the dma info for pci_unmap_page() | |
290 | */ | |
291 | struct qlcnic_cmd_buffer { | |
292 | struct sk_buff *skb; | |
ef71ff83 | 293 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
294 | u32 frag_count; |
295 | }; | |
296 | ||
297 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
298 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 299 | u16 ref_handle; |
af19b491 | 300 | struct sk_buff *skb; |
b1fc6d3c | 301 | struct list_head list; |
af19b491 | 302 | u64 dma; |
af19b491 AKS |
303 | }; |
304 | ||
305 | /* Board types */ | |
306 | #define QLCNIC_GBE 0x01 | |
307 | #define QLCNIC_XGBE 0x02 | |
308 | ||
8816d009 AC |
309 | /* |
310 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
311 | * adjusted based on configured MTU. | |
312 | */ | |
313 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
314 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
315 | ||
316 | #define QLCNIC_INTR_DEFAULT 0x04 | |
317 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
318 | ||
319 | struct qlcnic_nic_intr_coalesce { | |
320 | u8 type; | |
321 | u8 sts_ring_mask; | |
322 | u16 rx_packets; | |
323 | u16 rx_time_us; | |
324 | u16 flag; | |
325 | u32 timer_out; | |
326 | }; | |
327 | ||
18f2f616 | 328 | struct qlcnic_dump_template_hdr { |
63507592 SS |
329 | u32 type; |
330 | u32 offset; | |
331 | u32 size; | |
332 | u32 cap_mask; | |
333 | u32 num_entries; | |
334 | u32 version; | |
335 | u32 timestamp; | |
336 | u32 checksum; | |
337 | u32 drv_cap_mask; | |
338 | u32 sys_info[3]; | |
339 | u32 saved_state[16]; | |
340 | u32 cap_sizes[8]; | |
341 | u32 rsvd[0]; | |
18f2f616 AC |
342 | }; |
343 | ||
344 | struct qlcnic_fw_dump { | |
345 | u8 clr; /* flag to indicate if dump is cleared */ | |
9d6a6440 | 346 | u8 enable; /* enable/disable dump */ |
18f2f616 AC |
347 | u32 size; /* total size of the dump */ |
348 | void *data; /* dump data area */ | |
349 | struct qlcnic_dump_template_hdr *tmpl_hdr; | |
350 | }; | |
351 | ||
af19b491 AKS |
352 | /* |
353 | * One hardware_context{} per adapter | |
354 | * contains interrupt info as well shared hardware info. | |
355 | */ | |
356 | struct qlcnic_hardware_context { | |
357 | void __iomem *pci_base0; | |
358 | void __iomem *ocm_win_crb; | |
359 | ||
360 | unsigned long pci_len0; | |
361 | ||
af19b491 AKS |
362 | rwlock_t crb_lock; |
363 | struct mutex mem_lock; | |
364 | ||
af19b491 AKS |
365 | u8 revision_id; |
366 | u8 pci_func; | |
367 | u8 linkup; | |
22c8c934 | 368 | u8 loopback_state; |
79788450 SC |
369 | u8 beacon_state; |
370 | u8 has_link_events; | |
371 | u8 fw_type; | |
372 | u8 physical_port; | |
373 | u8 reset_context; | |
374 | u8 msix_supported; | |
375 | u8 max_mac_filters; | |
376 | u8 mc_enabled; | |
377 | u8 max_mc_count; | |
378 | u8 diag_test; | |
379 | u8 num_msix; | |
380 | u8 nic_mode; | |
381 | char diag_cnt; | |
382 | ||
af19b491 AKS |
383 | u16 port_type; |
384 | u16 board_type; | |
8816d009 | 385 | |
79788450 SC |
386 | u16 link_speed; |
387 | u16 link_duplex; | |
388 | u16 link_autoneg; | |
389 | u16 module_type; | |
390 | ||
391 | u16 op_mode; | |
392 | u16 switch_mode; | |
393 | u16 max_tx_ques; | |
394 | u16 max_rx_ques; | |
395 | u16 max_mtu; | |
396 | u32 msg_enable; | |
397 | u16 act_pci_func; | |
728a98b8 | 398 | |
79788450 SC |
399 | u32 capabilities; |
400 | u32 temp; | |
401 | u32 int_vec_bit; | |
402 | u32 fw_hal_version; | |
7f966452 | 403 | u32 port_config; |
79788450 | 404 | struct qlcnic_hardware_ops *hw_ops; |
8816d009 | 405 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 406 | struct qlcnic_fw_dump fw_dump; |
7f966452 | 407 | struct qlcnic_intrpt_config *intr_tbl; |
7e2cf4fe | 408 | u32 *reg_tbl; |
7f966452 SC |
409 | u32 *ext_reg_tbl; |
410 | u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; | |
411 | u32 mbox_reg[4]; | |
412 | spinlock_t mbx_lock; | |
af19b491 AKS |
413 | }; |
414 | ||
415 | struct qlcnic_adapter_stats { | |
416 | u64 xmitcalled; | |
417 | u64 xmitfinished; | |
418 | u64 rxdropped; | |
419 | u64 txdropped; | |
420 | u64 csummed; | |
421 | u64 rx_pkts; | |
422 | u64 lro_pkts; | |
423 | u64 rxbytes; | |
424 | u64 txbytes; | |
8bfe8b91 SC |
425 | u64 lrobytes; |
426 | u64 lso_frames; | |
427 | u64 xmit_on; | |
428 | u64 xmit_off; | |
429 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
430 | u64 null_rxbuf; |
431 | u64 rx_dma_map_error; | |
432 | u64 tx_dma_map_error; | |
7f966452 | 433 | u64 spurious_intr; |
af19b491 AKS |
434 | }; |
435 | ||
436 | /* | |
437 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
438 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
439 | */ | |
440 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
441 | void __iomem *crb_rcv_producer; |
442 | struct rcv_desc *desc_head; | |
443 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 444 | u32 num_desc; |
036d61f0 | 445 | u32 producer; |
af19b491 AKS |
446 | u32 dma_size; |
447 | u32 skb_size; | |
448 | u32 flags; | |
af19b491 AKS |
449 | struct list_head free_list; |
450 | spinlock_t lock; | |
451 | dma_addr_t phys_addr; | |
036d61f0 | 452 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
453 | |
454 | struct qlcnic_host_sds_ring { | |
455 | u32 consumer; | |
456 | u32 num_desc; | |
457 | void __iomem *crb_sts_consumer; | |
af19b491 AKS |
458 | |
459 | struct status_desc *desc_head; | |
460 | struct qlcnic_adapter *adapter; | |
461 | struct napi_struct napi; | |
462 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
463 | ||
036d61f0 | 464 | void __iomem *crb_intr_mask; |
af19b491 AKS |
465 | int irq; |
466 | ||
467 | dma_addr_t phys_addr; | |
468 | char name[IFNAMSIZ+4]; | |
036d61f0 | 469 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
470 | |
471 | struct qlcnic_host_tx_ring { | |
7f966452 SC |
472 | void __iomem *crb_intr_mask; |
473 | char name[IFNAMSIZ+4]; | |
79788450 | 474 | u16 ctx_id; |
af19b491 | 475 | u32 producer; |
af19b491 | 476 | u32 sw_consumer; |
af19b491 | 477 | u32 num_desc; |
036d61f0 | 478 | void __iomem *crb_cmd_producer; |
af19b491 | 479 | struct cmd_desc_type0 *desc_head; |
036d61f0 AC |
480 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
481 | __le32 *hw_consumer; | |
482 | ||
af19b491 AKS |
483 | dma_addr_t phys_addr; |
484 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 AC |
485 | struct netdev_queue *txq; |
486 | } ____cacheline_internodealigned_in_smp; | |
af19b491 AKS |
487 | |
488 | /* | |
489 | * Receive context. There is one such structure per instance of the | |
490 | * receive processing. Any state information that is relevant to | |
491 | * the receive, and is must be in this structure. The global data may be | |
492 | * present elsewhere. | |
493 | */ | |
494 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
495 | struct qlcnic_host_rds_ring *rds_rings; |
496 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
497 | u32 state; |
498 | u16 context_id; | |
499 | u16 virt_port; | |
500 | ||
af19b491 AKS |
501 | }; |
502 | ||
503 | /* HW context creation */ | |
504 | ||
505 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
af19b491 AKS |
506 | |
507 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
508 | ||
509 | /* | |
510 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
511 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
512 | */ | |
513 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
514 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
515 | ||
516 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
517 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
518 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
519 | ||
520 | /* | |
521 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
522 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
523 | */ | |
524 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
525 | #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) | |
526 | ||
527 | #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
528 | #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
529 | #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
530 | #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
531 | #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
532 | #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
533 | #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
534 | #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
535 | #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
536 | #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
7777de9a | 537 | #define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011 |
af19b491 AKS |
538 | #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 |
539 | #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 | |
540 | #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 | |
541 | #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 | |
542 | #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 | |
543 | #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 | |
544 | #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 | |
545 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 | |
2e9d722d AC |
546 | #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f |
547 | ||
548 | #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 | |
549 | #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 | |
550 | #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 | |
2e9d722d AC |
551 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 |
552 | #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 | |
553 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 | |
554 | #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 | |
555 | #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 | |
4e8acb01 | 556 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 |
b6021212 | 557 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a |
7e610caa | 558 | #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E |
18f2f616 AC |
559 | #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f |
560 | #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030 | |
54a8997c | 561 | #define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037 |
af19b491 AKS |
562 | |
563 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 564 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 565 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
566 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
567 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
568 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
569 | #define QLCNIC_RCODE_TIMEOUT 17 |
570 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
571 | ||
572 | /* | |
573 | * Capabilities Announced | |
574 | */ | |
575 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
576 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
577 | #define QLCNIC_CAP0_LSO (1 << 6) | |
578 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
579 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 580 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 581 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
af19b491 AKS |
582 | |
583 | /* | |
584 | * Context state | |
585 | */ | |
d626ad4d | 586 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
587 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
588 | ||
589 | /* | |
590 | * Rx context | |
591 | */ | |
592 | ||
593 | struct qlcnic_hostrq_sds_ring { | |
594 | __le64 host_phys_addr; /* Ring base addr */ | |
595 | __le32 ring_size; /* Ring entries */ | |
596 | __le16 msi_index; | |
597 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 598 | } __packed; |
af19b491 AKS |
599 | |
600 | struct qlcnic_hostrq_rds_ring { | |
601 | __le64 host_phys_addr; /* Ring base addr */ | |
602 | __le64 buff_size; /* Packet buffer size */ | |
603 | __le32 ring_size; /* Ring entries */ | |
604 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 605 | } __packed; |
af19b491 AKS |
606 | |
607 | struct qlcnic_hostrq_rx_ctx { | |
608 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
609 | __le32 capabilities[4]; /* Flag bit vector */ | |
610 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
611 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
612 | /* These ring offsets are relative to data[0] below */ | |
613 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
614 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
615 | __le16 num_rds_rings; /* Count of RDS rings */ | |
616 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 617 | __le16 valid_field_offset; |
618 | u8 txrx_sds_binding; | |
619 | u8 msix_handler; | |
620 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
621 | /* MUST BE 64-bit aligned. |
622 | The following is packed: | |
623 | - N hostrq_rds_rings | |
624 | - N hostrq_sds_rings */ | |
625 | char data[0]; | |
b1fc6d3c | 626 | } __packed; |
af19b491 AKS |
627 | |
628 | struct qlcnic_cardrsp_rds_ring{ | |
629 | __le32 host_producer_crb; /* Crb to use */ | |
630 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 631 | } __packed; |
af19b491 AKS |
632 | |
633 | struct qlcnic_cardrsp_sds_ring { | |
634 | __le32 host_consumer_crb; /* Crb to use */ | |
635 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 636 | } __packed; |
af19b491 AKS |
637 | |
638 | struct qlcnic_cardrsp_rx_ctx { | |
639 | /* These ring offsets are relative to data[0] below */ | |
640 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
641 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
642 | __le32 host_ctx_state; /* Starting State */ | |
643 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
644 | __le16 num_rds_rings; /* Count of RDS rings */ | |
645 | __le16 num_sds_rings; /* Count of SDS rings */ | |
646 | __le16 context_id; /* Handle for context */ | |
647 | u8 phys_port; /* Physical id of port */ | |
648 | u8 virt_port; /* Virtual/Logical id of port */ | |
649 | u8 reserved[128]; /* save space for future expansion */ | |
650 | /* MUST BE 64-bit aligned. | |
651 | The following is packed: | |
652 | - N cardrsp_rds_rings | |
653 | - N cardrs_sds_rings */ | |
654 | char data[0]; | |
b1fc6d3c | 655 | } __packed; |
af19b491 AKS |
656 | |
657 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
658 | (sizeof(HOSTRQ_RX) + \ | |
659 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
660 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
661 | ||
662 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
663 | (sizeof(CARDRSP_RX) + \ | |
664 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
665 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
666 | ||
667 | /* | |
668 | * Tx context | |
669 | */ | |
670 | ||
671 | struct qlcnic_hostrq_cds_ring { | |
672 | __le64 host_phys_addr; /* Ring base addr */ | |
673 | __le32 ring_size; /* Ring entries */ | |
674 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 675 | } __packed; |
af19b491 AKS |
676 | |
677 | struct qlcnic_hostrq_tx_ctx { | |
678 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
679 | __le64 cmd_cons_dma_addr; /* */ | |
680 | __le64 dummy_dma_addr; /* */ | |
681 | __le32 capabilities[4]; /* Flag bit vector */ | |
682 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
683 | __le32 rsvd1; /* Padding */ | |
684 | __le16 rsvd2; /* Padding */ | |
685 | __le16 interrupt_ctl; | |
686 | __le16 msi_index; | |
687 | __le16 rsvd3; /* Padding */ | |
688 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
689 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 690 | } __packed; |
af19b491 AKS |
691 | |
692 | struct qlcnic_cardrsp_cds_ring { | |
693 | __le32 host_producer_crb; /* Crb to use */ | |
694 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 695 | } __packed; |
af19b491 AKS |
696 | |
697 | struct qlcnic_cardrsp_tx_ctx { | |
698 | __le32 host_ctx_state; /* Starting state */ | |
699 | __le16 context_id; /* Handle for context */ | |
700 | u8 phys_port; /* Physical id of port */ | |
701 | u8 virt_port; /* Virtual/Logical id of port */ | |
702 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
703 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 704 | } __packed; |
af19b491 AKS |
705 | |
706 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
707 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
708 | ||
709 | /* CRB */ | |
710 | ||
711 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
712 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
713 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
714 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
715 | ||
716 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
717 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
718 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
719 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
720 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
721 | ||
722 | ||
723 | /* MAC */ | |
724 | ||
ff1b1bf8 | 725 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
726 | |
727 | #define QLCNIC_MAC_NOOP 0 | |
728 | #define QLCNIC_MAC_ADD 1 | |
729 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
730 | #define QLCNIC_MAC_VLAN_ADD 3 |
731 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 AKS |
732 | |
733 | struct qlcnic_mac_list_s { | |
734 | struct list_head list; | |
735 | uint8_t mac_addr[ETH_ALEN+2]; | |
736 | }; | |
737 | ||
af19b491 AKS |
738 | #define QLCNIC_HOST_REQUEST 0x13 |
739 | #define QLCNIC_REQUEST 0x14 | |
740 | ||
741 | #define QLCNIC_MAC_EVENT 0x1 | |
742 | ||
743 | #define QLCNIC_IP_UP 2 | |
744 | #define QLCNIC_IP_DOWN 3 | |
745 | ||
22c8c934 | 746 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 747 | #define QLCNIC_ELB_MODE 0x2 |
22c8c934 SC |
748 | |
749 | #define QLCNIC_LINKEVENT 0x1 | |
750 | #define QLCNIC_LB_RESPONSE 0x2 | |
751 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
752 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
753 | ||
af19b491 AKS |
754 | /* |
755 | * Driver --> Firmware | |
756 | */ | |
b1fc6d3c AC |
757 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
758 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
759 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
760 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
761 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
762 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 763 | |
b1fc6d3c AC |
764 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
765 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
766 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
767 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
768 | ||
af19b491 AKS |
769 | /* |
770 | * Firmware --> Driver | |
771 | */ | |
772 | ||
22c8c934 | 773 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
7f966452 | 774 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D |
af19b491 AKS |
775 | |
776 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
777 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
778 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
779 | ||
780 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
781 | ||
782 | /* Capabilites received */ | |
ac8d0c4f AC |
783 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
784 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
785 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
786 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
fef0c060 | 787 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
788 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
789 | ||
790 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
af19b491 AKS |
791 | |
792 | /* module types */ | |
793 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
794 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
795 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
796 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
797 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
798 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
799 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
800 | #define LINKEVENT_MODULE_TWINAX 8 | |
801 | ||
802 | #define LINKSPEED_10GBPS 10000 | |
803 | #define LINKSPEED_1GBPS 1000 | |
804 | #define LINKSPEED_100MBPS 100 | |
805 | #define LINKSPEED_10MBPS 10 | |
806 | ||
807 | #define LINKSPEED_ENCODED_10MBPS 0 | |
808 | #define LINKSPEED_ENCODED_100MBPS 1 | |
809 | #define LINKSPEED_ENCODED_1GBPS 2 | |
810 | ||
811 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
812 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
813 | ||
814 | #define LINKEVENT_HALF_DUPLEX 0 | |
815 | #define LINKEVENT_FULL_DUPLEX 1 | |
816 | ||
817 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
818 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
819 | ||
af19b491 AKS |
820 | /* firmware response header: |
821 | * 63:58 - message type | |
822 | * 57:56 - owner | |
823 | * 55:53 - desc count | |
824 | * 52:48 - reserved | |
825 | * 47:40 - completion id | |
826 | * 39:32 - opcode | |
827 | * 31:16 - error code | |
828 | * 15:00 - reserved | |
829 | */ | |
830 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
831 | ((msg_hdr >> 32) & 0xFF) | |
832 | ||
833 | struct qlcnic_fw_msg { | |
834 | union { | |
835 | struct { | |
836 | u64 hdr; | |
837 | u64 body[7]; | |
838 | }; | |
839 | u64 words[8]; | |
840 | }; | |
841 | }; | |
842 | ||
843 | struct qlcnic_nic_req { | |
844 | __le64 qhdr; | |
845 | __le64 req_hdr; | |
846 | __le64 words[6]; | |
b1fc6d3c | 847 | } __packed; |
af19b491 AKS |
848 | |
849 | struct qlcnic_mac_req { | |
850 | u8 op; | |
851 | u8 tag; | |
852 | u8 mac_addr[6]; | |
853 | }; | |
854 | ||
7e56cac4 SC |
855 | struct qlcnic_vlan_req { |
856 | __le16 vlan_id; | |
857 | __le16 rsvd[3]; | |
b1fc6d3c | 858 | } __packed; |
7e56cac4 | 859 | |
b501595c SC |
860 | struct qlcnic_ipaddr { |
861 | __be32 ipv4; | |
862 | __be32 ipv6[4]; | |
863 | }; | |
864 | ||
af19b491 AKS |
865 | #define QLCNIC_MSI_ENABLED 0x02 |
866 | #define QLCNIC_MSIX_ENABLED 0x04 | |
7f966452 | 867 | #define QLCNIC_LRO_ENABLED 0x01 |
24763d80 | 868 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
869 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
870 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 871 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 872 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 873 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 874 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 875 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 876 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 877 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 878 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 879 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 880 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
af19b491 AKS |
881 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
882 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
883 | ||
f94bc1e7 | 884 | #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 |
af19b491 AKS |
885 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
886 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 887 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 AKS |
888 | |
889 | #define QLCNIC_NETDEV_WEIGHT 128 | |
890 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
891 | ||
892 | #define __QLCNIC_FW_ATTACHED 0 | |
893 | #define __QLCNIC_DEV_UP 1 | |
894 | #define __QLCNIC_RESETTING 2 | |
895 | #define __QLCNIC_START_FW 4 | |
451724c8 | 896 | #define __QLCNIC_AER 5 |
89b4208e | 897 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 898 | #define __QLCNIC_LED_ENABLE 7 |
af19b491 | 899 | |
7eb9855d | 900 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 901 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 902 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 903 | |
b5e5492c | 904 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 905 | #define QLCNIC_READD_AGE 20 |
b5e5492c | 906 | #define QLCNIC_LB_MAX_FILTERS 64 |
7f966452 | 907 | #define QLCNIC_LB_BUCKET_SIZE 32 |
b5e5492c | 908 | |
fef0c060 AKS |
909 | /* QLCNIC Driver Error Code */ |
910 | #define QLCNIC_FW_NOT_RESPOND 51 | |
911 | #define QLCNIC_TEST_IN_PROGRESS 52 | |
912 | #define QLCNIC_UNDEFINED_ERROR 53 | |
913 | #define QLCNIC_LB_CABLE_NOT_CONN 54 | |
914 | ||
b5e5492c AKS |
915 | struct qlcnic_filter { |
916 | struct hlist_node fnode; | |
917 | u8 faddr[ETH_ALEN]; | |
7e56cac4 | 918 | __le16 vlan_id; |
b5e5492c AKS |
919 | unsigned long ftime; |
920 | }; | |
921 | ||
922 | struct qlcnic_filter_hash { | |
923 | struct hlist_head *fhead; | |
924 | u8 fnum; | |
7f966452 SC |
925 | u16 fmax; |
926 | u16 fbucket_size; | |
b5e5492c AKS |
927 | }; |
928 | ||
af19b491 | 929 | struct qlcnic_adapter { |
b1fc6d3c AC |
930 | struct qlcnic_hardware_context *ahw; |
931 | struct qlcnic_recv_context *recv_ctx; | |
932 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
933 | struct net_device *netdev; |
934 | struct pci_dev *pdev; | |
af19b491 | 935 | |
b1fc6d3c AC |
936 | unsigned long state; |
937 | u32 flags; | |
af19b491 | 938 | |
79788450 | 939 | int max_drv_tx_rings; |
af19b491 AKS |
940 | u16 num_txd; |
941 | u16 num_rxd; | |
942 | u16 num_jumbo_rxd; | |
90d19005 SC |
943 | u16 max_rxd; |
944 | u16 max_jumbo_rxd; | |
af19b491 AKS |
945 | |
946 | u8 max_rds_rings; | |
947 | u8 max_sds_rings; | |
7f966452 | 948 | u8 rx_csum; |
af19b491 | 949 | u8 portnum; |
af19b491 | 950 | |
af19b491 AKS |
951 | u8 fw_wait_cnt; |
952 | u8 fw_fail_cnt; | |
953 | u8 tx_timeo_cnt; | |
954 | u8 need_fw_reset; | |
955 | ||
af19b491 | 956 | u16 is_up; |
8cf61f89 | 957 | u16 pvid; |
2e9d722d | 958 | |
af19b491 | 959 | u32 irq; |
4e70812b | 960 | u32 heartbeat; |
af19b491 AKS |
961 | |
962 | u8 dev_state; | |
aa5e18c0 SC |
963 | u8 reset_ack_timeo; |
964 | u8 dev_init_timeo; | |
af19b491 AKS |
965 | |
966 | u8 mac_addr[ETH_ALEN]; | |
967 | ||
6df900e9 | 968 | u64 dev_rst_time; |
e5dcf6dc | 969 | u8 mac_learn; |
b9796a14 | 970 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
346fe763 | 971 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
972 | struct qlcnic_eswitch *eswitch; |
973 | struct qlcnic_nic_template *nic_ops; | |
974 | ||
af19b491 | 975 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 976 | struct list_head mac_list; |
af19b491 AKS |
977 | |
978 | void __iomem *tgt_mask_reg; | |
979 | void __iomem *tgt_status_reg; | |
980 | void __iomem *crb_int_state_reg; | |
981 | void __iomem *isr_int_vec; | |
982 | ||
f94bc1e7 | 983 | struct msix_entry *msix_entries; |
7f966452 | 984 | struct workqueue_struct *qlcnic_wq; |
af19b491 | 985 | struct delayed_work fw_work; |
7f966452 | 986 | struct delayed_work idc_aen_work; |
af19b491 | 987 | |
b5e5492c AKS |
988 | struct qlcnic_filter_hash fhash; |
989 | ||
b1fc6d3c AC |
990 | spinlock_t tx_clean_lock; |
991 | spinlock_t mac_learn_lock; | |
63507592 | 992 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 AKS |
993 | u32 fw_version; |
994 | const struct firmware *fw; | |
995 | }; | |
996 | ||
63507592 | 997 | struct qlcnic_info_le { |
2e9d722d | 998 | __le16 pci_func; |
63507592 | 999 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 1000 | __le16 phys_port; |
63507592 | 1001 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
1002 | |
1003 | __le32 capabilities; | |
1004 | u8 max_mac_filters; | |
1005 | u8 reserved1; | |
1006 | __le16 max_mtu; | |
1007 | ||
1008 | __le16 max_tx_ques; | |
1009 | __le16 max_rx_ques; | |
1010 | __le16 min_tx_bw; | |
1011 | __le16 max_tx_bw; | |
7f966452 SC |
1012 | __le32 op_type; |
1013 | __le16 max_bw_reg_offset; | |
1014 | __le16 max_linkspeed_reg_offset; | |
1015 | __le32 capability1; | |
1016 | __le32 capability2; | |
1017 | __le32 capability3; | |
1018 | __le16 max_tx_mac_filters; | |
1019 | __le16 max_rx_mcast_mac_filters; | |
1020 | __le16 max_rx_ucast_mac_filters; | |
1021 | __le16 max_rx_ip_addr; | |
1022 | __le16 max_rx_lro_flow; | |
1023 | __le16 max_rx_status_rings; | |
1024 | __le16 max_rx_buf_rings; | |
1025 | __le16 max_tx_vlan_keys; | |
1026 | u8 total_pf; | |
1027 | u8 total_rss_engines; | |
1028 | __le16 max_vports; | |
1029 | u8 reserved2[64]; | |
b1fc6d3c | 1030 | } __packed; |
2e9d722d | 1031 | |
63507592 SS |
1032 | struct qlcnic_info { |
1033 | u16 pci_func; | |
1034 | u16 op_mode; | |
1035 | u16 phys_port; | |
1036 | u16 switch_mode; | |
1037 | u32 capabilities; | |
1038 | u8 max_mac_filters; | |
1039 | u8 reserved1; | |
1040 | u16 max_mtu; | |
1041 | u16 max_tx_ques; | |
1042 | u16 max_rx_ques; | |
1043 | u16 min_tx_bw; | |
1044 | u16 max_tx_bw; | |
7f966452 SC |
1045 | u32 op_type; |
1046 | u16 max_bw_reg_offset; | |
1047 | u16 max_linkspeed_reg_offset; | |
1048 | u32 capability1; | |
1049 | u32 capability2; | |
1050 | u32 capability3; | |
1051 | u16 max_tx_mac_filters; | |
1052 | u16 max_rx_mcast_mac_filters; | |
1053 | u16 max_rx_ucast_mac_filters; | |
1054 | u16 max_rx_ip_addr; | |
1055 | u16 max_rx_lro_flow; | |
1056 | u16 max_rx_status_rings; | |
1057 | u16 max_rx_buf_rings; | |
1058 | u16 max_tx_vlan_keys; | |
1059 | u8 total_pf; | |
1060 | u8 total_rss_engines; | |
1061 | u16 max_vports; | |
63507592 | 1062 | }; |
2e9d722d | 1063 | |
63507592 SS |
1064 | struct qlcnic_pci_info_le { |
1065 | __le16 id; /* pci function id */ | |
1066 | __le16 active; /* 1 = Enabled */ | |
1067 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1068 | __le16 default_port; /* default port number */ | |
1069 | ||
1070 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1071 | __le16 tx_max_bw; |
1072 | __le16 reserved1[2]; | |
1073 | ||
1074 | u8 mac[ETH_ALEN]; | |
7f966452 SC |
1075 | __le16 func_count; |
1076 | u8 reserved2[104]; | |
1077 | ||
b1fc6d3c | 1078 | } __packed; |
2e9d722d | 1079 | |
63507592 SS |
1080 | struct qlcnic_pci_info { |
1081 | u16 id; | |
1082 | u16 active; | |
1083 | u16 type; | |
1084 | u16 default_port; | |
1085 | u16 tx_min_bw; | |
1086 | u16 tx_max_bw; | |
1087 | u8 mac[ETH_ALEN]; | |
7f966452 | 1088 | u16 func_count; |
63507592 SS |
1089 | }; |
1090 | ||
346fe763 | 1091 | struct qlcnic_npar_info { |
4e8acb01 | 1092 | u16 pvid; |
cea8975e AC |
1093 | u16 min_bw; |
1094 | u16 max_bw; | |
346fe763 RB |
1095 | u8 phy_port; |
1096 | u8 type; | |
1097 | u8 active; | |
1098 | u8 enable_pm; | |
1099 | u8 dest_npar; | |
346fe763 | 1100 | u8 discard_tagged; |
7373373d | 1101 | u8 mac_override; |
4e8acb01 RB |
1102 | u8 mac_anti_spoof; |
1103 | u8 promisc_mode; | |
1104 | u8 offload_flags; | |
bff57d8e | 1105 | u8 pci_func; |
346fe763 | 1106 | }; |
4e8acb01 | 1107 | |
2e9d722d AC |
1108 | struct qlcnic_eswitch { |
1109 | u8 port; | |
1110 | u8 active_vports; | |
1111 | u8 active_vlans; | |
1112 | u8 active_ucast_filters; | |
1113 | u8 max_ucast_filters; | |
1114 | u8 max_active_vlans; | |
1115 | ||
1116 | u32 flags; | |
1117 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1118 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1119 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1120 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1121 | }; | |
1122 | ||
346fe763 RB |
1123 | |
1124 | /* Return codes for Error handling */ | |
1125 | #define QL_STATUS_INVALID_PARAM -1 | |
1126 | ||
2abea2f0 | 1127 | #define MAX_BW 100 /* % of link speed */ |
346fe763 RB |
1128 | #define MAX_VLAN_ID 4095 |
1129 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1130 | #define DEFAULT_MAC_LEARN 1 |
1131 | ||
0184bbba | 1132 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1133 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1134 | |
1135 | struct qlcnic_pci_func_cfg { | |
1136 | u16 func_type; | |
1137 | u16 min_bw; | |
1138 | u16 max_bw; | |
1139 | u16 port_num; | |
1140 | u8 pci_func; | |
1141 | u8 func_state; | |
1142 | u8 def_mac_addr[6]; | |
1143 | }; | |
1144 | ||
1145 | struct qlcnic_npar_func_cfg { | |
1146 | u32 fw_capab; | |
1147 | u16 port_num; | |
1148 | u16 min_bw; | |
1149 | u16 max_bw; | |
1150 | u16 max_tx_queues; | |
1151 | u16 max_rx_queues; | |
1152 | u8 pci_func; | |
1153 | u8 op_mode; | |
1154 | }; | |
1155 | ||
1156 | struct qlcnic_pm_func_cfg { | |
1157 | u8 pci_func; | |
1158 | u8 action; | |
1159 | u8 dest_npar; | |
1160 | u8 reserved[5]; | |
1161 | }; | |
1162 | ||
1163 | struct qlcnic_esw_func_cfg { | |
1164 | u16 vlan_id; | |
4e8acb01 RB |
1165 | u8 op_mode; |
1166 | u8 op_type; | |
346fe763 RB |
1167 | u8 pci_func; |
1168 | u8 host_vlan_tag; | |
1169 | u8 promisc_mode; | |
1170 | u8 discard_tagged; | |
7373373d | 1171 | u8 mac_override; |
4e8acb01 RB |
1172 | u8 mac_anti_spoof; |
1173 | u8 offload_flags; | |
1174 | u8 reserved[5]; | |
346fe763 RB |
1175 | }; |
1176 | ||
b6021212 AKS |
1177 | #define QLCNIC_STATS_VERSION 1 |
1178 | #define QLCNIC_STATS_PORT 1 | |
1179 | #define QLCNIC_STATS_ESWITCH 2 | |
1180 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1181 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1182 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1183 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1184 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1185 | #define QLCNIC_MAC_STATS 1 | |
1186 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1187 | |
1188 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1189 | do { \ | |
54a8997c JK |
1190 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1191 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1192 | (VAL1) = (VAL2); \ |
54a8997c JK |
1193 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1194 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1195 | (VAL1) += (VAL2); \ |
1196 | } while (0) | |
1197 | ||
63507592 | 1198 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1199 | __le64 mac_tx_frames; |
1200 | __le64 mac_tx_bytes; | |
1201 | __le64 mac_tx_mcast_pkts; | |
1202 | __le64 mac_tx_bcast_pkts; | |
1203 | __le64 mac_tx_pause_cnt; | |
1204 | __le64 mac_tx_ctrl_pkt; | |
1205 | __le64 mac_tx_lt_64b_pkts; | |
1206 | __le64 mac_tx_lt_127b_pkts; | |
1207 | __le64 mac_tx_lt_255b_pkts; | |
1208 | __le64 mac_tx_lt_511b_pkts; | |
1209 | __le64 mac_tx_lt_1023b_pkts; | |
1210 | __le64 mac_tx_lt_1518b_pkts; | |
1211 | __le64 mac_tx_gt_1518b_pkts; | |
1212 | __le64 rsvd1[3]; | |
1213 | ||
1214 | __le64 mac_rx_frames; | |
1215 | __le64 mac_rx_bytes; | |
1216 | __le64 mac_rx_mcast_pkts; | |
1217 | __le64 mac_rx_bcast_pkts; | |
1218 | __le64 mac_rx_pause_cnt; | |
1219 | __le64 mac_rx_ctrl_pkt; | |
1220 | __le64 mac_rx_lt_64b_pkts; | |
1221 | __le64 mac_rx_lt_127b_pkts; | |
1222 | __le64 mac_rx_lt_255b_pkts; | |
1223 | __le64 mac_rx_lt_511b_pkts; | |
1224 | __le64 mac_rx_lt_1023b_pkts; | |
1225 | __le64 mac_rx_lt_1518b_pkts; | |
1226 | __le64 mac_rx_gt_1518b_pkts; | |
1227 | __le64 rsvd2[3]; | |
1228 | ||
1229 | __le64 mac_rx_length_error; | |
1230 | __le64 mac_rx_length_small; | |
1231 | __le64 mac_rx_length_large; | |
1232 | __le64 mac_rx_jabber; | |
1233 | __le64 mac_rx_dropped; | |
1234 | __le64 mac_rx_crc_error; | |
1235 | __le64 mac_align_error; | |
1236 | } __packed; | |
1237 | ||
63507592 SS |
1238 | struct qlcnic_mac_statistics { |
1239 | u64 mac_tx_frames; | |
1240 | u64 mac_tx_bytes; | |
1241 | u64 mac_tx_mcast_pkts; | |
1242 | u64 mac_tx_bcast_pkts; | |
1243 | u64 mac_tx_pause_cnt; | |
1244 | u64 mac_tx_ctrl_pkt; | |
1245 | u64 mac_tx_lt_64b_pkts; | |
1246 | u64 mac_tx_lt_127b_pkts; | |
1247 | u64 mac_tx_lt_255b_pkts; | |
1248 | u64 mac_tx_lt_511b_pkts; | |
1249 | u64 mac_tx_lt_1023b_pkts; | |
1250 | u64 mac_tx_lt_1518b_pkts; | |
1251 | u64 mac_tx_gt_1518b_pkts; | |
1252 | u64 rsvd1[3]; | |
1253 | u64 mac_rx_frames; | |
1254 | u64 mac_rx_bytes; | |
1255 | u64 mac_rx_mcast_pkts; | |
1256 | u64 mac_rx_bcast_pkts; | |
1257 | u64 mac_rx_pause_cnt; | |
1258 | u64 mac_rx_ctrl_pkt; | |
1259 | u64 mac_rx_lt_64b_pkts; | |
1260 | u64 mac_rx_lt_127b_pkts; | |
1261 | u64 mac_rx_lt_255b_pkts; | |
1262 | u64 mac_rx_lt_511b_pkts; | |
1263 | u64 mac_rx_lt_1023b_pkts; | |
1264 | u64 mac_rx_lt_1518b_pkts; | |
1265 | u64 mac_rx_gt_1518b_pkts; | |
1266 | u64 rsvd2[3]; | |
1267 | u64 mac_rx_length_error; | |
1268 | u64 mac_rx_length_small; | |
1269 | u64 mac_rx_length_large; | |
1270 | u64 mac_rx_jabber; | |
1271 | u64 mac_rx_dropped; | |
1272 | u64 mac_rx_crc_error; | |
1273 | u64 mac_align_error; | |
1274 | }; | |
1275 | ||
1276 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1277 | __le16 context_id; |
1278 | __le16 version; | |
1279 | __le16 size; | |
1280 | __le16 unused; | |
1281 | __le64 unicast_frames; | |
1282 | __le64 multicast_frames; | |
1283 | __le64 broadcast_frames; | |
1284 | __le64 dropped_frames; | |
1285 | __le64 errors; | |
1286 | __le64 local_frames; | |
1287 | __le64 numbytes; | |
1288 | __le64 rsvd[3]; | |
b1fc6d3c | 1289 | } __packed; |
b6021212 | 1290 | |
63507592 SS |
1291 | struct __qlcnic_esw_statistics { |
1292 | u16 context_id; | |
1293 | u16 version; | |
1294 | u16 size; | |
1295 | u16 unused; | |
1296 | u64 unicast_frames; | |
1297 | u64 multicast_frames; | |
1298 | u64 broadcast_frames; | |
1299 | u64 dropped_frames; | |
1300 | u64 errors; | |
1301 | u64 local_frames; | |
1302 | u64 numbytes; | |
1303 | u64 rsvd[3]; | |
1304 | }; | |
1305 | ||
b6021212 AKS |
1306 | struct qlcnic_esw_statistics { |
1307 | struct __qlcnic_esw_statistics rx; | |
1308 | struct __qlcnic_esw_statistics tx; | |
1309 | }; | |
1310 | ||
40522998 | 1311 | #define QLCNIC_DUMP_MASK_DEF 0x1f |
18f2f616 | 1312 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1313 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1314 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1315 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1316 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1317 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1318 | |
7777de9a | 1319 | struct _cdrp_cmd { |
7e2cf4fe SC |
1320 | u32 num; |
1321 | u32 *arg; | |
7777de9a AC |
1322 | }; |
1323 | ||
1324 | struct qlcnic_cmd_args { | |
1325 | struct _cdrp_cmd req; | |
1326 | struct _cdrp_cmd rsp; | |
1327 | }; | |
1328 | ||
18f2f616 | 1329 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1330 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1331 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); |
1332 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1333 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1334 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1335 | ||
1336 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1337 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 AKS |
1338 | |
1339 | #define QLCRD32(adapter, off) \ | |
7e2cf4fe SC |
1340 | (adapter->ahw->hw_ops->read_reg)(adapter, off) |
1341 | ||
af19b491 | 1342 | #define QLCWR32(adapter, off, val) \ |
7e2cf4fe | 1343 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
af19b491 AKS |
1344 | |
1345 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1346 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1347 | ||
1348 | #define qlcnic_rom_lock(a) \ | |
1349 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1350 | #define qlcnic_rom_unlock(a) \ | |
1351 | qlcnic_pcie_sem_unlock((a), 2) | |
1352 | #define qlcnic_phy_lock(a) \ | |
1353 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1354 | #define qlcnic_phy_unlock(a) \ | |
1355 | qlcnic_pcie_sem_unlock((a), 3) | |
af19b491 AKS |
1356 | #define qlcnic_sw_lock(a) \ |
1357 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1358 | #define qlcnic_sw_unlock(a) \ | |
1359 | qlcnic_pcie_sem_unlock((a), 6) | |
1360 | #define crb_win_lock(a) \ | |
1361 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1362 | #define crb_win_unlock(a) \ | |
1363 | qlcnic_pcie_sem_unlock((a), 7) | |
1364 | ||
728a98b8 SC |
1365 | #define __QLCNIC_MAX_LED_RATE 0xf |
1366 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1367 | ||
58634e74 SC |
1368 | #define MAX_CTL_CHECK 1000 |
1369 | ||
af19b491 | 1370 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); |
b5e5492c AKS |
1371 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1372 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1373 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
af19b491 AKS |
1374 | |
1375 | /* Functions from qlcnic_init.c */ | |
af19b491 AKS |
1376 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1377 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1378 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1379 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1380 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1381 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1382 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1383 | |
18f2f616 | 1384 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1385 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1386 | u8 *bytes, size_t size); | |
1387 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1388 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1389 | ||
15087c2b | 1390 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); |
af19b491 AKS |
1391 | |
1392 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1393 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1394 | ||
8a15ad1f AKS |
1395 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1396 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1397 | ||
1398 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1399 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
1400 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); | |
1401 | ||
d4066833 | 1402 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1403 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1404 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
af19b491 AKS |
1405 | struct qlcnic_host_rds_ring *rds_ring); |
1406 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); | |
1407 | void qlcnic_set_multi(struct net_device *netdev); | |
1408 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1409 | |
1410 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
1411 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); | |
c8f44aff MM |
1412 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1413 | netdev_features_t features); | |
1414 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
2e9d722d | 1415 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 | 1416 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
5ad6ff9d | 1417 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
22c8c934 SC |
1418 | |
1419 | /* Functions from qlcnic_ethtool.c */ | |
1420 | int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]); | |
af19b491 AKS |
1421 | |
1422 | /* Functions from qlcnic_main.c */ | |
1423 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1424 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); |
1425 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 | 1426 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
f94bc1e7 | 1427 | int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data); |
7e2cf4fe | 1428 | int qlcnic_validate_max_rss(struct net_device *netdev, u8, u8); |
e5dcf6dc | 1429 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
7f966452 | 1430 | int qlcnic_enable_msix(struct qlcnic_adapter *, u32); |
af19b491 | 1431 | |
2e9d722d | 1432 | /* eSwitch management functions */ |
4e8acb01 RB |
1433 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1434 | struct qlcnic_esw_func_cfg *); | |
1435 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, | |
1436 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1437 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1438 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1439 | struct __qlcnic_esw_statistics *); | |
1440 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1441 | struct __qlcnic_esw_statistics *); | |
1442 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1443 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d | 1444 | |
7e2cf4fe SC |
1445 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); |
1446 | void qlcnic_napi_del(struct qlcnic_adapter *); | |
1447 | ||
c70001a9 SC |
1448 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); |
1449 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
7f966452 | 1450 | void qlcnic_advert_link_change(struct qlcnic_adapter *, int); |
c70001a9 SC |
1451 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); |
1452 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
1453 | ||
ec079a07 SC |
1454 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1455 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
1456 | void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); | |
1457 | void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); | |
7e2cf4fe SC |
1458 | void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); |
1459 | void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); | |
1460 | ||
ec079a07 SC |
1461 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); |
1462 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1463 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1464 | struct qlcnic_esw_func_cfg *); | |
1465 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1466 | struct qlcnic_esw_func_cfg *); | |
1467 | ||
af19b491 AKS |
1468 | /* |
1469 | * QLOGIC Board information | |
1470 | */ | |
1471 | ||
02420be6 | 1472 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
22999798 | 1473 | struct qlcnic_board_info { |
af19b491 AKS |
1474 | unsigned short vendor; |
1475 | unsigned short device; | |
1476 | unsigned short sub_vendor; | |
1477 | unsigned short sub_device; | |
1478 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1479 | }; | |
1480 | ||
af19b491 AKS |
1481 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) |
1482 | { | |
036d61f0 | 1483 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1484 | return tx_ring->sw_consumer - tx_ring->producer; |
1485 | else | |
1486 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1487 | tx_ring->producer; | |
1488 | } | |
1489 | ||
7e2cf4fe SC |
1490 | struct qlcnic_nic_template { |
1491 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1492 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
1493 | int (*start_firmware) (struct qlcnic_adapter *); | |
1494 | int (*init_driver) (struct qlcnic_adapter *); | |
1495 | void (*request_reset) (struct qlcnic_adapter *, u32); | |
1496 | void (*cancel_idc_work) (struct qlcnic_adapter *); | |
1497 | int (*napi_add)(struct qlcnic_adapter *, struct net_device *); | |
1498 | void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); | |
1499 | irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); | |
1500 | }; | |
1501 | ||
1502 | /* Adapter hardware abstraction */ | |
1503 | struct qlcnic_hardware_ops { | |
1504 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1505 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1506 | int (*read_reg) (struct qlcnic_adapter *, ulong); | |
1507 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); | |
1508 | void (*get_ocm_win) (struct qlcnic_hardware_context *); | |
1509 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *); | |
1510 | int (*setup_intr) (struct qlcnic_adapter *, u8); | |
1511 | int (*alloc_mbx_args)(struct qlcnic_cmd_args *, | |
1512 | struct qlcnic_adapter *, u32); | |
1513 | int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1514 | void (*get_func_no) (struct qlcnic_adapter *); | |
1515 | int (*api_lock) (struct qlcnic_adapter *); | |
1516 | void (*api_unlock) (struct qlcnic_adapter *); | |
1517 | void (*add_sysfs) (struct qlcnic_adapter *); | |
1518 | void (*remove_sysfs) (struct qlcnic_adapter *); | |
1519 | void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); | |
1520 | int (*create_rx_ctx) (struct qlcnic_adapter *); | |
1521 | int (*create_tx_ctx) (struct qlcnic_adapter *, | |
1522 | struct qlcnic_host_tx_ring *, int); | |
1523 | int (*setup_link_event) (struct qlcnic_adapter *, int); | |
1524 | int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
1525 | int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
1526 | int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); | |
1527 | int (*change_macvlan) (struct qlcnic_adapter *, u8*, __le16, u8); | |
1528 | void (*napi_enable) (struct qlcnic_adapter *); | |
1529 | void (*napi_disable) (struct qlcnic_adapter *); | |
1530 | void (*config_intr_coal) (struct qlcnic_adapter *); | |
1531 | int (*config_rss) (struct qlcnic_adapter *, int); | |
1532 | int (*config_hw_lro) (struct qlcnic_adapter *, int); | |
1533 | int (*config_loopback) (struct qlcnic_adapter *, u8); | |
1534 | int (*clear_loopback) (struct qlcnic_adapter *, u8); | |
1535 | int (*config_promisc_mode) (struct qlcnic_adapter *, u32); | |
1536 | void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, __le16); | |
1537 | int (*get_board_info) (struct qlcnic_adapter *); | |
1538 | }; | |
1539 | ||
1540 | extern struct qlcnic_nic_template qlcnic_vf_ops; | |
1541 | ||
1542 | static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) | |
1543 | { | |
1544 | return adapter->nic_ops->start_firmware(adapter); | |
1545 | } | |
1546 | ||
1547 | static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1548 | loff_t offset, size_t size) | |
1549 | { | |
1550 | adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); | |
1551 | } | |
1552 | ||
1553 | static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1554 | loff_t offset, size_t size) | |
1555 | { | |
1556 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); | |
1557 | } | |
1558 | ||
7f966452 | 1559 | static inline int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, |
7e2cf4fe SC |
1560 | ulong off) |
1561 | { | |
1562 | return adapter->ahw->hw_ops->read_reg(adapter, off); | |
1563 | } | |
1564 | ||
1565 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, | |
1566 | ulong off, u32 data) | |
1567 | { | |
1568 | return adapter->ahw->hw_ops->write_reg(adapter, off, data); | |
1569 | } | |
1570 | ||
1571 | static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, | |
1572 | u8 *mac) | |
1573 | { | |
1574 | return adapter->ahw->hw_ops->get_mac_address(adapter, mac); | |
1575 | } | |
1576 | ||
1577 | static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr) | |
1578 | { | |
1579 | return adapter->ahw->hw_ops->setup_intr(adapter, num_intr); | |
1580 | } | |
1581 | ||
1582 | static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
1583 | struct qlcnic_adapter *adapter, u32 arg) | |
1584 | { | |
1585 | return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); | |
1586 | } | |
1587 | ||
1588 | static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, | |
1589 | struct qlcnic_cmd_args *cmd) | |
1590 | { | |
1591 | return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); | |
1592 | } | |
1593 | ||
1594 | static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) | |
1595 | { | |
1596 | adapter->ahw->hw_ops->get_func_no(adapter); | |
1597 | } | |
1598 | ||
1599 | static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) | |
1600 | { | |
1601 | return adapter->ahw->hw_ops->api_lock(adapter); | |
1602 | } | |
1603 | ||
1604 | static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) | |
1605 | { | |
1606 | adapter->ahw->hw_ops->api_unlock(adapter); | |
1607 | } | |
1608 | ||
1609 | static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) | |
1610 | { | |
1611 | adapter->ahw->hw_ops->add_sysfs(adapter); | |
1612 | } | |
1613 | ||
1614 | static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) | |
1615 | { | |
1616 | adapter->ahw->hw_ops->remove_sysfs(adapter); | |
1617 | } | |
1618 | ||
1619 | static inline void | |
1620 | qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) | |
1621 | { | |
1622 | sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); | |
1623 | } | |
1624 | ||
1625 | static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
1626 | { | |
1627 | return adapter->ahw->hw_ops->create_rx_ctx(adapter); | |
1628 | } | |
1629 | ||
1630 | static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, | |
1631 | struct qlcnic_host_tx_ring *ptr, | |
1632 | int ring) | |
1633 | { | |
1634 | return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); | |
1635 | } | |
1636 | ||
1637 | static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, | |
1638 | int enable) | |
1639 | { | |
1640 | return adapter->ahw->hw_ops->setup_link_event(adapter, enable); | |
1641 | } | |
1642 | ||
1643 | static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, | |
1644 | struct qlcnic_info *info, u8 id) | |
1645 | { | |
1646 | return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); | |
1647 | } | |
1648 | ||
1649 | static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, | |
1650 | struct qlcnic_pci_info *info) | |
1651 | { | |
1652 | return adapter->ahw->hw_ops->get_pci_info(adapter, info); | |
1653 | } | |
1654 | ||
1655 | static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, | |
1656 | struct qlcnic_info *info) | |
1657 | { | |
1658 | return adapter->ahw->hw_ops->set_nic_info(adapter, info); | |
1659 | } | |
1660 | ||
1661 | static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, | |
1662 | u8 *addr, __le16 id, u8 cmd) | |
1663 | { | |
1664 | return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); | |
1665 | } | |
1666 | ||
1667 | static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, | |
1668 | struct net_device *netdev) | |
1669 | { | |
1670 | return adapter->nic_ops->napi_add(adapter, netdev); | |
1671 | } | |
1672 | ||
1673 | static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) | |
1674 | { | |
1675 | adapter->ahw->hw_ops->napi_enable(adapter); | |
1676 | } | |
1677 | ||
1678 | static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) | |
1679 | { | |
1680 | adapter->ahw->hw_ops->napi_disable(adapter); | |
1681 | } | |
1682 | ||
1683 | static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) | |
1684 | { | |
1685 | adapter->ahw->hw_ops->config_intr_coal(adapter); | |
1686 | } | |
1687 | ||
1688 | static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) | |
1689 | { | |
1690 | return adapter->ahw->hw_ops->config_rss(adapter, enable); | |
1691 | } | |
1692 | ||
1693 | static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, | |
1694 | int enable) | |
1695 | { | |
1696 | return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); | |
1697 | } | |
1698 | ||
1699 | static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1700 | { | |
1701 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
1702 | } | |
1703 | ||
1704 | static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1705 | { | |
1706 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
1707 | } | |
1708 | ||
1709 | static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, | |
1710 | u32 mode) | |
1711 | { | |
1712 | return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); | |
1713 | } | |
1714 | ||
1715 | static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, | |
1716 | u64 *addr, __le16 id) | |
1717 | { | |
1718 | adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); | |
1719 | } | |
1720 | ||
1721 | static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) | |
1722 | { | |
1723 | return adapter->ahw->hw_ops->get_board_info(adapter); | |
1724 | } | |
1725 | ||
1726 | static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, | |
1727 | u32 key) | |
1728 | { | |
1729 | adapter->nic_ops->request_reset(adapter, key); | |
1730 | } | |
1731 | ||
1732 | static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) | |
1733 | { | |
1734 | adapter->nic_ops->cancel_idc_work(adapter); | |
1735 | } | |
1736 | ||
1737 | static inline irqreturn_t | |
1738 | qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
1739 | { | |
1740 | return adapter->nic_ops->clear_legacy_intr(adapter); | |
1741 | } | |
1742 | ||
1743 | static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, | |
1744 | u32 rate) | |
1745 | { | |
1746 | return adapter->nic_ops->config_led(adapter, state, rate); | |
1747 | } | |
1748 | ||
1749 | static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, | |
1750 | __be32 ip, int cmd) | |
1751 | { | |
1752 | adapter->nic_ops->config_ipaddr(adapter, ip, cmd); | |
1753 | } | |
1754 | ||
c70001a9 SC |
1755 | static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) |
1756 | { | |
1757 | writel(0, sds_ring->crb_intr_mask); | |
1758 | } | |
1759 | ||
1760 | static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) | |
1761 | { | |
1762 | struct qlcnic_adapter *adapter = sds_ring->adapter; | |
1763 | ||
1764 | writel(0x1, sds_ring->crb_intr_mask); | |
1765 | ||
1766 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
1767 | writel(0xfbff, adapter->tgt_mask_reg); | |
1768 | } | |
1769 | ||
af19b491 | 1770 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 1771 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 1772 | |
65b5b420 | 1773 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
79788450 | 1774 | if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ |
65b5b420 AKS |
1775 | printk(KERN_INFO "%s: %s: " _fmt, \ |
1776 | dev_name(&adapter->pdev->dev), \ | |
1777 | __func__, ##_args); \ | |
1778 | } while (0) | |
1779 | ||
7f966452 | 1780 | #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 |
97ee45eb SC |
1781 | #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 |
1782 | static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) | |
1783 | { | |
1784 | unsigned short device = adapter->pdev->device; | |
1785 | return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; | |
1786 | } | |
1787 | ||
7f966452 SC |
1788 | static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) |
1789 | { | |
1790 | unsigned short device = adapter->pdev->device; | |
1791 | return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false; | |
1792 | } | |
1793 | ||
1794 | ||
af19b491 | 1795 | #endif /* __QLCNIC_H_ */ |