Commit | Line | Data |
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af19b491 | 1 | /* |
40839129 | 2 | * QLogic qlcnic NIC Driver |
577ae39d | 3 | * Copyright (c) 2009-2013 QLogic Corporation |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
af19b491 AKS |
23 | #include <linux/ethtool.h> |
24 | #include <linux/mii.h> | |
25 | #include <linux/timer.h> | |
acdd32be | 26 | #include <linux/irq.h> |
af19b491 AKS |
27 | |
28 | #include <linux/vmalloc.h> | |
29 | ||
30 | #include <linux/io.h> | |
31 | #include <asm/byteorder.h> | |
b9796a14 AC |
32 | #include <linux/bitops.h> |
33 | #include <linux/if_vlan.h> | |
af19b491 AKS |
34 | |
35 | #include "qlcnic_hdr.h" | |
7f966452 SC |
36 | #include "qlcnic_hw.h" |
37 | #include "qlcnic_83xx_hw.h" | |
14d385b9 | 38 | #include "qlcnic_dcb.h" |
af19b491 AKS |
39 | |
40 | #define _QLCNIC_LINUX_MAJOR 5 | |
4cffa13d | 41 | #define _QLCNIC_LINUX_MINOR 3 |
28470572 HP |
42 | #define _QLCNIC_LINUX_SUBVERSION 61 |
43 | #define QLCNIC_LINUX_VERSIONID "5.3.61" | |
96f8118c | 44 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
45 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
46 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
47 | |
48 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
49 | #define _major(v) (((v) >> 24) & 0xff) | |
50 | #define _minor(v) (((v) >> 16) & 0xff) | |
51 | #define _build(v) ((v) & 0xffff) | |
52 | ||
53 | /* version in image has weird encoding: | |
54 | * 7:0 - major | |
55 | * 15:8 - minor | |
56 | * 31:16 - build (little endian) | |
57 | */ | |
58 | #define QLCNIC_DECODE_VERSION(v) \ | |
59 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
60 | ||
8f891387 | 61 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
62 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
63 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
64 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
65 | * QLCNIC_FLASH_SECTOR_SIZE) | |
66 | ||
67 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
68 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
69 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
70 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
71 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
72 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
73 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
74 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
75 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
76 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
77 | ||
78 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 79 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
80 | |
81 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
82 | ||
83 | #define FIRST_PAGE_GROUP_START 0 | |
84 | #define FIRST_PAGE_GROUP_END 0x100000 | |
85 | ||
ff1b1bf8 SV |
86 | #define P3P_MAX_MTU (9600) |
87 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
88 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
89 | ||
ff1b1bf8 SV |
90 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
91 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
92 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
93 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
94 | ||
af19b491 | 95 | /* Tx defines */ |
91a403ca | 96 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
97 | #define MAX_TSO_HEADER_DESC 2 |
98 | #define MGMT_CMD_DESC_RESV 4 | |
99 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
100 | + MGMT_CMD_DESC_RESV) | |
af19b491 | 101 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
34e8c406 HM |
102 | |
103 | /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */ | |
104 | #define QLCNIC_SINGLE_RING 1 | |
105 | #define QLCNIC_DEF_SDS_RINGS 4 | |
106 | #define QLCNIC_DEF_TX_RINGS 4 | |
107 | #define QLCNIC_MAX_VNIC_TX_RINGS 4 | |
108 | #define QLCNIC_MAX_VNIC_SDS_RINGS 4 | |
cb9327d5 HM |
109 | #define QLCNIC_83XX_MINIMUM_VECTOR 3 |
110 | #define QLCNIC_82XX_MINIMUM_VECTOR 2 | |
34e8c406 HM |
111 | |
112 | enum qlcnic_queue_type { | |
113 | QLCNIC_TX_QUEUE = 1, | |
114 | QLCNIC_RX_QUEUE, | |
115 | }; | |
116 | ||
117 | /* Operational mode for driver */ | |
118 | #define QLCNIC_VNIC_MODE 0xFF | |
119 | #define QLCNIC_DEFAULT_MODE 0x0 | |
012ec812 | 120 | |
2f514c52 JK |
121 | /* Virtual NIC function count */ |
122 | #define QLC_DEFAULT_VNIC_COUNT 8 | |
123 | #define QLC_84XX_VNIC_COUNT 16 | |
124 | ||
af19b491 AKS |
125 | /* |
126 | * Following are the states of the Phantom. Phantom will set them and | |
127 | * Host will read to check if the fields are correct. | |
128 | */ | |
129 | #define PHAN_INITIALIZE_FAILED 0xffff | |
130 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
131 | ||
132 | /* Host writes the following to notify that it has done the init-handshake */ | |
133 | #define PHAN_INITIALIZE_ACK 0xf00f | |
134 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
135 | ||
136 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
137 | |
138 | #define RCV_RING_NORMAL 0 | |
139 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
140 | |
141 | #define MIN_CMD_DESCRIPTORS 64 | |
142 | #define MIN_RCV_DESCRIPTORS 64 | |
143 | #define MIN_JUMBO_DESCRIPTORS 32 | |
144 | ||
145 | #define MAX_CMD_DESCRIPTORS 1024 | |
146 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
147 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 148 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
149 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
150 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
151 | |
152 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
153 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 154 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 155 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
156 | |
157 | #define get_next_index(index, length) \ | |
158 | (((index) + 1) & ((length) - 1)) | |
159 | ||
af19b491 AKS |
160 | /* |
161 | * Following data structures describe the descriptors that will be used. | |
162 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
163 | * we are doing LSO (above the 1500 size packet) only. | |
164 | */ | |
af19b491 AKS |
165 | struct cmd_desc_type0 { |
166 | u8 tcp_hdr_offset; /* For LSO only */ | |
167 | u8 ip_hdr_offset; /* For LSO only */ | |
168 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
169 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
170 | ||
171 | __le64 addr_buffer2; | |
172 | ||
381709de SS |
173 | __le16 encap_descr; /* 15:10 offset of outer L3 header, |
174 | * 9:6 number of 32bit words in outer L3 header, | |
175 | * 5 offload outer L4 checksum, | |
176 | * 4 offload outer L3 checksum, | |
177 | * 3 Inner L4 type, TCP=0, UDP=1, | |
178 | * 2 Inner L3 type, IPv4=0, IPv6=1, | |
179 | * 1 Outer L3 type,IPv4=0, IPv6=1, | |
180 | * 0 type of encapsulation, GRE=0, VXLAN=1 | |
181 | */ | |
af19b491 AKS |
182 | __le16 mss; |
183 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
381709de SS |
184 | u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ |
185 | u8 outer_hdr_length; /* Encapsulation only */ | |
186 | u8 rsvd1; | |
af19b491 AKS |
187 | |
188 | __le64 addr_buffer3; | |
189 | __le64 addr_buffer1; | |
190 | ||
191 | __le16 buffer_length[4]; | |
192 | ||
193 | __le64 addr_buffer4; | |
194 | ||
2e9d722d | 195 | u8 eth_addr[ETH_ALEN]; |
381709de SS |
196 | __le16 vlan_TCI; /* In case of encapsulation, |
197 | * this is for outer VLAN | |
198 | */ | |
af19b491 AKS |
199 | |
200 | } __attribute__ ((aligned(64))); | |
201 | ||
202 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
203 | struct rcv_desc { | |
204 | __le16 reference_handle; | |
205 | __le16 reserved; | |
206 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
207 | __le64 addr_buffer; | |
b1fc6d3c | 208 | } __packed; |
af19b491 | 209 | |
af19b491 AKS |
210 | struct status_desc { |
211 | __le64 status_desc_data[2]; | |
212 | } __attribute__ ((aligned(16))); | |
213 | ||
214 | /* UNIFIED ROMIMAGE */ | |
215 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
216 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
217 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
218 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
219 | ||
220 | /*Offsets */ | |
221 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
222 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
223 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
224 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
225 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
226 | ||
227 | struct uni_table_desc{ | |
63507592 SS |
228 | __le32 findex; |
229 | __le32 num_entries; | |
230 | __le32 entry_size; | |
231 | __le32 reserved[5]; | |
af19b491 AKS |
232 | }; |
233 | ||
234 | struct uni_data_desc{ | |
63507592 SS |
235 | __le32 findex; |
236 | __le32 size; | |
237 | __le32 reserved[5]; | |
af19b491 AKS |
238 | }; |
239 | ||
0e5f20b6 | 240 | /* Flash Defines and Structures */ |
241 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
d865ebb4 | 242 | #define QLCNIC_FDT_LOCATION 0x3F0000 |
a2050c7e SV |
243 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
244 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 245 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 246 | struct qlcnic_flt_header { |
247 | u16 version; | |
248 | u16 len; | |
249 | u16 checksum; | |
250 | u16 reserved; | |
251 | }; | |
252 | ||
253 | struct qlcnic_flt_entry { | |
254 | u8 region; | |
255 | u8 reserved0; | |
256 | u8 attrib; | |
257 | u8 reserved1; | |
258 | u32 size; | |
259 | u32 start_addr; | |
f8d54811 | 260 | u32 end_addr; |
0e5f20b6 | 261 | }; |
262 | ||
d865ebb4 SC |
263 | /* Flash Descriptor Table */ |
264 | struct qlcnic_fdt { | |
265 | u32 valid; | |
266 | u16 ver; | |
267 | u16 len; | |
268 | u16 cksum; | |
269 | u16 unused; | |
270 | u8 model[16]; | |
26acc712 | 271 | u8 mfg_id; |
d865ebb4 SC |
272 | u16 id; |
273 | u8 flag; | |
274 | u8 erase_cmd; | |
275 | u8 alt_erase_cmd; | |
276 | u8 write_enable_cmd; | |
277 | u8 write_enable_bits; | |
278 | u8 write_statusreg_cmd; | |
279 | u8 unprotected_sec_cmd; | |
280 | u8 read_manuf_cmd; | |
281 | u32 block_size; | |
282 | u32 alt_block_size; | |
283 | u32 flash_size; | |
284 | u32 write_enable_data; | |
285 | u8 readid_addr_len; | |
286 | u8 write_disable_bits; | |
287 | u8 read_dev_id_len; | |
288 | u8 chip_erase_cmd; | |
289 | u16 read_timeo; | |
290 | u8 protected_sec_cmd; | |
291 | u8 resvd[65]; | |
292 | }; | |
af19b491 AKS |
293 | /* Magic number to let user know flash is programmed */ |
294 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
295 | ||
ff1b1bf8 SV |
296 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
297 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
298 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
299 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
300 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
301 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
302 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
303 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
304 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
305 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
306 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
307 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
308 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
309 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 310 | |
2e9d722d AC |
311 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
312 | ||
af19b491 AKS |
313 | /* Flash memory map */ |
314 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
315 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
316 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
317 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
318 | ||
319 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
320 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
321 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
322 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
323 | ||
324 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
325 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
326 | ||
327 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
328 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
329 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
330 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
331 | ||
332 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
333 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
334 | ||
335 | extern char qlcnic_driver_name[]; | |
336 | ||
629263ac SC |
337 | extern int qlcnic_use_msi; |
338 | extern int qlcnic_use_msi_x; | |
339 | extern int qlcnic_auto_fw_reset; | |
340 | extern int qlcnic_load_fw_file; | |
629263ac | 341 | |
af19b491 AKS |
342 | /* Number of status descriptors to handle per interrupt */ |
343 | #define MAX_STATUS_HANDLE (64) | |
344 | ||
345 | /* | |
346 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
347 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
348 | */ | |
349 | struct qlcnic_skb_frag { | |
350 | u64 dma; | |
351 | u64 length; | |
352 | }; | |
353 | ||
af19b491 AKS |
354 | /* Following defines are for the state of the buffers */ |
355 | #define QLCNIC_BUFFER_FREE 0 | |
356 | #define QLCNIC_BUFFER_BUSY 1 | |
357 | ||
358 | /* | |
359 | * There will be one qlcnic_buffer per skb packet. These will be | |
360 | * used to save the dma info for pci_unmap_page() | |
361 | */ | |
362 | struct qlcnic_cmd_buffer { | |
363 | struct sk_buff *skb; | |
ef71ff83 | 364 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
365 | u32 frag_count; |
366 | }; | |
367 | ||
368 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
369 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 370 | u16 ref_handle; |
af19b491 | 371 | struct sk_buff *skb; |
b1fc6d3c | 372 | struct list_head list; |
af19b491 | 373 | u64 dma; |
af19b491 AKS |
374 | }; |
375 | ||
376 | /* Board types */ | |
377 | #define QLCNIC_GBE 0x01 | |
378 | #define QLCNIC_XGBE 0x02 | |
379 | ||
8816d009 AC |
380 | /* |
381 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
382 | * adjusted based on configured MTU. | |
383 | */ | |
be273dc1 HM |
384 | #define QLCNIC_INTR_COAL_TYPE_RX 1 |
385 | #define QLCNIC_INTR_COAL_TYPE_TX 2 | |
a514722a | 386 | #define QLCNIC_INTR_COAL_TYPE_RX_TX 3 |
be273dc1 HM |
387 | |
388 | #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 | |
389 | #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 | |
390 | ||
391 | #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 | |
392 | #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 | |
8816d009 AC |
393 | |
394 | #define QLCNIC_INTR_DEFAULT 0x04 | |
395 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
2f514c52 | 396 | #define QLCNIC_DEV_INFO_SIZE 2 |
8816d009 AC |
397 | |
398 | struct qlcnic_nic_intr_coalesce { | |
399 | u8 type; | |
400 | u8 sts_ring_mask; | |
401 | u16 rx_packets; | |
402 | u16 rx_time_us; | |
be273dc1 HM |
403 | u16 tx_packets; |
404 | u16 tx_time_us; | |
8816d009 AC |
405 | u16 flag; |
406 | u32 timer_out; | |
407 | }; | |
408 | ||
225837a0 | 409 | struct qlcnic_83xx_dump_template_hdr { |
63507592 SS |
410 | u32 type; |
411 | u32 offset; | |
412 | u32 size; | |
413 | u32 cap_mask; | |
414 | u32 num_entries; | |
415 | u32 version; | |
416 | u32 timestamp; | |
417 | u32 checksum; | |
418 | u32 drv_cap_mask; | |
419 | u32 sys_info[3]; | |
420 | u32 saved_state[16]; | |
421 | u32 cap_sizes[8]; | |
4e60ac46 | 422 | u32 ocm_wnd_reg[16]; |
63507592 | 423 | u32 rsvd[0]; |
18f2f616 AC |
424 | }; |
425 | ||
225837a0 SS |
426 | struct qlcnic_82xx_dump_template_hdr { |
427 | u32 type; | |
428 | u32 offset; | |
429 | u32 size; | |
430 | u32 cap_mask; | |
431 | u32 num_entries; | |
432 | u32 version; | |
433 | u32 timestamp; | |
434 | u32 checksum; | |
435 | u32 drv_cap_mask; | |
436 | u32 sys_info[3]; | |
437 | u32 saved_state[16]; | |
438 | u32 cap_sizes[8]; | |
439 | u32 rsvd[7]; | |
440 | u32 capabilities; | |
441 | u32 rsvd1[0]; | |
442 | }; | |
443 | ||
4da005cf SS |
444 | #define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16) |
445 | ||
18f2f616 AC |
446 | struct qlcnic_fw_dump { |
447 | u8 clr; /* flag to indicate if dump is cleared */ | |
890b6e02 | 448 | bool enable; /* enable/disable dump */ |
18f2f616 | 449 | u32 size; /* total size of the dump */ |
225837a0 | 450 | u32 cap_mask; /* Current capture mask */ |
18f2f616 | 451 | void *data; /* dump data area */ |
225837a0 | 452 | void *tmpl_hdr; |
9baf1aa9 SS |
453 | dma_addr_t phys_addr; |
454 | void *dma_buffer; | |
455 | bool use_pex_dma; | |
225837a0 SS |
456 | /* Read only elements which are common between 82xx and 83xx |
457 | * template header. Update these values immediately after we read | |
458 | * template header from Firmware | |
459 | */ | |
460 | u32 tmpl_hdr_size; | |
461 | u32 version; | |
462 | u32 num_entries; | |
463 | u32 offset; | |
18f2f616 AC |
464 | }; |
465 | ||
af19b491 AKS |
466 | /* |
467 | * One hardware_context{} per adapter | |
468 | * contains interrupt info as well shared hardware info. | |
469 | */ | |
470 | struct qlcnic_hardware_context { | |
471 | void __iomem *pci_base0; | |
472 | void __iomem *ocm_win_crb; | |
473 | ||
474 | unsigned long pci_len0; | |
475 | ||
af19b491 AKS |
476 | rwlock_t crb_lock; |
477 | struct mutex mem_lock; | |
478 | ||
af19b491 AKS |
479 | u8 revision_id; |
480 | u8 pci_func; | |
481 | u8 linkup; | |
22c8c934 | 482 | u8 loopback_state; |
79788450 SC |
483 | u8 beacon_state; |
484 | u8 has_link_events; | |
485 | u8 fw_type; | |
486 | u8 physical_port; | |
487 | u8 reset_context; | |
488 | u8 msix_supported; | |
489 | u8 max_mac_filters; | |
490 | u8 mc_enabled; | |
491 | u8 max_mc_count; | |
492 | u8 diag_test; | |
493 | u8 num_msix; | |
494 | u8 nic_mode; | |
97f3f6fc | 495 | int diag_cnt; |
79788450 | 496 | |
52e493d0 | 497 | u16 max_uc_count; |
af19b491 AKS |
498 | u16 port_type; |
499 | u16 board_type; | |
b938662d | 500 | u16 supported_type; |
8816d009 | 501 | |
79788450 SC |
502 | u16 link_speed; |
503 | u16 link_duplex; | |
504 | u16 link_autoneg; | |
505 | u16 module_type; | |
506 | ||
507 | u16 op_mode; | |
508 | u16 switch_mode; | |
509 | u16 max_tx_ques; | |
510 | u16 max_rx_ques; | |
511 | u16 max_mtu; | |
512 | u32 msg_enable; | |
2f514c52 | 513 | u16 total_nic_func; |
ee9e8b6c | 514 | u16 max_pci_func; |
2f514c52 JK |
515 | u32 max_vnic_func; |
516 | u32 total_pci_func; | |
728a98b8 | 517 | |
79788450 | 518 | u32 capabilities; |
db131786 | 519 | u32 extra_capability[3]; |
79788450 SC |
520 | u32 temp; |
521 | u32 int_vec_bit; | |
522 | u32 fw_hal_version; | |
7f966452 | 523 | u32 port_config; |
79788450 | 524 | struct qlcnic_hardware_ops *hw_ops; |
8816d009 | 525 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 526 | struct qlcnic_fw_dump fw_dump; |
d865ebb4 | 527 | struct qlcnic_fdt fdt; |
81d0aeb0 | 528 | struct qlc_83xx_reset reset; |
629263ac | 529 | struct qlc_83xx_idc idc; |
7000078a | 530 | struct qlc_83xx_fw_info *fw_info; |
7f966452 | 531 | struct qlcnic_intrpt_config *intr_tbl; |
02feda17 | 532 | struct qlcnic_sriov *sriov; |
7e2cf4fe | 533 | u32 *reg_tbl; |
7f966452 SC |
534 | u32 *ext_reg_tbl; |
535 | u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; | |
536 | u32 mbox_reg[4]; | |
e5c4e6c6 | 537 | struct qlcnic_mailbox *mailbox; |
77bead46 | 538 | u8 extend_lb_time; |
07a251c8 | 539 | u8 phys_port_id[ETH_ALEN]; |
d9c602f0 | 540 | u8 lb_mode; |
2b3d7b75 | 541 | u16 vxlan_port; |
1f0f467b | 542 | struct device *hwmon_dev; |
af19b491 AKS |
543 | }; |
544 | ||
545 | struct qlcnic_adapter_stats { | |
546 | u64 xmitcalled; | |
547 | u64 xmitfinished; | |
548 | u64 rxdropped; | |
549 | u64 txdropped; | |
550 | u64 csummed; | |
551 | u64 rx_pkts; | |
552 | u64 lro_pkts; | |
553 | u64 rxbytes; | |
554 | u64 txbytes; | |
8bfe8b91 SC |
555 | u64 lrobytes; |
556 | u64 lso_frames; | |
381709de SS |
557 | u64 encap_lso_frames; |
558 | u64 encap_tx_csummed; | |
2b3d7b75 | 559 | u64 encap_rx_csummed; |
8bfe8b91 SC |
560 | u64 xmit_on; |
561 | u64 xmit_off; | |
562 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
563 | u64 null_rxbuf; |
564 | u64 rx_dma_map_error; | |
565 | u64 tx_dma_map_error; | |
7f966452 | 566 | u64 spurious_intr; |
4be41e92 | 567 | u64 mac_filter_limit_overrun; |
af19b491 AKS |
568 | }; |
569 | ||
570 | /* | |
571 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
572 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
573 | */ | |
574 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
575 | void __iomem *crb_rcv_producer; |
576 | struct rcv_desc *desc_head; | |
577 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 578 | u32 num_desc; |
036d61f0 | 579 | u32 producer; |
af19b491 AKS |
580 | u32 dma_size; |
581 | u32 skb_size; | |
582 | u32 flags; | |
af19b491 AKS |
583 | struct list_head free_list; |
584 | spinlock_t lock; | |
585 | dma_addr_t phys_addr; | |
036d61f0 | 586 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
587 | |
588 | struct qlcnic_host_sds_ring { | |
589 | u32 consumer; | |
590 | u32 num_desc; | |
591 | void __iomem *crb_sts_consumer; | |
af19b491 | 592 | |
012ec812 | 593 | struct qlcnic_host_tx_ring *tx_ring; |
af19b491 AKS |
594 | struct status_desc *desc_head; |
595 | struct qlcnic_adapter *adapter; | |
596 | struct napi_struct napi; | |
597 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
598 | ||
036d61f0 | 599 | void __iomem *crb_intr_mask; |
af19b491 AKS |
600 | int irq; |
601 | ||
602 | dma_addr_t phys_addr; | |
ddb2e174 | 603 | char name[IFNAMSIZ + 12]; |
036d61f0 | 604 | } ____cacheline_internodealigned_in_smp; |
af19b491 | 605 | |
f27c75b3 HM |
606 | struct qlcnic_tx_queue_stats { |
607 | u64 xmit_on; | |
608 | u64 xmit_off; | |
609 | u64 xmit_called; | |
610 | u64 xmit_finished; | |
611 | u64 tx_bytes; | |
612 | }; | |
613 | ||
af19b491 | 614 | struct qlcnic_host_tx_ring { |
4be41e92 | 615 | int irq; |
7f966452 | 616 | void __iomem *crb_intr_mask; |
ddb2e174 | 617 | char name[IFNAMSIZ + 12]; |
79788450 | 618 | u16 ctx_id; |
012ec812 HM |
619 | |
620 | u32 state; | |
af19b491 | 621 | u32 producer; |
af19b491 | 622 | u32 sw_consumer; |
af19b491 | 623 | u32 num_desc; |
012ec812 | 624 | |
f27c75b3 | 625 | struct qlcnic_tx_queue_stats tx_stats; |
012ec812 | 626 | |
036d61f0 | 627 | void __iomem *crb_cmd_producer; |
af19b491 | 628 | struct cmd_desc_type0 *desc_head; |
4be41e92 SC |
629 | struct qlcnic_adapter *adapter; |
630 | struct napi_struct napi; | |
036d61f0 AC |
631 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
632 | __le32 *hw_consumer; | |
633 | ||
af19b491 AKS |
634 | dma_addr_t phys_addr; |
635 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 | 636 | struct netdev_queue *txq; |
a02bdd42 SS |
637 | /* Lock to protect Tx descriptors cleanup */ |
638 | spinlock_t tx_clean_lock; | |
036d61f0 | 639 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
640 | |
641 | /* | |
642 | * Receive context. There is one such structure per instance of the | |
643 | * receive processing. Any state information that is relevant to | |
644 | * the receive, and is must be in this structure. The global data may be | |
645 | * present elsewhere. | |
646 | */ | |
647 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
648 | struct qlcnic_host_rds_ring *rds_rings; |
649 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
650 | u32 state; |
651 | u16 context_id; | |
652 | u16 virt_port; | |
af19b491 AKS |
653 | }; |
654 | ||
655 | /* HW context creation */ | |
656 | ||
657 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
af19b491 AKS |
658 | |
659 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
660 | ||
661 | /* | |
662 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
663 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
664 | */ | |
665 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
666 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
667 | ||
668 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
669 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
670 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
671 | ||
672 | /* | |
673 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
674 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
675 | */ | |
676 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
af19b491 AKS |
677 | |
678 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 679 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 680 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
681 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
682 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
683 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
684 | #define QLCNIC_RCODE_TIMEOUT 17 |
685 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
686 | ||
687 | /* | |
688 | * Capabilities Announced | |
689 | */ | |
690 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
691 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
692 | #define QLCNIC_CAP0_LSO (1 << 6) | |
693 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
694 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 695 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 696 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
012ec812 | 697 | #define QLCNIC_CAP0_TX_MULTI (1 << 22) |
af19b491 AKS |
698 | |
699 | /* | |
700 | * Context state | |
701 | */ | |
d626ad4d | 702 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
703 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
704 | ||
705 | /* | |
706 | * Rx context | |
707 | */ | |
708 | ||
709 | struct qlcnic_hostrq_sds_ring { | |
710 | __le64 host_phys_addr; /* Ring base addr */ | |
711 | __le32 ring_size; /* Ring entries */ | |
712 | __le16 msi_index; | |
713 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 714 | } __packed; |
af19b491 AKS |
715 | |
716 | struct qlcnic_hostrq_rds_ring { | |
717 | __le64 host_phys_addr; /* Ring base addr */ | |
718 | __le64 buff_size; /* Packet buffer size */ | |
719 | __le32 ring_size; /* Ring entries */ | |
720 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 721 | } __packed; |
af19b491 AKS |
722 | |
723 | struct qlcnic_hostrq_rx_ctx { | |
724 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
012ec812 | 725 | __le32 capabilities[4]; /* Flag bit vector */ |
af19b491 AKS |
726 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
727 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
728 | /* These ring offsets are relative to data[0] below */ | |
729 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
730 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
731 | __le16 num_rds_rings; /* Count of RDS rings */ | |
732 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 733 | __le16 valid_field_offset; |
734 | u8 txrx_sds_binding; | |
735 | u8 msix_handler; | |
736 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
737 | /* MUST BE 64-bit aligned. |
738 | The following is packed: | |
739 | - N hostrq_rds_rings | |
740 | - N hostrq_sds_rings */ | |
741 | char data[0]; | |
b1fc6d3c | 742 | } __packed; |
af19b491 AKS |
743 | |
744 | struct qlcnic_cardrsp_rds_ring{ | |
745 | __le32 host_producer_crb; /* Crb to use */ | |
746 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 747 | } __packed; |
af19b491 AKS |
748 | |
749 | struct qlcnic_cardrsp_sds_ring { | |
750 | __le32 host_consumer_crb; /* Crb to use */ | |
751 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 752 | } __packed; |
af19b491 AKS |
753 | |
754 | struct qlcnic_cardrsp_rx_ctx { | |
755 | /* These ring offsets are relative to data[0] below */ | |
756 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
757 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
758 | __le32 host_ctx_state; /* Starting State */ | |
759 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
760 | __le16 num_rds_rings; /* Count of RDS rings */ | |
761 | __le16 num_sds_rings; /* Count of SDS rings */ | |
762 | __le16 context_id; /* Handle for context */ | |
763 | u8 phys_port; /* Physical id of port */ | |
764 | u8 virt_port; /* Virtual/Logical id of port */ | |
765 | u8 reserved[128]; /* save space for future expansion */ | |
766 | /* MUST BE 64-bit aligned. | |
767 | The following is packed: | |
768 | - N cardrsp_rds_rings | |
769 | - N cardrs_sds_rings */ | |
770 | char data[0]; | |
b1fc6d3c | 771 | } __packed; |
af19b491 AKS |
772 | |
773 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
774 | (sizeof(HOSTRQ_RX) + \ | |
775 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
776 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
777 | ||
778 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
779 | (sizeof(CARDRSP_RX) + \ | |
780 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
781 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
782 | ||
783 | /* | |
784 | * Tx context | |
785 | */ | |
786 | ||
787 | struct qlcnic_hostrq_cds_ring { | |
788 | __le64 host_phys_addr; /* Ring base addr */ | |
789 | __le32 ring_size; /* Ring entries */ | |
790 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 791 | } __packed; |
af19b491 AKS |
792 | |
793 | struct qlcnic_hostrq_tx_ctx { | |
794 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
795 | __le64 cmd_cons_dma_addr; /* */ | |
796 | __le64 dummy_dma_addr; /* */ | |
797 | __le32 capabilities[4]; /* Flag bit vector */ | |
798 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
799 | __le32 rsvd1; /* Padding */ | |
800 | __le16 rsvd2; /* Padding */ | |
801 | __le16 interrupt_ctl; | |
802 | __le16 msi_index; | |
803 | __le16 rsvd3; /* Padding */ | |
804 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
805 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 806 | } __packed; |
af19b491 AKS |
807 | |
808 | struct qlcnic_cardrsp_cds_ring { | |
809 | __le32 host_producer_crb; /* Crb to use */ | |
810 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 811 | } __packed; |
af19b491 AKS |
812 | |
813 | struct qlcnic_cardrsp_tx_ctx { | |
814 | __le32 host_ctx_state; /* Starting state */ | |
815 | __le16 context_id; /* Handle for context */ | |
816 | u8 phys_port; /* Physical id of port */ | |
817 | u8 virt_port; /* Virtual/Logical id of port */ | |
818 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
819 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 820 | } __packed; |
af19b491 AKS |
821 | |
822 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
823 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
824 | ||
825 | /* CRB */ | |
826 | ||
827 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
828 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
829 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
830 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
831 | ||
832 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
833 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
834 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
835 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
836 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
837 | ||
838 | ||
839 | /* MAC */ | |
840 | ||
ff1b1bf8 | 841 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
842 | |
843 | #define QLCNIC_MAC_NOOP 0 | |
844 | #define QLCNIC_MAC_ADD 1 | |
845 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
846 | #define QLCNIC_MAC_VLAN_ADD 3 |
847 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 | 848 | |
154d0c81 | 849 | struct qlcnic_mac_vlan_list { |
af19b491 AKS |
850 | struct list_head list; |
851 | uint8_t mac_addr[ETH_ALEN+2]; | |
154d0c81 | 852 | u16 vlan_id; |
af19b491 AKS |
853 | }; |
854 | ||
fe1adc6b JK |
855 | /* MAC Learn */ |
856 | #define NO_MAC_LEARN 0 | |
857 | #define DRV_MAC_LEARN 1 | |
858 | #define FDB_MAC_LEARN 2 | |
859 | ||
af19b491 AKS |
860 | #define QLCNIC_HOST_REQUEST 0x13 |
861 | #define QLCNIC_REQUEST 0x14 | |
862 | ||
863 | #define QLCNIC_MAC_EVENT 0x1 | |
864 | ||
865 | #define QLCNIC_IP_UP 2 | |
866 | #define QLCNIC_IP_DOWN 3 | |
867 | ||
22c8c934 | 868 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 869 | #define QLCNIC_ELB_MODE 0x2 |
d9c602f0 | 870 | #define QLCNIC_LB_MODE_MASK 0x3 |
22c8c934 SC |
871 | |
872 | #define QLCNIC_LINKEVENT 0x1 | |
873 | #define QLCNIC_LB_RESPONSE 0x2 | |
874 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
875 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
876 | ||
af19b491 AKS |
877 | /* |
878 | * Driver --> Firmware | |
879 | */ | |
b1fc6d3c AC |
880 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
881 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
882 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
883 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
884 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
885 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 886 | |
b1fc6d3c AC |
887 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
888 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
889 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
890 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
891 | ||
af19b491 AKS |
892 | /* |
893 | * Firmware --> Driver | |
894 | */ | |
895 | ||
22c8c934 | 896 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
7f966452 | 897 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D |
2d8ebcab | 898 | #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 |
af19b491 AKS |
899 | |
900 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
901 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
902 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
903 | ||
904 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
905 | ||
906 | /* Capabilites received */ | |
ac8d0c4f AC |
907 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
908 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
909 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
910 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
012ec812 | 911 | #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 |
fef0c060 | 912 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
913 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
914 | ||
915 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
776e7bde | 916 | #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 |
8af3f33d | 917 | #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 |
487042af | 918 | #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 |
2f514c52 | 919 | #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9 |
af19b491 | 920 | |
2b3d7b75 | 921 | #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0 |
381709de SS |
922 | #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1 |
923 | #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4 | |
924 | ||
af19b491 AKS |
925 | /* module types */ |
926 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
927 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
928 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
929 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
930 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
931 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
932 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
933 | #define LINKEVENT_MODULE_TWINAX 8 | |
934 | ||
935 | #define LINKSPEED_10GBPS 10000 | |
936 | #define LINKSPEED_1GBPS 1000 | |
937 | #define LINKSPEED_100MBPS 100 | |
938 | #define LINKSPEED_10MBPS 10 | |
939 | ||
940 | #define LINKSPEED_ENCODED_10MBPS 0 | |
941 | #define LINKSPEED_ENCODED_100MBPS 1 | |
942 | #define LINKSPEED_ENCODED_1GBPS 2 | |
943 | ||
944 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
945 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
946 | ||
947 | #define LINKEVENT_HALF_DUPLEX 0 | |
948 | #define LINKEVENT_FULL_DUPLEX 1 | |
949 | ||
950 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
951 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
952 | ||
af19b491 AKS |
953 | /* firmware response header: |
954 | * 63:58 - message type | |
955 | * 57:56 - owner | |
956 | * 55:53 - desc count | |
957 | * 52:48 - reserved | |
958 | * 47:40 - completion id | |
959 | * 39:32 - opcode | |
960 | * 31:16 - error code | |
961 | * 15:00 - reserved | |
962 | */ | |
963 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
964 | ((msg_hdr >> 32) & 0xFF) | |
965 | ||
966 | struct qlcnic_fw_msg { | |
967 | union { | |
968 | struct { | |
969 | u64 hdr; | |
970 | u64 body[7]; | |
971 | }; | |
972 | u64 words[8]; | |
973 | }; | |
974 | }; | |
975 | ||
976 | struct qlcnic_nic_req { | |
977 | __le64 qhdr; | |
978 | __le64 req_hdr; | |
979 | __le64 words[6]; | |
b1fc6d3c | 980 | } __packed; |
af19b491 AKS |
981 | |
982 | struct qlcnic_mac_req { | |
983 | u8 op; | |
984 | u8 tag; | |
985 | u8 mac_addr[6]; | |
986 | }; | |
987 | ||
7e56cac4 SC |
988 | struct qlcnic_vlan_req { |
989 | __le16 vlan_id; | |
990 | __le16 rsvd[3]; | |
b1fc6d3c | 991 | } __packed; |
7e56cac4 | 992 | |
b501595c SC |
993 | struct qlcnic_ipaddr { |
994 | __be32 ipv4; | |
995 | __be32 ipv6[4]; | |
996 | }; | |
997 | ||
af19b491 AKS |
998 | #define QLCNIC_MSI_ENABLED 0x02 |
999 | #define QLCNIC_MSIX_ENABLED 0x04 | |
7f966452 | 1000 | #define QLCNIC_LRO_ENABLED 0x01 |
24763d80 | 1001 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
1002 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
1003 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 1004 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 1005 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 1006 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 1007 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 1008 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 1009 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 1010 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 1011 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 1012 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 1013 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
da6c8063 | 1014 | #define QLCNIC_TX_INTR_SHARED 0x10000 |
147a9088 | 1015 | #define QLCNIC_APP_CHANGED_FLAGS 0x20000 |
07a251c8 | 1016 | #define QLCNIC_HAS_PHYS_PORT_ID 0x40000 |
cb9327d5 | 1017 | #define QLCNIC_TSS_RSS 0x80000 |
7f1f6056 SS |
1018 | |
1019 | #ifdef CONFIG_QLCNIC_VXLAN | |
2b3d7b75 SS |
1020 | #define QLCNIC_ADD_VXLAN_PORT 0x100000 |
1021 | #define QLCNIC_DEL_VXLAN_PORT 0x200000 | |
7f1f6056 | 1022 | #endif |
07a251c8 | 1023 | |
d747c333 RB |
1024 | #define QLCNIC_VLAN_FILTERING 0x800000 |
1025 | ||
af19b491 AKS |
1026 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
1027 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
147a9088 SS |
1028 | #define QLCNIC_IS_TSO_CAPABLE(adapter) \ |
1029 | ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) | |
af19b491 | 1030 | |
487042af HM |
1031 | #define QLCNIC_BEACON_EANBLE 0xC |
1032 | #define QLCNIC_BEACON_DISABLE 0xD | |
1033 | ||
a0431589 HM |
1034 | #define QLCNIC_BEACON_ON 2 |
1035 | #define QLCNIC_BEACON_OFF 0 | |
1036 | ||
af19b491 AKS |
1037 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
1038 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 1039 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 | 1040 | |
af19b491 AKS |
1041 | #define QLCNIC_ADAPTER_UP_MAGIC 777 |
1042 | ||
1043 | #define __QLCNIC_FW_ATTACHED 0 | |
1044 | #define __QLCNIC_DEV_UP 1 | |
1045 | #define __QLCNIC_RESETTING 2 | |
1046 | #define __QLCNIC_START_FW 4 | |
451724c8 | 1047 | #define __QLCNIC_AER 5 |
89b4208e | 1048 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 1049 | #define __QLCNIC_LED_ENABLE 7 |
02feda17 | 1050 | #define __QLCNIC_ELB_INPROGRESS 8 |
012ec812 | 1051 | #define __QLCNIC_MULTI_TX_UNIQUE 9 |
02feda17 RB |
1052 | #define __QLCNIC_SRIOV_ENABLE 10 |
1053 | #define __QLCNIC_SRIOV_CAPABLE 11 | |
7ed3ce48 | 1054 | #define __QLCNIC_MBX_POLL_ENABLE 12 |
4690a7e4 | 1055 | #define __QLCNIC_DIAG_MODE 13 |
78ea2d97 | 1056 | #define __QLCNIC_MAINTENANCE_MODE 16 |
af19b491 | 1057 | |
7eb9855d | 1058 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 1059 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 1060 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 1061 | |
b5e5492c | 1062 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 1063 | #define QLCNIC_READD_AGE 20 |
b5e5492c | 1064 | #define QLCNIC_LB_MAX_FILTERS 64 |
7f966452 | 1065 | #define QLCNIC_LB_BUCKET_SIZE 32 |
629263ac | 1066 | #define QLCNIC_ILB_MAX_RCV_LOOP 10 |
fef0c060 | 1067 | |
b5e5492c AKS |
1068 | struct qlcnic_filter { |
1069 | struct hlist_node fnode; | |
1070 | u8 faddr[ETH_ALEN]; | |
f80bc8fe | 1071 | u16 vlan_id; |
b5e5492c AKS |
1072 | unsigned long ftime; |
1073 | }; | |
1074 | ||
1075 | struct qlcnic_filter_hash { | |
1076 | struct hlist_head *fhead; | |
1077 | u8 fnum; | |
7f966452 SC |
1078 | u16 fmax; |
1079 | u16 fbucket_size; | |
b5e5492c AKS |
1080 | }; |
1081 | ||
e5c4e6c6 MC |
1082 | /* Mailbox specific data structures */ |
1083 | struct qlcnic_mailbox { | |
1084 | struct workqueue_struct *work_q; | |
1085 | struct qlcnic_adapter *adapter; | |
1086 | struct qlcnic_mbx_ops *ops; | |
1087 | struct work_struct work; | |
1088 | struct completion completion; | |
1089 | struct list_head cmd_q; | |
1090 | unsigned long status; | |
1091 | spinlock_t queue_lock; /* Mailbox queue lock */ | |
1092 | spinlock_t aen_lock; /* Mailbox response/AEN lock */ | |
1093 | atomic_t rsp_status; | |
1094 | u32 num_cmds; | |
1095 | }; | |
1096 | ||
af19b491 | 1097 | struct qlcnic_adapter { |
b1fc6d3c AC |
1098 | struct qlcnic_hardware_context *ahw; |
1099 | struct qlcnic_recv_context *recv_ctx; | |
1100 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
1101 | struct net_device *netdev; |
1102 | struct pci_dev *pdev; | |
af19b491 | 1103 | |
b1fc6d3c AC |
1104 | unsigned long state; |
1105 | u32 flags; | |
af19b491 AKS |
1106 | |
1107 | u16 num_txd; | |
1108 | u16 num_rxd; | |
1109 | u16 num_jumbo_rxd; | |
90d19005 SC |
1110 | u16 max_rxd; |
1111 | u16 max_jumbo_rxd; | |
af19b491 AKS |
1112 | |
1113 | u8 max_rds_rings; | |
34e8c406 HM |
1114 | |
1115 | u8 max_sds_rings; /* max sds rings supported by adapter */ | |
1116 | u8 max_tx_rings; /* max tx rings supported by adapter */ | |
1117 | ||
1118 | u8 drv_tx_rings; /* max tx rings supported by driver */ | |
1119 | u8 drv_sds_rings; /* max sds rings supported by driver */ | |
1120 | ||
cb9327d5 HM |
1121 | u8 drv_tss_rings; /* tss ring input */ |
1122 | u8 drv_rss_rings; /* rss ring input */ | |
1123 | ||
7f966452 | 1124 | u8 rx_csum; |
af19b491 | 1125 | u8 portnum; |
af19b491 | 1126 | |
af19b491 AKS |
1127 | u8 fw_wait_cnt; |
1128 | u8 fw_fail_cnt; | |
1129 | u8 tx_timeo_cnt; | |
1130 | u8 need_fw_reset; | |
f036e4f4 | 1131 | u8 reset_ctx_cnt; |
af19b491 | 1132 | |
af19b491 | 1133 | u16 is_up; |
91b7282b RB |
1134 | u16 rx_pvid; |
1135 | u16 tx_pvid; | |
2e9d722d | 1136 | |
af19b491 | 1137 | u32 irq; |
4e70812b | 1138 | u32 heartbeat; |
af19b491 AKS |
1139 | |
1140 | u8 dev_state; | |
aa5e18c0 SC |
1141 | u8 reset_ack_timeo; |
1142 | u8 dev_init_timeo; | |
af19b491 AKS |
1143 | |
1144 | u8 mac_addr[ETH_ALEN]; | |
1145 | ||
6df900e9 | 1146 | u64 dev_rst_time; |
fe1adc6b JK |
1147 | bool drv_mac_learn; |
1148 | bool fdb_mac_learn; | |
72ebe349 | 1149 | bool rx_mac_learn; |
b9796a14 | 1150 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
d865ebb4 | 1151 | u8 flash_mfg_id; |
346fe763 | 1152 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
1153 | struct qlcnic_eswitch *eswitch; |
1154 | struct qlcnic_nic_template *nic_ops; | |
1155 | ||
af19b491 | 1156 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 1157 | struct list_head mac_list; |
af19b491 AKS |
1158 | |
1159 | void __iomem *tgt_mask_reg; | |
1160 | void __iomem *tgt_status_reg; | |
1161 | void __iomem *crb_int_state_reg; | |
1162 | void __iomem *isr_int_vec; | |
1163 | ||
f94bc1e7 | 1164 | struct msix_entry *msix_entries; |
7f966452 | 1165 | struct workqueue_struct *qlcnic_wq; |
af19b491 | 1166 | struct delayed_work fw_work; |
7f966452 | 1167 | struct delayed_work idc_aen_work; |
7ed3ce48 | 1168 | struct delayed_work mbx_poll_work; |
14d385b9 | 1169 | struct qlcnic_dcb *dcb; |
af19b491 | 1170 | |
b5e5492c | 1171 | struct qlcnic_filter_hash fhash; |
53643a75 | 1172 | struct qlcnic_filter_hash rx_fhash; |
e8b508ef | 1173 | struct list_head vf_mc_list; |
b5e5492c | 1174 | |
b1fc6d3c | 1175 | spinlock_t mac_learn_lock; |
53643a75 SS |
1176 | /* spinlock for catching rcv filters for eswitch traffic */ |
1177 | spinlock_t rx_mac_learn_lock; | |
63507592 | 1178 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 | 1179 | u32 fw_version; |
147a9088 | 1180 | u32 offload_flags; |
af19b491 AKS |
1181 | const struct firmware *fw; |
1182 | }; | |
1183 | ||
63507592 | 1184 | struct qlcnic_info_le { |
2e9d722d | 1185 | __le16 pci_func; |
63507592 | 1186 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 1187 | __le16 phys_port; |
63507592 | 1188 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
1189 | |
1190 | __le32 capabilities; | |
1191 | u8 max_mac_filters; | |
1192 | u8 reserved1; | |
1193 | __le16 max_mtu; | |
1194 | ||
1195 | __le16 max_tx_ques; | |
1196 | __le16 max_rx_ques; | |
1197 | __le16 min_tx_bw; | |
1198 | __le16 max_tx_bw; | |
7f966452 SC |
1199 | __le32 op_type; |
1200 | __le16 max_bw_reg_offset; | |
1201 | __le16 max_linkspeed_reg_offset; | |
1202 | __le32 capability1; | |
1203 | __le32 capability2; | |
1204 | __le32 capability3; | |
1205 | __le16 max_tx_mac_filters; | |
1206 | __le16 max_rx_mcast_mac_filters; | |
1207 | __le16 max_rx_ucast_mac_filters; | |
1208 | __le16 max_rx_ip_addr; | |
1209 | __le16 max_rx_lro_flow; | |
1210 | __le16 max_rx_status_rings; | |
1211 | __le16 max_rx_buf_rings; | |
1212 | __le16 max_tx_vlan_keys; | |
1213 | u8 total_pf; | |
1214 | u8 total_rss_engines; | |
1215 | __le16 max_vports; | |
02feda17 RB |
1216 | __le16 linkstate_reg_offset; |
1217 | __le16 bit_offsets; | |
1218 | __le16 max_local_ipv6_addrs; | |
1219 | __le16 max_remote_ipv6_addrs; | |
1220 | u8 reserved2[56]; | |
b1fc6d3c | 1221 | } __packed; |
2e9d722d | 1222 | |
63507592 SS |
1223 | struct qlcnic_info { |
1224 | u16 pci_func; | |
1225 | u16 op_mode; | |
1226 | u16 phys_port; | |
1227 | u16 switch_mode; | |
1228 | u32 capabilities; | |
1229 | u8 max_mac_filters; | |
63507592 SS |
1230 | u16 max_mtu; |
1231 | u16 max_tx_ques; | |
1232 | u16 max_rx_ques; | |
1233 | u16 min_tx_bw; | |
1234 | u16 max_tx_bw; | |
7f966452 SC |
1235 | u32 op_type; |
1236 | u16 max_bw_reg_offset; | |
1237 | u16 max_linkspeed_reg_offset; | |
1238 | u32 capability1; | |
1239 | u32 capability2; | |
1240 | u32 capability3; | |
1241 | u16 max_tx_mac_filters; | |
1242 | u16 max_rx_mcast_mac_filters; | |
1243 | u16 max_rx_ucast_mac_filters; | |
1244 | u16 max_rx_ip_addr; | |
1245 | u16 max_rx_lro_flow; | |
1246 | u16 max_rx_status_rings; | |
1247 | u16 max_rx_buf_rings; | |
1248 | u16 max_tx_vlan_keys; | |
1249 | u8 total_pf; | |
1250 | u8 total_rss_engines; | |
1251 | u16 max_vports; | |
02feda17 RB |
1252 | u16 linkstate_reg_offset; |
1253 | u16 bit_offsets; | |
1254 | u16 max_local_ipv6_addrs; | |
1255 | u16 max_remote_ipv6_addrs; | |
63507592 | 1256 | }; |
2e9d722d | 1257 | |
63507592 SS |
1258 | struct qlcnic_pci_info_le { |
1259 | __le16 id; /* pci function id */ | |
1260 | __le16 active; /* 1 = Enabled */ | |
1261 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1262 | __le16 default_port; /* default port number */ | |
1263 | ||
1264 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1265 | __le16 tx_max_bw; |
1266 | __le16 reserved1[2]; | |
1267 | ||
1268 | u8 mac[ETH_ALEN]; | |
7f966452 SC |
1269 | __le16 func_count; |
1270 | u8 reserved2[104]; | |
1271 | ||
b1fc6d3c | 1272 | } __packed; |
2e9d722d | 1273 | |
63507592 SS |
1274 | struct qlcnic_pci_info { |
1275 | u16 id; | |
1276 | u16 active; | |
1277 | u16 type; | |
1278 | u16 default_port; | |
1279 | u16 tx_min_bw; | |
1280 | u16 tx_max_bw; | |
1281 | u8 mac[ETH_ALEN]; | |
7f966452 | 1282 | u16 func_count; |
63507592 SS |
1283 | }; |
1284 | ||
346fe763 | 1285 | struct qlcnic_npar_info { |
35dafcb0 | 1286 | bool eswitch_status; |
4e8acb01 | 1287 | u16 pvid; |
cea8975e AC |
1288 | u16 min_bw; |
1289 | u16 max_bw; | |
346fe763 RB |
1290 | u8 phy_port; |
1291 | u8 type; | |
1292 | u8 active; | |
1293 | u8 enable_pm; | |
1294 | u8 dest_npar; | |
346fe763 | 1295 | u8 discard_tagged; |
7373373d | 1296 | u8 mac_override; |
4e8acb01 RB |
1297 | u8 mac_anti_spoof; |
1298 | u8 promisc_mode; | |
1299 | u8 offload_flags; | |
bff57d8e | 1300 | u8 pci_func; |
9e630955 | 1301 | u8 mac[ETH_ALEN]; |
346fe763 | 1302 | }; |
4e8acb01 | 1303 | |
2e9d722d AC |
1304 | struct qlcnic_eswitch { |
1305 | u8 port; | |
1306 | u8 active_vports; | |
1307 | u8 active_vlans; | |
1308 | u8 active_ucast_filters; | |
1309 | u8 max_ucast_filters; | |
1310 | u8 max_active_vlans; | |
1311 | ||
1312 | u32 flags; | |
1313 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1314 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1315 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1316 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1317 | }; | |
1318 | ||
346fe763 RB |
1319 | |
1320 | /* Return codes for Error handling */ | |
1321 | #define QL_STATUS_INVALID_PARAM -1 | |
1322 | ||
2abea2f0 | 1323 | #define MAX_BW 100 /* % of link speed */ |
ed616689 | 1324 | #define MIN_BW 1 /* % of link speed */ |
346fe763 RB |
1325 | #define MAX_VLAN_ID 4095 |
1326 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1327 | #define DEFAULT_MAC_LEARN 1 |
1328 | ||
0184bbba | 1329 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1330 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1331 | |
1332 | struct qlcnic_pci_func_cfg { | |
1333 | u16 func_type; | |
1334 | u16 min_bw; | |
1335 | u16 max_bw; | |
1336 | u16 port_num; | |
1337 | u8 pci_func; | |
1338 | u8 func_state; | |
f3c0773f | 1339 | u8 def_mac_addr[ETH_ALEN]; |
346fe763 RB |
1340 | }; |
1341 | ||
1342 | struct qlcnic_npar_func_cfg { | |
1343 | u32 fw_capab; | |
1344 | u16 port_num; | |
1345 | u16 min_bw; | |
1346 | u16 max_bw; | |
1347 | u16 max_tx_queues; | |
1348 | u16 max_rx_queues; | |
1349 | u8 pci_func; | |
1350 | u8 op_mode; | |
1351 | }; | |
1352 | ||
1353 | struct qlcnic_pm_func_cfg { | |
1354 | u8 pci_func; | |
1355 | u8 action; | |
1356 | u8 dest_npar; | |
1357 | u8 reserved[5]; | |
1358 | }; | |
1359 | ||
1360 | struct qlcnic_esw_func_cfg { | |
1361 | u16 vlan_id; | |
4e8acb01 RB |
1362 | u8 op_mode; |
1363 | u8 op_type; | |
346fe763 RB |
1364 | u8 pci_func; |
1365 | u8 host_vlan_tag; | |
1366 | u8 promisc_mode; | |
1367 | u8 discard_tagged; | |
7373373d | 1368 | u8 mac_override; |
4e8acb01 RB |
1369 | u8 mac_anti_spoof; |
1370 | u8 offload_flags; | |
1371 | u8 reserved[5]; | |
346fe763 RB |
1372 | }; |
1373 | ||
b6021212 AKS |
1374 | #define QLCNIC_STATS_VERSION 1 |
1375 | #define QLCNIC_STATS_PORT 1 | |
1376 | #define QLCNIC_STATS_ESWITCH 2 | |
1377 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1378 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1379 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1380 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1381 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1382 | #define QLCNIC_MAC_STATS 1 | |
1383 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1384 | |
1385 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1386 | do { \ | |
54a8997c JK |
1387 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1388 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1389 | (VAL1) = (VAL2); \ |
54a8997c JK |
1390 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1391 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1392 | (VAL1) += (VAL2); \ |
1393 | } while (0) | |
1394 | ||
63507592 | 1395 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1396 | __le64 mac_tx_frames; |
1397 | __le64 mac_tx_bytes; | |
1398 | __le64 mac_tx_mcast_pkts; | |
1399 | __le64 mac_tx_bcast_pkts; | |
1400 | __le64 mac_tx_pause_cnt; | |
1401 | __le64 mac_tx_ctrl_pkt; | |
1402 | __le64 mac_tx_lt_64b_pkts; | |
1403 | __le64 mac_tx_lt_127b_pkts; | |
1404 | __le64 mac_tx_lt_255b_pkts; | |
1405 | __le64 mac_tx_lt_511b_pkts; | |
1406 | __le64 mac_tx_lt_1023b_pkts; | |
1407 | __le64 mac_tx_lt_1518b_pkts; | |
1408 | __le64 mac_tx_gt_1518b_pkts; | |
1409 | __le64 rsvd1[3]; | |
1410 | ||
1411 | __le64 mac_rx_frames; | |
1412 | __le64 mac_rx_bytes; | |
1413 | __le64 mac_rx_mcast_pkts; | |
1414 | __le64 mac_rx_bcast_pkts; | |
1415 | __le64 mac_rx_pause_cnt; | |
1416 | __le64 mac_rx_ctrl_pkt; | |
1417 | __le64 mac_rx_lt_64b_pkts; | |
1418 | __le64 mac_rx_lt_127b_pkts; | |
1419 | __le64 mac_rx_lt_255b_pkts; | |
1420 | __le64 mac_rx_lt_511b_pkts; | |
1421 | __le64 mac_rx_lt_1023b_pkts; | |
1422 | __le64 mac_rx_lt_1518b_pkts; | |
1423 | __le64 mac_rx_gt_1518b_pkts; | |
1424 | __le64 rsvd2[3]; | |
1425 | ||
1426 | __le64 mac_rx_length_error; | |
1427 | __le64 mac_rx_length_small; | |
1428 | __le64 mac_rx_length_large; | |
1429 | __le64 mac_rx_jabber; | |
1430 | __le64 mac_rx_dropped; | |
1431 | __le64 mac_rx_crc_error; | |
1432 | __le64 mac_align_error; | |
1433 | } __packed; | |
1434 | ||
63507592 SS |
1435 | struct qlcnic_mac_statistics { |
1436 | u64 mac_tx_frames; | |
1437 | u64 mac_tx_bytes; | |
1438 | u64 mac_tx_mcast_pkts; | |
1439 | u64 mac_tx_bcast_pkts; | |
1440 | u64 mac_tx_pause_cnt; | |
1441 | u64 mac_tx_ctrl_pkt; | |
1442 | u64 mac_tx_lt_64b_pkts; | |
1443 | u64 mac_tx_lt_127b_pkts; | |
1444 | u64 mac_tx_lt_255b_pkts; | |
1445 | u64 mac_tx_lt_511b_pkts; | |
1446 | u64 mac_tx_lt_1023b_pkts; | |
1447 | u64 mac_tx_lt_1518b_pkts; | |
1448 | u64 mac_tx_gt_1518b_pkts; | |
1449 | u64 rsvd1[3]; | |
1450 | u64 mac_rx_frames; | |
1451 | u64 mac_rx_bytes; | |
1452 | u64 mac_rx_mcast_pkts; | |
1453 | u64 mac_rx_bcast_pkts; | |
1454 | u64 mac_rx_pause_cnt; | |
1455 | u64 mac_rx_ctrl_pkt; | |
1456 | u64 mac_rx_lt_64b_pkts; | |
1457 | u64 mac_rx_lt_127b_pkts; | |
1458 | u64 mac_rx_lt_255b_pkts; | |
1459 | u64 mac_rx_lt_511b_pkts; | |
1460 | u64 mac_rx_lt_1023b_pkts; | |
1461 | u64 mac_rx_lt_1518b_pkts; | |
1462 | u64 mac_rx_gt_1518b_pkts; | |
1463 | u64 rsvd2[3]; | |
1464 | u64 mac_rx_length_error; | |
1465 | u64 mac_rx_length_small; | |
1466 | u64 mac_rx_length_large; | |
1467 | u64 mac_rx_jabber; | |
1468 | u64 mac_rx_dropped; | |
1469 | u64 mac_rx_crc_error; | |
1470 | u64 mac_align_error; | |
1471 | }; | |
1472 | ||
1473 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1474 | __le16 context_id; |
1475 | __le16 version; | |
1476 | __le16 size; | |
1477 | __le16 unused; | |
1478 | __le64 unicast_frames; | |
1479 | __le64 multicast_frames; | |
1480 | __le64 broadcast_frames; | |
1481 | __le64 dropped_frames; | |
1482 | __le64 errors; | |
1483 | __le64 local_frames; | |
1484 | __le64 numbytes; | |
1485 | __le64 rsvd[3]; | |
b1fc6d3c | 1486 | } __packed; |
b6021212 | 1487 | |
63507592 SS |
1488 | struct __qlcnic_esw_statistics { |
1489 | u16 context_id; | |
1490 | u16 version; | |
1491 | u16 size; | |
1492 | u16 unused; | |
1493 | u64 unicast_frames; | |
1494 | u64 multicast_frames; | |
1495 | u64 broadcast_frames; | |
1496 | u64 dropped_frames; | |
1497 | u64 errors; | |
1498 | u64 local_frames; | |
1499 | u64 numbytes; | |
1500 | u64 rsvd[3]; | |
1501 | }; | |
1502 | ||
b6021212 AKS |
1503 | struct qlcnic_esw_statistics { |
1504 | struct __qlcnic_esw_statistics rx; | |
1505 | struct __qlcnic_esw_statistics tx; | |
1506 | }; | |
1507 | ||
18f2f616 | 1508 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1509 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1510 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1511 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1512 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1513 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1514 | |
7777de9a | 1515 | struct _cdrp_cmd { |
7e2cf4fe SC |
1516 | u32 num; |
1517 | u32 *arg; | |
7777de9a AC |
1518 | }; |
1519 | ||
1520 | struct qlcnic_cmd_args { | |
e5c4e6c6 MC |
1521 | struct completion completion; |
1522 | struct list_head list; | |
1523 | struct _cdrp_cmd req; | |
1524 | struct _cdrp_cmd rsp; | |
1525 | atomic_t rsp_status; | |
1526 | int pay_size; | |
1527 | u32 rsp_opcode; | |
1528 | u32 total_cmds; | |
1529 | u32 op_type; | |
1530 | u32 type; | |
1531 | u32 cmd_op; | |
1532 | u32 *hdr; /* Back channel message header */ | |
1533 | u32 *pay; /* Back channel message payload */ | |
1534 | u8 func_num; | |
7777de9a AC |
1535 | }; |
1536 | ||
18f2f616 | 1537 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1538 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1539 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); |
1540 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1541 | |
1542 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1543 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 | 1544 | |
4bd8e738 HM |
1545 | #define QLCRD32(adapter, off, err) \ |
1546 | (adapter->ahw->hw_ops->read_reg)(adapter, off, err) | |
7e2cf4fe | 1547 | |
af19b491 | 1548 | #define QLCWR32(adapter, off, val) \ |
7e2cf4fe | 1549 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
af19b491 AKS |
1550 | |
1551 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1552 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1553 | ||
1554 | #define qlcnic_rom_lock(a) \ | |
1555 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1556 | #define qlcnic_rom_unlock(a) \ | |
1557 | qlcnic_pcie_sem_unlock((a), 2) | |
1558 | #define qlcnic_phy_lock(a) \ | |
1559 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1560 | #define qlcnic_phy_unlock(a) \ | |
1561 | qlcnic_pcie_sem_unlock((a), 3) | |
af19b491 AKS |
1562 | #define qlcnic_sw_lock(a) \ |
1563 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1564 | #define qlcnic_sw_unlock(a) \ | |
1565 | qlcnic_pcie_sem_unlock((a), 6) | |
1566 | #define crb_win_lock(a) \ | |
1567 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1568 | #define crb_win_unlock(a) \ | |
1569 | qlcnic_pcie_sem_unlock((a), 7) | |
1570 | ||
728a98b8 SC |
1571 | #define __QLCNIC_MAX_LED_RATE 0xf |
1572 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1573 | ||
58634e74 SC |
1574 | #define MAX_CTL_CHECK 1000 |
1575 | ||
b5e5492c AKS |
1576 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1577 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1578 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
890b6e02 SS |
1579 | int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); |
1580 | bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); | |
af19b491 AKS |
1581 | |
1582 | /* Functions from qlcnic_init.c */ | |
13159183 | 1583 | void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); |
af19b491 AKS |
1584 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1585 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1586 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1587 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1588 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1589 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1590 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1591 | |
18f2f616 | 1592 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1593 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1594 | u8 *bytes, size_t size); | |
1595 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1596 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1597 | ||
15087c2b | 1598 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); |
af19b491 AKS |
1599 | |
1600 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1601 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1602 | ||
8a15ad1f AKS |
1603 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1604 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1605 | ||
1606 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 | 1607 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
012ec812 HM |
1608 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *, |
1609 | struct qlcnic_host_tx_ring *); | |
af19b491 | 1610 | |
d4066833 | 1611 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1612 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1613 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
4be41e92 | 1614 | struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); |
af19b491 | 1615 | void qlcnic_set_multi(struct net_device *netdev); |
91b7282b | 1616 | int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16); |
fe1adc6b | 1617 | int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); |
91b7282b | 1618 | void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); |
07a251c8 | 1619 | int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); |
af19b491 AKS |
1620 | |
1621 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
8af3f33d | 1622 | int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); |
af19b491 | 1623 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); |
c8f44aff MM |
1624 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1625 | netdev_features_t features); | |
1626 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
2e9d722d | 1627 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
5ad6ff9d | 1628 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
22c8c934 SC |
1629 | |
1630 | /* Functions from qlcnic_ethtool.c */ | |
ba4468db JK |
1631 | int qlcnic_check_loopback_buff(unsigned char *, u8 []); |
1632 | int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); | |
af19b491 AKS |
1633 | |
1634 | /* Functions from qlcnic_main.c */ | |
1635 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
34e8c406 HM |
1636 | void qlcnic_diag_free_res(struct net_device *netdev, int); |
1637 | int qlcnic_diag_alloc_res(struct net_device *netdev, int); | |
1638 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *); | |
1639 | void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8); | |
1640 | void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8); | |
cb9327d5 | 1641 | int qlcnic_setup_rings(struct qlcnic_adapter *); |
34e8c406 | 1642 | int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int); |
e5dcf6dc | 1643 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
7f966452 | 1644 | int qlcnic_enable_msix(struct qlcnic_adapter *, u32); |
8af3f33d | 1645 | void qlcnic_set_drv_version(struct qlcnic_adapter *); |
af19b491 | 1646 | |
2e9d722d | 1647 | /* eSwitch management functions */ |
4e8acb01 RB |
1648 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1649 | struct qlcnic_esw_func_cfg *); | |
629263ac | 1650 | |
4e8acb01 RB |
1651 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, |
1652 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1653 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1654 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1655 | struct __qlcnic_esw_statistics *); | |
1656 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1657 | struct __qlcnic_esw_statistics *); | |
1658 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1659 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d | 1660 | |
7e2cf4fe | 1661 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); |
7e2cf4fe | 1662 | |
c70001a9 SC |
1663 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); |
1664 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
7f966452 | 1665 | void qlcnic_advert_link_change(struct qlcnic_adapter *, int); |
c70001a9 SC |
1666 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); |
1667 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
012ec812 | 1668 | void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); |
c70001a9 | 1669 | |
ec079a07 SC |
1670 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1671 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
7e2cf4fe SC |
1672 | void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); |
1673 | void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); | |
1674 | ||
ec079a07 SC |
1675 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); |
1676 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1677 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1678 | struct qlcnic_esw_func_cfg *); | |
1679 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1680 | struct qlcnic_esw_func_cfg *); | |
cb9327d5 | 1681 | int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *); |
629263ac SC |
1682 | void qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1683 | int qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
319ecf12 SC |
1684 | void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1685 | void qlcnic_detach(struct qlcnic_adapter *); | |
1686 | void qlcnic_teardown_intr(struct qlcnic_adapter *); | |
1687 | int qlcnic_attach(struct qlcnic_adapter *); | |
1688 | int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
1689 | void qlcnic_restore_indev_addr(struct net_device *, unsigned long); | |
1690 | ||
629263ac | 1691 | int qlcnic_check_temp(struct qlcnic_adapter *); |
d71170fb SC |
1692 | int qlcnic_init_pci_info(struct qlcnic_adapter *); |
1693 | int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); | |
1694 | int qlcnic_reset_npar_config(struct qlcnic_adapter *); | |
1695 | int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); | |
02feda17 | 1696 | int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); |
f8468331 RB |
1697 | int qlcnic_read_mac_addr(struct qlcnic_adapter *); |
1698 | int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); | |
147a9088 SS |
1699 | void qlcnic_set_netdev_features(struct qlcnic_adapter *, |
1700 | struct qlcnic_esw_func_cfg *); | |
74b7ba1a | 1701 | void qlcnic_sriov_vf_set_multi(struct net_device *); |
2f514c52 JK |
1702 | int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8); |
1703 | int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *, | |
1704 | u16 *); | |
f8468331 | 1705 | |
af19b491 AKS |
1706 | /* |
1707 | * QLOGIC Board information | |
1708 | */ | |
1709 | ||
02420be6 | 1710 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
22999798 | 1711 | struct qlcnic_board_info { |
af19b491 AKS |
1712 | unsigned short vendor; |
1713 | unsigned short device; | |
1714 | unsigned short sub_vendor; | |
1715 | unsigned short sub_device; | |
1716 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1717 | }; | |
1718 | ||
af19b491 AKS |
1719 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) |
1720 | { | |
036d61f0 | 1721 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1722 | return tx_ring->sw_consumer - tx_ring->producer; |
1723 | else | |
1724 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1725 | tx_ring->producer; | |
1726 | } | |
1727 | ||
7e2cf4fe SC |
1728 | struct qlcnic_nic_template { |
1729 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1730 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
1731 | int (*start_firmware) (struct qlcnic_adapter *); | |
1732 | int (*init_driver) (struct qlcnic_adapter *); | |
1733 | void (*request_reset) (struct qlcnic_adapter *, u32); | |
1734 | void (*cancel_idc_work) (struct qlcnic_adapter *); | |
1735 | int (*napi_add)(struct qlcnic_adapter *, struct net_device *); | |
4be41e92 | 1736 | void (*napi_del)(struct qlcnic_adapter *); |
7e2cf4fe SC |
1737 | void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); |
1738 | irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); | |
486a5bc7 RB |
1739 | int (*shutdown)(struct pci_dev *); |
1740 | int (*resume)(struct qlcnic_adapter *); | |
7e2cf4fe SC |
1741 | }; |
1742 | ||
e5c4e6c6 MC |
1743 | struct qlcnic_mbx_ops { |
1744 | int (*enqueue_cmd) (struct qlcnic_adapter *, | |
1745 | struct qlcnic_cmd_args *, unsigned long *); | |
1746 | void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1747 | void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1748 | void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1749 | void (*nofity_fw) (struct qlcnic_adapter *, u8); | |
1750 | }; | |
1751 | ||
1752 | int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); | |
1753 | void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); | |
1754 | void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); | |
1755 | void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); | |
1ac6762a | 1756 | void qlcnic_update_stats(struct qlcnic_adapter *); |
e5c4e6c6 | 1757 | |
7e2cf4fe SC |
1758 | /* Adapter hardware abstraction */ |
1759 | struct qlcnic_hardware_ops { | |
1760 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1761 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
4bd8e738 | 1762 | int (*read_reg) (struct qlcnic_adapter *, ulong, int *); |
7e2cf4fe SC |
1763 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); |
1764 | void (*get_ocm_win) (struct qlcnic_hardware_context *); | |
07a251c8 | 1765 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); |
34e8c406 | 1766 | int (*setup_intr) (struct qlcnic_adapter *); |
7e2cf4fe SC |
1767 | int (*alloc_mbx_args)(struct qlcnic_cmd_args *, |
1768 | struct qlcnic_adapter *, u32); | |
1769 | int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1770 | void (*get_func_no) (struct qlcnic_adapter *); | |
1771 | int (*api_lock) (struct qlcnic_adapter *); | |
1772 | void (*api_unlock) (struct qlcnic_adapter *); | |
1773 | void (*add_sysfs) (struct qlcnic_adapter *); | |
1774 | void (*remove_sysfs) (struct qlcnic_adapter *); | |
1775 | void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); | |
1776 | int (*create_rx_ctx) (struct qlcnic_adapter *); | |
1777 | int (*create_tx_ctx) (struct qlcnic_adapter *, | |
1778 | struct qlcnic_host_tx_ring *, int); | |
7cb03b23 RB |
1779 | void (*del_rx_ctx) (struct qlcnic_adapter *); |
1780 | void (*del_tx_ctx) (struct qlcnic_adapter *, | |
1781 | struct qlcnic_host_tx_ring *); | |
7e2cf4fe SC |
1782 | int (*setup_link_event) (struct qlcnic_adapter *, int); |
1783 | int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
1784 | int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
1785 | int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); | |
f80bc8fe | 1786 | int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); |
7e2cf4fe SC |
1787 | void (*napi_enable) (struct qlcnic_adapter *); |
1788 | void (*napi_disable) (struct qlcnic_adapter *); | |
a514722a HM |
1789 | int (*config_intr_coal) (struct qlcnic_adapter *, |
1790 | struct ethtool_coalesce *); | |
7e2cf4fe SC |
1791 | int (*config_rss) (struct qlcnic_adapter *, int); |
1792 | int (*config_hw_lro) (struct qlcnic_adapter *, int); | |
1793 | int (*config_loopback) (struct qlcnic_adapter *, u8); | |
1794 | int (*clear_loopback) (struct qlcnic_adapter *, u8); | |
1795 | int (*config_promisc_mode) (struct qlcnic_adapter *, u32); | |
f80bc8fe | 1796 | void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16); |
7e2cf4fe | 1797 | int (*get_board_info) (struct qlcnic_adapter *); |
52e493d0 | 1798 | void (*set_mac_filter_count) (struct qlcnic_adapter *); |
91b7282b | 1799 | void (*free_mac_list) (struct qlcnic_adapter *); |
07a251c8 | 1800 | int (*read_phys_port_id) (struct qlcnic_adapter *); |
4460f2e8 PP |
1801 | pci_ers_result_t (*io_error_detected) (struct pci_dev *, |
1802 | pci_channel_state_t); | |
1803 | pci_ers_result_t (*io_slot_reset) (struct pci_dev *); | |
1804 | void (*io_resume) (struct pci_dev *); | |
a0431589 | 1805 | void (*get_beacon_state)(struct qlcnic_adapter *); |
2cc5752e M |
1806 | void (*enable_sds_intr) (struct qlcnic_adapter *, |
1807 | struct qlcnic_host_sds_ring *); | |
1808 | void (*disable_sds_intr) (struct qlcnic_adapter *, | |
1809 | struct qlcnic_host_sds_ring *); | |
1810 | void (*enable_tx_intr) (struct qlcnic_adapter *, | |
1811 | struct qlcnic_host_tx_ring *); | |
1812 | void (*disable_tx_intr) (struct qlcnic_adapter *, | |
1813 | struct qlcnic_host_tx_ring *); | |
225837a0 SS |
1814 | u32 (*get_saved_state)(void *, u32); |
1815 | void (*set_saved_state)(void *, u32, u32); | |
1816 | void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *); | |
1817 | u32 (*get_cap_size)(void *, int); | |
1818 | void (*set_sys_info)(void *, int, u32); | |
1819 | void (*store_cap_mask)(void *, u32); | |
7e2cf4fe SC |
1820 | }; |
1821 | ||
1822 | extern struct qlcnic_nic_template qlcnic_vf_ops; | |
1823 | ||
381709de SS |
1824 | static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter) |
1825 | { | |
1826 | return adapter->ahw->extra_capability[0] & | |
1827 | QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD; | |
1828 | } | |
1829 | ||
2b3d7b75 SS |
1830 | static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter) |
1831 | { | |
1832 | return adapter->ahw->extra_capability[0] & | |
1833 | QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD; | |
1834 | } | |
1835 | ||
7e2cf4fe SC |
1836 | static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) |
1837 | { | |
1838 | return adapter->nic_ops->start_firmware(adapter); | |
1839 | } | |
1840 | ||
1841 | static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1842 | loff_t offset, size_t size) | |
1843 | { | |
1844 | adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); | |
1845 | } | |
1846 | ||
1847 | static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1848 | loff_t offset, size_t size) | |
1849 | { | |
1850 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); | |
1851 | } | |
1852 | ||
7e2cf4fe SC |
1853 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, |
1854 | ulong off, u32 data) | |
1855 | { | |
1856 | return adapter->ahw->hw_ops->write_reg(adapter, off, data); | |
1857 | } | |
1858 | ||
1859 | static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, | |
07a251c8 | 1860 | u8 *mac, u8 function) |
7e2cf4fe | 1861 | { |
07a251c8 | 1862 | return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); |
7e2cf4fe SC |
1863 | } |
1864 | ||
34e8c406 | 1865 | static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter) |
7e2cf4fe | 1866 | { |
34e8c406 | 1867 | return adapter->ahw->hw_ops->setup_intr(adapter); |
7e2cf4fe SC |
1868 | } |
1869 | ||
1870 | static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
1871 | struct qlcnic_adapter *adapter, u32 arg) | |
1872 | { | |
1873 | return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); | |
1874 | } | |
1875 | ||
1876 | static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, | |
1877 | struct qlcnic_cmd_args *cmd) | |
1878 | { | |
f8468331 RB |
1879 | if (adapter->ahw->hw_ops->mbx_cmd) |
1880 | return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); | |
1881 | ||
1882 | return -EIO; | |
7e2cf4fe SC |
1883 | } |
1884 | ||
1885 | static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) | |
1886 | { | |
1887 | adapter->ahw->hw_ops->get_func_no(adapter); | |
1888 | } | |
1889 | ||
1890 | static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) | |
1891 | { | |
1892 | return adapter->ahw->hw_ops->api_lock(adapter); | |
1893 | } | |
1894 | ||
1895 | static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) | |
1896 | { | |
1897 | adapter->ahw->hw_ops->api_unlock(adapter); | |
1898 | } | |
1899 | ||
1900 | static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) | |
1901 | { | |
f8468331 RB |
1902 | if (adapter->ahw->hw_ops->add_sysfs) |
1903 | adapter->ahw->hw_ops->add_sysfs(adapter); | |
7e2cf4fe SC |
1904 | } |
1905 | ||
1906 | static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) | |
1907 | { | |
f8468331 RB |
1908 | if (adapter->ahw->hw_ops->remove_sysfs) |
1909 | adapter->ahw->hw_ops->remove_sysfs(adapter); | |
7e2cf4fe SC |
1910 | } |
1911 | ||
1912 | static inline void | |
1913 | qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) | |
1914 | { | |
1915 | sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); | |
1916 | } | |
1917 | ||
1918 | static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
1919 | { | |
1920 | return adapter->ahw->hw_ops->create_rx_ctx(adapter); | |
1921 | } | |
1922 | ||
1923 | static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, | |
1924 | struct qlcnic_host_tx_ring *ptr, | |
1925 | int ring) | |
1926 | { | |
1927 | return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); | |
1928 | } | |
1929 | ||
7cb03b23 RB |
1930 | static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) |
1931 | { | |
1932 | return adapter->ahw->hw_ops->del_rx_ctx(adapter); | |
1933 | } | |
1934 | ||
1935 | static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, | |
1936 | struct qlcnic_host_tx_ring *ptr) | |
1937 | { | |
1938 | return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); | |
1939 | } | |
1940 | ||
7e2cf4fe SC |
1941 | static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, |
1942 | int enable) | |
1943 | { | |
1944 | return adapter->ahw->hw_ops->setup_link_event(adapter, enable); | |
1945 | } | |
1946 | ||
1947 | static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, | |
1948 | struct qlcnic_info *info, u8 id) | |
1949 | { | |
1950 | return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); | |
1951 | } | |
1952 | ||
1953 | static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, | |
1954 | struct qlcnic_pci_info *info) | |
1955 | { | |
1956 | return adapter->ahw->hw_ops->get_pci_info(adapter, info); | |
1957 | } | |
1958 | ||
1959 | static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, | |
1960 | struct qlcnic_info *info) | |
1961 | { | |
1962 | return adapter->ahw->hw_ops->set_nic_info(adapter, info); | |
1963 | } | |
1964 | ||
1965 | static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, | |
f80bc8fe | 1966 | u8 *addr, u16 id, u8 cmd) |
7e2cf4fe SC |
1967 | { |
1968 | return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); | |
1969 | } | |
1970 | ||
1971 | static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, | |
1972 | struct net_device *netdev) | |
1973 | { | |
1974 | return adapter->nic_ops->napi_add(adapter, netdev); | |
1975 | } | |
1976 | ||
4be41e92 SC |
1977 | static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) |
1978 | { | |
1979 | adapter->nic_ops->napi_del(adapter); | |
1980 | } | |
1981 | ||
7e2cf4fe SC |
1982 | static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) |
1983 | { | |
1984 | adapter->ahw->hw_ops->napi_enable(adapter); | |
1985 | } | |
1986 | ||
486a5bc7 RB |
1987 | static inline int __qlcnic_shutdown(struct pci_dev *pdev) |
1988 | { | |
1989 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
1990 | ||
1991 | return adapter->nic_ops->shutdown(pdev); | |
1992 | } | |
1993 | ||
1994 | static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) | |
1995 | { | |
1996 | return adapter->nic_ops->resume(adapter); | |
1997 | } | |
1998 | ||
7e2cf4fe SC |
1999 | static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) |
2000 | { | |
2001 | adapter->ahw->hw_ops->napi_disable(adapter); | |
2002 | } | |
2003 | ||
a514722a HM |
2004 | static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter, |
2005 | struct ethtool_coalesce *ethcoal) | |
7e2cf4fe | 2006 | { |
a514722a | 2007 | return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal); |
7e2cf4fe SC |
2008 | } |
2009 | ||
2010 | static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) | |
2011 | { | |
2012 | return adapter->ahw->hw_ops->config_rss(adapter, enable); | |
2013 | } | |
2014 | ||
2015 | static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, | |
2016 | int enable) | |
2017 | { | |
2018 | return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); | |
2019 | } | |
2020 | ||
2021 | static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
2022 | { | |
2023 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
2024 | } | |
2025 | ||
2026 | static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
2027 | { | |
d09529e6 | 2028 | return adapter->ahw->hw_ops->clear_loopback(adapter, mode); |
7e2cf4fe SC |
2029 | } |
2030 | ||
2031 | static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, | |
2032 | u32 mode) | |
2033 | { | |
2034 | return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); | |
2035 | } | |
2036 | ||
2037 | static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, | |
f80bc8fe | 2038 | u64 *addr, u16 id) |
7e2cf4fe SC |
2039 | { |
2040 | adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); | |
2041 | } | |
2042 | ||
2043 | static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) | |
2044 | { | |
2045 | return adapter->ahw->hw_ops->get_board_info(adapter); | |
2046 | } | |
2047 | ||
91b7282b RB |
2048 | static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) |
2049 | { | |
2050 | return adapter->ahw->hw_ops->free_mac_list(adapter); | |
2051 | } | |
2052 | ||
52e493d0 JK |
2053 | static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) |
2054 | { | |
e9a355a9 SC |
2055 | if (adapter->ahw->hw_ops->set_mac_filter_count) |
2056 | adapter->ahw->hw_ops->set_mac_filter_count(adapter); | |
52e493d0 JK |
2057 | } |
2058 | ||
a0431589 HM |
2059 | static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter) |
2060 | { | |
2061 | adapter->ahw->hw_ops->get_beacon_state(adapter); | |
2062 | } | |
2063 | ||
07a251c8 SS |
2064 | static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) |
2065 | { | |
2066 | if (adapter->ahw->hw_ops->read_phys_port_id) | |
2067 | adapter->ahw->hw_ops->read_phys_port_id(adapter); | |
2068 | } | |
2069 | ||
225837a0 SS |
2070 | static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter, |
2071 | void *t_hdr, u32 index) | |
2072 | { | |
2073 | return adapter->ahw->hw_ops->get_saved_state(t_hdr, index); | |
2074 | } | |
2075 | ||
2076 | static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter, | |
2077 | void *t_hdr, u32 index, u32 value) | |
2078 | { | |
2079 | adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value); | |
2080 | } | |
2081 | ||
2082 | static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter, | |
2083 | struct qlcnic_fw_dump *fw_dump) | |
2084 | { | |
2085 | adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump); | |
2086 | } | |
2087 | ||
2088 | static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter, | |
2089 | void *tmpl_hdr, int index) | |
2090 | { | |
2091 | return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index); | |
2092 | } | |
2093 | ||
2094 | static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter, | |
2095 | void *tmpl_hdr, int idx, u32 value) | |
2096 | { | |
2097 | adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value); | |
2098 | } | |
2099 | ||
2100 | static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter, | |
2101 | void *tmpl_hdr, u32 mask) | |
2102 | { | |
2103 | adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask); | |
2104 | } | |
2105 | ||
7e2cf4fe SC |
2106 | static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, |
2107 | u32 key) | |
2108 | { | |
f8468331 RB |
2109 | if (adapter->nic_ops->request_reset) |
2110 | adapter->nic_ops->request_reset(adapter, key); | |
7e2cf4fe SC |
2111 | } |
2112 | ||
2113 | static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) | |
2114 | { | |
f8468331 RB |
2115 | if (adapter->nic_ops->cancel_idc_work) |
2116 | adapter->nic_ops->cancel_idc_work(adapter); | |
7e2cf4fe SC |
2117 | } |
2118 | ||
2119 | static inline irqreturn_t | |
2120 | qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
2121 | { | |
2122 | return adapter->nic_ops->clear_legacy_intr(adapter); | |
2123 | } | |
2124 | ||
2125 | static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, | |
2126 | u32 rate) | |
2127 | { | |
2128 | return adapter->nic_ops->config_led(adapter, state, rate); | |
2129 | } | |
2130 | ||
2131 | static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, | |
2132 | __be32 ip, int cmd) | |
2133 | { | |
2134 | adapter->nic_ops->config_ipaddr(adapter, ip, cmd); | |
2135 | } | |
2136 | ||
012ec812 HM |
2137 | static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) |
2138 | { | |
2139 | return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
2140 | } | |
2141 | ||
2cc5752e M |
2142 | static inline void |
2143 | qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter, | |
2144 | struct qlcnic_host_tx_ring *tx_ring) | |
2145 | { | |
2146 | if (qlcnic_check_multi_tx(adapter) && | |
2147 | !adapter->ahw->diag_test) | |
2148 | writel(0x0, tx_ring->crb_intr_mask); | |
2149 | } | |
2150 | ||
2151 | static inline void | |
2152 | qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter, | |
2153 | struct qlcnic_host_tx_ring *tx_ring) | |
2154 | { | |
2155 | if (qlcnic_check_multi_tx(adapter) && | |
2156 | !adapter->ahw->diag_test) | |
2157 | writel(1, tx_ring->crb_intr_mask); | |
2158 | } | |
2159 | ||
2160 | static inline void | |
2161 | qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter, | |
2162 | struct qlcnic_host_tx_ring *tx_ring) | |
2163 | { | |
2164 | writel(0, tx_ring->crb_intr_mask); | |
2165 | } | |
2166 | ||
2167 | static inline void | |
2168 | qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter, | |
2169 | struct qlcnic_host_tx_ring *tx_ring) | |
2170 | { | |
2171 | writel(1, tx_ring->crb_intr_mask); | |
2172 | } | |
2173 | ||
2174 | /* Enable MSI-x and INT-x interrupts */ | |
2175 | static inline void | |
2176 | qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter, | |
2177 | struct qlcnic_host_sds_ring *sds_ring) | |
2178 | { | |
2179 | writel(0, sds_ring->crb_intr_mask); | |
2180 | } | |
2181 | ||
2182 | /* Disable MSI-x and INT-x interrupts */ | |
2183 | static inline void | |
2184 | qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter, | |
2185 | struct qlcnic_host_sds_ring *sds_ring) | |
2186 | { | |
2187 | writel(1, sds_ring->crb_intr_mask); | |
2188 | } | |
2189 | ||
012ec812 HM |
2190 | static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) |
2191 | { | |
2192 | test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
34e8c406 | 2193 | adapter->drv_tx_rings = QLCNIC_SINGLE_RING; |
012ec812 HM |
2194 | } |
2195 | ||
2196 | /* When operating in a muti tx mode, driver needs to write 0x1 | |
2197 | * to src register, instead of 0x0 to disable receiving interrupt. | |
2198 | */ | |
2cc5752e M |
2199 | static inline void |
2200 | qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter, | |
2201 | struct qlcnic_host_sds_ring *sds_ring) | |
c70001a9 | 2202 | { |
012ec812 | 2203 | if (qlcnic_check_multi_tx(adapter) && |
c2c5e3a0 | 2204 | !adapter->ahw->diag_test && |
012ec812 HM |
2205 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2206 | writel(0x1, sds_ring->crb_intr_mask); | |
2207 | else | |
2208 | writel(0, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2209 | } |
2210 | ||
2cc5752e M |
2211 | static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter, |
2212 | struct qlcnic_host_sds_ring *sds_ring) | |
2213 | { | |
2214 | if (adapter->ahw->hw_ops->enable_sds_intr) | |
2215 | adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring); | |
2216 | } | |
2217 | ||
2218 | static inline void | |
2219 | qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter, | |
2220 | struct qlcnic_host_sds_ring *sds_ring) | |
2221 | { | |
2222 | if (adapter->ahw->hw_ops->disable_sds_intr) | |
2223 | adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring); | |
2224 | } | |
2225 | ||
2226 | static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter, | |
2227 | struct qlcnic_host_tx_ring *tx_ring) | |
2228 | { | |
2229 | if (adapter->ahw->hw_ops->enable_tx_intr) | |
2230 | adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring); | |
2231 | } | |
2232 | ||
2233 | static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter, | |
2234 | struct qlcnic_host_tx_ring *tx_ring) | |
2235 | { | |
2236 | if (adapter->ahw->hw_ops->disable_tx_intr) | |
2237 | adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring); | |
2238 | } | |
2239 | ||
012ec812 HM |
2240 | /* When operating in a muti tx mode, driver needs to write 0x0 |
2241 | * to src register, instead of 0x1 to enable receiving interrupts. | |
2242 | */ | |
2cc5752e M |
2243 | static inline void |
2244 | qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter, | |
2245 | struct qlcnic_host_sds_ring *sds_ring) | |
c70001a9 | 2246 | { |
012ec812 | 2247 | if (qlcnic_check_multi_tx(adapter) && |
c2c5e3a0 | 2248 | !adapter->ahw->diag_test && |
012ec812 HM |
2249 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2250 | writel(0, sds_ring->crb_intr_mask); | |
2251 | else | |
2252 | writel(0x1, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2253 | |
2254 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
2255 | writel(0xfbff, adapter->tgt_mask_reg); | |
2256 | } | |
2257 | ||
4690a7e4 SC |
2258 | static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) |
2259 | { | |
2260 | return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2261 | } | |
2262 | ||
2263 | static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) | |
2264 | { | |
2265 | clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2266 | } | |
2267 | ||
099907fa SC |
2268 | static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) |
2269 | { | |
2270 | return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2271 | } | |
2272 | ||
d1a1105e | 2273 | extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; |
af19b491 | 2274 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 2275 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 2276 | |
65b5b420 | 2277 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
79788450 | 2278 | if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ |
65b5b420 AKS |
2279 | printk(KERN_INFO "%s: %s: " _fmt, \ |
2280 | dev_name(&adapter->pdev->dev), \ | |
2281 | __func__, ##_args); \ | |
2282 | } while (0) | |
2283 | ||
15ca140f MC |
2284 | #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 |
2285 | #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 | |
40e2b8ed | 2286 | #define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830 |
f8468331 | 2287 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 |
15ca140f MC |
2288 | #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 |
2289 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 | |
f8468331 | 2290 | |
97ee45eb SC |
2291 | static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) |
2292 | { | |
2293 | unsigned short device = adapter->pdev->device; | |
2294 | return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; | |
2295 | } | |
2296 | ||
991ca269 MC |
2297 | static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) |
2298 | { | |
2299 | unsigned short device = adapter->pdev->device; | |
2300 | ||
2301 | return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || | |
2302 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; | |
2303 | } | |
2304 | ||
7f966452 SC |
2305 | static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) |
2306 | { | |
2307 | unsigned short device = adapter->pdev->device; | |
f8468331 RB |
2308 | bool status; |
2309 | ||
2310 | status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || | |
40e2b8ed | 2311 | (device == PCI_DEVICE_ID_QLOGIC_QLE8830) || |
15ca140f MC |
2312 | (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || |
2313 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || | |
f8468331 RB |
2314 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false; |
2315 | ||
2316 | return status; | |
7f966452 SC |
2317 | } |
2318 | ||
02feda17 RB |
2319 | static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) |
2320 | { | |
2321 | return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; | |
2322 | } | |
7f966452 | 2323 | |
f8468331 RB |
2324 | static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) |
2325 | { | |
2326 | unsigned short device = adapter->pdev->device; | |
15ca140f MC |
2327 | bool status; |
2328 | ||
2329 | status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || | |
2330 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; | |
f8468331 | 2331 | |
15ca140f | 2332 | return status; |
f8468331 | 2333 | } |
154d0c81 MC |
2334 | |
2335 | static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter) | |
2336 | { | |
2337 | unsigned short device = adapter->pdev->device; | |
2338 | ||
2339 | return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false; | |
2340 | } | |
2341 | ||
2342 | static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter) | |
2343 | { | |
2344 | unsigned short device = adapter->pdev->device; | |
2345 | ||
2346 | return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false; | |
2347 | } | |
2f514c52 | 2348 | |
d747c333 RB |
2349 | static inline bool qlcnic_sriov_check(struct qlcnic_adapter *adapter) |
2350 | { | |
2351 | bool status; | |
2352 | ||
2353 | status = (qlcnic_sriov_pf_check(adapter) || | |
2354 | qlcnic_sriov_vf_check(adapter)) ? true : false; | |
2355 | ||
2356 | return status; | |
2357 | } | |
2358 | ||
2f514c52 JK |
2359 | static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter) |
2360 | { | |
2361 | if (qlcnic_84xx_check(adapter)) | |
2362 | return QLC_84XX_VNIC_COUNT; | |
2363 | else | |
2364 | return QLC_DEFAULT_VNIC_COUNT; | |
2365 | } | |
1f0f467b | 2366 | |
26acc712 JK |
2367 | static inline void qlcnic_swap32_buffer(u32 *buffer, int count) |
2368 | { | |
2369 | #if defined(__BIG_ENDIAN) | |
2370 | u32 *tmp = buffer; | |
2371 | int i; | |
2372 | ||
2373 | for (i = 0; i < count; i++) { | |
2374 | *tmp = swab32(*tmp); | |
2375 | tmp++; | |
2376 | } | |
2377 | #endif | |
2378 | } | |
2379 | ||
1f0f467b HP |
2380 | #ifdef CONFIG_QLCNIC_HWMON |
2381 | void qlcnic_register_hwmon_dev(struct qlcnic_adapter *); | |
2382 | void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *); | |
2383 | #else | |
2384 | static inline void qlcnic_register_hwmon_dev(struct qlcnic_adapter *adapter) | |
2385 | { | |
2386 | return; | |
2387 | } | |
2388 | static inline void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *adapter) | |
2389 | { | |
2390 | return; | |
2391 | } | |
2392 | #endif | |
af19b491 | 2393 | #endif /* __QLCNIC_H_ */ |